Neural network hardware implementation method and system based on incompletely specified function

Abstract

The present invention provides a method and system for implementing neural network hardware based on an incompletely specified function. The method comprises: quantizing the input data and weights of the neural network and obtaining positional indices of non-zero weights; traversing a training set and obtaining multiple data sets related to the non-zero weights based on the positional indices of the non-zero weights using the incompletely specified function; performing logical minimization on the multiple data sets to generate a Boolean logic expression based on the incompletely specified function; determining the size and internal port connections of a flash memory logic array based on a cube of the Boolean logic expression and logical variables in the Boolean logic expression; constructing a flash memory logic array based on the size and internal port connections of the flash memory logic array, and constructing peripheral circuits for the flash memory logic array, wherein the peripheral circuits are primarily used to process the output data of the flash memory logic array. The present invention reduces power consumption and latency during neural network hardware implementation.

Description

Technical Field

[0001] The present invention relates to the field of neural network technology, and in particular to a neural network hardware implementation method and system based on an incompletely specified function. Background Art

[0002] With the advent of the big data era, people are placing higher demands on computers' information processing capabilities. Artificial intelligence technology, centered around neural network algorithms, has demonstrated remarkable application potential in a variety of fields, including image processing, speech recognition, and natural language processing. However, the computational and storage complexity faced by neural network models when processing data makes them highly dependent on high-end computing platforms or cloud computing resources. In particular, in big data applications based on the traditional von Neumann architecture, the physical separation of storage and computing units leads to frequent data movement between them, further amplifying computing performance bottlenecks. This limits computing performance in terms of power consumption and latency, hindering the further development of artificial intelligence technology.

[0003] The implementation of neural network models involves a large number of multiplication-accumulation operations, which require frequent memory access to retrieve model parameters, resulting in high energy consumption and latency. To ensure the widespread application of deep learning models, improving the computational and storage costs of neural networks has become a critical task. Scholars have widely used various methods, such as weight pruning and quantization, to reduce the number of parameters or the bit precision of network layer parameters to lower computational and memory access costs. However, while these methods have alleviated the problem to some extent, they are still insufficient to fundamentally solve the problems of frequent memory access and high energy consumption.

[0004] In modern technology, analog computing solutions based on analog-to-digital converters (ADCs) primarily implement multiplication-accumulation operations on memory and computation arrays based on physical laws such as Ohm's law and Kirchhoff's law. This type of analog computing solution is characterized by the fact that the result of its computational unit is an analog signal of voltage or current. After the calculation is completed, the ADC is used to convert the current or voltage information of the calculated result into the corresponding digital information. Although this solution has obvious advantages in terms of read latency, it faces several significant disadvantages in practical applications. Because analog signals are susceptible to environmental factors such as noise, temperature fluctuations, and process variations, these factors can lead to errors and loss of precision in the calculation results. Therefore, the stability and reliability of this solution are relatively low, especially in applications with high precision requirements. In addition, the accuracy of the analog computing solution directly depends on the accuracy of the ADC used. High-precision ADCs generally require more complex circuit designs, including higher sampling rates and more detailed quantization levels, which not only increases system complexity but also increases power consumption.

[0005] Similar to the analog computing scheme, the enumeration-based computing scheme also has obvious limitations, especially when processing large-scale data. This method requires creating a huge truth table covering all input combinations for each network layer. When the number of inputs is large, the size of the truth table will grow exponentially. For example, 25 inputs will require a truth table containing 2 25 This exponential growth in size makes this method unsuitable for scenarios with a large number of inputs, as the truth table becomes too large to manage and compute. As the number of inputs increases, the computational resources and time required to enumerate all possible input combinations also increase significantly.

[0006] Therefore, in the hardware implementation process of neural networks in the existing technology, there are a lot of computing requirements and resource consumption problems, especially the frequent operations of data transmission and storage access will lead to higher power consumption and delay. Summary of the Invention

[0007] The present invention provides a neural network hardware implementation method and system based on an incompletely specified function, which is used to solve the defects of excessive power consumption and delay in the implementation process of the neural network model in the prior art, and to reduce the power consumption and delay in the implementation process of the neural network model.

[0008] The present invention provides a method for realizing neural network hardware based on an incompletely specified function, comprising:

[0009] Quantize the input data and weights of the neural network and obtain the position index of non-zero weights;

[0010] Traversing the training set, obtaining multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on the incompletely specified function;

[0011] Performing logic minimization based on the multiple data sets to generate a Boolean logic expression based on an incompletely specified function, and determining a flash memory logic array size and internal port connections based on a cube of the Boolean logic expression and logic variables in the Boolean logic expression;

[0012] The flash memory logic array is constructed according to the size of the flash memory logic array and the internal port connections, and a peripheral circuit of the flash memory logic array is constructed. The peripheral circuit is used to process the output data of the flash memory logic array.

[0013] According to a method for implementing a neural network hardware based on an incompletely specified function provided by the present invention, the quantization of the input data and weights of the neural network includes:

[0014] Converting input data of the neural network into unsigned data and converting weights of the neural network into signed data based on a quantization-aware training algorithm;

[0015] The unsigned data and the signed data have the same number of bits, and a sign bit is used to indicate whether the signed data is positive or negative.

[0016] According to a method for implementing a neural network hardware based on an incompletely specified function provided by the present invention, obtaining the position index of the non-zero weight includes:

[0017] According to the sign bit of the weight after quantization, the weight is divided into a positive weight and a negative weight;

[0018] Filtering a first non-zero weight from the positive weights, and recording a first position index of the first non-zero weight;

[0019] A second non-zero weight is screened out from the negative weights, and a second position index of the second non-zero weight is recorded.

[0020] According to the present invention, a method for implementing a neural network hardware based on an incompletely specified function is provided, wherein the method obtains multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on the incompletely specified function, including:

[0021] Obtaining a first input combination corresponding to the position index from different windows of input data corresponding to the weight;

[0022] The second input combination is a combination of input variables corresponding to the non-zero weights obtained when the input variable corresponding to each non-zero weight is 0 or 1;

[0023] Inputting the first input combination into an incompletely specified function to obtain an output of the convolution calculation of each layer of the neural network specified by the incompletely specified function according to the non-zero weights;

[0024] The second input combinations are divided into a plurality of sets according to the outputs.

[0025] According to a neural network hardware implementation method based on an incompletely specified function provided by the present invention, the output bit width n corresponding to the convolution calculation of each layer of the neural network is determined according to the number m of variables in the input combination, n = [log2(m)], and n and m are positive integers.

[0026] According to a neural network hardware implementation method based on an incompletely specified function provided by the present invention, dividing the second input combination into multiple sets according to the output includes:

[0027] When the value of each bit of the output is 1, dividing the first input combination corresponding to the output into a first set corresponding to each bit;

[0028] When the value of each bit of the output is 0, dividing the first input combination corresponding to the output into a second set corresponding to each bit;

[0029] Second input combinations other than the first input combination in the second input combinations are divided into third sets corresponding to respective bits.

[0030] According to a method for implementing a neural network hardware based on an incompletely specified function provided by the present invention, performing logical minimization based on the multiple data sets to generate a Boolean logic expression based on the incompletely specified function includes:

[0031] The first set, the second set, and the third set corresponding to each bit are processed based on the QM method, and the QM method merges the second input combination in the third set into the first set or the second set, so that the Boolean logic expression contains the least cubes and each cube contains the least logical variables.

[0032] According to a neural network hardware implementation method based on an incompletely specified function provided by the present invention, determining the size of a flash memory logic array and internal port connections based on a cube of the Boolean logic expression and logical variables in the Boolean logic expression includes:

[0033] The flash logic array includes a clock signal, a plurality of pull-down stacks, and pre-charge transistors;

[0034] determining the pull-down stack in the flash logic array according to the cube in the Boolean logic expression, and determining the number of rows in the flash logic array according to the logical variable in the Boolean logic expression;

[0035] The pull-down stack includes an evaluation transistor and a flash memory device, the gates of the precharge transistor and the evaluation transistor being connected to the clock signal, the flash memory device being configured to be programmed according to a logic function;

[0036] When the logic variable does not exist in the cube, the flash memory device in the pull-down stack corresponding to the cube is programmed to an erased state, the flash memory device is always turned on, and a metal line is used to replace the flash memory device;

[0037] When the clock signal is at a low level, the precharge transistor is turned on, and the output node of the flash logic array performs a precharge operation to raise the output signal to a high level;

[0038] When the clock signal is high, the evaluation transistor is turned on, the pull-down stack performs a logic operation, and the SL line of the pull-down stack is grounded. When at least one pull-down stack is turned on, the output signal is pulled down to a low level, otherwise the output signal remains at a high level.

[0039] According to a method for implementing a neural network hardware based on an incompletely specified function provided by the present invention, the peripheral circuit for constructing the flash memory logic array includes:

[0040] The peripheral circuit includes an input image control module, a network layer function module and an intermediate data cache module;

[0041] The input image cache module is used to cache the input image data, and extract the data in the convolution window by controlling the sliding of the convolution window and input it into the flash memory logic array;

[0042] The output port of the flash memory logic array is connected to the network layer function module, and the network layer function module is used to perform shift weighting operation, requantization operation and activation function processing on the output of the flash memory logic array to obtain the output of each layer of the neural network;

[0043] The output is stored in the intermediate data cache module for pooling operation, and the result is used as the input of the next layer of network.

[0044] The Boolean logic expression based on the incompletely specified function obtained using the QM algorithm can also be mapped to a CMOS (Complementary Metal Oxide Semiconductor) logic circuit. The arrangement of the logic circuit is consistent with the flash memory logic array. The flash memory devices in the erased state are replaced by depletion-mode NMOS (N Metal Oxide Semiconductor) tubes, and the flash memory devices in the programmed state are replaced by enhancement-mode NMOS tubes.

[0045] The present invention also provides a neural network hardware implementation system based on an incompletely specified function, comprising:

[0046] The data preprocessing module is used to quantize the input data and weights of the neural network and obtain the position index of non-zero weights;

[0047] A partitioning module, configured to traverse the training set and obtain multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on an incompletely specified function;

[0048] a determination module, configured to perform logic minimization based on the multiple data sets to generate a Boolean logic expression based on an incompletely specified function, and determine the size of the flash memory logic array and internal port connections based on a cube of the Boolean logic expression and the non-zero weights;

[0049] A construction module is used to construct the flash memory logic array according to the size of the flash memory logic array and the internal port connections, and to construct a peripheral circuit of the flash memory logic array, wherein the peripheral circuit is used to process output data of the flash memory logic array.

[0050] The neural network hardware implementation method and system based on incompletely specified functions provided by the present invention first quantizes the input data and weights of each layer of the neural network, converts complex floating-point numbers into integer data for calculation, reduces the occupation of hardware computing resources, and can reduce computational complexity and power consumption while maintaining computational accuracy; then determines the first input combination corresponding to the position index of the non-zero weight in the input data, thereby reducing the number of input combinations and avoiding the enumeration of all input combinations, reducing computational complexity and resource consumption, making it more efficient when processing a large number of input variables; then describes the multiplication and accumulation operations of the neural network layer through Boolean logic expressions, converts complex mathematical operations into logical operations, and maps the Boolean logic expressions in the logic circuit at the hardware level, significantly reducing computational complexity, thereby avoiding high-energy multiplication operations. The present invention performs targeted design and optimization of the hardware structure through algorithms, significantly improving the operating efficiency of the neural network model on hardware. Specifically, it reduces data transmission and storage access by combining quantization processing, Boolean logic optimization and logic circuit design, and improves the execution efficiency of the neural network at the hardware level. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 It is a flowchart of the method for realizing neural network hardware based on incompletely specified functions provided by the present invention;

[0053] Figure 2 Schematic diagram of the weight parameter processing process of a convolution kernel with a size of 5x5 in the neural network hardware implementation method based on an incompletely specified function provided by the present invention;

[0054] Figure 3It is a representation of the true value of the input combination corresponding to the weight data of the network layer in the neural network hardware implementation method based on the incompletely specified function provided by the present invention;

[0055] Figure 4 Schematic diagram of a flash memory logic array for implementing a logical expression in the form of an SOP in the neural network hardware implementation method based on an incompletely specified function provided by the present invention;

[0056] Figure 5 Schematic diagram of a simplified flash memory logic array in the neural network hardware implementation method based on incompletely specified functions provided by the present invention;

[0057] Figure 6 The logic function F in the neural network hardware implementation method based on the incomplete specified function provided by the present invention is m,n Schematic diagram of logic circuit framework;

[0058] Figure 7 It is the hardware architecture applied to the convolutional neural network in the neural network hardware implementation method based on the incompletely specified function provided by the present invention;

[0059] Figure 8 It is a structural diagram of the neural network hardware implementation system based on incompletely specified functions provided by the present invention. DETAILED DESCRIPTION

[0060] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0061] The following combination Figure 1 A method for implementing a neural network hardware based on an incompletely specified function according to the present invention is described, comprising:

[0062] Step 101, quantize the input data and weights of the neural network, and obtain the position index of non-zero weights;

[0063] For adaptation, the input data and weights of each layer of the neural network are quantized, such as 4-bit quantization.

[0064] Since the quantized weight data is highly sparse, containing a large number of zero weights, these zero weights do not contribute effectively to the actual multiplication-accumulation operation. The multiplication-accumulation result is only related to the input activation values multiplied by the non-zero weights. Therefore, by filtering out the input variables corresponding to zero weights, the number of input combinations that need to be calculated can be effectively reduced.

[0065] For example, if the weights of the neural network are 5x5 convolution kernel weights and the input data is 100x100, then the window size corresponding to the weights in the input data is 5x5. Get the position index of the non-zero weight from the 5x5 convolution kernel weights.

[0066] Step 102, traversing the training set, and obtaining multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on the incompletely specified function;

[0067] The multiplication and addition operations of each binary combination of non-zero weights with each bit of the neural network input activation are then performed using an incompletely specified function (ISF). An incompletely specified function is a Boolean function that defines its output value only for a subset of its input combinations.

[0068] All data in the training set can be applied to the neural network at once, obtaining the input and output data for each layer. Due to the quantization of data between neural network layers, the output data is 4-bit unsigned data, which is further decomposed into four binary arrays. The training set is then traversed based on the partially specified function to obtain multiple data sets associated with non-zero weights.

[0069] Step 103: Performing logic minimization based on the multiple data sets to generate a Boolean logic expression based on an incompletely specified function, and determining the size of the flash memory logic array and internal port connections based on a cube of the Boolean logic expression and logic variables in the Boolean logic expression;

[0070] Multiple sets are input into the QM algorithm for calculation to obtain a Boolean logic expression based on ISF implementation.

[0071] The QM algorithm seeks to find the smallest possible disjunctive normal form (DNF) that covers the solution of the ON set. The goal of this function is to generate a logical expression that contains as few cubes (logical conjunctions) as possible, and each cube contains as few literals (logical variables) as possible.

[0072] Step 104 : constructing the flash logic array according to the size of the flash logic array and the internal port connections, and constructing a peripheral circuit of the flash logic array, wherein the peripheral circuit is used to process the output data of the flash logic array.

[0073] A flash logic array is constructed for each layer of the neural network based on the Boolean logic expression, thereby mapping the Boolean logic expression to the flash logic array for calculation. The rows of the flash logic array correspond one-to-one to the logical variables in the Boolean logic expression, and the columns of the flash logic array correspond one-to-one to the cubes in the Boolean logic expression.

[0074] This embodiment first quantizes the input data and weights of each layer of the neural network, converts complex floating-point numbers into integer data for calculation, reduces the occupation of hardware computing resources, and can reduce computational complexity and power consumption while maintaining computational accuracy; then determines the first input combination corresponding to the position index of the non-zero weight in the input data, thereby reducing the number of input combinations and avoiding the enumeration of all input combinations, reducing computational complexity and resource consumption, making it more efficient when processing a large number of input variables; then describes the multiplication and accumulation operations of the neural network layer through Boolean logic expressions, converts complex mathematical operations into logical operations, and maps Boolean logic expressions in logic circuits at the hardware level, significantly reducing computational complexity, thereby avoiding high-energy multiplication operations. The present invention uses algorithms to design and optimize the hardware structure in a targeted manner, significantly improving the operating efficiency of the neural network model on hardware. Specifically, it optimizes the logical structure and data access method by combining quantization processing, Boolean logic optimization and logic circuit design, reduces data transmission and storage access, reduces energy consumption and delay, and improves the execution efficiency of the neural network at the hardware level.

[0075] Based on the above embodiment, this embodiment quantizes the input data and weights of the neural network and obtains the position index of the non-zero weight, including:

[0076] Converting the input data of the neural network into unsigned data and converting the weights of the neural network into signed data based on a quantization-aware training algorithm (QAT);

[0077] The unsigned data and the signed data have the same number of bits, and a sign bit is used to indicate whether the signed data is positive or negative.

[0078] For example, a neural network is quantized to 4-bit precision. After quantization, the input data of each layer of the neural network is converted to unsigned 4-bit data, while the weight data is converted to signed 4-bit data. The positive and negative values can be represented by the joint representation of two bits (10 represents +1, 01 represents -1). The quantized weight data is stored bit by bit, and each group of signed 4-bit weight data is composed of eight groups of binary values.

[0079] Based on the above embodiment, the method of obtaining a position index with a non-zero weight in this embodiment includes:

[0080] According to the sign bit of the weight after quantization, the weight is divided into a positive weight and a negative weight;

[0081] Filtering a first non-zero weight from the positive weights, and recording a first position index of the first non-zero weight;

[0082] A second non-zero weight is screened out from the negative weights, and a second position index of the second non-zero weight is recorded.

[0083] Figure 2 The following is a processing process for the weight parameters of a quantized convolution kernel of size 5x5. A set of signed weights can be divided into positive weights and negative weights according to their sign bits, and non-zero weights can be filtered out. By traversing the convolution kernel, the position indexes of all non-zero weights are identified and recorded, and stored in the address list address. Since the number of input combinations is exponentially related to the number of non-zero weights n, the number of input combinations is reduced by 2. 25 Reduced to 2 n .

[0084] Based on the above embodiment, in this embodiment, the method of obtaining multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on the incompletely specified function includes:

[0085] Obtaining a first input combination corresponding to the position index from different windows of input data corresponding to the weight;

[0086] The second input combination is a combination of input variables corresponding to the non-zero weights obtained when the input variable corresponding to each non-zero weight is 0 or 1;

[0087] Inputting the first input combination into an incompletely specified function to obtain an output of the convolution calculation of each layer of the neural network specified by the incompletely specified function according to the non-zero weights;

[0088] The second input combinations are divided into a plurality of sets according to the outputs.

[0089] Determine the window corresponding to the weight in the input data, obtain the position index of the non-zero weight from the convolution kernel weight within the window, and use the input variable at the position index of the non-zero weight in each window as an input combination. The input combination obtained from the input data is used as the first input combination. The number of first input combinations obtained from the input data is determined by the window movement step size.

[0090] The second input combination is all possible input combinations enumerated based on the non-zero weights of each layer of the neural network. For example, if the number of non-zero weights is 7, the number of second input combinations is 2. 7 =128.

[0091] The first input combination is a subset of the second input combination. The output corresponding to each first input combination is 0 or 1, and the second input combination is divided into multiple sets according to the different outputs.

[0092] Based on the position index of the non-zero weight in the convolution kernel corresponding to the output data of each neural network layer, the binary values of the position index are combined into a single string called filtered_data.

[0093] By traversing the binary array of each sample data in the training set, all different first input combinations corresponding to filtered_data are identified and stored in the set data_input, and the same first input combination corresponding to filtered_data is only identified and stored once.

[0094] After the data is processed, each first input combination in the set data_input is used as the input of the ISF, and its output is specified according to the weight. In this process, the weight data is fixed and all input combinations in the set data_input are traversed to calculate the output Y = X0*A0+X1*A1+...+X m *A m Where X represents the weight, A represents the input activation value, that is, the input variable in the input combination, X0, X1, ...., X m The values in are not 0, and m represents the number of non-zero weights, which is equivalent to the number of input variables contained in each input combination.

[0095] The first set corresponds to an output of 1 and can be called the ON set. The second set corresponds to an output of 0 and can be called the OFF set. The third set corresponds to an unspecified output and can be called the don't care set (or simply the DC set). This method avoids enumerating all possible input combinations for each set of weight data by only evaluating the output corresponding to the input combinations of samples extracted from the training set and classifying the unevaluated input combinations into the DC set of the neural network. Therefore, the size of the ON set and the OFF set is linearly related to the size of the training set, rather than exponentially related to the number of inputs to the neural network layer.

[0096] This embodiment effectively utilizes don't care sets (DC sets) to simplify logical expressions and highly optimizes Boolean logical expressions based on incompletely specified functions, effectively reducing the number of disjunctive minors in logical expressions and compressing the number of logical variables in the disjunctive minors, thereby significantly reducing the usage of hardware resources, especially the area requirement of the flash memory array.

[0097] Based on the above embodiment, the output bit width n corresponding to the convolution calculation of each layer of the neural network in this embodiment is determined according to the number m of variables in the input combination, n=[log2(m)], and n and m are positive integers.

[0098] The output calculation formula can be expressed as a multi-input multi-output function F with m input variables and n output variables. m,n . Among them, its output n is the bit width of Y.

[0099] Based on the above embodiment, in this embodiment, the second input combination is divided into multiple sets according to the output, including:

[0100] When the value of each bit of the output is 1, dividing the first input combination corresponding to the output into a first set corresponding to each bit;

[0101] When the value of each bit of the output is 0, dividing the first input combination corresponding to the output into a second set corresponding to each bit;

[0102] Second input combinations other than the first input combination in the second input combinations are divided into third sets corresponding to respective bits.

[0103] For each bit of the output Y, the input combinations in its ON set, OFF set and DC set are obtained according to the value of each bit of the output.

[0104] Figure 3 for Figure 2The truth table of all input combinations in data_input corresponding to the positive weights after weight filtering. Since the number of non-zero weights m = 7, the bit width of the output Y can be calculated as 3 according to the formula n = [log2(m)], so the output can be divided into three independent bits Y0, Y1, and Y2.

[0105] By traversing all sample data in the training set, all input combinations in the set data_input can be obtained, and the outputs of Y0, Y1 and Y2 are defined according to the multiplication and accumulation formula, so as to obtain the first input combination in the ON set and OFF set of Y0, Y1 and Y2.

[0106] Figure 3 The first column on the left of the truth table represents the number of input combinations in data_inpu. It can be seen that the number of input combinations corresponding to this set of weights is reduced from 128 to 53. All input combinations except data_input in the 128 input combinations are included in the DC set.

[0107] The data of the ON set, OFF set and DC set of each bit outputted above are input into the QM algorithm for calculation to obtain the Boolean logic expression form based on ISF implementation.

[0108] Based on the above embodiment, the method of performing logical minimization based on the multiple data sets in this embodiment to generate a Boolean logic expression based on an incompletely specified function includes:

[0109] Based on the QM method for the first set, the second set, and the third set corresponding to each bit, the QM method merges the second input combination in the third set into the first set or the second set, so that the Boolean logic expression contains the least cubes and each cube contains the least logical variables.

[0110] When generating Boolean logic expressions based on the QM algorithm, since the ISF output regarding the DC set is unspecified, it can be set to logic 0 or logic 1 as needed. Typically, DC set elements close to the ON set in the input space are assigned a value of 1, while DC set elements close to the OFF set are assigned a value of 0. This strategy allows some DC set data to be incorporated into the ON set, highly optimizing the logic expression. This optimization significantly reduces the overall logic gate count.

[0111] As shown in Table 1, Figure 3 The data shows the usage of logic resources before and after using the ISF and QM algorithms. It can be seen that the number of AND gates and OR gates is significantly reduced after using the ISF and QM algorithms. This reduction in the number of logic gates directly leads to a reduction in circuit area overhead and power consumption, improving the economic benefits and energy efficiency of circuit design.

[0112] In the process of logic minimization, the QM method can not only use the AND and OR logical operators to implement logical expressions, namely the SOP (Sum of Products) form, but also introduce the XNOR and XOR operators to achieve a more compact logical expression form.

[0113] Table 1 Logical resource usage before and after using ISF and QM algorithms

[0114]

[0115] Based on the above embodiments, Figure 4 As shown, in this embodiment, determining the size of the flash memory logic array and the internal port connections based on the cube of the Boolean logic expression and the logical variables in the Boolean logic expression includes:

[0116] The flash memory logic array is designed based on a dynamic logic circuit, including a clock signal clk, a plurality of NAND-like (NotAND, NAND gate) flash memory pull-down stacks and precharge transistors M sharing the same output. pch ;

[0117] determining the pull-down stack in the flash logic array according to the cube in the Boolean logic expression, and determining the number of rows in the flash logic array according to the logical variable in the Boolean logic expression;

[0118] The pull-down stack includes an evaluation transistor and a flash memory device, the gates of the precharge transistor and the evaluation transistor are connected to the clock signal, and the flash memory device is used to be programmed accordingly according to the logic function required to be implemented by the circuit, wherein VT0 is an erase state threshold and VT1 is a programming state threshold;

[0119] When the logic variable does not exist in the cube, the flash memory device in the pull-down stack corresponding to the cube is programmed to an erased state, the flash memory device is always turned on, and a metal line is used to replace the flash memory device;

[0120] When the clock signal clk is at a low level, the precharge transistor is turned on, and the output node of the flash logic array performs a precharge operation, and the output signal Y bit Raise to high level;

[0121] When the clock signal clk is high, the evaluation transistor is turned on, and the pull-down stack performs a logic operation. The SL (Source Lines) line of the pull-down stack is grounded during the logic calculation phase to allow the NAND stack to be pulled low during evaluation when at least one pull-down stack in the array forms a conductive path, and the output signal Y is output. bitPull down to low level.

[0122] The multiplication and accumulation calculation is equivalent to a multi-input multi-output logic function, and the formula is as follows:

[0123]

[0124] The output Y is represented by binary as (Y n-1 Y n-2 Y1Y0)2, m is the number of non-zero weights, is the bit width of output Y.

[0125] The optimized algorithm implicitly incorporates weight data into the logic function. By mapping the logic function to the flash logic array, multiplication and accumulation calculations can be performed in the array without frequently reading the weight data. This effectively reduces the burden of data transmission and memory access, and solves the power consumption and latency issues caused by the frequent data movement between memory and processor in traditional von Neumann architectures.

[0126] A flash logic array with a known number of rows and columns is constructed using a logic function. The flash devices in each column are connected in series via their source and drain electrodes to form a pull-down stack, with the ends of the pull-down stack connected to the source line (SL). The gates of the flash devices in the pull-down stack must be connected to word lines, with two word lines for each row of flash devices. The number of rows and columns in the array is related to the logic function generated by the algorithm. The resulting SOP-form logic function contains multiple disjuncts, each containing a number of logical variables. The number of drop-down stacks in the array (i.e., the number of columns) is equal to the number of disjuncts (cubes) in the logic function, while the number of flash devices in each drop-down stack (i.e., the number of rows in the flash logic array) is equal to the number of non-zero weights in the convolution kernel. Therefore, the area occupied by the flash logic array is closely related to the generated logic function.

[0127] By traversing the training set, the system systematically searches for and utilizes DC set data, merging portions of the DC set data into the ON set data to significantly simplify the logic function. This process effectively reduces the number of disjunctive minors in the logical expression. Furthermore, by merging disjunctive minors, the number of logical variables in the disjunctive minors is further compressed, significantly reducing hardware resource usage. This is particularly true with regard to the area required for the flash logic array. By reducing the number of pull-down stacks and the number of required flash memory devices, the area occupied by the flash array is significantly reduced.

[0128] The flash logic array consists of multiple NAND-like flash pull-down stacks sharing the same output. It also includes precharge transistors Mpch and evaluation transistors. The array's logic computing functions are controlled through the coordinated action of precharge and evaluation transistors. The gates of both the precharge and evaluation transistors are connected to the clock signal, clk. The precharge transistor is a PMOS (Positive channel Metal Oxide Semiconductor) transistor, while the evaluation transistor is an NMOS (N-type Metal Oxide Semiconductor) transistor. Only one of the two transistors is conductive at any given time, enabling the flash memory logic array to switch between precharge and logic computing operations.

[0129] When clk is low, the precharge transistor is turned on and the evaluation transistor is turned off. At this time, the pull-down stack is in the cut-off state and the output signal Y bit Will be precharged to a high level. When clk is high, the precharge transistor is turned off and the evaluation transistor is turned on. At this time, the array performs logical calculation operations and outputs Y bit Depending on the conduction state of the pull-down stack, it will remain at a high level or be pulled down to a low level. bit is the result of multiplication and accumulation calculation (Y n-1 Y n-2 The method constructs n flash memory logic arrays that share the same set of word lines. The word lines of the arrays are connected to a data cache module, which stores data that needs to be input to the array for convolution calculation. The convolution window sliding control is used to input the input data selected by the convolution window sliding module into the word line bit by bit, thereby achieving the multiplication and accumulation calculation results of each bit of input data and each bit of weight data in the array.

[0130] In the logic function cube, when a logic variable does not exist, the flash memory device in the corresponding pull-down stack is programmed to the erased state (VT0). In this state, the flash memory device is always in the "ON" state and has no direct impact on the result of the logic operation. Therefore, it can be replaced by metal wires to simplify the circuit design. The simplified flash memory array is as follows: Figure 5 shown.

[0131] Other flash memory devices that need to indicate the presence of a logical variable are programmed into a programming state (VT1). These devices can only conduct when the gate drive voltage exceeds VT1. The connection of the gate of these flash memory devices in the programming state is determined by the logic state of the corresponding text in the cube, that is, it is connected to the original state or the complement state of the input variable.

[0132] For example, Figure 4 The leftmost stack in the programming state of the flash memory device has F b,0 、Fc,0 , F e,0 and F f,0 , so the cube of the logic function implemented by the stack only involves four input logic variables bcef, and according to the connection of the gates of these four flash memory devices, the cube of the logic function implemented by the stack can be obtained as

[0133] For the logic function F m,n , the framework diagram of its logic circuit is as follows Figure 6 Each Flash Logic Array (FLA) configuration is based on Figure 5 It is worth noting that since the output of the logic array defaults to the inverse logic state of the logic function, an inverter is added at the output of the array to ensure the correct logic output result.

[0134] Based on the above embodiment, the peripheral circuit of the flash memory logic array in this embodiment includes:

[0135] The peripheral circuit includes an input image control module, a network layer function module and an intermediate data cache module;

[0136] The input image cache module is used to cache the input image data, and extract the data in the convolution window by controlling the sliding of the convolution window and input it into the flash memory logic array;

[0137] The output port of the flash memory logic array is connected to the network layer function module, and the network layer function module is used to perform shift weighting operation, requantization operation and activation function processing on the output of the flash memory logic array to obtain the output of each layer of the neural network;

[0138] The output is stored in the intermediate data cache module for pooling operation, and the result is used as the input of the next layer of network.

[0139] like Figure 7As shown, when flash memory logic circuits are applied to a convolutional neural network hardware architecture, the array, connected to peripheral circuits, can perform convolution calculations on the input image data and weight data without having to read weight data from external storage. The test set image data is stored in the input image buffer img_buffer. The convolution control circuit controls the sliding of the convolution window, sequentially retrieving the corresponding data within the sliding window from img_buffer and inputting it into the array via word lines for calculation. Each row of the array is equipped with two word lines: one for inputting the original data and the other for inputting the inverse of the original data. The array output is the multiplication and accumulation calculation result of each bit of data, which is input into the shift and weight module to obtain the final convolution output. The array output is directly a digital signal with high and low levels, eliminating the need for a high-precision ADC to convert the current signal into a voltage signal, thereby reducing the accuracy loss and energy consumption associated with the ADC. This design effectively solves the power consumption and efficiency issues of traditional computing architectures and significantly improves the execution efficiency of convolutional neural network hardware. The result of a single convolution calculation is input into the network layer function module for subsequent quantization operations and activation function processing. The obtained data is stored in the intermediate data buffer for pooling operations. After the convolution sliding calculation is completed, the complete feature map data is obtained as the input of the next layer of the network.

[0140] The following describes the neural network hardware implementation system based on an incompletely specified function provided by the present invention. The neural network hardware implementation system based on an incompletely specified function described below and the neural network hardware implementation method based on an incompletely specified function described above can refer to each other.

[0141] like Figure 8 As shown, the system includes data preprocessing 801, a division module 802, a determination module 803 and a construction module 804:

[0142] Data preprocessing 801 is used to quantize the input data and weights of the neural network and obtain the position index of non-zero weights;

[0143] The partitioning module 802 is used to traverse the training set and obtain multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on the incomplete specified function;

[0144] The determination module 803 is configured to perform logic minimization based on the multiple data sets to generate a Boolean logic expression based on an incompletely specified function, and determine the size of the flash memory logic array and internal port connections based on a cube of the Boolean logic expression and the non-zero weights;

[0145] The construction module 804 is used to construct the flash logic array according to the size of the flash logic array and the internal port connections, and to construct the peripheral circuit of the flash logic array. The peripheral circuit is used to process the output data of the flash logic array.

[0146] This embodiment first quantizes the input data and weights of each layer of the neural network, converts complex floating-point numbers into integer data for calculation, reduces the occupation of hardware computing resources, and can reduce computational complexity and power consumption while maintaining computational accuracy; then determines the first input combination corresponding to the position index of the non-zero weight in the input data, thereby reducing the number of input combinations and avoiding the enumeration of all input combinations, reducing computational complexity and resource consumption, making it more efficient when processing a large number of input variables; then describes the multiplication and accumulation operations of the neural network layer through Boolean logic expressions, converts complex mathematical operations into logical operations, and maps the Boolean logic expressions in the logic circuit at the hardware level, significantly reducing computational complexity, thereby avoiding high-energy multiplication operations. The present invention uses algorithms to carry out targeted design and optimization of the hardware structure, significantly improving the operating efficiency of the neural network model on hardware.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for hardware implementation of a neural network based on an incompletely specified function, characterized in that: include: Quantize the input data and weights of the neural network and obtain the position index of non-zero weights; Traversing the training set, obtaining multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on the incompletely specified function; Performing logic minimization based on the multiple data sets to generate a Boolean logic expression based on an incompletely specified function, and determining a flash memory logic array size and internal port connections based on a cube of the Boolean logic expression and logic variables in the Boolean logic expression; A flash memory logic array is constructed according to the size of the flash memory logic array and the internal port connections, and a peripheral circuit of the flash memory logic array is constructed. The peripheral circuit is mainly used for processing the output data of the flash memory logic array.

2. The method for realizing a neural network hardware based on an incompletely specified function according to claim 1, wherein: The quantization of the input data and weights of the neural network includes: Converting input data of the neural network into unsigned data and converting weights of the neural network into signed data based on quantization-aware training; The unsigned data and the signed data have the same number of bits, and a sign bit is used to indicate whether the signed data is positive or negative.

3. The method for realizing a neural network hardware based on an incompletely specified function according to claim 1, wherein: The obtaining of the position index of the non-zero weight includes: According to the sign bit of the weight after quantization, the weight is divided into a positive weight and a negative weight; Filtering a first non-zero weight from the positive weights, and recording a first position index of the first non-zero weight; A second non-zero weight is screened out from the negative weights, and a second position index of the second non-zero weight is recorded.

4. The method for realizing a neural network hardware based on an incompletely specified function according to claim 1, wherein: The acquiring of multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on the incompletely specified function includes: Obtaining a first input combination corresponding to the position index from different windows of input data corresponding to the weight; The second input combination is a combination of input variables corresponding to non-zero weights obtained when the input variable corresponding to each non-zero weight is 0 or 1; Inputting the first input combination into an incompletely specified function to obtain an output of the convolution calculation of each layer of the neural network specified by the incompletely specified function according to the non-zero weights; The second input combinations are divided into a plurality of sets according to the outputs.

5. The method for realizing a neural network hardware based on an incompletely specified function according to claim 4, wherein: The output bit width n corresponding to the convolution calculation of each layer of the neural network is determined according to the number of variables m in the input combination. n and m are positive integers.

6. The method for realizing a neural network hardware based on an incompletely specified function according to claim 5, wherein: The step of dividing the second input into a plurality of sets according to the output comprises: When the value of each bit of the output is 1, dividing the first input combination corresponding to the output into a first set corresponding to each bit; When the value of each bit of the output is 0, dividing the first input combination corresponding to the output into a second set corresponding to each bit; Second input combinations other than the first input combination in the second input combinations are divided into third sets corresponding to respective bits.

7. The method for realizing a neural network hardware based on an incompletely specified function according to claim 6, wherein: The performing logical minimization based on the multiple data sets to generate a Boolean logic expression based on an incompletely specified function includes: The first set, the second set, and the third set corresponding to each bit are processed based on the QM method, and the QM method merges the second input combination in the third set into the first set or the second set, so that the Boolean logic expression contains the least cubes and each cube contains the least logical variables.

8. The method for realizing a neural network hardware based on an incompletely specified function according to any one of claims 1 to 7, characterized in that: The step of determining the size of the flash memory logic array and internal port connections based on the cube of the Boolean logic expression and the logic variables in the Boolean logic expression includes: The flash logic array includes a clock signal, a plurality of pull-down stacks, and pre-charge transistors; determining the pull-down stack in the flash logic array according to the cube in the Boolean logic expression, and determining the number of rows in the flash logic array according to the logical variable in the Boolean logic expression; The pull-down stack includes an evaluation transistor and a flash memory device, the gates of the precharge transistor and the evaluation transistor being connected to the clock signal, the flash memory device being configured to be programmed according to a logic function; When the logic variable does not exist in the cube, the flash memory device in the pull-down stack corresponding to the cube is programmed to an erased state, the flash memory device is always turned on, and a metal line is used to replace the flash memory device; When the clock signal is at a low level, the precharge transistor is turned on, and the output node of the flash logic array performs a precharge operation to raise the output signal to a high level; When the clock signal is high, the evaluation transistor is turned on, the pull-down stack performs a logic operation, and the SL line of the pull-down stack is grounded. When at least one pull-down stack is turned on, the output signal is pulled down to a low level, otherwise the output signal remains at a high level.

9. The method for realizing a neural network hardware based on an incompletely specified function according to any one of claim 1, wherein: The peripheral circuit for constructing the flash memory logic array includes: The peripheral circuit includes an input image control module, a network layer function module and an intermediate data cache module; The input image cache module is used to cache the input image data, and extract the data in the convolution window by controlling the sliding of the convolution window and input it into the flash memory logic array; The output port of the flash memory logic array is connected to the network layer function module, and the network layer function module is used to perform shift weighting operation, requantization operation and activation function processing on the output of the flash memory logic array to obtain the output of each layer of the neural network; The output is stored in the intermediate data cache module for pooling operation, and the result is used as the input of the next layer of network.

10. A neural network hardware implementation system based on an incompletely specified function, characterized in that: include: The data preprocessing module is used to quantize the input data and weights of the neural network and obtain the position index of non-zero weights; A partitioning module, configured to traverse the training set and obtain multiple data sets related to the non-zero weights according to the position index of the non-zero weights based on an incompletely specified function; a determination module, configured to perform logic minimization based on the multiple data sets to generate a Boolean logic expression based on an incompletely specified function, and determine a flash memory logic array size and internal port connections based on a cube of the Boolean logic expression and the non-zero weights; A construction module is used to construct a flash memory logic array according to the size of the flash memory logic array and the internal port connections, and to construct a peripheral circuit of the flash memory logic array, wherein the peripheral circuit is used to process output data of the flash memory logic array.

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