Array substrate, driving method and display device

Abstract

The invention provides an array substrate, a driving method and a display device. The array substrate comprises a driving module, a plurality of scanning lines, a plurality of data lines and a plurality of pixels, two scanning lines are arranged between two adjacent rows of sub-pixels; two columns of sub-pixels are arranged between the two columns of data lines; in the same row of sub-pixels, the plurality of sub-pixels electrically connected with the same data line have at least two colors; in the adjacent rows of sub-pixels, at least two sub-pixels electrically connected with the same data line have the same color; the driving module controls an overlapping time period and a non-overlapping time period to exist between effective time periods of scanning signals provided by at least two scanning lines which are opened in sequence in a display frame; the data voltage received by the data line in at least part of time in the overlapping time period is the same as the data voltage received by the data line in at least part of time in the non-overlapping time period. The charging rate and the refresh rate can be improved, and the display quality is improved.

Description

Technical Field

[0001] The present invention relates to the technical field, and in particular to an array substrate, a driving method and a display device. Background Art

[0002] In related technologies, the pixel structure using the Dual Gate drive architecture can reduce the display cost by reducing the data signal lines and thus reducing the number of channels of the source driver chip. As the display panel develops towards large size and high resolution, the display industry continues to explore how to balance cost while ensuring display charging rate. Summary of the invention

[0003] The main purpose of the present invention is to provide an array substrate, a driving method and a display device to solve the problem of low display charging rate of the pixel structure of the dual-gate driving architecture in the prior art.

[0004] In one aspect, an embodiment of the present invention provides an array substrate, comprising a driving module, a plurality of scan lines extending along a first direction, a plurality of data lines extending along a second direction, and a plurality of pixels; the pixel comprises at least three sub-pixels with different colors; two scan lines are arranged between two adjacent rows of sub-pixels; two columns of sub-pixels are arranged between two columns of data lines; the sub-pixels are electrically connected to the scan lines and the data lines, respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines;

[0005] In the same row of sub-pixels, a plurality of sub-pixels electrically connected to the same data line have at least two colors;

[0006] In adjacent rows of sub-pixels, at least two sub-pixels electrically connected to the same data line have the same color;

[0007] The driving module is used to provide a scanning signal to the scanning line, so as to control the existence of an overlapping time period and a non-overlapping time period between the effective time periods of the scanning signals provided by at least two scanning lines turned on in sequence within a display frame;

[0008] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0009] Optionally, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer;

[0010] The sub-pixels in the odd columns of the 4m-3rd row are electrically connected to the scan lines in the 8m-7th row, and the sub-pixels in the even columns of the 4m-3rd row are electrically connected to the scan lines in the 8m-6th row;

[0011] The sub-pixels in the odd columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even columns of the 4m-2th row are electrically connected to the scan lines in the 8m-5th row;

[0012] The sub-pixels in the odd columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row, and the sub-pixels in the even columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row;

[0013] The sub-pixels in the odd columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even columns of the 4mth row are electrically connected to the scan line in the 8mth row;

[0014] a and m are positive integers.

[0015] Optionally, the sub-pixel in the 2b-1 column of the 4m-3th row, the sub-pixel in the 2b-1 column of the 4m-2th row, the sub-pixel in the 2b column of the 4m-3th row, and the sub-pixel in the 2b column of the 4m-2th row are electrically connected to the data line in the bth column;

[0016] The sub-pixel in the 2b-1th column of the 4m-1th row, the sub-pixel in the 2b ...th row, and the sub-pixel in the 2bth column of the 4mth row are all electrically connected to the data line in the b+1th

[0017] b is a positive integer.

[0018] Optionally, the 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line;

[0019] The 8n-6th level driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-4th line scanning signal according to the second clock signal provided by the second clock signal line;

[0020] The 8n-5th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-6th line scanning signal according to the third clock signal provided by the third clock signal line;

[0021] The 8n-4th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-5th row scanning signal according to the fourth clock signal provided by the fourth clock signal line;

[0022] The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line;

[0023] The 8n-2-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line;

[0024] The 8n-1th stage driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-2th row scanning signal according to the seventh clock signal provided by the seventh clock signal line;

[0025] The 8n-th level driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-1-th row scanning signal according to the eighth clock signal provided by the eighth clock signal line;

[0026] n is a positive integer.

[0027] Optionally, the 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line;

[0028] The 8n-6th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-6th line scanning signal according to the third clock signal provided by the third clock signal line;

[0029] The 8n-5th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-5th row scanning signal according to the fourth clock signal provided by the fourth clock signal line;

[0030] The 8n-4th stage driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-4th row scanning signal according to the second clock signal provided by the second clock signal line;

[0031] The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line;

[0032] The 8n-2-th level driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-2-th row scanning signal according to the seventh clock signal provided by the seventh clock signal line;

[0033] The 8n-1th stage driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-1th row scanning signal according to the eighth clock signal provided by the eighth clock signal line;

[0034] The 8n-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line;

[0035] n is a positive integer.

[0036] Optionally, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer;

[0037] The sub-pixels in the odd columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even columns of the 4m-2th row are electrically connected to the scan lines in the 8m-3th column;

[0038] The sub-pixels in the odd columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row, and the sub-pixels in the even columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row;

[0039] The sub-pixels in the odd columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even columns of the 4mth row are electrically connected to the scan line in the 8mth row;

[0040] The 4m+1th row of odd-numbered columns of sub-pixels are electrically connected to the 8m+2th row of scan lines, and the 4m+1th row of even-numbered columns of sub-pixels are electrically connected to the 8m+1th row of scan lines;

[0041] a and m are positive integers.

[0042] Optionally, the sub-pixel in the 2b-1 column of the 4m-2th row, the sub-pixel in the 2b-2th column of the 4m-2th row, the sub-pixel in the 2b-1th column of the 4m-1th row, and the sub-pixel in the 2b-1th column of the 4m-1th row are electrically connected to the data line in the bth column;

[0043] The sub-pixel in the 2b-1th column of the 4mth row, the sub-pixel in the 2bth column of the 4mth row, the sub-pixel in the 2bth column of the 4m+1th row, and the sub-pixel in the 2b-1th column of the 4m+1th row are electrically connected to the data line in the b+1th column;

[0044] b is a positive integer.

[0045] Optionally, the sub-pixels in the odd-numbered columns of the first row are electrically connected to the scan lines in the second row, and the sub-pixels in the even-numbered columns of the first row are electrically connected to the scan lines in the first column;

[0046] The sub-pixel in the first row and the 2b-1th column and the sub-pixel in the first row and the 2bth column are both electrically connected to the data line in the b+1th column.

[0047] Optionally, the 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line;

[0048] The 8n-6th level driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-6th row scanning signal according to the second clock signal provided by the second clock signal line;

[0049] The 8n-5th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-5th row scanning signal according to the third clock signal provided by the third clock signal line;

[0050] The 8n-4th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-4th row scanning signal according to the fourth clock signal provided by the fourth clock signal line;

[0051] The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line;

[0052] The 8n-2-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-2-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line;

[0053] The 8n-1th stage driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-1th row scanning signal according to the seventh clock signal provided by the seventh clock signal line;

[0054] The 8n-th level driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-th row scanning signal according to the eighth clock signal provided by the eighth clock signal line;

[0055] n is a positive integer.

[0056] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned array substrate, and the driving method includes:

[0057] The sub-pixel receives the data voltage provided by the data line under the control of the scan signal provided by the scan line;

[0058] The driving module provides a scanning signal to the scanning line to control the existence of an overlapping time period and a non-overlapping time period between the effective time periods of the scanning signals provided by at least two scanning lines turned on in sequence within a display frame;

[0059] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0060] Optionally, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3a column have a third color; a is a positive integer; the sub-pixels in the odd-numbered columns of the 4m-3th row are electrically connected to the scan lines in the 8m-7th row, and the sub-pixels in the even-numbered columns of the 4m-3th row are electrically connected to the scan lines in the 8m-6th row; the sub-pixels in the odd-numbered columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even-numbered columns of the 4m-2th row are electrically connected to the scan lines in the 8m-5th row; the sub-pixels in the odd-numbered columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row, and the sub-pixels in the even-numbered columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row. The scan lines are electrically connected; the odd-numbered column subpixels in the 4mth row are electrically connected to the 8m-1th row scan line, and the even-numbered column subpixels in the 4mth row are electrically connected to the 8mth row scan line; a and m are positive integers; the 2b-1th column subpixel in the 4m-3th row, the 2b-1th column subpixel in the 4m-2th row, the 2b-3th column subpixel in the 4m-3th row, and the 2b-2th column subpixel in the 4m-2th row are electrically connected to the bth column data line; the 2b-1th column subpixel in the 4m-1th row, the 2b-1th column subpixel in the 4m-1th row, the 2b-1th column subpixel in the 4m-1th row, and the 2b-1th column subpixel in the 4mth row are all electrically connected to the b+1th column data line; b is a positive integer;

[0061] The driving method comprises:

[0062] The driving module controls the 8n-7th row scanning line and the 8n-4th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-7th row scanning signal and the effective time periods of the 8n-4th row scanning signal;

[0063] The driving module controls the 8n-6th row scanning line and the 8n-5th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-6th row scanning signal and the effective time periods of the 8n-5th row scanning signal;

[0064] The driving module controls the 8n-3rd row scanning line and the 8nth row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-3rd row scanning signal and the effective time periods of the 8nth row scanning signal;

[0065] The driving module controls the 8n-2th row scanning line and the 8n-1th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-2th row scanning signal and the effective time periods of the 8n-1th row scanning signal;

[0066] n is a positive integer.

[0067] Optionally, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer; the sub-pixels in the odd-numbered columns of the 4m-2th row are electrically connected to the scan line in the 8m-4th row, and the sub-pixels in the even-numbered columns of the 4m-2th row are electrically connected to the scan line in the 8m-3th row; the sub-pixels in the odd-numbered columns of the 4m-1th row are electrically connected to the scan line in the 8m-3th row, and the sub-pixels in the even-numbered columns of the 4m-1th row are electrically connected to the scan line in the 8m-2th row; the sub-pixels in the odd-numbered columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even-numbered columns of the 4mth row are electrically connected to the scan line in the 8mth row The 4m+1th row odd column sub-pixel is electrically connected to the 8m+2th row scan line, and the 4m+1th even column sub-pixel is electrically connected to the 8m+1th row scan line; a and m are positive integers; the 4m-2th row 2b-1th column sub-pixel, the 4m-2th row 2bth column sub-pixel, the 4m-1th row 2b-1th column sub-pixel and the 4m-1th row 2bth column sub-pixel are electrically connected to the bth column data line; the 4mth row 2b-1th column sub-pixel, the 4mth row 2bth column sub-pixel, the 4m+1th row 2b-1th column sub-pixel and the 4m+1th row 2bth column sub-pixel are electrically connected to the b+1th column data line; b is a positive integer;

[0068] The driving method comprises:

[0069] The driving module controls the 8n-6th row scanning line and the 8n-5th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-6th row scanning signal and the effective time periods of the 8n-5th row scanning signal;

[0070] The driving module controls the 8n-4th row scanning line and the 8n-3th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-4th row scanning signal and the effective time periods of the 8n-3th row scanning signal;

[0071] The driving module controls the 8n-2th row scanning line and the 8n-1th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-2th row scanning signal and the effective time periods of the 8n-1th row scanning signal;

[0072] The driving module controls the 8nth row of scanning lines and the 8n+1th row of scanning lines to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8nth row of scanning signals and the effective time periods of the 8n+1th row of scanning signals;

[0073] n is a positive integer.

[0074] Optionally, the odd-numbered column subpixels in the first row are electrically connected to the second-row scan line, and the even-numbered column subpixels in the first row are electrically connected to the first-column scan line; the 2b-1st column subpixel in the first row and the 2bth column subpixel in the first row are both electrically connected to the b+1th column data line; and the driving method further comprises:

[0075] The driving module controls the first row of scan lines to be turned on before the second row of scan lines is turned on, and there is no overlapping time period between the effective time period of the first row of scan signals and the effective time periods of other row of scan signals.

[0076] In a third aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned array substrate.

[0077] Compared with the prior art, the array substrate, driving method and display device described in the embodiments of the present invention can realize the HSR (Hardware Super Resulation) function of the pixel structure of the dual gate architecture, so as to reduce costs while improving the charging time of at least some sub-pixels, improve the charging rate and refresh rate, and improve the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0079] Figure 2 is a structural diagram of at least one embodiment of a driving module in an array substrate according to at least one embodiment of the present invention;

[0080] Figure 3 yes Figure 2 Working timing diagram of each signal in;

[0081] Figure 4 is a structural diagram of at least one embodiment of a driving module in an array substrate according to at least one embodiment of the present invention;

[0082] Figure 5 yes Figure 4 Working timing diagram of each signal in;

[0083] Figure 6 is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0084] Figure 7 is a structural diagram of at least one embodiment of a driving module in an array substrate according to at least one embodiment of the present invention;

[0085] Figure 8 yes Figure 7 The working timing diagram of each signal in . DETAILED DESCRIPTION

[0086] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0087] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0088] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0089] The array substrate of the embodiment of the present invention comprises a driving module, a plurality of scan lines extending along a first direction, a plurality of data lines extending along a second direction, and a plurality of pixels; the pixel comprises at least three sub-pixels with different colors; two scan lines are arranged between two adjacent rows of sub-pixels; two columns of sub-pixels are arranged between two columns of data lines; the sub-pixels are electrically connected to the scan lines and the data lines, respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines;

[0090] In the same row of sub-pixels, a plurality of sub-pixels electrically connected to the same data line have at least two colors;

[0091] In adjacent rows of sub-pixels, at least two sub-pixels electrically connected to the same data line have the same color;

[0092] The driving module is used to provide a scanning signal to the scanning line, so as to control the existence of an overlapping time period and a non-overlapping time period between the effective time periods of the scanning signals provided by at least two scanning lines turned on in sequence within a display frame;

[0093] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0094] In the array substrate described in the embodiment of the present invention, two scan lines are arranged between two adjacent rows of sub-pixels, two columns of sub-pixels are arranged between two columns of data lines, and in the same row of sub-pixels, a plurality of sub-pixels electrically connected to the same data line have at least two colors; in adjacent rows of sub-pixels, at least two sub-pixels electrically connected to the same data line have the same color; the driving module is used to provide a scan signal to the scan line to control the existence of an overlapping time period and a non-overlapping time period between the effective time periods of the scan signals provided by at least two sequentially turned-on scan lines within a display frame; the data voltage received by the data line at least part of the time in the overlapping time period is the same as the data voltage received by the data line at least part of the time in the non-overlapping time period. The embodiment of the present invention can realize the HSR (Hardware Super Resulation) function of the pixel structure of the dual gate architecture, so as to reduce the cost while improving the charging time of at least part of the sub-pixels, improve the charging rate and refresh rate, and improve the display quality.

[0095] In the related art, the pixel structure using the Dual Gate drive architecture has horizontal and vertical stripes image quality problems on large-size display products. The dual gate drive pixel structure used in the embodiment of the present invention improves the horizontal and vertical stripes image quality problems. At the same time, in order to improve the charging rate and meet high-resolution display, the HSR function is used.

[0096] The embodiment of the present invention can achieve 120Hz HSR mode output by adjusting the output of the driving circuit, and the image quality will not be sacrificed in the 60Hz mode, thereby achieving the goal of one screen for multiple uses, and the production cost will not increase, thereby reducing the cost of the display panel.

[0097] In at least one embodiment of the present invention, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer;

[0098] The sub-pixels in the odd columns of the 4m-3rd row are electrically connected to the scan lines in the 8m-7th row, and the sub-pixels in the even columns of the 4m-3rd row are electrically connected to the scan lines in the 8m-6th row;

[0099] The sub-pixels in the odd columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even columns of the 4m-2th row are electrically connected to the scan lines in the 8m-5th row;

[0100] The sub-pixels in the odd columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row, and the sub-pixels in the even columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row;

[0101] The sub-pixels in the odd columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even columns of the 4mth row are electrically connected to the scan line in the 8mth row;

[0102] a and m are positive integers.

[0103] Optionally, the sub-pixel in the 2b-1 column of the 4m-3th row, the sub-pixel in the 2b-1 column of the 4m-2th row, the sub-pixel in the 2b column of the 4m-3th row, and the sub-pixel in the 2b column of the 4m-2th row are electrically connected to the data line in the bth column;

[0104] The sub-pixel in the 2b-1th column of the 4m-1th row, the sub-pixel in the 2b ...th row, and the sub-pixel in the 2bth column of the 4mth row are all electrically connected to the data line in the b+1th

[0105] b is a positive integer.

[0106] In at least one embodiment of the present invention, the 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line;

[0107] The 8n-6th level driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-4th line scanning signal according to the second clock signal provided by the second clock signal line;

[0108] The 8n-5th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-6th line scanning signal according to the third clock signal provided by the third clock signal line;

[0109] The 8n-4th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-5th row scanning signal according to the fourth clock signal provided by the fourth clock signal line;

[0110] The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line;

[0111] The 8n-2-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line;

[0112] The 8n-1th stage driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-2th row scanning signal according to the seventh clock signal provided by the seventh clock signal line;

[0113] The 8n-th level driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-1-th row scanning signal according to the eighth clock signal provided by the eighth clock signal line;

[0114] n is a positive integer.

[0115] like Figure 1 As shown, the array substrate according to at least one embodiment of the present invention exemplarily includes a first row of scan lines G1, a second row of scan lines G2, a third row of scan lines G3, a fourth row of scan lines G4, a fifth row of scan lines G5, a sixth row of scan lines G6, a seventh row of scan lines G7, an eighth row of scan lines G8, a first column of data lines D1, a second column of data lines D2, a third column of data lines D3, a fourth column of data lines D4, a fifth column of data lines D5, a sixth column of data lines D6, and a seventh column of data lines D7;

[0116] The array substrate described in at least one embodiment of the present invention further includes a first row and first column red sub-pixel R11, a first row and second column green sub-pixel G12, a first row and third column blue sub-pixel B13, a first row and fourth column red sub-pixel R14, a first row and fifth column green sub-pixel G15, a first row and sixth column blue sub-pixel B16, a first row and seventh column red sub-pixel R17, a first row and eighth column green sub-pixel G18, a first row and ninth column blue sub-pixel B19, a first row and tenth column red sub-pixel R110, a first row and eleventh column green sub-pixel G111, a first row and tenth column green sub-pixel G112, a first row and tenth column green sub-pixel G113, a first row and tenth column green sub-pixel G114, a first row and tenth column green sub-pixel G115, a first row and tenth column green sub-pixel G116, a first row and tenth column green sub-pixel G117, a first row and tenth column green sub-pixel G118, a first row and tenth column green sub-pixel G119, a first row and tenth column green sub-pixel G110, a first row and tenth column green sub-pixel G111, a first row and tenth column green sub-pixel G112, a first row and tenth column green sub-pixel G113, a first row and tenth column green sub-pixel G114, a first row and tenth column green sub-pixel G115, a first row and tenth column green sub-pixel G116, a first row and tenth column green sub-pixel G117, a first row and tenth column green sub-pixel G118, a first row and tenth column green The blue sub-pixel B112 in the twelfth row, the red sub-pixel R21 in the first column of the second row, the green sub-pixel G22 in the second column of the second row, the blue sub-pixel B23 in the third column of the second row, the red sub-pixel R24 in the fourth column of the second row, the green sub-pixel G25 in the fifth column of the second row, the blue sub-pixel B26 in the sixth column of the second row, the red sub-pixel R27 in the seventh column of the second row, the green sub-pixel G28 in the eighth column of the second row, the blue sub-pixel B29 in the ninth column of the second row, the red sub-pixel R210 in the tenth row, the green sub-pixel G211 in the eleventh column of the second row, the blue sub-pixel B212 in the twelfth row The blue sub-pixel B212, the red sub-pixel R31 in the third row and the first column, the green sub-pixel G32 in the third row and the second column, the blue sub-pixel B33 in the third row and the third column, the red sub-pixel R34 in the third row and the fourth column, the green sub-pixel G35 in the third row and the fifth column, the blue sub-pixel B36 in the third row and the sixth column, the red sub-pixel R37 in the third row and the seventh column, the green sub-pixel G38 in the third row and the eighth column, the blue sub-pixel B39 in the third row and the ninth column, the red sub-pixel R310 in the third row and the green sub-pixel G311 in the third row and the twelfth column B312, the red sub-pixel R41 in the fourth row and the first column, the green sub-pixel G42 in the fourth row and the second column, the blue sub-pixel B43 in the fourth row and the third column, the red sub-pixel R44 in the fourth row and the fourth column, the green sub-pixel G45 in the fourth row and the fifth column, the blue sub-pixel B46 in the fourth row and the sixth column, the red sub-pixel R47 in the fourth row and the seventh column, the green sub-pixel G48 in the fourth row and the eighth column, the blue sub-pixel B49 in the fourth row and the ninth column, the red sub-pixel R410 in the fourth row and the tenth column, the green sub-pixel G411 in the fourth row and the blue sub-pixel B412 in the fourth row and the twelfth column;

[0117] R11 is electrically connected to G1 and D1 respectively, and G12 is electrically connected to G2 and D1 respectively;

[0118] B13 is electrically connected to G1 and D2, respectively, and R14 is electrically connected to G2 and D2, respectively;

[0119] G15 is electrically connected to G1 and D3, respectively, and B16 is electrically connected to G2 and D3, respectively;

[0120] R17 is electrically connected to G1 and D4, respectively, and G18 is electrically connected to G2 and D4, respectively;

[0121] B19 is electrically connected to G1 and D5, respectively, and R110 is electrically connected to G2 and D5, respectively;

[0122] G111 is electrically connected to G1 and D6, respectively, and B112 is electrically connected to G2 and D6, respectively;

[0123] R21 is electrically connected to G4 and D1, respectively, and G22 is electrically connected to G3 and D1, respectively;

[0124] B23 is electrically connected to G4 and D2, respectively, and R24 is electrically connected to G3 and D2, respectively;

[0125] G25 is electrically connected to G4 and D3, respectively, and B26 is electrically connected to G3 and D3, respectively;

[0126] R27 is electrically connected to G4 and D4, respectively, and G28 is electrically connected to G3 and D4, respectively;

[0127] B29 is electrically connected to G4 and D5, respectively, and R210 is electrically connected to G3 and D5, respectively;

[0128] G211 is electrically connected to G4 and D6, respectively, and B212 is electrically connected to G3 and D6, respectively;

[0129] R31 is electrically connected to G6 and D2, respectively, and G32 is electrically connected to G5 and D2, respectively;

[0130] B33 is electrically connected to G6 and D3, respectively, and R34 is electrically connected to G5 and D3, respectively;

[0131] G35 is electrically connected to G6 and D4, respectively, and B36 is electrically connected to G5 and D4, respectively;

[0132] R37 is electrically connected to G6 and D5, respectively, and G38 is electrically connected to G5 and D5, respectively;

[0133] B39 is electrically connected to G6 and D6, respectively, and R310 is electrically connected to G5 and D6, respectively;

[0134] G311 is electrically connected to G6 and D7, respectively, and B312 is electrically connected to G5 and D7, respectively;

[0135] R41 is electrically connected to G7 and D2, respectively, and G42 is electrically connected to G8 and D2, respectively;

[0136] B43 is electrically connected to G7 and D3, respectively, and R44 is electrically connected to G8 and D3, respectively;

[0137] G45 is electrically connected to G7 and D4, respectively, and B46 is electrically connected to G8 and D4, respectively;

[0138] R47 is electrically connected to G7 and D5, respectively, and G48 is electrically connected to G8 and D5, respectively;

[0139] B49 is electrically connected to G7 and D6, respectively, and R410 is electrically connected to G8 and D6, respectively;

[0140] G411 is electrically connected to G7 and D7, respectively, and R412 is electrically connected to G8 and D7, respectively.

[0141] like Figure 2 As shown, the driving module includes a first-level driving circuit GA1, a second-level driving circuit GA2, a third-level driving circuit GA3, a fourth-level driving circuit GA4, a fifth-level driving circuit GA5, a sixth-level driving circuit GA6, a seventh-level driving circuit GA7 and an eighth-level driving circuit GA8;

[0142] GA1 is electrically connected to the first clock signal line CLK1, and is used to generate a first row scanning signal according to a first clock signal provided by the first clock signal line CLK1, and provide the first row scanning signal to the first row scanning line G1;

[0143] GA2 is electrically connected to the second clock signal line CLK2, and is used to generate a fourth row scan signal according to the second clock signal provided by the second clock signal line CLK2, and provide the fourth row scan signal to the fourth row scan line G4;

[0144] GA3 is electrically connected to the third clock signal line CLK3, and is used to generate a second row scan signal according to a third clock signal provided by the third clock signal line CLK3, and provide the second row scan signal to the second row scan line G2;

[0145] GA4 is electrically connected to the fourth clock signal line CLK4, and is used to generate a third row scan signal according to a fourth clock signal provided by the fourth clock signal line CLK4, and provide the third row scan signal to the third row scan line G3;

[0146] GA5 is electrically connected to the fifth clock signal line CLK5, and is used to generate a fifth row scan signal according to a fifth clock signal provided by the fifth clock signal line CLK5, and provide the fifth row scan signal to the fifth row scan line G5;

[0147] GA6 is electrically connected to the sixth clock signal line CLK6, and is used to generate an eighth row scan signal according to the sixth clock signal provided by the sixth clock signal line CLK6, and provide the eighth row scan signal to the eighth row scan line G8;

[0148] GA7 is electrically connected to the seventh clock signal line CLK7, and is used to generate a sixth row scan signal according to the seventh clock signal provided by the seventh clock signal line CLK7, and provide the sixth row scan signal to the sixth row scan line G6;

[0149] GA8 is electrically connected to the eighth clock signal line CLK8, and is used for generating a seventh row scan signal according to the eighth clock signal provided by the eighth clock signal line CLK8, and providing the seventh row scan signal to the seventh row scan line G7.

[0150] like Figure 2 As shown, there is a signal crossover between the driving signal output end of the driving circuit in the driving module and the scanning line in the display panel, so as to achieve signal line insulation at the crossover position.

[0151] Figure 2 At least one embodiment of the driving module shown is Figure 1 The pixel structure shown provides a scanning signal;

[0152] Figure 3 yes Figure 2 The working timing diagram of each signal in .

[0153] exist Figure 3 Among them, the signal labeled STV is the start signal of G1 access;

[0154] like Figure 3 As shown, the duty cycle of the first clock signal, the duty cycle of the second clock signal, the duty cycle of the third clock signal, the duty cycle of the fourth clock signal, the duty cycle of the fifth clock signal, the duty cycle of the sixth clock signal, the duty cycle of the seventh clock signal and the duty cycle of the eighth clock signal are all 1 / 2;

[0155] The period of the first clock signal, the period of the second clock signal, the period of the third clock signal, the period of the fourth clock signal, the period of the fifth clock signal, the period of the sixth clock signal, the period of the seventh clock signal and the period of the eighth clock signal are all T, that is, the adjacent high level and low level of the clock signal are one period;

[0156] The second clock signal is delayed by T / 8 compared to the first clock signal, the third clock signal is delayed by T / 8 compared to the second clock signal, the fourth clock signal is delayed by T / 8 compared to the third clock signal, the fifth clock signal is delayed by T / 8 compared to the fourth clock signal, the sixth clock signal is delayed by T / 8 compared to the fifth clock signal, the seventh clock signal is delayed by T / 8 compared to the sixth clock signal, and the eighth clock signal is delayed by T / 8 compared to the seventh clock signal.

[0157] Figure 3When at least one embodiment of the driving module shown is in operation, the clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8 are sequentially turned on, and G1, G4, G2, G3, G5, G8, G6, and G7 are sequentially turned on;

[0158] There is a first overlapping time period J1 and a first non-overlapping time period N1 between the effective time period of the first row scanning signal provided by G1 and the effective time period of the fourth row scanning signal provided by G4; it should be noted that the effective time period in this case refers to if the transistor electrically connected to the pixel electrode included in the display area of ​​the display panel is an N-type transistor, then the effective time period refers to the timing is a high level; if the transistor electrically connected to the pixel electrode included in the display area of ​​the display panel is a P-type transistor, then the effective time period refers to the timing is a low level; this case only uses a high level as an illustration of the effective level, but is not limited to this.

[0159] There is a second overlapping time period J2 and a second non-overlapping time period N2 between the effective time period of the second row scanning signal provided by G2 and the effective time period of the third row scanning signal provided by G3;

[0160] There is a third overlapping time period J3 and a third non-overlapping time period N3 between the effective time period of the fifth row scanning signal provided by G5 and the effective time period of the eighth row scanning signal provided by G8;

[0161] There is a fourth overlapping time period J4 and a fourth non-overlapping time period N4 between the effective time period of the sixth row scanning signal provided by G6 and the effective time period of the seventh row scanning signal provided by G7;

[0162] The data voltage received by each of the data lines during at least a portion of the first overlapping period J1 is the same as the data voltage received by the data line during at least a portion of the first non-overlapping period N1;

[0163] The data voltage received by each of the data lines during at least a portion of the second overlapping period J2 is the same as the data voltage received by the data line during at least a portion of the second non-overlapping period N2;

[0164] The data voltage received by each of the data lines during at least a portion of the third overlapping period J3 is the same as the data voltage received by the data line during at least a portion of the third non-overlapping period N3;

[0165] The data voltage received by each of the data lines during at least a portion of the fourth overlapping period J4 is the same as the data voltage received by the data line during at least a portion of the fourth non-overlapping period N4.

[0166] Optionally, the data voltages received in the overlapping time periods and the non-overlapping time periods are the same, for example, the data voltage received in the first overlapping time period J1 is the same as the data voltage received in the first non-overlapping time period N1; the data voltage received in the second overlapping time period J2 is the same as the data voltage received in the second non-overlapping time period N2; the data voltage received in the third overlapping time period J3 is the same as the data voltage received in the third non-overlapping time period N3, and so on. They are not elaborated here.

[0167] like Figure 3 As shown, optionally, the charging time of the sub-pixel controlled by G1 is 1H (one row charging time), J1=1H, the charging time of the sub-pixel controlled by G4 is 2H, J1+N1=2H, the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G1 being 1H is the same as the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G4 being 2H, the charging time of the sub-pixel controlled by G2 is 1H, the charging time of the sub-pixel controlled by G3 is 2H, the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G2 being 1H is the same as the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G3 being 2H. The data signals charged into the pixels are the same, the charging time of the sub-pixels controlled by G5 is 1H (one row charging time), the charging time of the sub-pixels controlled by G8 is 2H, the data signals charged into the pixels when the charging time of the sub-pixels controlled by G51 is 1H is the same as the data signals charged into the pixels when the charging time of the sub-pixels controlled by G8 is 2H, the charging time of the sub-pixels controlled by G6 is 1H, the charging time of the sub-pixels controlled by G7 is 2H, the data signals charged into the pixels when the charging time of the sub-pixels controlled by G6 is 1H is the same as the data signals charged into the pixels when the charging time of the sub-pixels controlled by G7 is 2H.

[0168] In at least one embodiment of the present invention, the 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line;

[0169] The 8n-6th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-6th line scanning signal according to the third clock signal provided by the third clock signal line;

[0170] The 8n-5th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-5th row scanning signal according to the fourth clock signal provided by the fourth clock signal line;

[0171] The 8n-4th stage driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-4th row scanning signal according to the second clock signal provided by the second clock signal line;

[0172] The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line;

[0173] The 8n-2-th level driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-2-th row scanning signal according to the seventh clock signal provided by the seventh clock signal line;

[0174] The 8n-1th stage driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-1th row scanning signal according to the eighth clock signal provided by the eighth clock signal line;

[0175] The 8n-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line;

[0176] n is a positive integer.

[0177] like Figure 4 As shown, the driving module includes a first-level driving circuit GA1, a second-level driving circuit GA2, a third-level driving circuit GA3, a fourth-level driving circuit GA4, a fifth-level driving circuit GA5, a sixth-level driving circuit GA6, a seventh-level driving circuit GA7 and an eighth-level driving circuit GA8;

[0178] Figure 4 At least one embodiment of the driving module shown is Figure 1 The pixel structure shown provides a scanning signal;

[0179] GA1 is electrically connected to the first clock signal line CLK1, and is used to generate a first row scanning signal according to a first clock signal provided by the first clock signal line CLK1, and provide the first row scanning signal to the first row scanning line G1;

[0180] GA2 is electrically connected to the third clock signal line CLK3, and is used to generate a second row scan signal according to a third clock signal provided by the third clock signal line CLK3, and provide the second row scan signal to the second row scan line G2;

[0181] GA3 is electrically connected to the fourth clock signal line CLK4, and is used to generate a third row scan signal according to a fourth clock signal provided by the fourth clock signal line CLK4, and provide the third row scan signal to the third row scan line G3;

[0182] GA4 is electrically connected to the second clock signal line CLK2, and is used for generating a fourth row scanning signal according to the second clock signal provided by the second clock signal line CLK2, and providing the fourth row scanning signal to the fourth row scanning line G4;

[0183] GA5 is electrically connected to the fifth clock signal line CLK5, and is used to generate a fifth row scan signal according to a fifth clock signal provided by the fifth clock signal line CLK5, and provide the fifth row scan signal to the fifth row scan line G5;

[0184] GA6 is electrically connected to the seventh clock signal line CLK7, and is used to generate a sixth row scan signal according to the seventh clock signal provided by the seventh clock signal line CLK7, and provide the sixth row scan signal to the sixth row scan line G6;

[0185] GA7 is electrically connected to the eighth clock signal line CLK8, and is used to generate a seventh row scan signal according to the eighth clock signal provided by the eighth clock signal line CLK8, and provide the seventh row scan signal to the seventh row scan line G7;

[0186] GA8 is electrically connected to the sixth clock signal line CLK6, and is used for generating a sixth row scan signal according to a sixth clock signal provided by the sixth clock signal line CLK6, and providing the sixth row scan signal to the eighth row scan line G8.

[0187] Figure 5 yes Figure 4 The working timing diagram of each signal in .

[0188] exist Figure 5 Among them, the signal labeled STV is the start signal of G1 access;

[0189] like Figure 5 As shown, the duty cycle of the first clock signal, the duty cycle of the second clock signal, the duty cycle of the third clock signal, the duty cycle of the fourth clock signal, the duty cycle of the fifth clock signal, the duty cycle of the sixth clock signal, the duty cycle of the seventh clock signal and the duty cycle of the eighth clock signal are all 1 / 2;

[0190] The period of the first clock signal, the period of the second clock signal, the period of the third clock signal, the period of the fourth clock signal, the period of the fifth clock signal, the period of the sixth clock signal, the period of the seventh clock signal and the period of the eighth clock signal are all T;

[0191] The second clock signal is delayed by T / 8 compared to the first clock signal, the third clock signal is delayed by T / 8 compared to the second clock signal, the fourth clock signal is delayed by T / 8 compared to the third clock signal, the fifth clock signal is delayed by T / 8 compared to the fourth clock signal, the sixth clock signal is delayed by T / 8 compared to the fifth clock signal, the seventh clock signal is delayed by T / 8 compared to the sixth clock signal, and the eighth clock signal is delayed by T / 8 compared to the seventh clock signal.

[0192] Figure 5 When at least one embodiment of the driving module shown is in operation, the clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8 are sequentially turned on, and G1, G4, G2, G3, G5, G8, G6, and G7 are sequentially turned on;

[0193] There is a first overlapping time period J1 and a first non-overlapping time period N1 between the effective time period of the first row scanning signal provided by G1 and the effective time period of the fourth row scanning signal provided by G4;

[0194] There is a second overlapping time period J2 and a second non-overlapping time period N2 between the effective time period of the second row scanning signal provided by G2 and the effective time period of the third row scanning signal provided by G3;

[0195] There is a third overlapping time period J3 and a third non-overlapping time period N3 between the effective time period of the fifth row scanning signal provided by G5 and the effective time period of the eighth row scanning signal provided by G8;

[0196] There is a fourth overlapping time period J4 and a fourth non-overlapping time period N4 between the effective time period of the sixth row scanning signal provided by G6 and the effective time period of the seventh row scanning signal provided by G7;

[0197] The data voltage received by each of the data lines during at least a portion of the first overlapping period J1 is the same as the data voltage received by the data line during at least a portion of the first non-overlapping period N1;

[0198] The data voltage received by each of the data lines during at least a portion of the second overlapping period J2 is the same as the data voltage received by the data line during at least a portion of the second non-overlapping period N2;

[0199] The data voltage received by each of the data lines during at least a portion of the third overlapping period J3 is the same as the data voltage received by the data line during at least a portion of the third non-overlapping period N3;

[0200] The data voltage received by each of the data lines during at least a portion of the fourth overlapping time period J4 is the same as the data voltage received by the data line during at least a portion of the fourth non-overlapping time period N4;

[0201] Optionally, the data voltages received in the overlapping time periods and the non-overlapping time periods are the same, for example, the data voltage received in the first overlapping time period J1 is the same as the data voltage received in the first non-overlapping time period N1; the data voltage received in the second overlapping time period J2 is the same as the data voltage received in the second non-overlapping time period N2; the data voltage received in the third overlapping time period J3 is the same as the data voltage received in the third non-overlapping time period N3, and so on. They are not elaborated here.

[0202] like Figure 5 As shown, optionally, the charging time of the sub-pixel controlled by G1 is 1H (one row charging time), the charging time of the sub-pixel controlled by G4 is 2H, and the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G1 is 1H and the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G4 is the same; the charging time of the sub-pixel controlled by G2 is 1H, and the charging time of the sub-pixel controlled by G3 is 2H, and the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G2 is 1H and the data signal charged into the pixel corresponding to the charging time of the sub-pixel controlled by G3 is 2H. The charging time of the sub-pixel controlled by G5 is 1H (one row charging time), and the charging time of the sub-pixel controlled by G8 is 2H. The data signal charged into the pixel when the charging time of the sub-pixel controlled by G5 is 1H is the same as the data signal charged into the pixel when the charging time of the sub-pixel controlled by G8 is 2H. The charging time of the sub-pixel controlled by G6 is 1H, and the charging time of the sub-pixel controlled by G7 is 2H. The data signal charged into the pixel when the charging time of the sub-pixel controlled by G6 is 1H is the same as the data signal charged into the pixel when the charging time of the sub-pixel controlled by G7 is 2H.

[0203] In at least one embodiment of the present invention, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer;

[0204] The sub-pixels in the odd columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even columns of the 4m-2th row are electrically connected to the scan lines in the 8m-3th column;

[0205] The sub-pixels in the odd columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row, and the sub-pixels in the even columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row;

[0206] The sub-pixels in the odd columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even columns of the 4mth row are electrically connected to the scan line in the 8mth row;

[0207] The 4m+1th row of odd-numbered columns of sub-pixels are electrically connected to the 8m+2th row of scan lines, and the 4m+1th row of even-numbered columns of sub-pixels are electrically connected to the 8m+1th row of scan lines;

[0208] a and m are positive integers.

[0209] Optionally, the sub-pixel in the 2b-1 column of the 4m-2th row, the sub-pixel in the 2b-2th column of the 4m-2th row, the sub-pixel in the 2b-1th column of the 4m-1th row, and the sub-pixel in the 2b-1th column of the 4m-1th row are electrically connected to the data line in the bth column;

[0210] The sub-pixel in the 2b-1th column of the 4mth row, the sub-pixel in the 2bth column of the 4mth row, the sub-pixel in the 2bth column of the 4m+1th row, and the sub-pixel in the 2b-1th column of the 4m+1th row are electrically connected to the data line in the b+1th column;

[0211] b is a positive integer.

[0212] Optionally, the sub-pixels in the odd-numbered columns of the first row are electrically connected to the scan lines in the second row, and the sub-pixels in the even-numbered columns of the first row are electrically connected to the scan lines in the first column;

[0213] The sub-pixel in the first row and the 2b-1th column and the sub-pixel in the first row and the 2bth column are both electrically connected to the data line in the b+1th column.

[0214] In at least one embodiment of the present invention, the 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line;

[0215] The 8n-6th level driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-6th row scanning signal according to the second clock signal provided by the second clock signal line;

[0216] The 8n-5th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-5th row scanning signal according to the third clock signal provided by the third clock signal line;

[0217] The 8n-4th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-4th row scanning signal according to the fourth clock signal provided by the fourth clock signal line;

[0218] The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line;

[0219] The 8n-2-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-2-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line;

[0220] The 8n-1th stage driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-1th row scanning signal according to the seventh clock signal provided by the seventh clock signal line;

[0221] The 8n-th level driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-th row scanning signal according to the eighth clock signal provided by the eighth clock signal line;

[0222] n is a positive integer.

[0223] like Figure 6 As shown, the array substrate described in at least one embodiment of the present invention includes a first row of scan lines G1, a second row of scan lines G2, a third row of scan lines G3, a fourth row of scan lines G4, a fifth row of scan lines G5, a sixth row of scan lines G6, a seventh row of scan lines G7, an eighth row of scan lines G8, a ninth row of scan lines G9, a tenth row of scan lines G10, a first column of data lines D1, a second column of data lines D2, a third column of data lines D3, a fourth column of data lines D4, a fifth column of data lines D5, a sixth column of data lines D6, and a seventh column of data lines D7;

[0224] The array substrate described in at least one embodiment of the present invention further includes a first row and first column red sub-pixel R11, a first row and second column green sub-pixel G12, a first row and third column blue sub-pixel B13, a first row and fourth column red sub-pixel R14, a first row and fifth column green sub-pixel G15, a first row and sixth column blue sub-pixel B16, a first row and seventh column red sub-pixel R17, a first row and eighth column green sub-pixel G18, a first row and ninth column blue sub-pixel B19, a first row and tenth column red sub-pixel R110, a first row and eleventh column green sub-pixel G111, a first row and twelfth column blue sub-pixel B112, a second row and first column red sub-pixel R21, a second row and second column green sub-pixel G22, a second row and second column red sub-pixel R30, a first row and second column green sub-pixel G31, a first row and second column green sub-pixel G32, a first row and second column green sub-pixel G33, a first row and second column green sub-pixel G34, a first row and second column green sub-pixel G35, a first row and second column green sub-pixel G36, a first row and second column green sub-pixel G37, a first row and second column green sub-pixel G38, a first row and second column green sub-pixel G39, a first row and first column red sub-pixel R40, a first row and first column green sub-pixel G41, a first row and second column green sub-pixel G42, a first row and second column green sub-pixel G43, a first row and second column green sub-pixel G44, a first row and second column green sub-pixel G45, a first row and second The blue sub-pixel B23 in the third row, the red sub-pixel R24 in the fourth row, the green sub-pixel G25 in the fifth row, the blue sub-pixel B26 in the sixth row, the red sub-pixel R27 in the seventh row, the green sub-pixel G28 in the eighth row, the blue sub-pixel B29 in the ninth row, the red sub-pixel R210 in the tenth row, the green sub-pixel G211 in the eleventh row, the blue sub-pixel B212 in the twelfth row, the red sub-pixel R31 in the first row, the green sub-pixel G32 in the second row, the blue sub-pixel B33 in the third row, the red sub-pixel R34 in the fourth row, the green sub-pixel G35 in the fifth row, the blue sub-pixel R36 in the sixth row, the red sub-pixel R37 in the seventh row, the green sub-pixel G38 in the eighth row, the blue sub-pixel B29 in the ninth row, the red sub-pixel R210 in the tenth row, the green sub-pixel G211 in the eleventh row, the blue sub-pixel B212 in the twelfth row, the red sub-pixel R31 in the first row, the green sub-pixel G32 in the second row, the blue sub-pixel B33 in the third row, the red sub-pixel R34 in the fourth row, the green sub-pixel G35 in the fifth row, the blue sub-pixel Sub-pixel B36, red sub-pixel R37 in the third row and seventh column, green sub-pixel G38 in the third row and eighth column, blue sub-pixel B39 in the third row and ninth column, red sub-pixel R310 in the third row and tenth column, green sub-pixel G311 in the third row and twelfth column, blue sub-pixel B312 in the third row and twelfth column, red sub-pixel R41 in the fourth row and first column, green sub-pixel G42 in the fourth row and second column, blue sub-pixel B43 in the fourth row and third column, red sub-pixel R44 in the fourth row and fourth column, green sub-pixel G45 in the fourth row and fifth column, blue sub-pixel B46 in the fourth row and sixth column, red sub-pixel R47 in the fourth row and seventh column, green sub-pixel G48 in the fourth row and eighth column, blue sub-pixel B49 in the fourth row and ninth column , the red sub-pixel R410 in the fourth row and the tenth column, the green sub-pixel G411 in the fourth row and the twelfth column, the blue sub-pixel B412 in the fourth row and the twelfth column, the red sub-pixel R51 in the fifth row and the first column, the green sub-pixel G52 in the fifth row and the second column, the blue sub-pixel B53 in the fifth row and the third column, the red sub-pixel R54 in the fifth row and the fourth column, the green sub-pixel G55 in the fifth row and the fifth column, the blue sub-pixel B56 in the fifth row and the sixth column, the red sub-pixel R57 in the fifth row and the seventh column, the green sub-pixel G58 in the fifth row and the blue sub-pixel B59 in the fifth row and the ninth column, the red sub-pixel R510 in the fifth row and the tenth column, the green sub-pixel G511 in the fifth row and the blue sub-pixel B512 in the fifth row and the twelfth column;

[0225] R11 is electrically connected to G2 and D2, respectively, and G12 is electrically connected to G1 and D2, respectively;

[0226] B13 is electrically connected to G2 and D3, respectively, and R14 is electrically connected to G1 and D3, respectively;

[0227] G15 is electrically connected to G2 and D4, respectively, and B16 is electrically connected to G1 and D4, respectively;

[0228] R17 is electrically connected to G2 and D5, respectively, and G18 is electrically connected to G1 and D5, respectively;

[0229] B19 is electrically connected to G2 and D6, respectively, and R110 is electrically connected to G1 and D6, respectively;

[0230] G111 is electrically connected to G2 and D7, respectively, and B112 is electrically connected to G1 and D7, respectively;

[0231] R21 is electrically connected to G4 and D1, respectively, and G22 is electrically connected to G3 and D1, respectively;

[0232] B23 is electrically connected to G4 and D2, respectively, and R24 is electrically connected to G3 and D2, respectively;

[0233] G25 is electrically connected to G4 and D3, respectively, and B26 is electrically connected to G3 and D3, respectively;

[0234] R27 is electrically connected to G4 and D4, respectively, and G28 is electrically connected to G3 and D4, respectively;

[0235] B29 is electrically connected to G4 and D5, respectively, and R210 is electrically connected to G3 and D5, respectively;

[0236] G211 is electrically connected to G4 and D6, respectively, and B212 is electrically connected to G3 and D6, respectively;

[0237] R31 is electrically connected to G5 and D1, respectively, and G32 is electrically connected to G6 and D1, respectively;

[0238] B33 is electrically connected to G5 and D2, respectively, and R34 is electrically connected to G6 and D2, respectively;

[0239] G35 is electrically connected to G5 and D3, respectively, and B36 is electrically connected to G6 and D3, respectively;

[0240] R37 is electrically connected to G5 and D4, respectively, and G38 is electrically connected to G6 and D4, respectively;

[0241] B39 is electrically connected to G5 and D5, respectively, and R310 is electrically connected to G6 and D5, respectively;

[0242] G311 is electrically connected to G5 and D6, respectively, and B312 is electrically connected to G6 and D6, respectively;

[0243] R41 is electrically connected to G7 and D2, respectively, and G42 is electrically connected to G8 and D2, respectively;

[0244] B43 is electrically connected to G7 and D3, respectively, and R44 is electrically connected to G8 and D3, respectively;

[0245] G45 is electrically connected to G7 and D4, respectively, and B46 is electrically connected to G8 and D4, respectively;

[0246] R47 is electrically connected to G7 and D5, respectively, and G48 is electrically connected to G8 and D5, respectively;

[0247] B49 is electrically connected to G7 and D6, respectively, and R410 is electrically connected to G8 and D6, respectively;

[0248] G411 is electrically connected to G7 and D7, respectively, and R412 is electrically connected to G8 and D7, respectively;

[0249] R51 is electrically connected to G10 and D2, respectively, and G52 is electrically connected to G9 and D2, respectively;

[0250] B53 is electrically connected to G10 and D3, respectively, and R54 is electrically connected to G9 and D3, respectively;

[0251] G55 is electrically connected to G10 and D4, respectively, and B56 is electrically connected to G10 and D4, respectively;

[0252] R57 is electrically connected to G10 and D5, respectively, and G58 is electrically connected to G9 and D5, respectively;

[0253] B59 is electrically connected to G10 and D6, respectively, and R510 is electrically connected to G9 and D6, respectively;

[0254] G511 is electrically connected to G10 and D7 respectively, and R512 is electrically connected to G9 and D7 respectively.

[0255] like Figure 7 As shown, the driving module includes a first-level driving circuit GA1, a second-level driving circuit GA2, a third-level driving circuit GA3, a fourth-level driving circuit GA4, a fifth-level driving circuit GA5, a sixth-level driving circuit GA6, a seventh-level driving circuit GA7 and an eighth-level driving circuit GA8;

[0256] Figure 7 At least one embodiment of the driving module shown is Figure 6 The pixel structure shown provides a scanning signal;

[0257] GA1 is electrically connected to the first clock signal line CLK1, and is used to generate a first row scanning signal according to a first clock signal provided by the first clock signal line CLK1, and provide the first row scanning signal to the first row scanning line G1;

[0258] GA2 is electrically connected to the second clock signal line CLK2, and is used to generate a second row scan signal according to a second clock signal provided by the second clock signal line CLK2, and provide the second row scan signal to the second row scan line G2;

[0259] GA3 is electrically connected to the third clock signal line CLK3, and is used to generate a third row scan signal according to a third clock signal provided by the third clock signal line CLK3, and provide the third row scan signal to the third row scan line G3;

[0260] GA4 is electrically connected to the fourth clock signal line CLK4, and is used for generating a fourth row scanning signal according to a fourth clock signal provided by the fourth clock signal line CLK4, and providing the fourth row scanning signal to the fourth row scanning line G4;

[0261] GA5 is electrically connected to the fifth clock signal line CLK5, and is used to generate a fifth row scan signal according to a fifth clock signal provided by the fifth clock signal line CLK5, and provide the fifth row scan signal to the fifth row scan line G5;

[0262] GA6 is electrically connected to the sixth clock signal line CLK6, and is used to generate a sixth row scan signal according to a sixth clock signal provided by the sixth clock signal line CLK6, and provide the sixth row scan signal to the sixth row scan line G6;

[0263] GA7 is electrically connected to the seventh clock signal line CLK7, and is used to generate a seventh row scan signal according to the seventh clock signal provided by the seventh clock signal line CLK7, and provide the seventh row scan signal to the seventh row scan line G7;

[0264] GA8 is electrically connected to the eighth clock signal line CLK8, and is used for generating an eighth row scan signal according to the eighth clock signal provided by the eighth clock signal line CLK8, and providing the eighth row scan signal to the eighth row scan line G8.

[0265] Figure 8 yes Figure 7 The working timing diagram of each signal in .

[0266] exist Figure 8 Among them, the signal labeled STV is the start signal of G1 access;

[0267] like Figure 8 As shown, the duty cycle of the first clock signal, the duty cycle of the second clock signal, the duty cycle of the third clock signal, the duty cycle of the fourth clock signal, the duty cycle of the fifth clock signal, the duty cycle of the sixth clock signal, the duty cycle of the seventh clock signal and the duty cycle of the eighth clock signal are all 1 / 2;

[0268] The period of the first clock signal, the period of the second clock signal, the period of the third clock signal, the period of the fourth clock signal, the period of the fifth clock signal, the period of the sixth clock signal, the period of the seventh clock signal and the period of the eighth clock signal are all T;

[0269] The second clock signal is delayed by T / 8 compared to the first clock signal, the third clock signal is delayed by T / 8 compared to the second clock signal, the fourth clock signal is delayed by T / 8 compared to the third clock signal, the fifth clock signal is delayed by T / 8 compared to the fourth clock signal, the sixth clock signal is delayed by T / 8 compared to the fifth clock signal, the seventh clock signal is delayed by T / 8 compared to the sixth clock signal, and the eighth clock signal is delayed by T / 8 compared to the seventh clock signal.

[0270] Figure 8 In at least one embodiment of the driving module shown, when working, G1, G2, G3, G4, G5, G6, G7 and G8 are opened in sequence;

[0271] There is a first overlapping time period J1 and a first non-overlapping time period N1 between the effective time period of the second row scanning signal provided by G2 and the effective time period of the third row scanning signal provided by G3;

[0272] There is a second overlapping time period J2 and a second non-overlapping time period N2 between the effective time period of the fourth row scanning signal provided by G4 and the effective time period of the fifth row scanning signal provided by G5;

[0273] There is a third overlapping time period J3 and a third non-overlapping time period N3 between the effective time period of the sixth row scanning signal provided by G6 and the effective time period of the seventh row scanning signal provided by G7;

[0274] The data voltage received by each of the data lines during at least a portion of the first overlapping period J1 is the same as the data voltage received by the data line during at least a portion of the first non-overlapping period N1;

[0275] The data voltage received by each of the data lines during at least a portion of the second overlapping period J2 is the same as the data voltage received by the data line during at least a portion of the second non-overlapping period N2;

[0276] The data voltage received by each of the data lines during at least a portion of the third overlapping period J3 is the same as the data voltage received by the data line during at least a portion of the third non-overlapping period N3.

[0277] Optionally, the data voltages received in the overlapping time periods and the non-overlapping time periods are the same, for example, the data voltage received in the first overlapping time period J1 is the same as the data voltage received in the first non-overlapping time period N1; the data voltage received in the second overlapping time period J2 is the same as the data voltage received in the second non-overlapping time period N2; the data voltage received in the third overlapping time period J3 is the same as the data voltage received in the third non-overlapping time period N3, and so on. They are not elaborated here.

[0278] The present invention Figure 7 In at least one embodiment shown, when the HSR mode is not turned on for the first row of sub-pixels, the charging time of the first row of sub-pixels can be 1H, that is, the charging time of the sub-pixels electrically connected to the G1 gate line through the transistor is 1H, but the present invention is not limited thereto. In a specific implementation, the charging time of the first row of sub-pixels can also be 2H.

[0279] The present invention Figure 7 In at least one embodiment shown, when in operation, sub-pixels in other rows except the first row of sub-pixels turn on the HSR mode.

[0280] like Figure 8 As shown, the charging time of the sub-pixel controlled by G1 is 1H (one row charging time), the charging time of the sub-pixel controlled by G2 is 1H, and the charging time of the sub-pixel controlled by G3 is 2H. The data signal charged into the pixel when the charging time of the sub-pixel controlled by G2 is 1H is the same as the data signal charged into the pixel when the charging time of the sub-pixel controlled by G3 is 2H. The charging time of the sub-pixel controlled by G4 is 1H, and the charging time of the sub-pixel controlled by G5 is 2H (one row charging time). The data signal charged into the pixel when the charging time of the sub-pixel controlled by G4 is 1H is the same as the data signal charged into the pixel when the charging time of the sub-pixel controlled by G5 is 2H. The charging time of the sub-pixel controlled by G6 is 1H, and the charging time of the sub-pixel controlled by G7 is 2H. The charging time of the sub-pixel controlled by G8 is 1H, and the data signal charged into the pixel when the charging time of the sub-pixel controlled by G6 is 1H is the same as the data signal charged into the pixel when the charging time of the sub-pixel controlled by G7 is 2H.

[0281] The driving method described in the embodiment of the present invention is applied to the above-mentioned array substrate, and is characterized in that the driving method comprises:

[0282] The sub-pixel receives the data voltage provided by the data line under the control of the scan signal provided by the scan line;

[0283] The driving module provides a scanning signal to the scanning line to control the existence of an overlapping time period and a non-overlapping time period between the effective time periods of the scanning signals provided by at least two scanning lines turned on in sequence within a display frame;

[0284] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0285] In at least one embodiment of the present invention, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3a column have a third color; a is a positive integer; the sub-pixels in the odd-numbered columns of the 4m-3th row are electrically connected to the scan lines in the 8m-7th row, and the sub-pixels in the even-numbered columns of the 4m-3th row are electrically connected to the scan lines in the 8m-6th row; the sub-pixels in the odd-numbered columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even-numbered columns of the 4m-2th row are electrically connected to the scan lines in the 8m-5th row; the sub-pixels in the odd-numbered columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row, and the sub-pixels in the even-numbered columns of the 4m-1th row are electrically connected to the scan lines in the 8m- The m-3 row scan line is electrically connected; the odd-numbered column subpixels in the 4m-th row are electrically connected to the 8m-1 row scan line, and the even-numbered column subpixels in the 4m-th row are electrically connected to the 8m-row scan line; a and m are positive integers; the 2b-1 column subpixel in the 4m-3 row, the 2b-1 column subpixel in the 4m-2 row, the 2b column subpixel in the 4m-3 row, and the 2b column subpixel in the 4m-2 row are electrically connected to the b-th column data line; the 2b-1 column subpixel in the 4m-1 row, the 2b column subpixel in the 4m-1 row, the 2b-1 column subpixel in the 4m-th row, and the 2b column subpixel in the 4m-2 row are all electrically connected to the b+1-th column data line; b is a positive integer;

[0286] The driving method comprises:

[0287] The driving module controls the 8n-7th row scanning line and the 8n-4th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-7th row scanning signal and the effective time periods of the 8n-4th row scanning signal;

[0288] The driving module controls the 8n-6th row scanning line and the 8n-5th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-6th row scanning signal and the effective time periods of the 8n-5th row scanning signal;

[0289] The driving module controls the 8n-3rd row scanning line and the 8nth row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-3rd row scanning signal and the effective time periods of the 8nth row scanning signal;

[0290] The driving module controls the 8n-2th row scanning line and the 8n-1th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-2th row scanning signal and the effective time periods of the 8n-1th row scanning signal;

[0291] n is a positive integer.

[0292] In at least one embodiment of the present invention, the sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3a column have a third color; a is a positive integer; the sub-pixels in the odd-numbered columns of the 4m-2th row are electrically connected to the scan line in the 8m-4th row, and the sub-pixels in the even-numbered columns of the 4m-2th row are electrically connected to the scan line in the 8m-3th row; the sub-pixels in the odd-numbered columns of the 4m-1th row are electrically connected to the scan line in the 8m-3th row, and the sub-pixels in the even-numbered columns of the 4m-1th row are electrically connected to the scan line in the 8m-2th row; the sub-pixels in the odd-numbered columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even-numbered columns of the 4mth row are electrically connected to the scan line in the 8m- The 4m+1th row odd column sub-pixel is electrically connected to the 8m+2th row scan line, and the 4m+1th even column sub-pixel is electrically connected to the 8m+1th row scan line; a and m are positive integers; the 4m-2th row 2b-1th column sub-pixel, the 4m-2th row 2b column sub-display, the 4m-1th row 2b-1th column sub-pixel and the 4m-1th row 2b column sub-pixel are electrically connected to the bth column data line; the 4mth row 2b-1th column sub-pixel, the 4mth row 2b column sub-pixel, the 4m+1th row 2b-1th column sub-pixel and the 4m+1th row 2b column sub-display are electrically connected to the b+1th column data line; b is a positive integer;

[0293] The driving method comprises:

[0294] The driving module controls the 8n-6th row scanning line and the 8n-5th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-6th row scanning signal and the effective time periods of the 8n-5th row scanning signal;

[0295] The driving module controls the 8n-4th row scanning line and the 8n-3th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-4th row scanning signal and the effective time periods of the 8n-3th row scanning signal;

[0296] The driving module controls the 8n-2th row scanning line and the 8n-1th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-2th row scanning signal and the effective time periods of the 8n-1th row scanning signal;

[0297] The driving module controls the 8nth row of scanning lines and the 8n+1th row of scanning lines to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8nth row of scanning signals and the effective time periods of the 8n+1th row of scanning signals;

[0298] n is a positive integer.

[0299] Optionally, the odd-numbered column subpixels in the first row are electrically connected to the second-row scan line, and the even-numbered column subpixels in the first row are electrically connected to the first-column scan line; the 2b-1st column subpixel in the first row and the 2bth column subpixel in the first row are both electrically connected to the b+1th column data line; and the driving method further comprises:

[0300] The driving module controls the first row of scan lines to be turned on before the second row of scan lines is turned on, and there is no overlapping time period between the effective time period of the first row of scan signals and the effective time periods of other row of scan signals.

[0301] The display device described in the embodiment of the present invention is characterized by comprising the above-mentioned array substrate.

[0302] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: The invention comprises a driving module, a plurality of scan lines extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels; the pixels comprise at least three sub-pixels with different colors; two scan lines are arranged between two adjacent rows of sub-pixels; two columns of sub-pixels are arranged between two columns of data lines; the sub-pixels are electrically connected to the scan lines and the data lines, respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines; In the same row of sub-pixels, a plurality of sub-pixels electrically connected to the same data line have at least two colors; In adjacent rows of sub-pixels, at least two sub-pixels electrically connected to the same data line have the same color; The driving module is used to provide a scanning signal to the scanning line, so as to control the existence of an overlapping time period and a non-overlapping time period between the effective time periods of the scanning signals provided by at least two scanning lines turned on in sequence within a display frame; The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

2. The array substrate according to claim 1, characterized in that: The sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer; The sub-pixels in the odd columns of the 4m-3rd row are electrically connected to the scan lines in the 8m-7th row, and the sub-pixels in the even columns of the 4m-3rd row are electrically connected to the scan lines in the 8m-6th row; The sub-pixels in the odd columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even columns of the 4m-2th row are electrically connected to the scan lines in the 8m-5th row; The sub-pixels in the odd columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row, and the sub-pixels in the even columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row; The sub-pixels in the odd columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even columns of the 4mth row are electrically connected to the scan line in the 8mth row; a and m are positive integers.

3. The array substrate according to claim 2, characterized in that: The sub-pixel in the 2b-1th column of the 4m-3th row, the sub-pixel in the 2b-1th column of the 4m-2th row, the sub-pixel in the 2b-2th column of the 4m-3th row, and the sub-pixel in the 2bth column of the 4m-2th row are electrically connected to the data line in the bth column; The sub-pixel in the 2b-1th column of the 4m-1th row, the sub-pixel in the 2b ...th row, and the sub-pixel in the 2bth column of the 4mth row are all electrically connected to the data line in the b+1th b is a positive integer.

4. The array substrate according to claim 3, characterized in that: The 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line; The 8n-6th level driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-4th line scanning signal according to the second clock signal provided by the second clock signal line; The 8n-5th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-6th line scanning signal according to the third clock signal provided by the third clock signal line; The 8n-4th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-5th row scanning signal according to the fourth clock signal provided by the fourth clock signal line; The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line; The 8n-2-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line; The 8n-1th stage driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-2th row scanning signal according to the seventh clock signal provided by the seventh clock signal line; The 8n-th level driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-1-th row scanning signal according to the eighth clock signal provided by the eighth clock signal line; n is a positive integer.

5. The array substrate according to claim 3, characterized in that: The 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line; The 8n-6th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-6th line scanning signal according to the third clock signal provided by the third clock signal line; The 8n-5th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-5th row scanning signal according to the fourth clock signal provided by the fourth clock signal line; The 8n-4th stage driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-4th row scanning signal according to the second clock signal provided by the second clock signal line; The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line; The 8n-2-th level driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-2-th row scanning signal according to the seventh clock signal provided by the seventh clock signal line; The 8n-1th stage driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-1th row scanning signal according to the eighth clock signal provided by the eighth clock signal line; The 8n-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line; n is a positive integer.

6. The array substrate according to claim 1, characterized in that: The sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer; The sub-pixels in the odd columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even columns of the 4m-2th row are electrically connected to the scan lines in the 8m-3th column; The sub-pixels in the odd columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row, and the sub-pixels in the even columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row; The sub-pixels in the odd columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even columns of the 4mth row are electrically connected to the scan line in the 8mth row; The 4m+1th row of odd-numbered columns of sub-pixels are electrically connected to the 8m+2th row of scan lines, and the 4m+1th row of even-numbered columns of sub-pixels are electrically connected to the 8m+1th row of scan lines; a and m are positive integers.

7. The array substrate according to claim 6, characterized in that: The sub-pixel in the 4m-2th row and the 2b-1th column, the sub-pixel in the 4m-2th row and the 2bth column, the sub-pixel in the 4m-1th row and the 2b-1th column, and the sub-pixel in the 4m-1th row and the 2bth column are electrically connected to the data line in the bth column; The sub-pixel in the 2b-1th column of the 4mth row, the sub-pixel in the 2bth column of the 4mth row, the sub-pixel in the 2bth column of the 4m+1th row, and the sub-pixel in the 2b-1th column of the 4m+1th row are electrically connected to the data line in the b+1th column; b is a positive integer.

8. The array substrate according to claim 7, characterized in that: The first row of odd-numbered columns of sub-pixels are electrically connected to the second row of scan lines, and the first row of even-numbered columns of sub-pixels are electrically connected to the first column of scan lines; The sub-pixel in the first row and the 2b-1th column and the sub-pixel in the first row and the 2bth column are both electrically connected to the data line in the b+1th column.

9. The array substrate according to claim 8, characterized in that: The 8n-7th level driving circuit included in the driving module is electrically connected to the first clock signal line, and is used to generate the 8n-7th row scanning signal according to the first clock signal provided by the first clock signal line; The 8n-6th level driving circuit included in the driving module is electrically connected to the second clock signal line, and is used to generate the 8n-6th row scanning signal according to the second clock signal provided by the second clock signal line; The 8n-5th level driving circuit included in the driving module is electrically connected to the third clock signal line, and is used to generate the 8n-5th row scanning signal according to the third clock signal provided by the third clock signal line; The 8n-4th stage driving circuit included in the driving module is electrically connected to the fourth clock signal line, and is used to generate the 8n-4th row scanning signal according to the fourth clock signal provided by the fourth clock signal line; The 8n-3th stage driving circuit included in the driving module is electrically connected to the fifth clock signal line, and is used to generate the 8n-3th row scanning signal according to the fifth clock signal provided by the fifth clock signal line; The 8n-2-th level driving circuit included in the driving module is electrically connected to the sixth clock signal line, and is used to generate the 8n-2-th row scanning signal according to the sixth clock signal provided by the sixth clock signal line; The 8n-1th stage driving circuit included in the driving module is electrically connected to the seventh clock signal line, and is used to generate the 8n-1th row scanning signal according to the seventh clock signal provided by the seventh clock signal line; The 8n-th level driving circuit included in the driving module is electrically connected to the eighth clock signal line, and is used to generate the 8n-th row scanning signal according to the eighth clock signal provided by the eighth clock signal line; n is a positive integer.

10. A driving method, applied to the array substrate according to any one of claims 1 to 9, characterized in that: The driving method comprises: The sub-pixel receives the data voltage provided by the data line under the control of the scan signal provided by the scan line; The driving module provides a scanning signal to the scanning line to control the existence of an overlapping time period and a non-overlapping time period between the effective time periods of the scanning signals provided by at least two scanning lines turned on in sequence within a display frame; The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

11. The driving method according to claim 10, characterized in that: The sub-pixels in the 3a-2th column have the first color, the sub-pixels in the 3a-1th column have the second color, and the sub-pixels in the 3ath column have the third color; a is a positive integer; the sub-pixels in the odd-numbered columns of the 4m-3th row are electrically connected to the scan lines in the 8m-7th row, and the sub-pixels in the even-numbered columns of the 4m-3th row are electrically connected to the scan lines in the 8m-6th row; the sub-pixels in the odd-numbered columns of the 4m-2th row are electrically connected to the scan lines in the 8m-4th row, and the sub-pixels in the even-numbered columns of the 4m-2th row are electrically connected to the scan lines in the 8m-5th row; the sub-pixels in the odd-numbered columns of the 4m-1th row are electrically connected to the scan lines in the 8m-2th row, and the sub-pixels in the even-numbered columns of the 4m-1th row are electrically connected to the scan lines in the 8m-3th row. The odd-numbered column subpixel in the 4mth row is electrically connected to the 8m-1th row scan line, and the even-numbered column subpixel in the 4mth row is electrically connected to the 8mth row scan line; a and m are positive integers; the 2b-1th column subpixel in the 4m-3th row, the 2b-1th column subpixel in the 4m-2th row, the 2b-3th column subpixel and the 2b-2th column subpixel in the 4m-2th row are electrically connected to the bth column data line; the 2b-1th column subpixel in the 4m-1th row, the 2b-1th column subpixel in the 4m-1th row, the 2b-1th column subpixel in the 4m-1th row, and the 2b-1th column subpixel in the 4mth row are all electrically connected to the b+1th column data line; b is a positive integer; The driving method comprises: The driving module controls the 8n-7th row scanning line and the 8n-4th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-7th row scanning signal and the effective time periods of the 8n-4th row scanning signal; The driving module controls the 8n-6th row scanning line and the 8n-5th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-6th row scanning signal and the effective time periods of the 8n-5th row scanning signal; The driving module controls the 8n-3rd row scanning line and the 8nth row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-3rd row scanning signal and the effective time periods of the 8nth row scanning signal; The driving module controls the 8n-2th row scanning line and the 8n-1th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-2th row scanning signal and the effective time periods of the 8n-1th row scanning signal; n is a positive integer.

12. The driving method according to claim 10, characterized in that: The sub-pixels in the 3a-2th column have a first color, the sub-pixels in the 3a-1th column have a second color, and the sub-pixels in the 3ath column have a third color; a is a positive integer; the sub-pixels in the odd-numbered columns of the 4m-2th row are electrically connected to the scan line in the 8m-4th row, and the sub-pixels in the even-numbered columns of the 4m-2th row are electrically connected to the scan line in the 8m-3th row; the sub-pixels in the odd-numbered columns of the 4m-1th row are electrically connected to the scan line in the 8m-3th row, and the sub-pixels in the even-numbered columns of the 4m-1th row are electrically connected to the scan line in the 8m-2th row; the sub-pixels in the odd-numbered columns of the 4mth row are electrically connected to the scan line in the 8m-1th row, and the sub-pixels in the even-numbered columns of the 4mth row are electrically connected to the scan line in the 8m-2th row; The odd-numbered column subpixels in the 4m+1th row are electrically connected to the 8m+2th row scan line, and the even-numbered column subpixels in the 4m+1th row are electrically connected to the 8m+1th row scan line; a and m are positive integers; the 2b-1th column subpixels in the 4m-2th row, the 2bth column subpixels in the 4m-2th row, the 2bth column subpixels in the 4m-1th row, the 2b-1th column subpixels in the 4m-1th row, and the 2bth column subpixels in the 4m-1th row are electrically connected to the bth column data line; the 2b-1th column subpixels in the 4mth row, the 2bth column subpixels in the 4mth row, the 2b-1th column subpixels in the 4m+1th row, and the 2bth column subpixels in the 4m+1th row are electrically connected to the b+1th column data line; b is a positive integer; The driving method comprises: The driving module controls the 8n-6th row scanning line and the 8n-5th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-6th row scanning signal and the effective time periods of the 8n-5th row scanning signal; The driving module controls the 8n-4th row scanning line and the 8n-3th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-4th row scanning signal and the effective time periods of the 8n-3th row scanning signal; The driving module controls the 8n-2th row scanning line and the 8n-1th row scanning line to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8n-2th row scanning signal and the effective time periods of the 8n-1th row scanning signal; The driving module controls the 8nth row of scanning lines and the 8n+1th row of scanning lines to be turned on in sequence, so as to control that within a subframe, there are overlapping time periods and non-overlapping time periods between the effective time periods of the 8nth row of scanning signals and the effective time periods of the 8n+1th row of scanning signals; n is a positive integer.

13. The driving method according to claim 12, characterized in that: The first row of odd-numbered columns of sub-pixels are electrically connected to the second row of scan lines, and the first row of even-numbered columns of sub-pixels are electrically connected to the first column of scan lines; The sub-pixel in the first row and the 2b-1 column and the sub-pixel in the first row and the 2b column are both electrically connected to the data line in the b+1 column; the driving method further includes: The driving module controls the first row of scan lines to be turned on before the second row of scan lines is turned on, and there is no overlapping time period between the effective time period of the first row of scan signals and the effective time periods of other row of scan signals.

14. A display device, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 9.

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