Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel comprises a driving circuit and a pixel circuit, the driving circuit provides a driving signal for the pixel circuit, and the pixel circuit provides a driving current for a light-emitting element of the display panel; a light emitting element including a first electrode and a second electrode; a first power supply signal bus and a second power supply signal bus, the first power supply signal bus is used for transmitting a first power supply signal V1, the second power supply bus is used for transmitting a second power supply signal V2, and V1 is not equal to V2; wherein the first power signal bus is connected to the pixel circuit, the pixel circuit is connected to the first electrode, and the second power signal bus is connected to the second electrode; the second power signal bus is at least partially overlapped with the driving circuit. According to the display panel, the problem that an existing display panel is large in frame is solved, and the narrow-frame design of the display panel is achieved.

Description

[0001] This application is a divisional application of a patent for display panel and display device, with application date of June 30, 2022, application number: 202210771371.4, and invention name: Technical Field

[0002] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the development of display technology, display panels with narrow borders and high screen-to-body ratio are becoming more and more popular. The border area of ​​the existing display panel includes a peripheral driving circuit for providing driving signals for the pixel units in the display area.

[0004] In a display panel, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to a peripheral driving circuit in the frame area, and the peripheral driving circuit provides a scanning control signal and a light-emitting control signal to the pixel circuit to control the pixel circuit to provide a driving current to the light-emitting element. However, the existing driving circuit occupies a large space, making it difficult to further reduce the frame width of the display panel. Summary of the invention

[0005] Embodiments of the present invention provide a display panel and a display device to effectively solve the technical problems existing in the prior art and ensure that the border width of the display panel is small.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0007] A driving circuit and a pixel circuit, wherein the driving circuit provides a driving signal for the pixel circuit, and the pixel circuit provides a driving current for the light-emitting element of the display panel;

[0008] A light-emitting element, the light-emitting element comprising a first electrode and a second electrode;

[0009] A first power signal bus and a second power signal bus, wherein the first power signal bus is used to transmit a first power signal V1, and the second power bus is used to transmit a second power signal V2, V1≠V2;

[0010] The first power signal bus is connected to the pixel circuit, the pixel circuit is connected to the first electrode, and the second power signal bus is connected to the second electrode;

[0011] The second power signal bus at least partially overlaps with the driving circuit.

[0012] In a second aspect, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0013] The display panel provided by the embodiment of the present invention provides a driving signal for a pixel circuit through a driving circuit, and provides a driving current for a light-emitting element of the display panel through the pixel circuit; is connected to the pixel circuit through a first power signal bus, the pixel circuit is connected to the first electrode of the light-emitting element, and a first power signal V1 is transmitted to the first electrode; a second power signal bus is connected to the second electrode of the light-emitting element, and a second power signal V2 is transmitted to the second electrode to drive the light-emitting element to emit light; by setting the second power signal bus to at least partially overlap with the driving circuit, the occupied area of ​​the border area can be effectively reduced, thereby reducing the border width of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0017] Figure 4 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0018] Figure 5 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0019] Figure 6 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0020] Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0021] Figure 8 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0022] Figures 9 to 11 They are schematic diagrams of the structure of another display panel provided by an embodiment of the present invention;

[0023] Fig.12 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0024] Fig.13 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0025] Fig.14A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0026] Fig.15 and Fig.16 They are schematic diagrams of the structure of another display panel provided by an embodiment of the present invention;

[0027] Fig.17 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0028] Fig.18 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention;

[0029] Fig.19 for Fig.18 The structural layout of the shift register shown;

[0030] Fig. 20 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0031] Fig.21 for Fig. 20 The structural layout of the shift register shown;

[0032] Fig. 22 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0033] Fig.23 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention;

[0034] Fig.24 for Fig.23 The structural layout of the shift register shown;

[0035] Fig.25 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0036] Fig.26 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0038] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second" and the like are only used for descriptive purposes and do not indicate any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0039] As described in the background art, the border area of ​​the existing display panel includes a peripheral driving circuit for providing a driving signal to the pixel unit in the display area. In the display panel, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuit in the border area, and the peripheral driving circuit provides a scanning control signal and a light-emitting control signal to the pixel circuit to control the pixel circuit to provide a driving current to the light-emitting element. However, the existing driving circuit occupies a large space, which makes it difficult to reduce the border width of the display panel.

[0040] In view of this, an embodiment of the present invention provides a display panel to ensure that the border width of the display panel is small. The technical solution of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.

[0041] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 1 The display panel includes a driving circuit 10 and a pixel circuit 20, the driving circuit 10 provides a driving signal for the pixel circuit 20, and the pixel circuit 20 provides a driving current for the light-emitting element 30 of the display panel; the light-emitting element 30, the light-emitting element 30 includes a first electrode 301 and a second electrode 302; a first power signal bus 40 and a second power signal bus 50, the first power signal bus 40 is used to transmit a first power signal V1, and the second power bus 50 is used to transmit a second power signal V2, V1≠V2; wherein the first power signal bus 40 is connected to the pixel circuit 20, the pixel circuit 20 is connected to the first electrode 301, and the second power signal bus 50 is connected to the second electrode 302; the second power signal bus 50 at least partially overlaps with the driving circuit 10.

[0042] The display panel includes a display area AA and a non-display area NA (i.e., a frame area). Figure 1In the illustrated embodiment, the driving circuit 10 is located on one side of the display area AA, and drives the pixel circuit 20 by unilateral driving. The driving circuit 10 and the pixel circuit 20 may be formed by a plurality of transistors and at least one capacitor. The driving circuit 10 provides the driving signal required to control the pixel circuit 20, and the pixel circuit 20 controls the light-emitting element 30 to emit light. The light-emitting element 30 may be an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode Mini LED, or a micro light-emitting diode Micro LED, which may be selected according to actual conditions during specific implementation. The first electrode 301 may be an anode of the light-emitting element 30, the second electrode 302 may be a cathode of the light-emitting element 30, the first power supply signal V1 may be an anode voltage signal PVDD, and the second power supply signal V2 may be a cathode voltage signal PVEE. The first power signal bus 40 is generally connected to the pixel circuit 20 through the first power signal line located in the display area AA, and the second power signal bus 50 is generally located in the non-display area NA, and the non-display area NA is generally also provided with a driving circuit 10. In this embodiment, in order to fully save the frame area, at least part of the area of ​​the second power signal bus 50 can be arranged to overlap with the driving circuit 10. Such an arrangement can save the panel frame and realize a narrow frame display. It should be noted that the second power signal bus 50 described in this embodiment overlaps with the driving circuit 10 in the sense that it overlaps at least partly with the active layer of at least one transistor and / or the plate of at least one capacitor in the driving circuit 10. If it only overlaps with the edge routing of the driving circuit 10, it is not considered as an overlap.

[0043] It should be noted that, except for special provisions, the overlap described in this article can generally be considered as an overlapping relationship in a direction perpendicular to the surface of the display panel, because the border of the display panel mainly refers to the left and right borders or the upper and lower borders of the display panel. In the direction perpendicular to the surface of the display panel, the structures overlap with each other, which helps to reduce the border area.

[0044] The display panel provided by the embodiment of the present invention provides a driving signal for a pixel circuit through a driving circuit, and provides a driving current for a light-emitting element of the display panel through the pixel circuit; is connected to the pixel circuit through a first power signal bus, the pixel circuit is connected to the first electrode of the light-emitting element, and a first power signal V1 is transmitted to the first electrode; a second power signal bus is connected to the second electrode of the light-emitting element, and a second power signal V2 is transmitted to the second electrode to drive the light-emitting element to emit light; by setting the second power signal bus to at least partially overlap with the driving circuit, the occupied area of ​​the border area can be effectively reduced, thereby reducing the border width of the display panel.

[0045] Figure 1In the illustrated embodiment, the driving circuit 10 is located at one side of the display area AA, and the display panel is a single-sided driven display panel structure. In another embodiment, the display panel may be a double-sided driven display panel structure. Figure 2 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 2 The driving circuit 10 is included in the non-display area NA located on both sides of the display area AA, and the pixel circuit 20 is driven by the driving circuits 10 on both sides.

[0046] like Figure 2 As shown, in the double-sided driven panel structure provided by the embodiment of the present invention, the pixel circuits 20 in the same row can be driven simultaneously by two driving circuits 10 located on different sides of the display area AA. It can be understood that each driving circuit 10 includes a plurality of cascaded shift registers ( Figure 2 (not shown), the first-stage shift register of the first side driving circuit 10 and the first-stage shift register of the second side driving circuit 10 are both electrically connected to the pixel circuit 20 of the first row, the second-stage shift register of the first side driving circuit 10 and the second-stage shift register of the second side driving circuit 10 are both electrically connected to the pixel circuit 20 of the second row, and so on, the last-stage shift register of the first side driving circuit 10 and the last-stage shift register of the second side driving circuit 10 are both electrically connected to the pixel circuit 20 of the last row.

[0047] Figure 3 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 3 In the double-sided driven panel structure provided by the embodiment of the present invention, pixel circuits 20 in different rows can be driven respectively by two driving circuits 10 located on different sides of the display area AA.

[0048] It can be understood that in this embodiment, the odd-numbered driving circuit is located on the first side of the display area, and the even-numbered driving circuit is located on the second side of the display area, wherein the odd-numbered driving circuit is electrically connected to the pixel circuits of the odd rows, and the even-numbered driving circuit is electrically connected to the pixel circuits of the even rows.

[0049] In a certain embodiment of the present invention, a display panel provided by the embodiment of the present invention includes a base substrate, and a driving circuit, a pixel circuit and a light-emitting element are all located on the base substrate. Figure 4 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 4The display panel includes a substrate 100; a transistor array layer located on the substrate 100, the transistor array layer including a semiconductor layer 210 located on the substrate 100, the semiconductor layer 210 including a plurality of active regions; a gate insulating layer 220 located on a side of the semiconductor layer 210 away from the substrate 100; a gate metal layer 230 located on a side of the gate insulating layer 220 away from the substrate 100, the gate metal layer 230 including a plurality of gates and a plurality of first capacitor plates; an interlayer insulating layer 240 located on a side of the gate metal layer 230 away from the substrate 100 0; a capacitor metal layer 250 located on the side of the interlayer insulating layer 240 away from the substrate 100, the capacitor metal layer 250 includes a second capacitor plate arranged to overlap with the first capacitor plate; an isolation layer 260 located on the side of the capacitor metal layer 250 away from the substrate 100; a source-drain metal layer 270 located on the side of the isolation layer 260 away from the substrate 100, the source-drain metal layer 270 includes a plurality of source electrodes and drain electrodes, and the source electrodes and drain electrodes are contacted and connected with the active area through respective corresponding vias; wherein the transistor array layer includes a driving circuit and a pixel circuit. A first insulating layer 310 and a second insulating layer 320 located on the side of the source-drain metal layer 270 away from the substrate 100. In the display area AA, a first electrode 301, a light-emitting layer 303 and a second electrode 302 located on the side of the second insulating layer 310 away from the substrate 100 are provided; in the non-display area NA, a second power signal bus 50 is provided on the side of the first insulating layer 310 away from the substrate 100.

[0050] Continue to refer Figure 4 Optionally, the display panel also includes an auxiliary connection layer 330; wherein the auxiliary connection layer 330 is located between the film layer where the second electrode 302 is located and the film layer where the second power signal bus 50 is located, and the auxiliary connection layer 330 is connected to the second electrode 302 and the second power signal bus 50.

[0051] It can be understood that in this embodiment, the second electrode 302 is the cathode of the light-emitting element, and its film layer is located on the top of the light-emitting element. The second power signal bus 50 is a metal wiring arranged in the transistor array layer and is located inside the transistor array layer. Therefore, the distance between the second electrode 302 and the second power signal bus 50 is relatively large. If they are directly connected, a deeper via is required, and the connection effect may be poor. In the embodiment of the present invention, by setting the auxiliary connection layer 330, the second power signal bus 50 is first connected to the auxiliary connection layer 330, and the auxiliary connection layer 330 is then connected to the second electrode 302 ( Figure 4The structure of the partial display area AA and the partial non-display area NA is shown, so the connection relationship between the auxiliary connection layer 330 and the second electrode 302 is not shown in the figure. The auxiliary connection layer 330 plays the role of intermediate transition, so that it can ensure a better connection and help reduce resistance. Optionally, the auxiliary connection layer 330 and the first electrode 301 are located in the same layer.

[0052] In this embodiment, the film layer where the first electrode (anode of the light-emitting element) 301 is located is located between the second power signal bus 50 and the second electrode 302. By setting the auxiliary connection layer 330 in the same layer as the first electrode 301, the process can be simplified and the manufacturing cost of the display panel can be reduced. In other embodiments, the auxiliary connection layer 330 can be located in other film layers between the second power signal bus 50 and the second electrode 302, and can be designed according to actual conditions during specific implementation.

[0053] Figure 5 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 5 Optionally, the second power signal bus 50 includes a first sub-signal line 51 and a second sub-signal line 52 , the first sub-signal line 51 and the second sub-signal line 52 are arranged in different layers, and the first sub-signal line 51 and the second sub-signal line 52 are connected through a first via 53 .

[0054] The second power signal bus 50 serves as a second electrode ( Figure 5 The structure of the display area is not shown in the figure) to provide a second power signal V2, and the voltage drop on the second power signal bus 50 will cause the signal on the second electrode to be inaccurate, which will in turn cause the luminous brightness of the light-emitting element to be inconsistent with the desired display brightness. In order to avoid this problem, it is necessary to reduce the resistance of the second power signal bus 50 as much as possible to ensure that the voltage drop on the second power signal bus 50 is small, so that the luminous brightness of the light-emitting element is as accurate as possible. In addition, in order to achieve the effect of a narrow frame, the single-layer wiring cannot be set too wide. Based on this, in this embodiment, the second power signal bus 50 is set to include a first sub-signal line 51 and a second sub-signal line 52 set in different layers. The two wirings are electrically connected to reduce the resistance on the second power signal bus 50, which is conducive to reducing the voltage drop on the second power signal bus 50 and improving the display effect.

[0055] Continue to refer Figure 5 Optionally, the first sub-signal line 51 and the driving circuit 10 at least partially overlap each other, and the second sub-signal line 52 and the driving circuit 10 do not overlap each other; the width D1 of the first sub-signal line 51 is greater than the width D2 of the second sub-signal line 52.

[0056] In one embodiment, the first sub-signal line 51 and the driving circuit 10 can be overlapped, while the second sub-signal line 52 and the driving circuit 10 do not overlap. In this way, the voltage drop on the second sub-signal line 52 can be fully reduced through the first sub-signal line 51 by increasing the width of the first sub-signal line 51 and other factors, and the border area of ​​the display panel will not be increased. That is, by setting the width D1 of the first sub-signal line 51 to be greater than the width D2 of the second sub-signal line 52, the voltage drop on the second power signal bus 50 can be avoided to be low, and the border area will not be increased. It should be noted that Figure 5 Only the structure of the non-display area NA is shown in the figure, wherein the arrow points from the display area to the edge of the display panel, and the representation method in the following embodiments is the same.

[0057] In another embodiment, the first sub-signal line and the second sub-signal line may be arranged to overlap with the driving circuit. For example, Figure 6 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 6 Optionally, the first sub-signal line 51 overlaps with the driving circuit 10, and the second sub-signal line 52 overlaps with the driving circuit 10; the first sub-signal line 51 and the second sub-signal line 52 are both located at the first electrode ( Figure 6 The structure of the display area is not shown in the figure and the film layer where the driving circuit 10 is located. By setting the first sub-signal line 51 and the second sub-signal line 52 to overlap with the driving circuit 10, it is helpful to minimize the width of the frame area. In specific implementation, the size of the overlapping area of ​​the first sub-signal line 51 and the second sub-signal line 52 can be set according to actual conditions, and the embodiment of the present invention is not limited to this.

[0058] Continue to refer Figure 5 Optionally, the first sub-signal line 51 includes a first area 510 and a second area 520, the first area 510 overlaps with the driving circuit 10, the second area 520 does not overlap with the driving circuit 10, and the second area 520 is located on a side of the first area 510 away from the display area of ​​the display panel; the second area 520 overlaps with the second sub-signal line 52, and the second area 520 is connected to the second sub-signal line 52 through a first via 53, and the first via 53 does not overlap with the driving circuit 10.

[0059] By extending the first sub-signal line 51 to a side away from the display area of ​​the display panel to form a second area 520, the second area 520 is connected to the second sub-signal line 52 through the first via 53, so that the first via 53 and the driving circuit 10 do not overlap, thereby avoiding the influence of the via area on the driving circuit 10 during the process.

[0060] Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 7 Optionally, the first sub-signal line 51 is located on the side of the film layer where the first electrode is located facing the driving circuit 10, and the second sub-signal line 52 is located on the side of the film layer where the first sub-signal line 51 is located facing the driving circuit 10; the driving circuit includes a first transistor and / or a first capacitor ( Figure 7 A transistor and a capacitor are schematically shown in the figure); wherein, at least one film layer of the first transistor is located in the same layer as the second sub-signal line 52, and / or, at least one electrode plate of the first capacitor is located in the same layer as the second sub-signal line 52.

[0061] Understandably, Figure 7 The second sub-signal line 52 shown in the figure is in the same layer as the source-drain metal layer 270 for illustration only. In other embodiments, the second sub-signal line may be arranged in the same layer as the gate metal layer 230 (the first plate of the capacitor), or in the same layer as the capacitor metal layer 250, or in the same layer as other routing film layers in the driving circuit layer. The specific implementation may be flexibly selected according to the actual situation. In the present embodiment, since the second sub-signal line 52 does not overlap with the driving circuit 10, the second sub-signal line 52 is arranged in the same layer as some film layers in the driving circuit 10, thereby simplifying the process. In other embodiments, the second power signal bus may also be arranged to include three or more film layers arranged in parallel, if the circuit design conditions permit, to reduce the resistance of the second power signal bus and the voltage drop when transmitting the signal. The embodiments of the present invention are not limited to this.

[0062] Figure 8 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 8 Optionally, the first sub-signal line 51 is located on a side of the second sub-signal line 52 facing the film layer where the first electrode is located; wherein the width of the first sub-signal line 51 is greater than the width of the second sub-signal line 52 .

[0063] Among them, in this embodiment, the second sub-signal line 52 is closer to the driving circuit 10 than the first sub-signal line 51. If the width of the second sub-signal line 52 is set too large, it may cause the signal crosstalk between the second sub-signal line 52 and the driving circuit 10 to increase due to coupling. The first sub-signal line 51 is farther away from the driving circuit 10 than the second sub-signal line 52, and the signal crosstalk between it and the driving circuit 10 is smaller. Therefore, the width of the first sub-signal line 51 can be appropriately increased to make it larger than the width of the second sub-signal line 52, thereby fully reducing the voltage drop.

[0064] Continue to refer Figure 8 Optionally, the driving circuit 10 includes a first capacitor 110, an overlapping area of ​​the first sub-signal line 51 and the first capacitor 110 is S1, and an overlapping area of ​​the second sub-signal line 52 and the first capacitor 100 is S2; wherein S1>S2≥0.

[0065] Among them, when the second power signal bus 50 overlaps with the first capacitor 110, parasitic capacitance may be formed, resulting in unstable capacitance and thus affecting the performance of the driving circuit 10. In order to avoid the occurrence of parasitic capacitance as much as possible, in this embodiment, the overlapping area S1 between the first sub-signal line 51 and the capacitor is set to be larger than the overlapping area S2 between the second sub-signal line 52 and the capacitor. In this way, the additional capacitance generated between the second sub-signal line 52 and the capacitor can be reduced as much as possible. Compared with the second sub-signal line 52, the first sub-signal line 51 is farther away from the driving circuit 10, and the parasitic capacitance value generated by it is smaller.

[0066] Figures 9 to 11 They are schematic diagrams of the structure of another display panel provided by an embodiment of the present invention. Figures 9 to 11 Optionally, the display panel includes a first retaining wall 410, which is located on a side of the driving circuit 10 away from the display area of ​​the display panel; wherein the first retaining wall 410 overlaps with at least one of the first sub-signal line 51 and the second sub-signal line 52.

[0067] Among them, the light-emitting layer material of the light-emitting element is relatively sensitive to external substances such as water and oxygen. When the light-emitting layer is invaded by external water and oxygen, it will fail, affecting the display effect. In order to protect the light-emitting layer, a multi-layer stacked encapsulation layer is generally set. In this embodiment, a first retaining wall 410 is set in the non-display area. The first retaining wall 410 can cut off part of the encapsulation layer (for example, an organic layer, and the figure specifically shows the structure of the encapsulation layer), while other encapsulation layers (for example, inorganic layers) cover the first retaining wall 410 to improve the encapsulation effect. Reference Fig. 9 , the first retaining wall 410 and the first sub-signal line 51 overlap each other; Fig.10 , the first retaining wall 410 and the second sub-signal line 52 overlap each other; Fig.11 The first retaining wall 410 overlaps with the first sub-signal line 51 and the second sub-signal line 52. By arranging the first retaining wall 410 to overlap with at least one of the first sub-signal line 51 and the second sub-signal line 52, the space occupied by the frame can be reduced as much as possible, achieving a narrow frame effect.

[0068] Optionally, the first via hole 53 does not overlap with the first retaining wall 410, see Fig. 9 or Fig.10 , the first via hole 53 is located between the driving circuit 10 and the first retaining wall 410, or, referring to Fig.11 The first via hole 53 is located on a side of the first retaining wall 410 away from the driving circuit 10 .

[0069] Since the first retaining wall 410 is responsible for blocking at least part of the film layer of the encapsulation layer of the display panel, it is generally required that the first retaining wall 410 should not have any concave structures. If the via hole is set below the retaining wall, it may cause a concave problem below the retaining wall. Therefore, the first via hole 53 is set not to overlap with the first retaining wall 410. On this basis, the first via hole 53 can be located between the driving circuit 10 and the first retaining wall 410 ( Fig. 9 and Fig.10 ), or, the first via hole 53 is located on the side of the first retaining wall 410 away from the driving circuit 10 ( Fig.11 ).

[0070] Fig.12 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.12 Because the first via hole 53 is a via hole connecting the first sub-signal line 51 and the second sub-signal line 52, in order to avoid the influence of the via hole on the driving circuit 10, it is generally set not to overlap with the driving circuit 10. In order to fully save the frame space, in this embodiment, the first retaining wall 410 is set to at least partially overlap with the first via hole 53, wherein the position of the first via hole 53 is only schematic and can be selected according to actual conditions during specific implementation. The embodiment of the present invention is not limited to this.

[0071] Fig.13 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.13 Optionally, the display panel further includes an encapsulation layer 500 and a second retaining wall 420. Fig.13 The encapsulation layer 500 schematically shows that it includes a first inorganic layer 501, an organic layer 502 and a second inorganic layer 503, at least one film layer (organic layer 502) of the encapsulation layer 500 ends at the first retaining wall 410, and the second retaining wall 420 is located on the side of the first retaining wall 410 away from the display area of ​​the display panel.

[0072] In the process of preparing the encapsulation layer 500, before film formation, the organic layer is generally in a flowable liquid form, so a retaining wall structure needs to be designed to stop it, and the inorganic layer generally adopts a deposition process and can cover the second retaining wall 420. The multiple retaining wall structures can further improve the encapsulation effect and enhance the performance of the display panel.

[0073] Fig.14 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.14 Optionally, the first via 53 includes a first sub-via 531 and a second sub-via 532 , the first sub-via 531 is located between the driving circuit 10 and the first retaining wall 410 , and the second sub-via 532 is located on a side of the first retaining wall 410 away from the driving circuit 10 .

[0074] In order to improve the electrical connection stability between the first sub-signal line 51 and the second sub-signal line 52, more than one via hole may be provided to increase the contact area between the two. Fig.14 In the embodiment of the present invention, two vias are provided between the first signal sub-line 51 and the second signal sub-line 52, and the two vias can be respectively located on both sides of the first retaining wall 410. In other embodiments, two vias can also be provided on one side of the first retaining wall 410, or a greater number of vias can be provided according to actual conditions, and the specific implementation can be designed according to actual conditions.

[0075] Continue to refer Fig.14 Optionally, a width D3 of the first sub-via hole 531 is greater than a width D4 of the second sub-via hole 532 .

[0076] In the present embodiment, the first sub-via 531 is located on a side of the first retaining wall 410 close to the display area, that is, it is arranged on the inner side closer to the display panel than the second via 532. This part is farther away from the edge of the display panel and can be better packaged and protected. Therefore, the width of the first sub-via 531 is set to be larger, which can reduce the probability of process defects of the display panel while ensuring the connectivity performance of the first sub-signal line 51 and the second sub-signal line 52.

[0077] Fig.15 and Fig.16 They are schematic diagrams of the structure of another display panel provided by an embodiment of the present invention. Fig.15 or Fig.16 Optionally, the display panel further includes a first power signal line 41, a first power signal bus ( Fig.15 and Fig.16 (not shown) provides a first power signal V1 to the pixel circuit through a first power signal line 41, and the first power signal line 41 is located in the display area AA of the display panel; wherein the first power signal line 41 and the second sub-signal line 52 are located in the same layer.

[0078] Among them, the first power signal line 41 is a PVDD signal line that provides a first power signal V1 to each pixel circuit. The PVDD signal line is generally arranged above the film layer where the transistor or capacitor is located in the panel (in some embodiments, it can be on the same layer as the source and drain metal layer) to facilitate routing. In this embodiment, the second sub-signal line 52 is arranged on the same layer as the first power signal line 41, so as to simplify the process.

[0079] Optionally, the width of the first sub-signal line 51 is greater than the width of the first power signal line 41 ; and / or the width of the second sub-signal line 52 is greater than or less than the width of the first power signal line 41 .

[0080] Among them, the first power signal line 41 is a line extending from the first power signal bus to the display area AA, and generally a column and / or a row of light-emitting elements share one line. Therefore, there are more interfaces of the first power signal 41 in the display panel, and the circuits in the display area AA are densely arranged. When the line width is set to be narrow, the voltage drop can be avoided to a certain extent; and the second electrode is often laid in a whole layer in a large area of ​​the panel, and is only connected to the second power signal bus in the frame area. In order to ensure the transmittance of the second electrode, its film thickness is relatively thin, and the voltage drop thereon is often more obvious. In order to fully reduce the voltage drop on the second electrode, the width of the second power signal bus needs to be set to be wide enough to reduce the resistance. Therefore, in this embodiment, the width of the first sub-signal line 51 can be set to be wider than the first power signal line 41, so as to reduce the line resistance without increasing the frame area.

[0081] As for the second sub-signal line 52, in some embodiments, it does not overlap with the driving circuit. If its width is large, it will lead to a larger border area. In other embodiments, when the first sub-signal line 51 and the second sub-signal line 52 overlap with the driving circuit, it is closer to the driving circuit than the first sub-signal line 51. In order to avoid signal crosstalk, its width is set as small as possible. Therefore, the width D5 of the second sub-signal line 52 can be smaller than the width D6 of the first power signal line 41 ( Fig.15 ); In another embodiment, for example, when the resistance requirement of the second power signal bus is relatively strict, the width D7 of the second sub-signal line 52 may be set larger than the width D8 of the first power signal line 41 ( Fig.16 ) to ensure that the resistance is small.

[0082] Fig.17 A schematic diagram of a display panel structure provided for the present invention is shown in FIG. Fig.17 In a certain embodiment, optionally, the driving circuit 10 includes a first transistor 101 and a second transistor 102, the active layer of the first transistor 101 includes silicon, and the active layer of the second transistor 102 includes an oxide semiconductor; wherein the second power signal bus 50 covers the active layer of the second transistor 102, and the second power signal bus 50 does not cover the active layer of the first transistor 101.

[0083] Among them, the active layer of the first transistor 101 may include low-temperature polycrystalline silicon LTPS, and the active layer of the second transistor 102 may include indium gallium zinc oxide IGZO. Compared with LTPS, IGZO has the characteristics of high transmittance, low electron mobility, large switching ratio and low power consumption. The driving circuit formed by the two transistors has better performance. Since the oxide semiconductor active layer is more sensitive to molecules such as hydrogen and water than the silicon active layer, the second power signal bus 50 is reused as a shielding layer for the oxide semiconductor active layer in this embodiment, thereby providing protection for the oxide semiconductor active layer and avoiding failure of the oxide semiconductor active layer. In specific implementation, the pixel circuit may also include two transistors, such as the driving module and data writing module in the pixel circuit, the light emitting control module uses LTPS PMOS transistors, and the initialization module and threshold compensation module use IGZO NMOS transistors.

[0084] Optionally, the driving circuit includes a first driving circuit, which is used to provide a first control signal to the pixel circuit, and the first driving circuit includes a multi-stage first shift register cascaded along a first direction; the display panel includes a first signal line group, the first signal line group is connected to the first driving circuit, and is used to provide a signal to the first driving circuit, and the first signal line in the first signal line group overlaps with the first shift register; along the second direction, the width of the overlapping area between the first shift register and the first signal line is W11, and the width of the overlapping area between the first shift register and the second power signal bus is W12, and the second direction intersects with the first direction, wherein W11<W12.

[0085] The first direction may be the row direction of the pixel unit, and the second direction may be the column direction of the pixel unit. The first control signal is an enable signal EMIT for controlling the light emission of the pixel circuit, and the first drive circuit is an EMIT VSR circuit corresponding to the light emission control module in the pixel circuit. Since the second power signal bus is used to provide a signal for the second electrode laid in the entire layer of the display panel, it has very high requirements for voltage drop and requires a sufficiently small resistance. Therefore, in this embodiment, W11<W12 is set, that is, without increasing the frame area, the width of the overlap between the second power signal bus and the drive circuit is increased as much as possible, thereby minimizing the voltage drop on the second electrode.

[0086] Optionally, the first signal line group includes: a first clock signal line, used to provide a first clock signal to the first driving circuit; and / or, a second clock signal line, used to provide a second clock signal to the first driving circuit; and / or, a first voltage signal line, used to provide a first voltage signal to the first driving circuit, the first voltage signal being a high-level signal; and / or, a second voltage signal line, used to provide a second voltage signal to the first driving circuit, the second voltage signal being a low-level signal; wherein the first signal line is one of the first clock signal line and the second clock signal line; or, the first signal line is one of the first voltage signal line and the second voltage signal line.

[0087] For example, Fig.18 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention, Fig.19 for Fig.18 The structural layout of the shift register shown in Figure 1 is shown in Figure 2. Fig.18 It can be a shift register in the first driving circuit, wherein the shift register in the first driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a first capacitor C11, a second capacitor C12 and a third capacitor C13, wherein the first signal line group includes a start signal line STV1 (wherein the start signal line STV1 provides a start signal for the shift register at the end of the cascaded shift register in the first driving circuit), a clock signal line CK1, a clock signal line XCK1 (the phase of the pulse signal transmitted by the clock signal line CK1 and the clock signal line XCK1 is inverted), a low-level voltage signal line VGL and a high-level voltage signal line VGH. Among them, the first signal line group provides a signal to the shift register in the first driving circuit, and then through the cooperation of the first transistor M1 to the thirteenth transistor M13 and the first capacitor C11 to the third capacitor C13, the shift register finally outputs a light-emitting control signal for controlling the operation of the light-emitting control transistor in the pixel circuit. The start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL and the high-level voltage signal line VGH provided in the embodiment of the present invention can all overlap with the first driving circuit, that is, the first signal line includes the start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL and the high-level voltage signal line VGH, ensuring that the border area width of the display panel is small.

[0088] Optionally, along the second direction, the total width of the overlapping region between the signal lines in the first signal line group and the first shift register is WS1; wherein WS1<W12.

[0089] In order to provide the second power signal bus with a sufficient width and an overlapping area with the first driving circuit, some signal lines in the first signal line group may be arranged not to overlap with the driving circuit, or the total width after the overlap may be smaller, that is, WS1<W12 is satisfied, thereby fully reducing the resistance on the second power signal bus.

[0090] Optionally, the driving circuit also includes a second driving circuit, which is used to provide a second control signal for the pixel circuit, and the second driving circuit includes a multi-stage second shift register cascaded with each other; along the second direction, the width of the overlapping area between the second shift register and the second power signal bus is W22; wherein W12>W22≥0.

[0091] The second power bus mainly overlaps with the first drive circuit and overlaps less or not with the second drive circuit. In this embodiment, the second drive circuit can be a drive circuit that provides a control signal for an NMOS transistor, and is used to provide a control signal for an initialization module and a threshold compensation module of a pixel circuit.

[0092] Optionally, the display panel includes a second signal line group, which is connected to the second driving circuit and is used to provide signals to the second driving circuit; along the second direction, the width of the overlapping area between the signal lines in the second signal line group and the second shift register is WS2; wherein WS1<WS2.

[0093] Since the second power signal bus does not overlap with the second driving circuit or the overlapping width is small, WS1<WS2 can be set, that is, the overlapping width of the signal lines in the second signal line group and the second driving circuit is large to achieve a narrow frame effect.

[0094] Optionally, the second signal line group includes: a third clock signal line, used to provide a third clock signal to the second drive circuit; and / or, a fourth clock signal line, used to provide a fourth clock signal to the second drive circuit; and / or, a third voltage signal line, used to provide a third voltage signal to the second drive circuit, the third voltage signal being a high level signal; and / or, a fourth voltage signal line, used to provide a fourth voltage signal to the first drive circuit, the fourth voltage signal being a low level signal.

[0095] For example, Fig. 20 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention, Fig.21 for Fig. 20 The structural layout of the shift register shown in Figure 1 is shown in Figure 2. Fig. 20It can be a shift register in the second driving circuit, wherein the second driving circuit is used to control the NMOS transistor in the pixel circuit, wherein the shift register in the second driving circuit includes a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor N6, a seventh transistor N7, an eighth transistor N8, a ninth transistor N9, a tenth transistor N10, an eleventh transistor N11, a twelfth transistor N12, a thirteenth transistor N13, a first capacitor C31, a second capacitor C32 and a third capacitor C33, wherein the second signal line group includes a start signal line STV3 (wherein the start signal line STV3 provides a start signal for the shift register at the end of the cascaded shift register in the second driving circuit), a clock signal line CK3, a clock signal line XCK3 (the phase of the pulse signal transmitted by the clock signal line CK3 and the clock signal line XCK3 is inverted), a low-level voltage signal line VGL and a high-level voltage signal line VGH. Among them, the second signal line group provides a signal to the shift register in the second driving circuit, and then through the cooperation of the first transistor N1 to the thirteenth transistor N13 and the first capacitor C31 to the third capacitor C33, the shift register finally outputs a control signal for controlling the operation of the NMOS transistor in the pixel circuit. The start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low-level voltage signal line VGL and the high-level voltage signal line VGH provided in the embodiment of the present invention can all overlap with the second driving circuit, that is, the second signal line includes the start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low-level voltage signal line VGL and the high-level voltage signal line VGH, ensuring that the border area width of the display panel is small.

[0096] Optionally, the first clock signal line overlaps with the first shift register, and the third clock signal line overlaps with the second shift register, wherein the width of the first clock signal line is smaller than the width of the third clock signal line; or, the second clock signal line overlaps with the first shift register, and the fourth clock signal line overlaps with the second shift register, wherein the width of the second clock signal line is smaller than the width of the fourth clock signal line.

[0097] Optionally, the first voltage signal line overlaps with the first shift register, and the third voltage signal line overlaps with the second shift register, wherein the width of the first voltage signal line is smaller than the width of the third voltage signal line; or, the second voltage signal line overlaps with the first shift register, and the fourth voltage signal line overlaps with the second shift register, wherein the width of the second voltage signal line is smaller than the width of the fourth voltage signal line.

[0098] In this embodiment, because the overlapping area of ​​the first driving circuit and the second power signal bus is larger than the overlapping area of ​​the second driving circuit and the second power signal bus, the width of the routing line in the first signal line group overlapping with the first driving circuit is set to be smaller than the width of the routing line with the same function in the second signal line group overlapping with the second driving circuit, so as to provide sufficient space for the second power signal bus to ensure its width and reduce resistance.

[0099] For example, Fig. 22 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig. 22 The width of the signal line in the first signal line group 120 overlapping with the first driving circuit 11 is smaller than the width of the signal line corresponding to the same signal transmitted in the second signal line group 130 overlapping with the second driving circuit 20 .

[0100] Continue to refer Fig. 22 Optionally, the second driving circuit 12 is located on a side of the first driving circuit 11 facing the display area AA of the display panel.

[0101] By arranging the second driving circuit 12 to be located on the side of the first driving circuit 11 facing the display area AA, it is convenient to connect the two layers of wiring in the second power signal bus through vias. Therefore, the second power signal bus is generally arranged to overlap with a driving circuit farthest from the display area AA, so that after extending out of the driving circuit, it is convenient to perform punching connection.

[0102] Optionally, the driving circuit also includes a third driving circuit, which is used to provide a third control signal for the pixel circuit, and the third driving circuit includes a multi-stage third shift register cascaded with each other; along the second direction, the width of the overlapping area between the third shift register and the second power signal bus is W32; wherein, W12>W22≥W32≥0, or, W12≥W22>W32≥0.

[0103] The second power signal bus mainly overlaps with the first drive circuit, and may have a small overlap or no overlap with the second drive circuit and / or the third drive circuit. In this embodiment, the third drive circuit may be a drive circuit that provides a control signal for a PMOS transistor, and is used to provide a control signal for a data writing module or a light emitting control module of a pixel circuit.

[0104] Fig.23 A schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention, Fig.24 for Fig.23 The structural layout of the shift register shown in Figure 1 is shown in Figure 2. Fig.23It can be a shift register in the third driving circuit, wherein the third driving circuit is used to control the PMOS transistor in the pixel circuit, and the shift register in the third driving circuit includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, a seventh transistor P7, an eighth transistor P8, a first capacitor C21 and a second capacitor C22, wherein the second signal line group includes a start signal line STV2 (wherein the start signal line STV2 provides a start signal for the shift register at the end of the cascade shift register in the third driving circuit), a clock signal line CK2, a clock signal line XCK2, a low-level voltage signal line VGL and a high-level voltage signal line VGH. The second signal line group provides a signal to the shift register in the second driving circuit, and then through the cooperation of the first transistor P1 to the eighth transistor P8, the first capacitor C21 and the second capacitor C22, the shift register finally outputs a control signal for controlling the operation of the PMOS transistor in the pixel circuit. The start signal line STV2, clock signal line CK2, clock signal line XCK2 (the phase of the pulse signal transmitted by the clock signal line CK2 and the clock signal line XCK2 is inverted), low-level voltage signal line VGL and high-level voltage signal line VGH provided in the embodiment of the present invention can all overlap with the third driving circuit, that is, the third signal line includes the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low-level voltage signal line VGL and the high-level voltage signal line VGH, thereby ensuring that the width of the border area of ​​the display panel is small.

[0105] Optionally, the display panel includes a third signal line group, which is connected to a third driving circuit and is used to provide signals to the third driving circuit; along the second direction, the total width of the overlapping area between the signal lines in the third signal line group and the third shift register is WS3; wherein WS1<WS3.

[0106] Similar to the setting of the second driving circuit, since the second power signal bus does not overlap with the third driving circuit or the overlapping width is small, WS1<WS3 can be set, that is, the width of the overlap between the signal line in the third signal line group and the third driving circuit is large to achieve a narrow frame effect.

[0107] Fig.25 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.25 Optionally, the second driving circuit 12 is located on the side of the first driving circuit 11 facing the display area AA of the display panel, and the third driving circuit 13 is located on the side of the second driving circuit 12 facing the display area AA of the display panel. That is, the first driving circuit 11, the second driving circuit 12 and the third driving circuit 13 are arranged in sequence along the edge of the display panel toward the display area, thereby facilitating the design of the second power signal bus to obtain a smaller frame.

[0108] It should be noted that Fig. 22 , Fig.25 Only the Figure 1 Similar unilateral driving mode can also be similar to Figure 2 and Figure 3 The double-sided drive method shown.

[0109] Fig.26 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. Fig.26 The display device 1 includes any one of the display panels 2 provided in the embodiments of the present invention. The display device 1 can be a mobile phone, a computer, a smart wearable device, etc.

[0110] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: Driving circuit and pixel circuit; A light-emitting element, the light-emitting element comprising a first electrode and a second electrode; a first power signal bus and a second power signal bus; The first power signal bus is connected to the pixel circuit, the pixel circuit is connected to the first electrode, and the second power signal bus is connected to the second electrode; The second power signal bus at least partially overlaps with the driving circuit; The driving circuit comprises a first driving circuit, the first driving circuit provides a first control signal for the pixel circuit, and the first driving circuit comprises a plurality of first shift registers cascaded with each other along a first direction; The display panel comprises a first signal line group, and the first signal line group is connected to the first driving circuit; Along the second direction, the total width of the overlapping area between the signal lines in the first signal line group and the first shift register is WS1, the width of the overlapping area between the first shift register and the second power signal bus is W12, and the second direction intersects the first direction, wherein, WS1<W12.

2. The display panel according to claim 1, characterized in that: The driving circuit further includes a second driving circuit, the second driving circuit is used to provide a second control signal for the pixel circuit, and the second driving circuit includes a plurality of second shift registers cascaded to each other; Along the second direction, the width of the overlapping area between the second shift register and the second power signal bus is W22; wherein, W12>W22≥0.

3. The display panel according to claim 2, characterized in that: The display panel comprises a second signal line group, and the second signal line group is connected to the second driving circuit; Along the second direction, the total width of the overlapping area between the signal lines in the second signal line group and the second shift register is WS2; wherein, WS1<WS2.

4. The display panel according to claim 3, characterized in that: The width of the signal line in the first signal line group overlapping with the first driving circuit is smaller than the width of the signal line corresponding to the same signal transmitted in the second signal line group overlapping with the second driving circuit.

5. The display panel according to claim 3, characterized in that: The first signal line group includes: A first clock signal line provides a first clock signal to the first driving circuit; and / or, A second clock signal line provides a second clock signal to the first driving circuit; and / or, A first voltage signal line provides a first voltage signal to the first driving circuit, wherein the first voltage signal is a high level signal; and / or, A second voltage signal line, providing a second voltage signal to the first driving circuit, wherein the second voltage signal is a low level signal; The second signal line group includes: A third clock signal line is used to provide a third clock signal to the second driving circuit; and / or, a fourth clock signal line, used to provide a fourth clock signal to the second driving circuit; and / or, A third voltage signal line is used to provide a third voltage signal to the second driving circuit, wherein the third voltage signal is a high level signal; and / or, The fourth voltage signal line is used to provide a fourth voltage signal to the first driving circuit, and the fourth voltage signal is a low level signal.

6. The display panel according to claim 5, characterized in that: The first clock signal line overlaps with the first shift register, and the third clock signal line overlaps with the second shift register, wherein the width of the first clock signal line is smaller than the width of the third clock signal line; or, The second clock signal line overlaps with the first shift register, and the fourth clock signal line overlaps with the second shift register, wherein a width of the second clock signal line is smaller than a width of the fourth clock signal line.

7. The display panel according to claim 5, characterized in that: The first voltage signal line overlaps with the first shift register, and the third voltage signal line overlaps with the second shift register, wherein the width of the first voltage signal line is smaller than the width of the third voltage signal line; or, The second voltage signal line overlaps with the first shift register, and the fourth voltage signal line overlaps with the second shift register, wherein a width of the second voltage signal line is smaller than a width of the fourth voltage signal line.

8. The display panel according to claim 2, characterized in that: The second driving circuit is located at a side of the first driving circuit facing the display area of ​​the display panel.

9. The display panel according to claim 2, characterized in that: The driving circuit further comprises a third driving circuit, the third driving circuit is used to provide a third control signal for the pixel circuit, and the third driving circuit comprises a plurality of third shift registers cascaded to each other; Along the second direction, the width of the overlapping area between the third shift register and the second power signal bus is W32; wherein, W12>W22≥W32≥0, or, W12≥W22>W32≥0.

10. The display panel according to claim 9, characterized in that: The display panel comprises a third signal line group, wherein the third signal line group is connected to the third driving circuit and is used to provide a signal to the third driving circuit; Along the second direction, the total width of the overlapping area between the signal lines in the third signal line group and the third shift register is WS3; wherein, WS1<WS3.

11. The display panel according to claim 9, characterized in that: The second driving circuit is located at a side of the first driving circuit facing the display area of ​​the display panel, and the third driving circuit is located at a side of the second driving circuit facing the display area of ​​the display panel.

12. The display panel according to claim 1, characterized in that: The display panel further includes an auxiliary connection layer; wherein, The auxiliary connection layer is located between the film layer where the second electrode is located and the film layer where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus.

13. The display panel according to claim 12, characterized in that: The auxiliary connection layer and the first electrode are located in the same layer.

14. The display panel according to claim 1, characterized in that: The second power signal bus includes a first sub-signal line and a second sub-signal line. The first sub-signal line and the second sub-signal line are arranged in different layers. The first sub-signal line and the second sub-signal line are connected through a first via.

15. The display panel according to claim 14, characterized in that: The first sub-signal line and the driving circuit at least partially overlap each other, and the second sub-signal line and the driving circuit do not overlap each other; The width of the first sub-signal line is greater than the width of the second sub-signal line.

16. The display panel according to claim 15, characterized in that: The first sub-signal line includes a first area and a second area, the first area overlaps with the driving circuit, the second area does not overlap with the driving circuit, and the second area is located on a side of the first area away from the display area of ​​the display panel; The second region overlaps with the second sub-signal line, and the second region and the second sub-signal line are connected through the first via hole, and the first via hole does not overlap with the driving circuit.

17. The display panel according to claim 15, characterized in that: The first sub-signal line is located at a side of the film layer where the first electrode is located facing the driving circuit, and the second sub-signal line is located at a side of the film layer where the first sub-signal line is located facing the driving circuit; The driving circuit includes a first transistor and / or a first capacitor; wherein, At least one film layer of the first transistor is located in the same layer as the second sub-signal line, and / or, At least one plate of the first capacitor and the second sub-signal line are located in the same layer.

18. The display panel according to claim 14, characterized in that: The display panel further includes a first power signal line, the first power signal bus is connected to the pixel circuit via the first power signal line, and the first power signal line is located in the display area of ​​the display panel; wherein, The first power signal line and the second sub-signal line are located in the same layer.

19. The display panel according to claim 18, characterized in that: The width of the first sub-signal line is greater than the width of the first power signal line; and / or, The width of the second sub-signal line is greater than or less than the width of the first power signal line.

20. The display panel according to claim 14, characterized in that: The first sub-signal line is located on the side of the second sub-signal line facing the film layer where the first electrode is located; wherein, The width of the first sub-signal line is greater than the width of the second sub-signal line.

21. The display panel according to claim 20, characterized in that: The driving circuit includes a first capacitor, the first sub-signal line and the first capacitor overlap in an area S1, and the second sub-signal line and the first capacitor overlap in an area S2; wherein, S1>S2≥0.

22. The display panel according to claim 1, characterized in that: The driving circuit includes a first transistor and a second transistor, the active layer of the first transistor includes silicon, and the active layer of the second transistor includes an oxide semiconductor; wherein, The second power signal bus covers the active layer of the second transistor, and the second power signal bus does not cover the active layer of the first transistor.

23. A display device, characterized in that: A display panel comprising any one of claims 1-22.

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