Memory device and method of manufacturing the same

Abstract

The invention relates to a memory device and a manufacturing method thereof. A memory device includes a first peripheral circuit having a first page buffer and functionally divided into a cell region and a connection region. A first memory cell array on a first peripheral circuit includes a first bit line electrically connected to a first page buffer. A second memory cell array on the first memory cell array includes second bit lines electrically connected to the first bit lines, respectively. The first peripheral circuit can utilize the two memory cell arrays using a connection between the two memory cell arrays.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method for manufacturing the same, and more particularly, to a memory device manufactured by a wafer bonding technology and a method for manufacturing the same. Background Art

[0002] The memory device may include a memory cell array storing data and a peripheral circuit configured to perform a program operation, a read operation, or an erase operation of the memory cell array.

[0003] The memory cell array of such a memory device may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells stacked in a vertical direction over a substrate supporting the memory cell array.

[0004] Because structures manufactured on different substrates need to be in physical contact with each other, the bonding strength between different substrates made of different materials may be reduced, or in the case of different materials, the connection resistance between the two substrates may be increased. Summary of the invention

[0005] Embodiments of the present disclosure provide a memory device including a plurality of devices stacked on each other and a method of manufacturing the same, wherein bonding strength between structures is increased and interconnection resistance is reduced by using bonding pads at interfaces where different structures contact each other.

[0006] According to an embodiment of the present disclosure, a memory device includes: a first peripheral circuit including a first page buffer and at least two memory cell arrays. The first peripheral circuit and the memory cell array are functionally divided or separated into a cell region and a connection region.

[0007] The first memory cell array is located, ie, positioned, on the first peripheral circuit. The first bit line electrically connects the first page buffer and the second memory cell array located on the first memory cell array, and the second bit line is electrically connected to the first bit line.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a memory device includes the following steps: forming a peripheral circuit on a first substrate; forming a first memory cell array including a first stack on a second substrate; forming a first cell plug passing through the first stack, and forming a first bit line on the first cell plug; forming a second memory cell array including a second stack on a third substrate; forming a second cell plug passing through the second stack; forming a second bit line on the second cell plug, so that the first memory cell array is in contact with the second memory cell array; exposing a portion of the first cell plug by removing the second substrate located on the first memory cell array adjacent to the second memory cell array; forming a first source line including source bonding pads spaced apart from each other on the first cell plug exposed in the first memory cell array, so that the first memory cell array including the source bonding pad is in contact with the peripheral circuit; exposing a portion of the second cell plug by removing the third substrate located on the second memory cell array; and forming a second source line on the second cell plug exposed in the second memory cell array.

[0009] According to an embodiment of the present disclosure, a memory device includes a first peripheral circuit, the first peripheral circuit includes a first page buffer. The first peripheral circuit is functionally divided or functionally separated into a cell area and a connection area. A first memory cell array includes a first bit line of a first page buffer electrically connected to a cell area of ​​the first peripheral circuit and is mounted above the first peripheral circuit. A second memory cell array located on the first memory cell array includes a second bit line in a cell area of ​​the second memory cell array.

[0010] In an alternative embodiment, a second peripheral circuit located on the second memory cell array includes a second page buffer electrically connected to the second bit line. The first memory cell array includes a first source line located at an upper end of the first memory cell array and a first source bonding pad included in the first source line and exposed through an upper surface of the first source line, and the second memory cell array includes a second source line located on the first memory cell array and a second source bonding pad included in the second source line and respectively contacting the first source bonding pad through a lower surface of the second source line.

[0011] According to an embodiment of the present disclosure, a method for manufacturing a memory device includes the following steps: forming a first peripheral circuit including a first contact bonding pad on a first substrate, forming a first memory cell array including a second contact bonding pad on a second substrate, flipping the first memory cell array so that the second substrate is located at an upper portion and the second contact bonding pad is located at a lower portion, and making the second contact bonding pad of the flipped first memory cell array contact the first peripheral circuit, removing the second substrate on the first memory cell array and forming a first source line on the first memory cell array, forming first source bonding pads having an exposed upper surface and spaced apart from each other in the first source line pads, forming a second peripheral circuit including a third contact bonding pad on a third substrate, forming a second memory cell array including a fourth contact bonding pad on a fourth substrate, flipping the second memory cell array so that the fourth substrate is located at an upper portion and the fourth contact bonding pad is located at a lower portion, and contacting the fourth contact bonding pad of the flipped second memory cell array with the second peripheral circuit, removing the fourth substrate on the second memory cell array and forming a second source line on the second memory cell array, forming second source bonding pads having an exposed upper surface and spaced apart from each other in the second source line, and contacting the first source bonding pad and the second source bonding pad, respectively.

[0012] The present technology can increase the bonding strength of the electrical connection interface between different structures in contact with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing a memory device.

[0014] Figure 2 is a diagram showing a memory cell array.

[0015] Figure 3 is a diagram showing a storage block.

[0016] Figure 4 is a perspective view showing a memory device according to a first embodiment of the present disclosure.

[0017] Figure 5 is a cross-sectional view showing a memory device according to a first embodiment of the present disclosure, showing a peripheral circuit formed on its own substrate joined to two stacked memory devices formed on its own substrate and joined to each other.

[0018] FIG. 6A to FIG. 6D 2 is a diagram showing various layouts of source bonding pads.

[0019] Figure 7 is a diagram showing the layout of a memory device according to the first embodiment of the present disclosure.

[0020] FIG. 8A to FIG. 8J 2 is a diagram illustrating a method for manufacturing a memory device according to a first embodiment of the present disclosure.

[0021] Fig. 9 is a cross-sectional view showing a memory device according to a second embodiment of the present disclosure.

[0022] Fig.10 is a diagram showing a layout of a memory device according to a second embodiment of the present disclosure.

[0023] Fig.11 is a perspective view showing a memory device according to a third embodiment of the present disclosure.

[0024] FIG. 12A to FIG. 12C is a cross-sectional view showing a memory device according to a third embodiment of the present disclosure.

[0025] Fig.13 is a diagram showing a layout of a memory device according to a third embodiment of the present disclosure.

[0026] FIG. 14A to FIG. 14K 2 is a diagram illustrating a method for manufacturing a memory device according to a third embodiment of the present disclosure.

[0027] Fig.15 is a diagram showing a memory card system to which the memory device of the present disclosure is applied.

[0028] Fig.16 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0029] The specific structural or functional description disclosed below describes preferred embodiments of the claimed subject matter. The disclosed embodiments should not be interpreted as limiting the scope of any claims.

[0030] Hereinafter, terms such as first and second may be used to describe various components, but these components are not limited by these terms. The terms first, second, etc. are used to distinguish one component from another component, and do not mean or imply something else.

[0031] Figure 1 is a diagram showing a memory device 100 .

[0032] Reference Figure 1 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 170 .

[0033] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include memory cells capable of storing data. Drain select lines DSL, word lines WL, source select lines SSL, and source lines SL may be connected between the row decoder 130 and each of the first to j-th memory blocks BLK1 to BLKj of the memory cell array 110. Bit lines BL may be connected between the page buffer group 140 and the first to j-th memory blocks BLKj of the same memory cell array 110.

[0034] The first memory block BLK1 to the j-th memory block BLKj may be formed into a two-dimensional structure or a three-dimensional structure. A memory block having a two-dimensional structure may include a memory cell formed by at least two semiconductor material layers formed on top of each other, both layers being on top of and parallel to the substrate. A memory block having a three-dimensional structure may include a memory cell formed by a plurality of separate two-dimensional memory cell structures stacked vertically on each other, and a plurality of two-dimensional memory cell structures are stacked on each other on the substrate. In this embodiment, a memory block formed into a three-dimensional structure is disclosed.

[0035] The memory cell can store 1 bit or 2 bits or more bits of data according to the programming method. For example, the method of storing 1 bit of data in one memory cell is called a single-level cell method. The method of storing 2 bits of data in one memory cell is called a multi-level cell method. The method of storing 3 bits of data in one memory cell is called a three-level cell method, and the method of storing 4 bits of data in one memory cell is called a four-level cell method. In addition, five bits or more of data can be stored in one memory cell.

[0036] The peripheral circuit 170 including the circuits and structures enclosed within the dotted line may be configured to perform a program operation (an operation for storing data in the memory cell array 110). The peripheral circuit 170 may also be configured to perform a read operation (an operation for outputting data stored in the memory cell array 110) and an erase operation (an operation for erasing data stored in the memory cell array 110). Figure 1 As shown, peripheral circuit 170 may include voltage generator 120, row decoder 130, page buffer group 140, column decoder 150, input / output circuit 160, and control circuit 180 (all enclosed within dashed lines).

[0037] The voltage generator 120 may generate various operation voltages Vop for a program operation, a read operation, or an erase operation in response to the operation code OPCD. The voltage generator 120 may therefore be configured to generate a program voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The various operation voltages Vop generated by the voltage generator 120 may be applied to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0038] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. A precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used to determine whether the threshold voltage of a selected memory cell is increased to a target level during a verification operation. The verification voltage may be set to various levels according to a target level, and may be applied to a selected word line.

[0039] The read voltage may be applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage may be set to various levels according to the programming method of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line among the word lines WL during a programming operation or a read operation, and may be used to turn on the memory cells connected to the unselected word lines.

[0040] The erase voltage may be used to erase memory cells included in a selected memory block during an erase operation, and may be applied to the source line SL.

[0041] The row decoder 130 may be configured to send an operating voltage Vop to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL connected to a selected memory block according to a row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through a global line, and may be connected to the first memory block BLK1 to the j-th memory block BLKj through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0042] The page buffer group 140 may include page buffers PB1 to PBn (not shown) connected to the first to j-th memory blocks BLK1 to BLKj. Each page buffer (not shown) may be connected to the first to j-th memory blocks BLK1 to BLKj through a corresponding bit line BL. During a read operation, the page buffer (not shown) may sense a current or voltage of a bit line that varies according to a threshold voltage of a selected memory cell. The page buffer may temporarily store the sensed data in response to a page buffer control signal PBSIG.

[0043] The column decoder 150 may be configured to transfer data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL, and may send an enable signal through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0044] The input / output circuit 160 may be configured to receive or output one or more of a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may send a command CMD and an address ADD received by the input / output circuit 160 from an external controller through the input / output line I / O to the control circuit 180. The input / output circuit 160 may also send data received by the page buffer group 140 from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the same input / output line I / O.

[0045] The control circuit 180 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD received by the control circuit 180 from an external controller (not shown) on an input / output line I / O. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the devices included in the peripheral circuit 170 so that they perform a program operation on a memory block selected by the address ADD received from the external controller. Similarly, when the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the devices included in the peripheral circuit 170 so that they perform a read operation of a memory block selected by an address accompanying the read command and output data read from a memory cell identified or corresponding to the address received together with the read command. When the command CMD input to the control circuit 180 is for an erase operation, the control circuit 180 may control the devices included in the peripheral circuit 170 to perform an erase operation on a memory block selected or corresponding to one or more addresses or address ranges received by the control circuit 180 together with the erase operation command.

[0046] Figure 2 is a diagram showing a portion of a memory cell array.

[0047] Reference Figure 2 , the memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a plurality of memory cells ( Figure 2 1 to 2 (not visible in the figure), which are vertically stacked with each other as described below to form a three-dimensional memory cell array 110. The first to j-th memory blocks BLK1 to BLKj may be arranged to be spaced apart from each other along the Y direction and may extend along the X direction.

[0048] Conceptually but not actually, the first to j-th memory blocks BLK1 to BLKj may be located or positioned between two vertically separated parallel XY planes where the source lines SL and the bit lines BL are located. The source lines SL may be commonly connected to the first to j-th memory blocks BLKj (i.e., connected to each of the first to j-th memory blocks BLKj). Each bit line BL may be commonly connected to the memory cells of each of the first to j-th memory blocks BLK1 to BLKj. The bit lines BL may extend in the Y direction and may be laterally spaced apart from each other along the X direction, so that the bit lines BL are electrically isolated from each other and laterally spaced apart from each other.

[0049] Figure 3 is a memory block BLK1, Figure 1 4 is a diagram of an example of memory blocks BLK1 -BLKj depicted in FIG.

[0050] Reference Figure 3 , the first memory block BLK1 may include a plurality of cell strings ST-STn. The cell strings ST-STn are parallel to each other in the XZ plane and the YZ plane. Each cell string ST-STn is connected between a source line SL and a corresponding bit line among the first to nth bit lines BL1 to BLn.

[0051] The cell strings ST-STn may be connected in common to the source line SL. Some cell strings ST may be connected to the first to nth bit lines BL1 to BLn, respectively, and some other cell strings ST may be connected to the same bit line among the first to nth bit lines BL1 to BLn. For example, the cell strings ST arranged in the X direction may be connected to the first to nth bit lines BL1 to BLn, respectively. The cell strings arranged in the Y direction may be connected to the same bit line.

[0052] The first to nth bit lines BL1 to BLn may be electrically connected to the first to nth page buffers PB1 to PBn, respectively, included in the page buffer group 140. For example, the first bit line BL1 may be electrically connected to the first page buffer PB1, and the nth bit line BLn may be electrically connected to the nth page buffer PBn.

[0053] Each of the plurality of cell strings ST may include a source selection transistor SST, first to i-th memory cells MC1 to MCi, and a drain selection transistor DST. A cell string ST connected to a first bit line BL1 among the plurality of cell strings ST is described as an example as follows.

[0054] The source selection transistor SST may be connected between the source line SL and the first memory cell MC1, and the drain selection transistor DST may be connected between the i-th memory cell MCi and the first bit line BL1. The first to i-th memory cells MC1 to MCi may be connected between the source selection transistor SST and the drain selection transistor DST. The number of the source selection transistors SST and the drain selection transistors DST is not limited to Figure 3 In addition to the first to i-th memory cells MC1 to MCi, dummy cells may be further connected between the source selection transistor SST and the drain selection transistor DST. The first to i-th memory cells MC1 to MCi may store user data or normal data, and the dummy cells may store dummy data.

[0055] The gates of the source selection transistors SST (one of which is included in each different cell string ST) located at the bottom of each cell string ST may be connected to the same source selection line SSL. The gates of the first to i-th memory cells MC1 to MCi included in different cell strings ST may be connected to the corresponding first to i-th word lines WL1 to WLi. The gates of the drain selection transistors DST, each located at the top of each cell string ST and included in each different cell string ST, may be connected to the same drain selection line DSL. The memory cells MC that constitute the cell string ST in the X direction and are connected to the same word line WL constitute a memory page PG. In the memory device 100, a program operation or a read operation of a selected storage block may be performed in units of page PG.

[0056] Figure 4 is a perspective view showing a memory device according to a first embodiment of the present disclosure.

[0057] Reference Figure 4 , the memory device 400 may include a first memory cell array 110a and a second memory cell array 110b stacked on each other in the Z direction. The two stacked memory cell arrays 110a and 110b are also stacked on top of the peripheral circuit 170 in the Z direction.

[0058] The peripheral circuit 170, the first memory cell array 110a, and the second memory cell array 110b can be formed independently of each other on different substrates. The two different memory cell array substrates can then be further processed to contact and bond with each other. The first memory cell array 110a can then be bonded to the peripheral circuit 170, which effectively bonds both memory cell arrays to the peripheral circuit 170.

[0059] The peripheral circuit 170 may be formed on a first substrate 171 , the first memory cell array 110 a may be formed on a second substrate 111 a , and the second memory cell array 110 b may be formed on a third substrate 111 b .

[0060] The first memory cell array 110a, the second memory cell array 110b, and the peripheral circuit 170 each have a top surface and an opposite bottom surface. Figure 4 The top surface of the second memory cell array 110b is identified as 110b-TOP; its bottom surface is identified as 110b-BOT. The top surface of the peripheral circuit 170 is identified as 170-TOP; the bottom surface is identified as 170-BOT.

[0061] When the first memory cell array 110a is formed on the second substrate 111a and the second memory cell array 110b is formed on the third substrate 111b, the first memory cell array 110a may physically touch (i.e., physically contact) the second memory cell array 110b. The second substrate 111a may thereafter be removed from the bottom surface of the first memory cell array 110a. When the second substrate 111a of the first memory cell array 110a is removed from the first memory cell array 110a, a source line and a source bonding pad (BOT) may be formed on the lower surface or bottom surface 110a-BOT of the first memory cell array 110a from which the second substrate is removed. Figure 4 170). The first memory cell array 110a including the formed source bonding pads may then contact and electrically connect to bonding pads or equivalent electrical connection structures on the "upper" surface 170-TOP of the peripheral circuit 170. The first memory cell array 110a may thus be stacked over the peripheral circuit 170 and electrically connected to electrical components of the peripheral circuit 170 via electrical connections extending through both structures 170 and 110a.

[0062] like Figure 5 As shown, the second memory cell array 110b may be inverted and then stacked on the first memory cell array 110a and electrically connected to the components of the first memory cell array 110a. If the third substrate on the bottom of the second memory cell array 110b is removed, a source line may be formed on the exposed bottom surface 110b-BOT of the second memory cell array 110b from which the third substrate is removed.

[0063] Because the top surfaces of the first memory cell array 110a and the second memory cell array 110b face each other, the two memory cell arrays are stacked on each other by connecting the two top surfaces to each other. The stacked combination is then stacked on top of the peripheral circuit 170. Electrical contacts and wires may be formed and appropriately located inside the peripheral circuit 170, and on the surface of the peripheral circuit 170 that cooperates (i.e., contacts and engages) with one or both of the memory cell arrays 110a and 110b. Similarly, electrical contacts and wires may be formed in the memory cell arrays 110a and 110b and on the mating outer surfaces of the first memory cell array 110a and the second memory cell array 110b so that the stacked peripheral circuit 170 and the stacked first memory cell array 110a and the second memory cell array 110b are electrically connected to each other. The electrical contacts and lines formed in and on the outer surfaces of the memory cell arrays 110a, 110b and the peripheral circuit 170 thus enable the peripheral circuit 170 to be independently connected to the two memory cell arrays 110a and 110b (and also to each other). Figure 5The electrically connected peripheral circuit 170 and the first and second memory cell arrays 110 a and 110 b are described.

[0064] Figure 5 is a cross-sectional view showing a memory device according to a first embodiment of the present disclosure.

[0065] like Figure 5 As shown, the second or top memory layer 110b is "inverted" relative to the first or bottom memory layer 110a. The top surfaces of the two memory layers 110a and 110b are therefore considered to be "facing" each other. For simplicity, the memory array layers 110a and 110b are hereinafter referred to as memory cell arrays, i.e., memory cell array 110a and memory cell array 110b.

[0066] Now refer to Figure 5 The peripheral circuit 170 of the first substrate 1SUB (which may be silicon) includes one or more transistors TR, first contacts 1CT and peripheral lines PL. The transistor TR may be a PMOS or NMOS transistor. The first contacts 1CT made of a conductive material may be located and formed in the first substrate 1SUB to electrically connect the components in the first substrate 1SUB and the peripheral lines PL to each other. Other first contacts 1CT may electrically connect the peripheral lines PL to each other. Therefore, the first contacts 1CT and the peripheral lines PL may be formed of a conductive material.

[0067] like Figure 5 As shown on the top mark, Figure 5 The bottom peripheral circuit 170 can be considered to be functionally (but not physically) separated or "partitioned" into Figure 5 The cell area CE on the left and Figure 5 The connection region CN on the right. The cell region CE and the connection region CN can be defined as regions that are laterally adjacent to each other. The cell region CE and the connection region CN are functionally separate regions on the same physical substrate 1SUB. They are not on separate or different physical substrates.

[0068] exist Figure 5 In the illustrated cross section, the cell region CE and the connection region CN are divided from each other at positions along the X direction, but may be divided from each other at positions along the Y direction or the XY direction. Figure 3 The plurality of page buffers depicted in FIG. 1 (including the first page buffer PB1) may be located at Figure 5 The first contact bonding pad 1CbPD may be located on the top surface of the peripheral circuit 170 in the cell region CE and in the connection region CN. Figure 5 Only one page buffer PB is depicted.

[0069] In addition to the page buffer PB, Figure 1 The voltage generator 120, Figure 1 The row decoder 130, Figure 1 The column decoder 150, Figure 1 The input / output circuit 160 and Figure 1 The control circuit 180 may be entirely included in the cell region CE and the connection region CN of the peripheral circuit 170. For simplicity of illustration, Figure 5 These structures are omitted.

[0070] A peripheral gap-filling layer pTIS may be formed between and around the transistor TR, the first contact 1CT, the peripheral line PL, a plurality of page buffers including the first page buffer PB1, and the first contact bonding pad 1CbPD, and the peripheral gap-filling layer pTIS may be an insulating or dielectric material and identified by stippling.

[0071] Figure 5 The first contact bonding pad 1CbPD located at the top 170-TOP of the peripheral circuit 170 may be in direct contact with the upper portion of the first contact 1CT in the peripheral circuit 170 and may be made of a conductive material such as tungsten (W). Figure 5 The peripheral circuit 170 shown is located in different layers and extends to Figure 5 Plane neutralization Figure 5 The peripheral lines PL outside the plane of the PCB can be electrically connected to each other through the first contact 1CT. Figure 5 In the vertical cross section of FIG. 1 , some peripheral lines PL that are spaced apart from each other and arranged on the same XY plane may be connected to each other.

[0072] The first memory cell array 110a stacked on the peripheral circuit 170 may include a line insulation layer LIS between each gate line GL, a second contact bonding pad 2CbPD, a first source line 1SL, a source bonding pad SbPD, a gate line GL, a sacrificial layer SF, a cell plug CP, a second contact 2CT, a first source contact 1SCT, a page buffer contact PCT, a gate line contact GCT, a first power contact 1WCT, a third contact bonding pad 3CbPD, a first bit line group BL1a and a first cell interlayer insulating layer 1cTIS.

[0073] The first source line 1SL and the source bonding pad SbPD in contact with the peripheral circuit 170 may be located in the cell area CE of the first memory cell array 110a. Because the first source line 1SL is used as a source line in the first memory cell array 110a, the first source line 1SL may be formed by a conductive layer. For example, the first source line 1SL may be formed by polysilicon. Inside the first source line 1SL, a source bonding pad SbPD of a peripheral gap filling layer pTIS contacting the peripheral circuit 170 may be included. The source bonding pad SbPD may be exposed through the lower surface of the first source line 1SL. The lower surface of the source bonding pad SbPD and the first source line 1SL may be located on the same plane. Therefore, the first source line 1SL and the source bonding pad SbPD may be in contact with the peripheral circuit 170. For example, in the cell region CE, since the peripheral gap filling layer pTIS is exposed through the upper surface of the peripheral circuit 170, the first source line 1SL and the source bonding pad SbPD exposed through the lower surface of the first memory cell array 110a may contact the peripheral gap filling layer pTIS. Since the peripheral gap filling layer pTIS is formed of an insulator or a dielectric, the bonding strength between the first source line 1SL as a conductive layer and the peripheral gap filling layer pTIS may be reduced. Since the source bonding pad SbPD is formed of a dielectric, the bonding strength between the peripheral gap filling layer pTIS and the source bonding pad SbPD may be greater than the bonding strength with the first source line 1SL.

[0074] Now referring to the enlarged views AA and BB, which show how and where portions of the source bonding pad SbPD and the peripheral gap filling layer pTIS contact each other, the source bonding pad SbPD may be formed as a single layer including a first dielectric layer 51. The peripheral gap filling layer pTIS may also be formed as a single layer of an insulating layer or a dielectric layer. Referring to the enlarged view "BB", each source bonding pad SbPD may be formed as a multilayer including a first dielectric layer 51 and a second dielectric layer 52a. The second dielectric layer 52a may be a dielectric material different from the dielectric material of the first dielectric layer 51. A third dielectric layer 52b may be further formed on the upper surface of the peripheral gap filling layer pTIS. The third dielectric layer 52b may be the same material as the second dielectric layer 52a.

[0075] Since the source bonding pad SbPD is included under the first source line 1SL, bonding strength between the peripheral circuit 170 and the first memory cell array 110a in the cell region CE may be increased.

[0076] The wire insulating layer LIS and the gate line GL may be alternately stacked on the first source line 1SL. The wire insulating layer LIS and the gate line GL may be stacked in a step shape. For example, a pair of the wire insulating layer LIS and the gate line GL may form a step. The wire insulating layer LIS may be an oxide layer, and the gate line GL may be a conductive layer. For example, the gate line GL may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polycrystalline silicon (poly-Si), and may be formed of various other conductive layers.

[0077] The cell plugs CP extending through the line insulation layer LIS and the gate line GL in the Z direction may be arranged so that the cell plugs CP are spaced apart from each other in the X, Y or XY direction and are vertically parallel to each other. Among the cell plugs CP, the portion surrounded by the gate line GL may be a source selection transistor, a memory cell or a drain selection transistor. The lower portion of the cell plug CP may contact the first source line 1SL. For example, the lower end or lower surface of the cell plug CP may contact the first source line 1SL.

[0078] like Figure 5 As shown, the first bit line group BL1a may be arranged on or at the top of the cell plug CP. The cell plug CP may thus be considered to be vertically located between the bit line BL at or near the top of the cell plug CP and the source line SL at or near the bottom of the cell plug CP.

[0079] The first bit line group BL1a may include a bit line electrically connected to the cell plug CP. For example, the bit line BL included in the first bit line group BL1a may contact the cell plug CP through the second contact 2CT. Some lines or some pads located on different layers in the first memory cell array 110a may be electrically connected to each other through the second contact 2CT. For example, the gate line GL having a step structure may contact the second contact bonding pad 2CbPD through the second contact 2CT. The second contact bonding pad 2CbPD may be formed by a conductive layer. For example, the second contact bonding pad 2CbPD may be formed by tungsten (W).

[0080] Line insulation layers LIS and sacrificial layers SF alternately stacked on the peripheral circuit 170 may be formed in the connection region CN of the first memory cell array 110a. Third contact bonding pads 3CbPD respectively contacting the first contact bonding pads 1CbPD may be formed in the lowermost line insulation layer LIS. The third contact bonding pads 3CbPD may be formed of a conductive material such as tungsten (W).

[0081] The first source contact 1SCT, the page buffer contact PCT, the gate line contact GCT, and the first power contact 1WCT may pass through the line insulating layer LIS and the sacrificial layer SF between the third contact bonding pad 3CbPD and the second contact bonding pad 2CbPD.

[0082] The first source contact 1SCT, the page buffer contact PCT, the gate line contact GCT and the first power contact 1WCT may be formed of a conductive material. The first source contact 1SCT, the page buffer contact PCT, the gate line contact GCT and the first power contact 1WCT may be electrically connected to the third contact pad 3CbPD and the second contact pad 2CbPD through the second contact 2CT.

[0083] The first source contact 1SCT may be electrically connected to the peripheral circuit 170 and the first source line 1SL through the third contact bonding pad 3CbPD. The side surface of the third contact bonding pad 3CbPD in contact with the first source contact 1SCT may be surrounded by a contact liner layer cLN, and the contact liner layer cLN may be formed of a conductive material such as titanium Ti or titanium silicide TiSi. Since the contact liner layer cLN and the third contact bonding pad 3CbPD are formed of a conductive layer, the source voltage generated in the peripheral circuit 170 may be transmitted to the first source line 1SL through the first contact bonding pad 1CbPD, the third contact bonding pad 3CbPD, and the contact liner layer cLN. The source voltage may be a ground voltage, a positive voltage, or a negative voltage. Since the first source contact 1SCT is in contact with the third contact bonding pad 3CbPD, the voltage applied to the third contact bonding pad 3CbPD may be transmitted to the second contact bonding pad 2CbPD located in the upper region of the first memory cell array 110a.

[0084] The page buffer contact PCT may be located between the third contact bonding pad 3CbPD and the second contact bonding pad 2CbPD. The page buffer contact PCT may be electrically connected to the page buffer PB through the first contact 1CT and the first contact bonding pad 1CbPD of the peripheral circuit 170. The first sub-bit line 1sBL connected to the first bit line group BL1a may be located between the page buffer contact PCT and the second contact bonding pad 2CbPD. For example, the bit line included in the first bit line group BL1a may be electrically connected to the page buffer PB of the peripheral circuit 170 through the first sub-bit line 1sBL and the page buffer contact PCT. The page buffer contact PCT connected to different bit lines may be connected to different page buffers PB included in the peripheral circuit 170.

[0085] The gate line contact GCT can be electrically connected to the gate line GL of the cell area CE through the first gate transfer line 1gTL and the second contact 2CT. For example, the word line voltage generated in the peripheral circuit 170 can be transmitted to the selected gate line GL through the first contact bonding pad 1CbPD, the gate line contact GCT, the first gate transfer line 1gTL and the second contact 2CT.

[0086] The first power contact 1WCT may supply external power applied through the second memory cell array 110 b to the peripheral circuit 170 through the second contact bonding pad 2CbPD and the first contact bonding pad 1CbPD.

[0087] The second memory cell array 110b, which is inverted or "reversed" relative to the first memory cell array 110a, can be a structure symmetrical with the remaining configuration except for the page buffer contact PCT, gate line contact GCT, source bonding pad SbPD and third contact bonding pad 3CbPD of the first memory cell array 110a.

[0088] For example, the second memory cell array 110b may include a structure that is symmetrical to the first memory cell array 110a but inverted relative to the XY plane. Therefore, the first cell interlayer insulating layer 1cTIS of the second memory cell array 110b and the first cell interlayer insulating layer 1cTIS of the first memory cell array 110a are vertically adjacent to each other in the Z direction and are in direct mechanical contact with each other. Figure 5 As shown, the second contact bonding pad 2CbPD located at the "top" of the "inverted" or reversed second memory cell array 110b (i.e., relative to the first memory cell array 110a) and the second contact bonding pad 2CbPD located at the top of the upright first memory cell array 110a are mechanically bonded to each other and electrically bonded to each other. The bonding between the second contact bonding pads 2CbPD in the first memory cell array 110a and the second memory cell array 110b enables the exchange of electrical signals between the two memory cell arrays 110a and 110b. Figure 5 Stacking multiple memory array devices on top of each other and stacking the stacked memory array devices on peripheral circuits thus provides a memory array device with double the data capacity within the same area or footprint required for a single memory array device.

[0089] The second source contact 2SCT included in the second memory cell array 110b can be electrically connected to the first source contact 1SCT of the first memory cell array 110a through the corresponding second contact bonding pads 2CbPD in the memory cell arrays 110a and 110b. Therefore, the source voltage applied to the first source contact 1SCT can be transmitted to the second source line 2SL of the second memory cell array 110b through the second source contact 2SCT.

[0090] The bit lines included in the second bit line group BL1b included in the second memory cell array 110b may be electrically connected to the page buffer PB of the peripheral circuit 170 through the second sub bit line 2sBL, the second contact bonding pad 2CbPD, the page buffer contact PCT, the third contact bonding pad 3CbPD, and the first contact bonding pad 1CbPD. Therefore, the page buffer PB of the peripheral circuit 170 may be simultaneously connected to the first bit line group BL1a of the first memory cell array 110a and the second bit line group BL1b of the second memory cell array 110b.

[0091] The gate line GL of the second memory cell array 110b can be electrically connected to the gate line contact GCT through the second contact 2CT, the second contact bonding pad 2CbPD and the second gate transmission line 2gTL. Therefore, the word line voltage generated in the peripheral circuit 170 can be transmitted to the selected gate line GL of the first memory cell array 110a and the second memory cell array 110b through the gate line contact GCT, the first gate transmission line 1gTL and the second gate transmission line 2gTL.

[0092] The external power pad ePWR_PD at the topmost layer of the stack of layers 170, 110a and 110b may preferably be formed on the "bottom" 110b-BOT of the second memory cell array 110b before the second memory cell array 110b is inverted and bonded to the first memory cell array 110a, so that the external power pad ePWR_PD is easily accessible after the second memory cell array 110b is inverted and bonded to the first memory cell array 110a. The external power pad ePWR_PD may be electrically connected to the first power contact 1WCT of the first memory cell array 110a through the third contact bonding pad 3CbPD, the second power contact 2WCT and the second contact bonding pad 2CbPD of the second memory cell array 110b.

[0093] As used herein, a horizontal cross section (also referred to as a parallel cross section) is a two-dimensional shape formed or made when a geometric plane cuts a solid shape in a horizontal direction such that the cut geometric plane produces a cross-sectional shape parallel to the base.

[0094] FIG. 6A to FIG. 6D are diagrams showing various horizontal cross-sectional shapes / layouts of source bonding pads.

[0095] Reference Figure 5 and Fig. 6A, the first source line 1SL of the first memory cell array 110a may include a source bonding pad SbPD contacting the peripheral gap filling layer pTIS of the peripheral circuit 170. Since the source bonding pad SbPD is included in the first source line 1SL, a size increase due to the source bonding pad SbPD does not occur. The source bonding pads SbPD may be formed to be spaced apart from each other within the first source line 1SL. Fig. 6A As shown, the source bonding pad SbPD may be formed to have a substantially rectangular horizontal cross-sectional shape with a major axis extending in the Y direction and a minor axis extending in the X direction, and may be spaced apart from adjacent source bonding pads SbPD in the X direction.

[0096] Reference Figure 5 and Figure 6B , each source bonding pad SbPD may be formed to have a substantially rectangular shape (in Figure 6B ) or a generally square shape (best shown in Figure 6C ). The source bonding pads SbPD may be arranged to be spaced apart from each other along the X or Y direction and staggered in a zigzag direction.

[0097] Reference Figure 5 and Figure 6C , each source bonding pad SbPD may be formed to have a substantially square shape. The source bonding pads SbPD may be arranged in a matrix form spaced apart from each other in the X or Y direction.

[0098] Reference Figure 5 and Fig.6D , each source bonding pad SbPD may be formed in a circular or elliptical shape. The source bonding pads SbPD may be arranged to be spaced apart from each other in a staggered or zigzag direction in the X or Y direction.

[0099] Figure 7 is a vertical cross-sectional view showing the layout of the memory device according to the first embodiment of the present disclosure.

[0100] Reference Figure 5 and Figure 7 , a memory device including first to sixteenth page buffers PB1 to PB16 in the peripheral circuit 170 is shown as an example, but the number of page buffers may vary according to the memory device.

[0101] The first to sixteenth page buffers PB1 to PB16 included in the peripheral circuit 170 may be connected to the bit lines BL1-1 to BL16-1 included in the first memory cell array 110a and the bit lines BL1-2 to BL16-2 included in the second memory cell array 110b, respectively. For example, the first page buffer PB1 may be commonly connected to the (1-1)th bit line BL1-1 of the first memory cell array 110a and the (1-2)th bit line BL1-2 of the second memory cell array 110b. The second page buffer PB2 may be commonly connected to the (2-1)th bit line BL2-1 of the first memory cell array 110a and the (2-2)th bit line BL2-2 of the second memory cell array 110b. In this method, the sixteenth page buffer PB16 may be commonly connected to the (16-1)th bit line BL16-1 of the first memory cell array 110a and the (16-2)th bit line BL16-2 of the second memory cell array 110b. That is, the first bit line BL1 connected to the first page buffer PB1 may be divided into the (1-1)th bit line BL1-1 included in the first memory cell array 110a and the (1-2)th bit line BL1-2 included in the second memory cell array 110b, and the (1-1)th bit line BL1-1 and the (1-2)th bit line BL1-2 may be electrically connected to each other. In this method, the sixteenth bit line BL16 connected to the sixteenth page buffer PB16 may be divided into the (16-1)th bit line BL16-1 included in the first memory cell array 110a and the (16-2)th bit line BL16-2 included in the second memory cell array 110b, and the (16-1)th bit line BL16-1 and the (16-2)th bit line BL16-2 may be electrically connected to each other.

[0102] FIG. 8A to FIG. 8J 1 is a diagram showing steps of a method for manufacturing the above-mentioned memory device.

[0103] Reference Fig. 8A , a transistor TR, a first contact 1CT and a peripheral line PL may be formed on the first substrate 1SUB. Each transistor TR may include a gate insulating layer GI and a gate conductive layer CD. The gate insulating layer GI may be formed of an oxide layer. The gate conductive layer CD may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) and polycrystalline silicon (poly-Si), and may be formed of various other conductive layers. The first contact 1CT and the peripheral line PL may also be formed of a conductive layer. A portion of the first contact 1CT may contact the source or drain of the transistor TR, and some peripheral lines PL located in different layers may be connected to each other. Some peripheral lines PL located on the same layer may be electrically connected to each other. A peripheral gap filling layer pTIS may be formed between the transistor TR, the first contact 1CT and the peripheral line PL.

[0104] Reference Figure 8B In order to form a first memory cell array, a first buffer layer 1BF may be formed on a second substrate 2SUB. Alternatingly stacked wire insulation layers LIS and gate lines GL are superimposed on the first buffer layer 1BF. A cell plug CP extending through (i.e., passing through) the wire insulation layer LIS and the gate line GL may be formed. The wire insulation layer LIS may be formed of an oxide layer. The gate line GL may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (poly-Si), but may be formed of various other conductive layers. The cell plug CP may be formed in a first vertical hole 1VH passing through the wire insulation layer LIS and the gate line GL.

[0105] Referring to the plan view 81 of the cell plug CP formed in the XY plane and extending downward in the Z direction through the alternately stacked layers, each cell plug CP may include a core column CR, a channel layer CH formed around the core column CR, and a memory layer ML formed around the channel layer CH. The memory layer ML may include a tunnel isolation layer TX, a charge capture layer CA, and a barrier layer BX. The core column CR may have a cylindrical shape and may be formed of an insulating material or a conductive material. The channel layer CH may have a cylindrical shape around the side surface of the core column CR and may be formed of polysilicon. The tunnel isolation layer TX may have a cylindrical shape around the side surface of the channel layer CH and may be formed of an oxide layer. The charge capture layer CA may have a cylindrical shape around the side surface of the tunnel isolation layer TX and may be formed of a nitride layer. The barrier layer BX may have a cylindrical shape around the side surface of the charge capture layer CA and may be formed of an oxide layer.

[0106] Since the second substrate 2SUB and the first buffer layer 1BF need to be removed in a subsequent process, the first buffer layer 1BF may be formed of a material having a higher etching selectivity than the line insulating layer LIS and the cell plug CP.

[0107] Reference Figure 8C, a first insulating layer 1TIS may be formed on the entire structure including the cell plug CP, and a bit line contact bCT that contacts the cell plug CP by passing through the first insulating layer 1TIS may be formed. The first insulating layer 1TIS may be formed of an oxide layer, and the bit line contact bCT may be formed of a conductive layer. Subsequently, a second insulating layer 2TIS and a bit line BL may be formed on the bit line contact bCT and the first insulating layer 1TIS. The second insulating layer 2TIS may be formed of an oxide layer, and the bit line BL may be formed of a conductive layer. The second insulating layer 2TIS may be formed on the bit line contact bCT and the first insulating layer 1TIS. A trench Tc exposing the bit line contact bCT may be formed. The width of each trench Tc may be wider than the width of each bit line contact bCT. A conductive layer may be formed on the trench Tc and the second insulating layer 2TIS to fill the inside of the trench Tc, and then an etching process or a planarization process may be performed until the second insulating layer 2TIS is exposed. A third insulating layer 3TIS may be formed on the bit line BL and the second insulating layer 2TIS, and thus a first cell interlayer insulating layer 1cTIS including the first to third insulating layers 1TIS to 3TIS may be formed. Thus, a first memory cell array 110a including cell plugs CP may be formed.

[0108] Reference Fig.8D , a second memory cell array 110b may be formed on the third substrate 3SUB. The second memory cell array 110b may be formed in accordance with Figure 8C The same structure as the first memory cell array 110a may be formed. For example, a second buffer layer 2BF may be formed on the third substrate 3SUB, and a line insulating layer LIS and a gate line GL alternately stacked on the second buffer layer 2BF and a cell plug CP passing through the line insulating layer LIS and the gate line GL may be formed. The line insulating layer LIS may be formed of an oxide layer, and the gate line GL may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (poly-Si), and may be formed of various other conductive layers. The cell plug CP may be formed in the same manner as in the reference. Figure 8B The same structure as described above is formed in the cell plug CP. In the second memory cell array 110b, the bit lines BL and the bit line contacts bCT may be covered by the second cell interlayer insulating layer 2cTIS.

[0109] Reference Fig. 8E , the first memory cell array 110a can be contacted on the second memory cell array 110b. For example, by referring to Figure 8C The entire structure is described to be reversed, with the first memory cell array 110a at the bottom and the second substrate 2SUB at the top. Subsequently, the first cell interlayer insulating layer 1cTIS of the first memory cell array 110a may contact on the second cell interlayer insulating layer 2cTIS of the second memory cell array 110b.

[0110] Reference Figure 8F , remove Fig. 8E The second substrate 2SUB and the first buffer layer 1BF located on the first memory cell array 110a. The second substrate 2SUB and the first buffer layer 1BF may be removed by a wet etching process. When the first buffer layer 1BF is removed and the line insulating layer LIS and the cell plug CP are exposed, a first source line 1SL may be formed on the exposed cell plug CP and the line insulating layer LIS. The first source line 1SL may be formed of a conductive layer. For example, the first source line 1SL may be formed of polysilicon. After forming the first source line 1SL, an opening OP may be formed by removing a portion of an upper portion of the first source line 1SL. The opening OP may have a rectangular, square, circular, or elliptical shape and may be spaced apart from each other.

[0111] Reference Figure 8G , a source bonding pad SbPD may be formed in the opening OP. The source bonding pad SbPD may be formed of a dielectric material. In one embodiment, a dielectric layer may be formed over the entire structure so that the opening OP is filled with the dielectric material. A planarization process may then be performed to make the upper surface of the first source line 1SL and the source bonding pad SbPD substantially flat, wherein the flatness or surface roughness may be quantified by calculating an arithmetic mean for a randomly sampled area.

[0112] Reference Figure 8H The stacked structure of the first memory cell array 110a and the second memory cell array 110b can be similar to that of the reference Fig. 8A For example, by referring to Figure 8G The entire structure described is flipped, with the first memory cell array 110a located at the bottom and the second memory cell array 110b located at the top. The source bonding pad SbPD included in the first source line 1SL of the first memory cell array 110a may contact the peripheral gap filling layer pTIS of the peripheral circuit 170. Because the source bonding pad SbPD is included in the first source line 1SL and the source bonding pad SbPD contacts the peripheral gap filling layer pTIS, the bonding strength between the first source line 1SL and the peripheral circuit 170 may be increased.

[0113] Reference Fig.8I , can be removed Figure 8H The third substrate 3SUB and the second buffer layer 2BF located on the second memory cell array 110b may be formed. For example, the third substrate 3SUB and the second buffer layer 2BF may be removed by a wet etching process, but the present disclosure is not limited to the wet etching process. When the second buffer layer 2BF is removed, the line insulation layer LIS and the cell plug CP included in the second memory cell array 110b may be exposed.

[0114] Reference Figure 8J , a second source line 2SL may be formed on the exposed cell plug CP and the line insulating layer LIS. The second source line 2SL may be formed of a conductive layer. For example, the second source line 2SL may be formed of polysilicon.

[0115] Fig. 9 is a vertical cross-sectional view showing a memory device according to a second embodiment of the present disclosure.

[0116] Reference Fig. 9 , since the memory device according to the second embodiment includes a structure similar to that of the memory device according to the first embodiment, FIG. 8A to FIG. 8J Description of the same structure as that of the first embodiment is repeated as described in FIG.

[0117] exist Fig. 9 In the second embodiment depicted in FIG, positions of the bit lines included in the first bit line group BL1a of the first memory cell array 110a and positions of the bit lines included in the second bit line group BL1b of the second memory cell array 110b match each other in the Z direction. However, in the second embodiment, positions of the bit lines included in the first bit line group BL1a of the first memory cell array 110a and positions of the bit lines included in the second bit line group BL1b of the second memory cell array 110b may not match each other in the Z direction. For example, the bit lines included in the second bit line group BL1b of the second memory cell array 110b may be located on a region between the bit lines included in the first bit line group BL1a of the first memory cell array 110a.

[0118] In the second embodiment, the bit lines included in the first bit line group BL1a may be electrically disconnected from the bit lines included in the second bit line group BL1b. For example, in the connection region CN of the first memory cell array 110a, a first page buffer contact 1PCT for electrically connecting the first bit line group BL1a included in the first memory cell array 110a and the page buffer PB1a of the peripheral circuit 170 and a third page buffer contact 3PCT for electrically connecting the second bit line group BL1b included in the second memory cell array 110b and the page buffer PB1b of the peripheral circuit 170 may be included. The page buffer PB1a connected to the first page buffer contact 1PCT is different from the page buffer PB1b connected to the third page buffer contact 3PCT. The first page buffer contact 1PCT may be electrically connected to the first bit line group BL1a included in the first memory cell array 110a through the first gate transmission line 1gTL. The third page buffer contact 3PCT may be electrically connected to the second bit line group BL1b included in the second memory cell array 110b through the second contact bonding pad 2CbPD and the second gate transmission line 2gTL.

[0119] Fig.10 is a diagram showing a layout of a memory device according to a second embodiment of the present disclosure.

[0120] Reference Fig. 9 and Fig.10 , because the first bit line group BL1a included in the first memory cell array 110a and the second bit line group BL1b included in the second memory cell array 110b are electrically separated from each other, the first bit line group BL1a included in the first memory cell array 110a may include odd bit lines BL1, BL3, BL5, ... and BL15, and the second bit line group BL1b included in the second memory cell array 110b may include even bit lines BL2, BL4, BL6, ... and BL16. Fig.10 16 bit lines are shown, however, the number of bit lines may vary depending on the memory device. For example, the first bit line BL1 included in the first memory cell array 110a may be connected to the first page buffer PB1 included in the peripheral circuit 170, and the second bit line BL2 included in the second memory cell array 110b may be connected to the second page buffer PB2 included in the peripheral circuit 170. In this method, the fifteenth bit line BL15 included in the first memory cell array 110a may be connected to the fifteenth page buffer PB15 included in the peripheral circuit 170, and the sixteenth bit line BL16 included in the second memory cell array 110b may be connected to the sixteenth page buffer PB16 included in the peripheral circuit 170.

[0121] Fig.11 is a perspective view showing a memory device according to a third embodiment of the present disclosure.

[0122] Reference Fig.11 In the memory device according to the third embodiment, structures manufactured on four different substrates may be stacked on each other. For example, the first memory cell array 110a may be stacked on the first peripheral circuit 170a. Before or after the first memory cell array 110a is stacked over the first peripheral circuit, the second memory cell array 110b may be stacked on the first memory cell array 110a. Before or after the second memory cell array 110b is stacked on the first memory cell array 110a, the second peripheral circuit 170b may be stacked on the second memory cell array 110b.

[0123] The first peripheral circuit 170a and the second peripheral circuit 170b may each be embodied as Figure 1 The first memory cell array 110a and the second memory cell array 110b may each be specifically implemented as Figure 1 A memory cell array 110 is shown.

[0124] FIG. 12A to FIG. 12C is a cross-sectional view showing a memory device according to a third embodiment of the present disclosure.

[0125] Reference Fig.11 and Fig. 12A , the page buffer PB1a may be included in the cell region CE of the first peripheral circuit 170a. The transistor TR electrically connected to the gate line GL of the first memory cell array 110a may also be included in the cell region CE. In the connection region CN of the first peripheral circuit 170a, a transistor configured to generate and output a source voltage may be included. The first contact bonding pad 1CbPD included in the first peripheral circuit 170a may be exposed through the upper surface of the first peripheral circuit 170a.

[0126] The first memory cell array 110a may be configured in the same manner as in the first embodiment. Figure 5 The structure of the second memory cell array 110b is similar to that of the second memory cell array 110b. For example, Fig. 12A The illustrated first memory cell array 110a may include second contact bonding pads 2CbPD, a first bit line group BL1a, a stack STK, first source lines 1SL, third contact bonding pads 3CbPD, cell plugs CP, first source contacts 1SCT, and first power contacts 1WCT.

[0127] The second contact pad 2CbPD may be located below the first memory cell array 110a and may contact the upper surface of the first contact pad 1CbPD of the first peripheral circuit 170a, respectively. The stack STK may be located on the second contact pad 2CbPD and may include an insulating layer, a gate line, and a sacrificial layer. For example, the insulating layer and the gate line may be alternately stacked in the cell region CE of the stack STK, and the insulating layer and the sacrificial layer may be alternately stacked in the connection region CN. The stack STK of the cell region CE may have a stepped structure in which the length becomes shorter from the upper part to the lower part. The cell plug CP may pass through the stack STK of the cell region CE. The bit line BL1a may be located between the cell plug CP and the second contact pad 2CbPD. The cell plug CP, the first bit line group BL1a, the second contact pad 2CbPD, the first contact pad 1CbPD, and the page buffer PB1a may be electrically connected to each other through the contact CT. The gate line GL of the cell region CE may also be electrically connected to the second contact bonding pad 2CbPD, the first contact bonding pad 1CbPD, and the transistor of the first peripheral circuit 170a through the contact CT. A portion of the upper portion of the cell plug CP may be in contact with the first source line 1SL. The first source bonding pad 1SbPD may be included in the first source line 1SL. For example, the first source bonding pad 1SbPD may be exposed through the upper surface of the first source line 1SL. The first source contact 1SCT and the first power contact 1WCT may pass through the stack STK of the connection region CN and may be located between the second contact bonding pad 2CbPD and the third contact bonding pad 3CbPD.

[0128] The second memory cell array 110b may be implemented in a structure that is symmetrical or identical to the first memory cell array 110a. For example, the second memory cell array 110b may be implemented in a structure that is symmetrical to the first memory cell array 110a about the XY plane. Therefore, the second memory cell array 110b and the first memory cell array 110a may contact each other through the second source bonding pad 2SbPD and the third contact bonding pad 3CbPD. In addition, the first memory cell array 110a and the second memory cell array 110b may also contact each other through the cell interlayer insulating layer.

[0129] The second peripheral circuit 170b may be implemented in a symmetrical structure with the first peripheral circuit 170a and may be contacted on the second memory cell array 110b. The page buffer PB1b of the second peripheral circuit 170b may be electrically connected to the second bit line group BL1b of the second memory cell array 110b through the first contact bonding pad 1CbPD included in the second peripheral circuit 170b, the second contact bonding pad 2CbPD included in the second memory cell array 110b, and the contact CT.

[0130] That is, in the memory device according to the third embodiment, the page buffer PB1a of the first peripheral circuit 170a can be connected to the bit lines included in the first bit line group BL1a of the first memory cell array 110a, and the page buffer PB1b of the second peripheral circuit 170b can be connected to the bit lines included in the second bit line group BL1b of the second memory cell array 110b.

[0131] Reference Fig. 12B , the source voltage applied to the first source line 1SL of the first memory cell array 110a and the second source line 2SL of the second memory cell array 110b may be supplied through the first peripheral circuit 170a. For example, the first source contact 1SCT connected to the first peripheral circuit 170a may be located only in the connection area CN of the first memory cell array 110a. Therefore, the source voltage generated in the first peripheral circuit 170a may be supplied to the first source line 1SL and the second source line 2SL through the first source contact 1SCT of the first memory cell array 110a. Because the remaining structure except the first source contact 1SCT is the same as Fig. 12A The structures shown are the same, so repeated descriptions are omitted.

[0132] Reference Fig. 12C , the source voltage applied to the first source line 1SL of the first memory cell array 110a and the second source line 2SL of the second memory cell array 110b may be supplied through the second peripheral circuit 170b. For example, the second source contact 2SCT connected to the second peripheral circuit 170b may be located only in the connection area CN of the second memory cell array 110b. Therefore, the source voltage generated in the second peripheral circuit 170b may be supplied to the first source line 1SL and the second source line 2SL through the second source contact 2SCT of the second memory cell array 110b. Because the remaining structure except the second source contact 2SCT is the same as Fig. 12A The structures shown are the same, so for the sake of brevity, their redundant descriptions are omitted.

[0133] Fig.13 is a diagram showing a layout of a memory device according to a third embodiment of the present disclosure.

[0134] Reference FIG. 12A to FIG. 12C and Fig.13 , the first peripheral circuit 170a may include first to eighth page buffers PB1 to PB8, and the second peripheral circuit 170b may include ninth to sixteenth page buffers PB9 to PB16. The number of page buffers PB1a and PB1b included in each of the first peripheral circuit 170a and the second peripheral circuit 170b is not limited to Fig.13 Quantity shown.

[0135] The first memory cell array 110a may include first to eighth bit lines BL1 to BL8 included in the first bit line group BL1a, and the second memory cell array 110b may include ninth to sixteenth bit lines BL9 to BL16 included in the second bit line group BL1b. The number of bit lines BL1 to BL16 included in each of the first memory cell array 110a and the second memory cell array 110b is not limited to Fig.13 Quantity shown.

[0136] The first to eighth page buffers PB1 to PB8 included in the first peripheral circuit 170a may be respectively connected to the first to eighth bit lines BL1 to BL8 included in the first memory cell array 110a, and the ninth to sixteenth page buffers PB9 to PB16 included in the second peripheral circuit 170b may be respectively connected to the ninth to sixteenth bit lines BL9 to BL16 included in the second memory cell array 110b.

[0137] FIG. 14A to FIG. 14K is a diagram showing steps of a method for manufacturing a memory device according to a third embodiment of the present disclosure. FIG. 14A to FIG. 14K In the structure shown, for the sake of simplicity, FIG. 8A to FIG. 8J Description of the structure shown in and described above.

[0138] Reference Fig.14A , a first peripheral circuit 170a may be formed on the first substrate 1SUB. The first peripheral circuit 170a may include a page buffer PB, a contact CT, a peripheral line PL, and a first contact bonding pad 1CbPD, and may also include the above reference Figure 1 At least one circuit among the circuits included in the described peripheral circuit 170. The contact CT, the peripheral line PL, and the first contact bonding pad 1CbPD may be formed of a conductive material. The area around the page buffer PB, the contact CT, the peripheral line PL, and the first contact bonding pad 1CbPD may be filled with a peripheral gap filling layer pTIS. The peripheral gap filling layer pTIS may be formed as an insulating layer. For example, the peripheral gap filling layer pTIS may be formed of an oxide layer, more specifically, may be formed of a silicon oxide layer.

[0139] Reference Fig. 14B, a first memory cell array 110a may be formed on the second substrate 2SUB. For example, the first memory cell array 110a may include a first buffer layer 1BF, a wire insulating layer LIS, a gate line GL, a cell plug CP, a bit line contact bCT, a bit line BL, a contact CT, a second contact bonding pad 2CbPD, and a first cell interlayer insulating layer 1cTIS located on the second substrate 2SUB. For example, the first buffer layer 1BF may be formed of a material having an etching selectivity relative to the wire insulating layer LIS and the cell plug CP, and may cover the second substrate 2SUB. The wire insulating layer LIS and the gate line GL may be alternately stacked on the first buffer layer 1BF. The wire insulating layer LIS may be an oxide layer, and the gate line GL may be a conductive layer. The cell plug CP may contact the first buffer layer 1BF by passing through the wire insulating layer LIS and the gate line GL. The cell plug CP may be arranged in accordance with the reference Figure 8B The cell plug CP described above is formed with the same structure. The bit line contact bCT, the bit line BL, the contact CT and the second contact pad 2CbPD may be located on the cell plug CP. The second contact pad 2CbPD may be formed with the same structure as that of the cell plug CP described above. Fig.14A The first unit interlayer insulating layer 1cTIS may be formed of the same material as the first contact bonding pad 1CbPD. The first unit interlayer insulating layer 1cTIS may be formed around the bit line contact bCT, the bit line BL, the contact CT, and the second contact bonding pad 2CbPD. The first unit interlayer insulating layer 1cTIS may be formed as an insulating layer. For example, the first unit interlayer insulating layer 1cTIS may be formed of an oxide layer, more specifically, may be formed of a silicon oxide layer.

[0140] Reference Fig. 14C , the first memory cell array 110a may be contacted on the first peripheral circuit 170a. For example, by referring to Fig. 14B The entire structure described is flipped, the second contact bonding pad 2CbPD is located at the bottom, and the second substrate 2SUB is located at the top. The upper surface of the first peripheral circuit 170a and the lower surface of the first memory cell array 110a are in contact with each other, and a bonding process of a heat treatment method may be performed. Due to the bonding process, the peripheral gap filling layer pTIS of the first peripheral circuit 170a and the first cell interlayer insulating layer 1cTIS of the first memory cell array 110a may be in contact with each other, and the first contact bonding pad 1CbPD of the first peripheral circuit 170a and the second contact bonding pad 2CbPD of the first memory cell array 110a may be in contact with each other.

[0141] Reference Fig.14D , the first memory cell array 110a may be removed. Fig. 14C The second substrate 2SUB and Fig. 14CThe first buffer layer 1BF may be formed by a wet etching process to remove the second substrate 2SUB. For example, a wet etching process for removing the second substrate 2SUB may be performed. The first buffer layer 1BF may protect the cell plug CP when the second substrate 2SUB is removed. The first buffer layer 1BF may be removed by a wet or dry etching process. When the first buffer layer 1BF is removed, a portion of the line insulating layer LIS and the cell plug CP may be exposed. Subsequently, a first source line 1SL may be formed to cover the exposed line insulating layer LIS and the cell plug CP.

[0142] Reference Fig.14E , openings OP spaced apart from each other may be formed by etching a portion of an upper portion of the first source line 1SL. For example, the opening OP may be formed by performing a dry etching process. The depth of the opening OP may be shallower than the thickness of the first source line 1SL. When the opening OP is formed, a first source bonding pad 1SbPD may be formed within the opening OP. The first source bonding pad 1SbPD may be formed of a dielectric layer.

[0143] Reference Fig.14F , a second peripheral circuit 170b may be formed on the third substrate 3SUB. The second peripheral circuit 170b may include a page buffer PB, a contact CT, a peripheral line PL, and a first contact bonding pad 1CbPD, and may also include a reference Figure 1 At least one circuit among the circuits included in the described peripheral circuit 170. The contact CT, the peripheral line PL, and the first contact bonding pad 1CbPD may be formed of a conductive material. The area around the page buffer PB, the contact CT, the peripheral line PL, and the first contact bonding pad 1CbPD may be filled with a peripheral gap filling layer pTIS. The peripheral gap filling layer pTIS may be formed as an insulating layer. For example, the peripheral gap filling layer pTIS may be formed of an oxide layer, more specifically, may be formed of a silicon oxide layer.

[0144] Reference Figure 14G , a second memory cell array 110b may be formed on the fourth substrate 4SUB. For example, the second memory cell array 110b may include a second buffer layer 2BF, a wire insulation layer LIS, a gate line GL, a cell plug CP, a bit line contact bCT, a bit line BL, a contact CT, a second contact pad 2CbPD, and a first cell interlayer insulation layer 1cTIS located on the fourth substrate 4SUB. For example, the first buffer layer 1BF may be formed of a material having an etching selectivity relative to the wire insulation layer LIS and the cell plug CP, and may cover the second substrate 2SUB. The alternately stacked wire insulation layer LIS and the gate line GL may be superimposed on the first buffer layer 1BF. The wire insulation layer LIS may be an oxide layer. The gate line GL may be formed as a conductive layer. The cell plug CP may contact the first buffer layer 1BF by passing through the wire insulation layer LIS and the gate line GL. The cell plug CP may be formed in accordance with the reference Figure 8BThe same structure as described for the cell plug CP is formed.

[0145] The bit line contact bCT, the bit line BL, the contact CT, and the second contact pad 2CbPD may be located or positioned on the cell plug CP. Fig.14A The first contact bonding pad 1Cb is formed of the same material as PD.

[0146] A first unit interlayer insulating layer 1cTIS may be formed around the bit line contact bCT, the bit line BL, the contact CT, and the second contact bonding pad 2CbPD. The first unit interlayer insulating layer 1cTIS may be formed as an insulating layer. For example, the first unit interlayer insulating layer 1cTIS may be formed of an oxide layer, more specifically, may be formed of a silicon oxide layer.

[0147] Reference Fig.14H , the second memory cell array 110b may contact the second peripheral circuit 170b. For example, by referring to Figure 14G The entire structure described is flipped, the second contact bonding pad 2CbPD is located at the bottom, and the fourth substrate 4SUB is located at the top. The upper surface of the second peripheral circuit 170b and the lower surface of the second memory cell array 110b may contact each other, and a bonding process of a heat treatment method may be performed. Due to the bonding process, the peripheral gap filling layer pTIS of the second peripheral circuit 170b and the first cell interlayer insulating layer 1cTIS of the second memory cell array 110b may contact each other, and the first contact bonding pad 1CbPD of the second peripheral circuit 170b and the second contact bonding pad 2CbPD of the second memory cell array 110b may contact each other.

[0148] Reference Fig.14I , the second memory cell array 110b may be removed Fig.14H The fourth substrate 4SUB and Fig.14H The second buffer layer 2BF may be formed by a wet etching process to remove the fourth substrate 4SUB. For example, a wet etching process for removing the fourth substrate 4SUB may be performed. The second buffer layer 2BF may protect the cell plug CP when the fourth substrate 4SUB is removed. The second buffer layer 2BF may be removed by a wet or dry etching process. When the second buffer layer 2BF is removed, a portion of the line insulating layer LIS and the cell plug CP may be exposed. Subsequently, a second source line 2SL may be formed to cover the exposed line insulating layer LIS and the cell plug CP.

[0149] Reference Fig.14J, openings OP spaced apart from each other may be formed by etching a portion of an upper portion of the second source line 2SL. For example, the opening OP may be formed by performing a dry etching process. The depth of the opening OP may be shallower than the thickness of the second source line 2SL. When the opening OP is formed, a second source bonding pad 2SbPD may be formed within the opening OP. The second source bonding pad 2SbPD may be formed of a dielectric layer.

[0150] Reference Figure 14K , by referring to Fig.14J The entire structure described is flipped, the second contact bonding pad 2CbPD is located at the bottom, and the third substrate 3SUB is located at the top. The bottom surface of the flipped structure is connected to the reference Fig.14E For example, the first source bonding pad 1SbPD of the first memory cell array 110a and the second source bonding pad 2SbPD of the second memory cell array 110b may contact each other.

[0151] Since the first source bonding pad 1SbPD included in the first source line 1SL of the first memory cell array 110a contacts the second source bonding pad 2SbPD included in the second source line 2SL of the second memory cell array 110b, the bonding strength of the first source line 1SL and the second source line 2SL may also be increased.

[0152] Fig.15 is a diagram showing a memory card system to which the memory device of the present disclosure is applied.

[0153] Reference Fig.15 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0154] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 may be configured to control a programming operation, a read operation, or an erase operation of the memory device 3200, or to control a background operation. The controller 3100 is configured to provide an interface between the memory device 3200 and a host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction circuit.

[0155] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a personal component interconnect (PCI), a high-speed PCI (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 may be defined by at least one of the various communication standards mentioned above.

[0156] The memory device 3200 may include a plurality of memory cells and may be connected to Figure 1 The illustrated memory devices 100 are configured identically.

[0157] The controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), and a Universal Flash Storage (UFS).

[0158] Fig.16 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0159] Reference Fig.16 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001, and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0160] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one interface such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0161] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be connected to Figure 1 The illustrated memory devices 100 are configured identically. A plurality of memory devices 4221 to 422n may communicate with a controller 4210 through channels CH1 to CHn.

[0162] The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive a power supply voltage from the host 4100 and be charged with the power supply voltage. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide the power supply voltage of the SSD 4200. For example, the auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard, and may provide auxiliary power to the SSD 4200.

[0163] The buffer memory 4240 operates as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0164] CROSS-REFERENCE TO RELATED APPLICATIONS

[0165] This application claims the priority of Korean Patent Application No. 10-2023-0111312 filed on August 24, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: a first peripheral circuit, the first peripheral circuit including a first page buffer, the first peripheral circuit having a cell region and a connection region; a first memory cell array located above the first peripheral circuit, the first memory cell array including a first bit line electrically connected to a corresponding first page buffer of the first page buffers; as well as A second memory cell array is located above the first memory cell array and includes second bit lines electrically connected to corresponding first ones of the first bit lines.

2. The memory device according to claim 1, wherein: The first memory cell array comprises: a first source line, the first source line being located in the unit region of the first peripheral circuit; a first gate line, the first gate line being located above the first source line; a first cell plug vertically passing through the first gate line between the first bit line and the first source line; the first bit line coupled to the first cell plug; a first page buffer contact located in the connection region of the first peripheral circuit and electrically connected to the first page buffer; and The first sub-bit lines electrically connect the first page buffer contacts and the first bit lines, respectively.

3. The memory device according to claim 2, wherein: The second memory cell array comprises: a second bit line, a second gate line, a second source line, a second cell plug, and a second sub bit line.

4. The memory device according to claim 2, wherein: The first source line also includes spaced apart source bond pads coupled to the first peripheral circuit.

5. The memory device according to claim 4, wherein: The source bonding pad contacts an upper surface of a peripheral gap-fill layer covering the transistor in the first peripheral circuit.

6. The memory device according to claim 4, wherein: Each source bond pad includes a dielectric layer.

7. The memory device according to claim 4, wherein: Each of the source bonding pads is configured from a plurality of different dielectric layers.

8. The memory device according to claim 4, wherein: The source bonding pad has a horizontal cross-sectional shape that is at least one of a substantially square, a substantially rectangular, a substantially circular, and a substantially elliptical shape.

9. The memory device according to claim 3, further comprising: a first gate transmission line located in the connection region of the first memory cell array and electrically connected to the first gate line; as well as A gate line contact is located in the connection region of the first memory cell array and transmits a word line voltage received from the first peripheral circuit to the first gate transmission line.

10. The memory device according to claim 9, further comprising: A second gate transmission line is located in the connection area of ​​the second memory cell array and electrically connects the second gate line and the first gate transmission line.

11. The memory device according to claim 3, further comprising: a bonding pad which is located in the connection region of the first memory cell array and transmits a source voltage generated in the first peripheral circuit to the first source line; a contact liner layer surrounding the bonding pad between the bonding pad and the first source line; a first source contact contacting the bonding pad by passing through a sacrificial layer stacked in the connection region of the first memory cell array; as well as A second source contact is located in the connection region of the second memory cell array and electrically connects the first source contact and the second source line.

12. The memory device according to claim 1, further comprising: an external power pad exposed on an upper portion of the second memory cell array; a second power contact located in the connection region of the second memory cell array and electrically connected to the external power pad; as well as A first power contact is located in the connection region of the first memory cell array and transmits external power supplied through the external power pad to the first peripheral circuit.

13. The memory device according to claim 2, further comprising: A second page buffer contact is located in the connection region of the first memory cell array, the second page buffer contact is electrically connected to a portion of the first page buffer of the first peripheral circuit and is electrically isolated from the first bit line.

14. The memory device according to claim 13, further comprising: A third sub bit line is located in the connection region of the second memory cell array and electrically connects the second bit line and the second page buffer contact.

15. The memory device according to claim 1, further comprising: A second peripheral circuit is located above the second memory cell array.

16. The memory device of claim 15, wherein: The first peripheral circuit comprises: first contacts adjacent to each of the first page buffers; and A first contact bonding pad is in contact with each of the first contacts and is exposed through an upper surface of the first peripheral circuit.

17. The memory device of claim 16, wherein: The first memory cell array comprises: a second contact bonding pad, the second contact bonding pad being in contact with the first contact bonding pad; a first bit line connected to the second contact bonding pad; a first gate line, the first gate line being located on the first bit line; A first source line, the first source line is located on the first gate line; a first cell plug that passes through the first gate line and extends between the first source line and the first bit line; and A first source bonding pad is included in the first source line and is exposed through an upper surface of the first source line.

18. The memory device of claim 17, wherein: The second memory cell array comprises: a second source line, the second source line being located above the first memory cell array; second source bonding pads located in the second source line and respectively contacting the first source bonding pads through a lower surface of the second source line; a second gate line, the second gate line being located above the second source line; a second bit line, the second bit line being located above the second gate line; a second cell plug that passes through the second gate line and extends between the second bit line and the second source line; and A third contact bonding pad is provided, the third contact bonding pad being connected to each of the second bit lines.

19. The memory device of claim 18, wherein: The second peripheral circuit comprises: fourth contact bonding pads, the fourth contact bonding pads contacting the third contact bonding pads respectively; and The second contacts contact the fourth contact bonding pads, respectively.

20. A method of manufacturing a memory device, the method comprising the steps of: forming a peripheral circuit on the first substrate; forming a first memory cell array over a second substrate, the first memory cell array comprising a first stack, a first cell plug passing through the first stack, and a first bit line located over the first cell plug; forming a second memory cell array over a third substrate, the second memory cell array comprising a second stack, a second cell plug passing through the second stack, and a second bit line located on the second cell plug; stacking the first memory cell array over the second memory cell array; exposing a portion of the first cell plug by removing the second substrate from the first memory cell array; forming a first source line over the first cell plugs exposed in the first memory cell array, the first source line including source bonding pads spaced apart from each other; contacting the first memory cell array including the source bonding pad on the peripheral circuit; exposing a portion of the second cell plug by removing the third substrate located on the second memory cell array; as well as A second source line is formed on the second cell plug exposed in the second memory cell array.

21. The method according to claim 20, wherein: The step of forming the peripheral circuit comprises the following steps: forming transistors and contacts over the first substrate; and A peripheral gap-fill layer is formed over the first substrate including the transistor and the contact.

22. The method according to claim 21, wherein: The peripheral gap-filling layer is formed of an oxide layer.

23. The method according to claim 20, wherein: The step of forming the first source line comprises the following steps: forming a first source line over the first cell plug exposed in the first memory cell array; forming openings spaced apart from each other by removing a portion of an upper portion of the first source line; and The source bonding pad is formed within the opening.

24. The method according to claim 23, wherein: The first source line is formed of polysilicon.

25. The method according to claim 23, wherein: The source bonding pad is formed from a dielectric layer.

26. A memory device, the memory device comprising: a first peripheral circuit having a cell region and a connection region, the first peripheral circuit having a first page buffer in the cell region; a first memory cell array located above the first peripheral circuit and including a first bit line electrically connected to the first page buffer; a second memory cell array, the second memory cell array being located above the first memory cell array and including a second bit line in the cell region; as well as a second peripheral circuit located above the second memory cell array and including a second page buffer electrically connected to the second bit line, Wherein, the first memory cell array comprises: a first source line located at an upper end of the first memory cell array; and a first source bonding pad included in the first source line and exposed through an upper surface of the first source line, and The second memory cell array comprises: a second source line located above the first memory cell array; and Second source bonding pads are included in the second source line and contact the first source bonding pads respectively through lower surfaces of the second source lines.

27. The memory device of claim 26, wherein: The first memory cell array comprises: a first stack located on the first bit line; a first unit plug extending through the first stack, wherein the first source line is located on the first cell plug and the first stack, and The first source bonding pad is included in the first source line and is exposed through an upper surface of the first memory cell array.

28. The memory device of claim 27, wherein: The first source bonding pad is formed from a dielectric layer.

29. The memory device of claim 27, further comprising: A first source contact is located in the connection region of the first memory cell array and transmits a source voltage generated in the first peripheral circuit to the first source line.

30. The memory device of claim 27, wherein: The second memory cell array comprises: the second source bonding pad, the second source bonding pad contacting the first source bonding pad; the second source line, the second source line covering the second source bonding pad; a second stack located above the second source line; a second unit plug that passes through the second stack; and The second bit line is located above the second cell plug.

31. The memory device of claim 30, wherein: The second source bonding pad is formed of the same material as the first source bonding pad.

32. The memory device of claim 30, further comprising: A second source contact is located in the connection region of the second memory cell array and transmits a source voltage generated in the second peripheral circuit to the second source line.

33. A method of manufacturing a memory device, the method comprising the steps of: forming a first peripheral circuit including a first contact bonding pad over the first substrate; forming a first memory cell array including second contact bonding pads over a second substrate; flipping the first memory cell array so that the second substrate is located at an upper portion and the second contact bonding pad is located at a lower portion, and making the second contact bonding pad of the flipped first memory cell array contact the first peripheral circuit; removing the second substrate above the first memory cell array and forming a first source line on the first memory cell array; forming first source bonding pads having exposed upper surfaces and spaced apart from each other within the first source line; forming a second peripheral circuit including a third contact bonding pad over the third substrate; forming a second memory cell array including fourth contact bonding pads over a fourth substrate; flipping the second memory cell array so that the fourth substrate is located at an upper portion and the fourth contact bonding pad is located at a lower portion, and making the fourth contact bonding pad of the flipped second memory cell array contact the second peripheral circuit; removing the fourth substrate above the second memory cell array and forming a second source line above the second memory cell array; forming second source bonding pads having exposed upper surfaces and spaced apart from each other in the second source line; as well as The first source bonding pad and the second source bonding pad are brought into contact with each other.

34. The method of claim 33, wherein: The step of forming the first memory cell array comprises the following steps: forming a first stack over the second substrate; forming a first unit plug through the first stack; forming a first bit line over the first cell plug; and The second contact pad is formed over the first bit line.

35. The method of claim 33, wherein: The step of forming the first source bonding pad comprises the following steps: forming openings spaced apart from each other by removing a portion of the first source line; and The first source bonding pad is formed by filling the opening with a dielectric layer.

36. The method of claim 33, wherein: The step of forming the second memory cell array comprises the following steps: forming a second stack over the third substrate; forming a second unit plug through the second stack; forming a second bit line over the second cell plug; and The fourth contact bond pad is formed over the second bit line.

37. The method of claim 33, wherein: The step of forming the second source bonding pad comprises the following steps: forming openings spaced apart from each other by removing a portion of the second source line; and The second source bonding pad is formed by filling the opening with a dielectric layer.

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