Multi-die module with low power operation

Abstract

The invention discloses a module for a plurality of dies. The module may include a set of dies including a first die having a first voltage block and a second die having a second voltage block. The module may also include an interconnect electrically connecting the first die and the second die. Power generation in the first die is enabled in an inactive mode, while power generation in the second die is disabled. The power generation in the second die may be enabled when the second die is in an active mode. The first die may send an enable signal to the second die to enable the second die. In the inactive mode, the first die may provide power to the second die. When the module is in a self-refresh mode, the first die may send a self-refresh timing command to the second die.

Description

[0001] This application is a divisional application of the Chinese invention patent application with invention name “Multi-die module with low-power operation”, application number 201980028766.1 and application date April 30, 2019.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 664,728, filed on April 30, 2018, entitled “MULTI-DIE MODULE WITH LOW POWER OPERATION,” the entire contents of which are hereby incorporated by reference. Background Art Technical Field

[0004] The present disclosure relates generally to die modules, and more particularly to multi-die modules that allow for a low power mode of operation. Summary of the invention

[0005] In a multi-die configuration, such as stacked memory dies (e.g., dynamic random access memory or DRAM), each die may use voltage regulation circuitry to generate one or more internal power supplies, typically in combination with a charge pump and other voltage control circuitry. It is desirable to distribute the power supplies among all the dies to allow identical dies to be manufactured and to avoid voltage differences due to differences in paths from external power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a group of devices organized in a module according to one embodiment, the module including first to fifth semiconductor devices.

[0007] Figure 2 is a schematic diagram of a module including first to fifth semiconductor devices according to an embodiment.

[0008] Figure 3A is shown in one embodiment included in Figure 1 to Figure 2 The modules shown are similar to the modules in the system diagram.

[0009] Figure 3B is shown in one embodiment included in Figure 1 to Figure 2 The modules shown are similar to the modules in the system diagram.

[0010] Figure 3C is shown in one embodiment included in Figure 1 to Figure 2 The modules shown are similar to the modules in the system diagram.

[0011] Figure 4 is shown included with Figure 1 and Figure 2 The modules shown are similar to the modules in the system diagram.

[0012] Figure 5A A circuit of a device included in a module according to one embodiment is shown.

[0013] Figure 5B A circuit of a device included in a module according to one embodiment is shown.

[0014] Fig. 6A shows the device designated as the master device Figure 3A system.

[0015] Figure 6B A system is shown in which a slave device has an instruction with a No Operation (NOP) command from its command decoder.

[0016] Figure 6C A system is shown in which a slave device has instructions for a bank activate command from its command decoder.

[0017] Figure 7 A diagram of a system for self-refresh mode (SRM) in a group of devices connected by signal interconnects is shown.

[0018] Figure 8 Logic for operation according to one embodiment is schematically shown.

[0019] Fig. 9 A schematic side view of a module is shown. DETAILED DESCRIPTION

[0020] While separate internal power supplies are desirable for the reasons discussed above, such arrangements increase power consumption.Therefore, there is a need to reduce power consumption between grouped dies, such as memory chips.

[0021] Various embodiments disclosed herein relate to a plurality of dies having internal voltage circuit blocks that can be used to maintain power supply levels so that the product meets functional and / or parameter specifications. Examples of functional specifications may include read and write delays, data output frequency, data retention time, setup and hold time, functional operation over temperature, etc. Parameter specifications may include standby power, active power, input and output levels, etc.

[0022] A voltage circuit block (also referred to herein as a voltage block) may include a voltage regulator and / or a voltage generator circuit (such as a charge pump) to generate a voltage that is at a different level than an external source or is simply more stable than the external source. A voltage block may have the regulator and voltage generation circuits in close proximity to each other, or they may be distributed on separate dies.

[0023] The embodiments disclosed herein may be particularly beneficial for grouping dies in a package, such as modules in a stacked die configuration. Non-limiting examples include memory modules that include stacked memory, such as dynamic random access memory (DRAM) chips. However, it should be understood that the embodiments disclosed herein may also be beneficial for dies connected in any other manner, particularly but not exclusively for co-packaged dies in a module (e.g., a multi-chip module or MCM).

[0024] As described above, it may be desirable to have distributed power regulation among multiple grouped chips. In some implementations, the chips correspond to semiconductor dies having the same design or part number. However, power regulation blocks may consume power even during inactive modes (such as standby operating modes and / or sleep modes), which is generally and specifically of interest for today's mobile and wearable markets. For example, in the case of stacked die memory modules, when many voltage blocks (e.g., pumps and / or regulators) on each die consume power during inactive modes, the current consumption during inactive modes (e.g., standby modes, sleep modes, etc.) can be a relatively large burden on the battery.

[0025] Therefore, in the embodiments taught herein, one or more dies in a group of multiple dies may be designated as providing at least some of the functions of the remaining dies in the group or a subset of the group in certain operating modes. For example, a die may be designated as a master die, and the remaining dies or a subset of them may be used as slave dies in an inactive mode. The term "master" is used herein to be configured or designated as a die that maintains its voltage block in an active mode, while the other dies in the group are in an inactive mode, and the power consumed in the inactive mode is less than the power consumed in the active mode. Such configuration or designation may be provided in any suitable manner, including but not limited to programming the die with master / slave configuration data via an interface or bus, controlling fuses and / or antifuses, and / or any other suitable configuration scheme.

[0026] In some embodiments, the voltage block of the main core can provide voltage for the operation of both the main core and the slave die in inactive mode. In some embodiments, the main core can provide control signals to the slave die in addition or alternatively. Active mode and inactive mode can refer to a single die, or to the state of a die group (e.g., a module, which can be packaged together). When the die group is in inactive mode, the main core in the group enables its voltage block. Therefore, even when the group to which the main core belongs is in inactive mode, the main core can also be considered to remain in active mode. Therefore, when the slave die can be in low power mode or high power mode, the main core can be in high power mode. Depending on the power supply loading level in inactive mode, the number of voltage blocks that remain active in the main core can vary. The technician will understand that in some embodiments, the foregoing description does not exclude that the main core has other modes in other conditions, including low power mode or inactive mode. For example, in the case where data retention is not required in volatile memory applications, the voltage block of the main core can be disabled.

[0027] In some embodiments, the master die provides voltage for certain slave die operations in inactive mode and / or provides control signals to the slave die. In other embodiments, the master die provides voltage for certain slave die operations, but control signals for such operations are processed within the slave die, such as through a local command decoder. Such control signals may enable and / or disable voltage blocks in the rest or subset of the group.

[0028] For example, a control signal may disable a voltage regulator in a slave die in an inactive mode (e.g., standby mode, sleep mode, etc.) where the power draw on the regulated power supply is low enough that one or more of the voltage blocks of one or more of the dies in the group can provide sufficient control (e.g., correct voltage levels, sufficient voltage stability, etc.) to keep the regulated power supply sufficiently stable, thereby allowing the product to meet functional specifications and parametric specifications.

[0029] Similarly, control signals can be used, for example, to selectively enable and / or disable charge pumps and / or other voltage generating circuits in slave dies. For example, a memory module may include a set of memory dies stacked vertically. Each memory die may include one or more internal voltage blocks. In one condition (e.g., inactive mode), a designated master die enables its internal voltage block and a slave die may disable its internal voltage block so that its power draw may be significantly reduced in inactive mode. In some embodiments, a voltage block may include more than one voltage regulating / generating circuit (e.g., voltage regulator, charge pump, etc.). In another condition (e.g., active mode), an internal voltage block of a slave die may be enabled to locally provide an internally generated voltage to each die.

[0030] In some embodiments, a module may specify more than one main core, each of which is capable of supplying voltage to one or more slave cores, at least for some operations in an inactive (or low-power) mode. The function of enabling and disabling the voltage block of the slave core may be handled by a control circuit (e.g., a command module) within the slave core in some embodiments, by a signal processing from the main core in other embodiments, and / or in response to a command received by the module. The main core may be configured to keep its voltage block enabled in an inactive mode (e.g., standby mode, sleep mode, and / or any other low-power mode). For example, if a die is designated as a slave die and it receives a no-operation command, it may automatically disable some or all of its voltage regulators and / or pumps, and rely on the main core to provide voltage control and voltage supply. Therefore, the module consumes less power in standby mode or sleep mode, where only the voltage block (e.g., regulation and generation circuit) of the main core is enabled.

[0031] Thus, the module consumes less power in a standby mode or sleep mode, wherein the voltage blocks (e.g., regulation and generation circuits) of the master die are enabled and some or all of the slave die voltage blocks are disabled. In some embodiments, the master die and the slave die are structurally identical, except for any differences caused by the nomenclature as the master die and the slave die and manufacturing variations between the dies. Thus, when a group (e.g., a module) is in an inactive mode, the master die may enable its voltage blocks, while at least some of the corresponding voltage blocks of the slave die are disabled.

[0032] In some embodiments, the master die may provide one or more power supplies to the slave die. For example, in an inactive mode, one or more of the master die may enable one or more of its voltage blocks, and the slave die may disable the voltage blocks. While the slave die or module remains in the inactive mode, the enabled voltage blocks of the master die may supply voltage to the slave die, which disables the voltage blocks for certain operations.

[0033] In some embodiments, the master die may provide a refresh timing signal to the slave die in response to an external self-refresh command. In some embodiments, the refresh timing signal may enable a voltage block of the slave die. In some embodiments, the self-refresh timing signal may be accompanied by a self-refresh-related power supply to perform a self-refresh of the slave die.

[0034] Figure 1 is a schematic diagram of a group of devices organized in a module 2, the module including first to fifth semiconductor devices 4a-4e. Each of the devices 4a-4e may represent a semiconductor die. It should be understood that a module may include any suitable number of semiconductor devices. Thus, although shown in the context of five devices, more or fewer devices may be included in a module 2. Furthermore, although Figure 2Other circuitry is not depicted, but may be included, such as additional dies, surface mount components, and / or integrated passives. Figure 1 The outer dashed box of module 2 may represent a substrate (eg, a laminate) to which the semiconductor device is directly or indirectly secured.

[0035] Module 2 may be co-packaged, with or without other devices (e.g., a processor die). In some embodiments, semiconductor devices 4a-4e may include memory dies (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc.), and module 2 may define a memory module. The module may include signal interconnects 6, power sharing lines 7, and external interconnects 8. In certain operations, signal interconnects 6 and power sharing lines 7 may be decoupled from the die. In some embodiments, signal interconnects may be omitted, such as embodiments where external (e.g., from a processor / controller) and / or internal slave commands execute the enabling and disabling of voltage blocks.

[0036] Although shown schematically with certain relationships to the various blocks of devices 4a-4e, skilled artisans will appreciate that lines 6-8 may communicate directly or indirectly with any circuit block within devices 4a-4e, and that each of the illustrated lines 6-8 may represent multiple lines or pins of each of devices 4a-4e.

[0037] The first to fifth semiconductor devices 4a-4e may include first to fifth control circuits 10a-10e, respectively. One or more of the control circuits 10a-10e are capable of transmitting control signals (e.g., operation commands, enable signals, and disable signals for regulators and / or charge pumps) to other blocks of the same device and / or other semiconductor devices. Each of the first to fifth semiconductor devices 4a-4e may include one or more voltage blocks 11a-11e. In some embodiments, the control circuits 10a-10e of each device 4a-4e may be capable of transmitting control signals to the voltage blocks 11a-11e of the same die, and may also be capable of transmitting signals to other devices, for example, along the signal interconnects 6.

[0038] Thus, the power circuits 10a-10e are each capable of enabling disabled voltage blocks 11a-11e and / or disabling enabled voltage blocks 11a-11e. In some embodiments, the signal interconnect 6 may include a plurality of lines (e.g., a multi-bit bus) for sending control signals. The power sharing line 7 may be coupled to the outputs from the voltage blocks 11a-11e. The power sharing line 7 may include a plurality of conductors for, for example, regulated VDD, VPP (e.g., an auxiliary power supply for word line boosting of a memory) and a reverse bias voltage (for biasing the body of a field effect transistor or FET), and may supply voltage from the master die to the slave die for operation in an inactive mode when the corresponding slave voltage block is disabled.

[0039] As described in more detail below, in operation, one of the semiconductor devices 4a-4e can be designated as a master die. In some embodiments, enabling / disabling the voltage blocks 11a-11e of a designated slave die can be controlled by a command decoder of the slave die, optionally combined with an external signal (e.g., from a central control processor), without communicating with the designated master die. In other embodiments, control of enabling / disabling the slave voltage blocks is handled by the master die control circuit. External interconnects 8 can be used to supply power and signals to the semiconductor devices 4a-4e of the module 2 from an external power supply and processor.

[0040] In some embodiments, the voltage blocks 11a-11e may be, for example, voltage regulators and / or charge pumps that regulate voltage distribution internally. Although represented by a single block per device for purposes of illustration, a skilled person will appreciate that the internal voltage blocks 11a-11e may each represent a plurality of different circuits for regulating different voltages employed internally by the operating circuitry.

[0041] For example, as will be appreciated by a skilled artisan, a memory die compliant with the DDR4 SDRAM standard may employ ground, VDD / VDDQ (e.g., 1.2V ± 60mV), VCC2, and VPP (e.g., (e.g., 2.5V - 125mV or +250mV) signals for various memory operations, where VPP may be regulated to an internal VPP voltage that is lower or higher than the voltage supplied to the chip. Similarly, VDD may be used to generate one or more internal VDD levels, such as by internal voltage regulation. These internal VDD levels may be used to supply voltages to a memory array, sense amplifiers (amps), and / or peripheral circuits. Additionally or alternatively, the internally generated VDD levels may be used as part of the regulation of other supply voltages (such as VPP internal).

[0042] The voltage blocks 11a-11e may be connected to other semiconductor devices 4a-4e via interconnects 7. The semiconductor devices 4a-4e also include operating circuits, such as memory circuits 12a-12e. The skilled person will appreciate that the memory circuits 12a-12e may include logic circuits (e.g., digital CMOS logic) that tend to use higher voltages, as well as memory arrays and sense amplifiers that tend to use relatively lower voltages, and word line voltages that may be maintained at about 2-3 times higher than the sense amplifier voltage.

[0043] In the semiconductor device 4a, in the active mode, the voltage block 11a may provide an internal power supply voltage to the first memory circuit 12a. Similarly, in the semiconductor devices 4b-4e, the voltage blocks 11b-11e may provide an internal power supply voltage to the second memory circuit to the fifth memory circuit 12b-12e, respectively. It should be understood that other voltage blocks (not shown) may be present in each semiconductor device, some of which may be enabled in both the active mode and the inactive mode. For the purpose of illustration, only those voltage blocks that are disabled in the inactive mode are shown.

[0044] In some embodiments, one of the semiconductor devices 4a-4e (e.g., semiconductor device 4a) can be designated as a master die for enabling / disabling voltage blocks (or portions thereof) in a module through signal interconnects 6 and / or providing power to other devices 4b-4e through power sharing lines 7. The remainder of the semiconductor devices 4b-4e or a subset of the remainder can be slave dies.

[0045] In some embodiments, a given module may include multiple master devices, each of which has one or more slave devices. In some embodiments, the master device may be selected at the hardware level. For example, a fuse and / or an anti-fuse may be included in module 2 to hardwire the master device at the manufacturer or client. In some embodiments, the fuse and / or the anti-fuse may be programmable during assembly or testing. For example, the configuration may be reprogrammed during testing so that different configurations (e.g., the number of the main cores in the stack) may be set based on the associated specifications of the market and the module. In other embodiments, the master device may be selected by software settings. For example, a die designator may set the master device according to the settings in the mode register, which may be programmable by a chip interface or bus. The settings in the mode register may be changed by the user.

[0046] In some embodiments, each die may be shipped as a slave die by default, particularly where the die lot will be primarily interconnected in groups (e.g., stacked). In other embodiments, each die may be shipped as a master die by default, particularly where the die lot will primarily be used without direct interconnection (e.g., non-stacked) and where only a few dies will be interconnected (e.g., stacked). As described elsewhere herein, for purposes of this disclosure, devices or dies are considered to be identical when they are manufactured by the same process and differ only in being named master or slave (whether by software or hardware). Of course, different data storage devices on different dies are not considered to have their states changed to be identical.

[0047] During operation, the module 2 may have a first state (e.g., an inactive mode) and a second state (e.g., an active mode). During the first state, a voltage block of the master device may be enabled and one or more corresponding voltage blocks of the slave device may be disabled. For example, when the semiconductor device 4a is designated as the master device, in the first state, only the first voltage block 11a may be enabled, while the second to fifth voltage blocks 11b-11e are disabled.

[0048] Disabling a voltage block may require disabling any portion of the voltage block. For example, a voltage block is considered disabled when one or more regulators, one or more voltage generating circuits (such as a charge pump), or a combination of regulators and voltage generating circuits of the voltage block are disabled. The disabled circuits reduce their power consumption, and thus, the disabled voltage block consumes less power in an inactive (e.g., sleep or standby) mode than an enabled voltage block. For example, static power dissipation and transistor leakage current may be reduced in an inactive mode.

[0049] Conventionally, sleep mode or standby mode includes disabling some voltage blocks, but other voltage blocks in the sleep or standby chip remain active to be able to process certain functions, such as refresh, during the inactive mode. However, according to some embodiments, a greater number and / or different types of voltage blocks in the slave die may be disabled in the inactive mode compared to the conventional sleep mode or standby mode, because in the inactive mode, the voltage supply from the main die 4a (higher, lower, or more stable than the external supply voltage along the external line 8) may facilitate these functions.

[0050] In the second condition, all or a subset of devices 4a-4e may be enabled. During the first condition, in some embodiments, one or more of the voltage blocks 11a-11e or one or more disabled portions of the voltage blocks 11b-11e may be controlled to be enabled. In various embodiments, the slave devices 4b-4e may receive an operational amplifier control signal from the corresponding control circuit 10b-10e or the first control circuit 10a. For example, the operational amplifier control signal may be used to enable a voltage regulator (e.g., a low dropout regulator or LDO) including an operational amplifier. Disabling one or more of the voltage blocks 11b-11e in the first condition may be beneficial because the voltage blocks 11b-11e tend to draw current and consume power in an inactive mode (e.g., a standby mode), and disabling the slave voltage blocks 11b-11e when the module 2 is in an inactive mode may reduce power consumption.

[0051] In various embodiments, when, for example, one or more of the slave memory circuits 12b-12e require a current load to maintain a voltage level that exceeds a first threshold load value, the first voltage block 11a of the master device 4a may supply power to the slave memory circuits 12b-12e. The first threshold load value may vary depending at least in part on a voltage supply from a voltage block (not shown) of the slave die 4b-4c, which remains enabled in the inactive mode and may provide power in the inactive mode.

[0052] In some embodiments, the first threshold may be zero when all voltage blocks of the slave device are disabled. As a simpler example, in the inactive mode, when the second memory circuit 12b requires a current load level below the first threshold, the enabled voltage block (not shown) of the slave die 4b may provide an internally generated power supply to the second memory circuit 12b. In the inactive mode, when the second memory circuit 12b requires a current load value between the first threshold and the second threshold, the main voltage block 11a may provide power to the second memory circuit 12b. The second threshold may be a current level that the main voltage block 11a may provide to the second memory circuit 12b. When the second memory circuit 12b requires a current load value exceeding the second threshold, the second voltage block 11b may be enabled, which places the second device 4b in an active mode. It should be understood that any one or more semiconductor devices 4a-4e may be designated as a master device.

[0053] therefore, Figure 1The semiconductor devices 4a-4e can be structurally identical devices. In some embodiments, it can be beneficial to have identical semiconductor devices in the module 2. For example, from a manufacturing point of view, it is more cost-effective to manufacture identical dies than to manufacture different dies. In addition, the inventory of devices can be more easily organized, and in the event that one device in the module fails, another device can be designated as the master device. However, in some embodiments, the devices or dies in the module may include different devices, for example where the master device is manufactured to have a different configuration than the slave device.

[0054] In some embodiments, a refresh command may trigger a voltage block 11b-11e from a semiconductor device 4b-4e to be enabled. In some embodiments, a refresh command may enable a portion or the entire voltage block of a voltage block 11b-11e. In some embodiments, a storage memory activation command may trigger a voltage block 11b-11e from a semiconductor 4b-4e to be enabled. In some embodiments, a read activation command may trigger a voltage block 11b-11e from a semiconductor 4b-4e to be enabled. In some embodiments, a write activation command may trigger a voltage block 11b-11e from a semiconductor 4b-4e to be enabled. In some embodiments, a precharge activation command may trigger a voltage block 11b-11e from a semiconductor 4b-4e to be enabled. However, when, for example, an external supply voltage is sufficiently stable and at a suitable level to execute such a command, and / or such a command requires a current load value below a first threshold, one or more of these commands may not trigger a voltage block 11b-11e from a device 4b-4e to be enabled.

[0055] The power sharing line 7, which may be electrically coupled to the voltage blocks 11a-11e, may carry a reference voltage supply and a generated and / or regulated power supply voltage. When a voltage block is disabled, the disabled voltage block may be electrically decoupled from the power sharing line 7, such that the voltage block is a high impedance node from the perspective of the power sharing line 7. The master device voltage block 11a may actively drive the power sharing line 7.

[0056] In some embodiments, the voltage blocks 11a-11e may include an internal power source, such as a linear voltage regulator that generates a regulated voltage and provides the regulated voltage to the memory circuits 12a-12e. For example, the voltage blocks 11a-11e may include a low dropout (LDO) voltage regulator. In some embodiments, the voltage blocks 11a-11e may include one or more voltage modification circuits (such as a charge pump) that provide a voltage that is increased or decreased relative to a voltage generated by an external or internal power source to other circuits in the die, as described below with respect to Figure 2 For example, the voltage blocks 11a-11e may include both a linear voltage regulator and a charge pump that receives a regulated voltage from the linear voltage regulator and outputs a pump voltage.

[0057] In some embodiments, the voltage blocks 11a-11e may each include a plurality of voltage generators or voltage regulators, such as a voltage regulator for VPP and a voltage regulator for VBB. In some embodiments, the voltage blocks 11a-11e may include a voltage generator including at least one of a power dissipation oscillator, a charge pump circuit, and / or an operational amplifier (e.g., for providing negative feedback in an LDO regulator).

[0058] In some embodiments, voltage blocks 11a-11e may include a reference circuit that can generate a constant voltage that is independent of loading on the device, power supply variations, temperature variations, and / or the passage of time. The reference circuit may include at least one of a power dissipating operational amplifier, a voltage divider, a current mirror, and / or a bandgap circuit. Additionally, in some embodiments, a regulated power supply (such as VDD internal) may be used to regulate the voltage of a different regulated power supply (such as VPP, VBB, or Vbitline precharge).

[0059] Figure 2 2 is a schematic diagram of a module 2 including first to fifth semiconductor devices 4a-4e. Each of the first to fifth semiconductor devices 4a-4e includes a power control circuit 10a-10e, a voltage block including a linear voltage regulator 20a-20e and a charge pump 22a-22e. For example, the linear voltage regulator 20a-20e may be a low dropout (LDO) voltage regulator or other common forms of internal power regulation circuits.

[0060] Unless otherwise specified, Figure 2 Parts and Figure 1 Like numbered components shown are identical or substantially similar. It should be understood that module 2 may include any suitable number of semiconductor devices. In some embodiments, semiconductor devices 4a-4e may include memory dies (such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc.), and module 2 may define a memory module.

[0061] The module may include a signal interconnect 6, a first power sharing line 7a and a second power sharing line 7b, and an external interconnect 8. In some embodiments, the signal interconnect 6 may include one or more coupling lines to individually control one or more of the voltage regulators 20a-20e and / or the charge pumps 22a-22e as needed. The coupling lines including the signal interconnect 6 may carry signals including commands (such as precharge, storage bank activation, refresh, etc.), and / or addressing signals indicating information that one or more dies are addressed. The signal may be generated by an external command to the module via the external interconnect 8. The external interconnect 8 can be used to supply power from an external power source to the first semiconductor device to the fifth semiconductor device 4a-4e.

[0062] The regulated voltage generated at the linear voltage regulator 20a-20e can be coupled to the first power sharing line 7a and coupled to the charge pump 22a-22e and / or the memory circuit 12a-12e, depending on the required current load level. In some embodiments, the first charge pump to the fifth charge pump 22a-22e can receive the regulated voltage from the linear voltage regulator 20a-20e, and generate a modified voltage and provide the modified voltage to the memory circuit 12a-12e. However, in some other embodiments, the charge pump 22a-22e can directly receive the voltage set by the external power supply, and generate a pump voltage and provide the pump voltage to the memory circuit 12a-12e. In some embodiments, the modified voltage generated in one or more of the charge pumps 22-22e can be shared with other devices in the module 2 through the second power sharing line 7b. Therefore, in some embodiments, the internal linear voltage regulator can be omitted.

[0063] In the semiconductor device 4a, the linear voltage regulator 20a may provide a regulated voltage to the first charge pump 22a and / or the first memory circuit 12a. The first charge pump 22a may provide a pump voltage to the first memory circuit 12a. Similarly, in the semiconductor devices 4b-4e, the linear voltage regulators 20b-20e may provide a second regulated voltage to a fifth regulated voltage to the second charge pump 22b-22e and / or to the second memory circuit 12b-12e, respectively. The second charge pump 22b-22e may provide a pump voltage to the second memory circuit 12b-12e, respectively.

[0064] For example, in an embodiment where the semiconductor device 4a is designated as the master device of the module 2, in a first state (e.g., inactive mode), the linear voltage regulator 20a and / or the charge pump 22a may be enabled, while the linear voltage regulators 20b-20e and / or the charge pumps 22b-22e are disabled. When transitioning from the first state to the second state (e.g., active mode), in some embodiments, an enable signal or activation signal from the power control circuit 10b-10e may be sent to enable the linear voltage regulators 20b-20e and / or enable one or more of the charge pumps 22b-22e, respectively. The linear voltage regulator 20a and / or the charge pump 22a of the master device 4a may remain active in the first state (e.g., inactive mode). In a first condition (e.g., when the entire module 2 is in an inactive mode, or when executing commands that do not significantly load the internally generated power supply of the master device 4A), disabling one or more of the voltage regulators 20b-20e and / or the charge pumps 22b-22e may be beneficial. Disabling one or more of the linear voltage regulators 20b-20e and / or the charge pumps 22b-22e (alone or together) during such conditions may reduce current consumption. It should be understood that any one or more semiconductor devices 4a-4e may be designated as a master device, and in some embodiments, there may be more than one designated master device within a module.

[0065] In some embodiments, all slave linear voltage regulators 20b-20e may be disabled, and the master linear voltage regulator 20a may control the charge pumps 22a-22e. In such embodiments, the voltage regulators 20b-20e may be decoupled from the charge pumps 22b-22e, and the master linear voltage regulator 20a and the charge pumps 22b-22e are electrically coupled via the first power sharing line 7a.

[0066] Figure 3A is shown in one embodiment included in Figure 1 to Figure 2 The modules shown are similar to a diagram of a system 30 in modules. The system 30 may reside within each of the control circuits 10a-10e of the semiconductor devices 4a-4e, respectively.

[0067] System 30 includes a mode register 32, a die designator 34, and a command decoder 36, which are included in each device. Figure 1 Components. Figure 3A As shown, for example, the mode register 32 may include a die designator 34 for designating the semiconductor devices 4 a - 4 e in the module 2 as a master device or a slave device.

[0068] exist Figure 3A, the die designator 34 output is shown to designate the device as a logic level 1 from the device and may disable the device's voltage blocks in standby mode. Figure 3A In the illustrated system 30, it is labeled VDISABLE. On the other hand, if the die designator 34 outputs a logic level 0, the device is designated as a master device and its voltage block remains enabled by default. Although various logic level examples have been described, other implementations are possible, such as configurations using opposite or inverted logic.

[0069] The settings in the mode register 32 can be modified by the user (e.g., via an interface or bus). In some embodiments, the mode register and die designator can be omitted where the master / slave selection occurs at the hardware level. For example, fuses and / or anti-fuses can be included in the module to set the master device, or only the master device can include control circuits that can transmit signals to enable / disable slave devices. As used herein, references to structurally "same" die include dies that are initially the same and are modified only by designation, whether only by software or by hardware changes (such as fuse or anti-fuse modifications). The voltage block can include an internal power supply, such as a linear voltage regulator (such as an LDO voltage regulator) and / or a voltage regulator (such as a charge pump).

[0070] In the system 30, the command from the command decoder 36 may cause the master device to enable or disable the voltage block in the device. For example, when the command decoder 36 receives a signal for executing a refresh command in the device, the command decoder 36 may enable the voltage block of the device. For example, when the command decoder 36 of the device receives a signal for executing a bank activation command, the command decoder 36 may enable the relevant voltage block of the device. Therefore, the output of the OR gate is Figure 3A The device's command decoder 36 may enable the relevant voltage block of the device when the command decoder 36 receives a signal for executing a read command, the command decoder 36 may enable the relevant voltage block of the device. When the device's command decoder 36 receives a signal for executing a write command, the command decoder 36 may enable the relevant voltage block of the device. When the device's command decoder 36 receives a signal for executing a precharge command, the command decoder 36 may enable the relevant voltage block of the device.

[0071] However, one or more of these commands may not enable the voltage regulator of the slave device under certain conditions. For example, the voltage regulator of the slave device in the inactive mode may remain disabled when an external supply voltage and / or an internal power supply regulated / generated in the master device is available to execute such commands. For example, Figure 3AAs indicated, read, write, precharge, and non-operation (NOP) commands may not enable the voltage regulator when the stability of the power supply is sufficient to maintain product performance at the current load associated with the command or when a regulated power supply is provided externally.

[0072] Figure 3B is shown in one embodiment included in Figure 1 to Figure 2 The system 30 may reside in each of the control circuits 10a-10e of the semiconductor devices 4a-4e. The die designator 34 included in the device designates the device as a master device or a slave device. When the device is designated as a master device, the die designator 34 sends a designation signal as a logic "1" to a first logic gate (e.g., buffer gate 40), and a voltage block included in the device may be enabled as a default setting. Therefore, the output of the OR gate is Figure 3B It is labeled VENABLE in the illustrated system 30. When the device is designated as a slave device, the die designator 34 sends the designation signal as a logic "0" to the first logic gate (eg, buffer gate 40), and the voltage blocks included in the device may be disabled in an inactive mode.

[0073] exist Figure 3B In the illustrated system 30 , a command decoder 36 included in the slave device may send an enable signal to a second logic gate (eg, OR gate 42 ) to enable the disabled voltage block. Figure 3B The system 30 includes a default value so that the command decoder 36 of the designated slave device does not rely on the disable signal, but defaults to keep the related voltage block disabled in the inactive mode in the absence of selected commands that need to be enabled (such as "refresh" and "bank activation" as shown), which can simplify the structure of the system 30. In the inactive mode, the designated slave device can be configured to respond only to the selected commands, which can temporarily enable the related voltage block to achieve these functions.

[0074] Figure 3C is shown in one embodiment included in Figure 1 to Figure 2 The system 30 may reside in each of the control circuits 10a-10e of the semiconductor devices 4a-4e. Figure 3C In the system 30 shown, Figure 3B Unlike the system 30, the die designator 34 sends a designation signal to the OR logic gate 42, thereby omitting Figure 3CThe buffer gate 40 present in the system 30 can simplify the structure of the system 30. When the device is a master device, the die designator 34 can output 1, thereby enabling the voltage block in the device. When the device is a slave device, the die designator outputs 0, so that in the absence of any 1 output from the command decoder, the relevant voltage block is disabled by default. Similar to Figure 3B In the embodiment of the present invention, in the inactive mode, a specified slave device can be configured to respond only to selected commands (such as "refresh" and "bank activation" as shown), which can temporarily enable the relevant voltage blocks to achieve these functions. Therefore, the output of the OR logic gate 42 is Figure 3C The system 30 is shown labeled VENABLE.

[0075] Figure 4 is shown included with Figure 1 and Figure 2 The modules shown are similar to the modules in the system 31 of FIG. It should be understood that even though Figure 4 A system 31 having three devices 4a-4c is shown, but the module may include any number of devices. For example, the module may include five devices, one of which is similar to the first device 4a, and four of which are similar to the second device 4b or the third device 4c.

[0076] The first die 4a may include a mode register 32 that designates the first device as a master device, and a command decoder 36 that may send an enable / disable signal to the other devices 4b, 4c. The voltage block 11A included in the master device 4A may be enabled by default. The enable / disable signal may be sent through the signal interconnect 6. The voltage blocks 11b, 11c of the slave devices 4b, 4c may be enabled / disabled by enabling / disabling the signal from the command decoder 36. For example, the voltage blocks 11b, 11c of the slave devices 4b, 4c may be enabled by default in a first state (e.g., an inactive mode), and when a high power command (e.g., a command requiring a current load value greater than a threshold) is received, the command decoder 36 may send an enable signal through the signal interconnect 6 to enable one or more of the slave voltage blocks 11b, 11c.

[0077] In some embodiments, in a low power or inactive mode, when a command requires a current load level equal to or below a threshold, power for the slave devices 4b, 4c may come from enabled portions of corresponding disabled voltage blocks 11b, 11c and / or from the corresponding master voltage block 11a via a power sharing line 7 to provide power consuming circuits (e.g., memory circuits 12b, 12c).

[0078] Figure 5AA circuit 38 of a device included in module 2 is shown. Such a circuit 38 may be provided in each of the devices 4a-4e, which have the same structure in an embodiment. The circuit 38 includes an input line 41a, an output line 41b, a NOT gate 43 (also referred to as an inverter), a PMOS transistor 45, an NMOS transistor 47, a transmission gate 49, and a voltage block 11. In some embodiments, the transmission gate 49 may include a first transistor 49a and a second transistor 49b.

[0079] In some embodiments, circuit 38 may be connected to other devices included in module 2 via power sharing line 7. For example, when a device is designated as a master device, the input signal on input line 41a may default to logic "1". NOT gate 43 receives a signal of 1 and outputs a gate output of 0. PMOS transistor 45 receives the gate output at its gate, thereby turning on PMOS transistor 45. The gate output is also received at the gate of first transistor 49a, thereby turning on transistor 49a. An enable signal may be received at the gate of NMOS transistor 47, thereby turning on NMOS transistor 47. An enable signal may also be received at the gate of second transistor 49b, thereby turning on transistor 49b.

[0080] Therefore, the voltage block 11 can generate power at the output line 41 b and output the power. The generated power can be sent to other devices in the module 2 via the power sharing line 7 .

[0081] When an input signal is received at the input line 41a corresponding to the slave device to enter the inactive mode, the NOT gate 43 receives a signal of 0 and outputs a gate output of 1. The PMOS transistor 45 receives the gate output at its gate, thereby turning off the PMOS transistor 45. The gate output is also received at the gate of the first transistor 49a, thereby turning off the first transistor 49a. The input signal can be received at the gate of the NMOS transistor 47, thereby turning off the NMOS transistor 47. The input signal can also be received at the gate of the second transistor 49b, thereby turning off the second transistor 49b. Therefore, the voltage block 11 is disabled. The transmission gate 49 can electrically decouple the voltage block 11 from the voltage block connected downstream of the voltage block 11, so that a high impedance node is formed when the input signal is received at the input line 41a.

[0082] In some embodiments, when an enable signal is received at input line 41a as an input signal corresponding to the slave device entering active mode, the circuit may behave in a manner similar to the master device and may enable voltage block 11. In such embodiments, output line 41b may be coupled to power share line 7.

[0083] In some embodiments, an external power supply may be provided at the source of the PMOS transistor 45. In some embodiments, a ground connection (e.g., a floating ground connection, etc.) may be provided at the source of the NMOS transistor 47. In some embodiments, a positive voltage supply VDD may be provided at the source of the PMOS 45, and a negative voltage supply VSS may be provided at the source of the NMOS transistor 47. In some embodiments, the power share line 7 may carry a generated power supply that may be accompanied by a control signal.

[0084] In some embodiments, when circuit 38 is used in a slave die, voltage block 11 may include voltage control circuitry that may be controlled by circuit 38 included in the slave die. For example, the voltage control circuitry of the slave die may be enabled and / or disabled by circuit 38.

[0085] Figure 5B 2. A circuit 38 of a device included in module 2 is shown. Such a circuit 38 may be provided in each of devices 4a-4e, which have the same structure in some embodiments. Circuit 38 includes input line 41a, first output line 41b, first NOT gate 43, second NOT gate 55, PMOS transistor 45, NMOS transistor 47, first transmission gate 49, second transmission gate 51, or gate 53, mode register 32, and voltage block 11. In some embodiments, transmission gate 49 may include first transistor 49a and second transistor 49b. In some embodiments, second transmission gate 51 may include third transistor 51a and fourth transistor 51b.

[0086] Figure 5B The implementation scheme is different from Figure 5A , so that when an enable signal is received at the input line 41a in the slave device, the output line 41b from the voltage block 11 can be decoupled by the second transmission gate 51. For example, as relative to Figure 5A As explained, when an enable signal is received as an input signal at input line 41a, the first NOT gate 43 receives an input signal of 1, and the voltage block 11 can generate power in the main device and output the power at output line 41b. The output power can be provided to the internal circuit of the device itself that uses the power.

[0087] When the device is a master device, the mode register 32 included in the device may send an input signal of 1 to the OR gate 53, and the OR gate 53 may output a logic 1. The output of the OR gate 53 may be received by the second NOT gate 55, thereby turning on the third transistor 51a. The output of the OR gate 53 may also be received by the fourth transistor 51b, thereby turning on the fourth transistor 51b. Therefore, the second transmission gate 51 may be turned on so that the output line 41b is electrically coupled to the power sharing line 7, and therefore, by default, when the slave device is coupled to the voltage sharing line 7, the master device is enabled to supply voltage to the slave device.

[0088] On the other hand, when the device is a slave device, the mode register 32 included in the device may send a logic 0 to the OR gate 53. The OR gate 53 now acts as a buffer for the output of the NOT gate 43. When the input signal received at the input line 41a is high for the slave device (e.g., enabling the voltage block 11), the second transmission gate 51 may be turned off, so that the output line 41b is electrically decoupled from the voltage sharing line 7 and the output line 41b is coupled to the output of the enabled voltage block 11. Conversely, for the slave device, when the signal received at the input line 41a is a logic 0, the transmission gate 51 is enabled and the output line 41b is coupled to the power sharing line 7, and the output line 41b is decoupled from the disabled voltage block 11.

[0089] In some embodiments, circuit 38 may be applied to Figure 2 The linear voltage regulator 20a-20e and / or the charge pump 22a-22e shown. When the circuit 38 is applied to the linear voltage regulator 20a-20e, the input line 41a can be connected to the corresponding power control circuit 10a-10e, and the output line 41b can be connected to the charge pump 22a-22e and the first power supply sharing line 7a. When the circuit 38 is applied to the charge pump 22a-22e, the input line 41a can be connected to the linear voltage regulator 20a-20e, and the output line 41b can be connected to the memory circuit 12a-12e and the second power supply sharing line 7b.

[0090] Input signals (e.g., enable and disable signals) may be provided within the device. For example, in a slave device, a disable signal is generated, and the slave device may be coupled to the power sharing line 7 to request power from the master device. More specifically, as with respect to Figure 5A As explained, when the disable signal is received at the input line 41a, the NOT gate 43 receives a signal of 0, and the voltage block 11 is disabled. The OR gate 53 receives an output signal of 1 from the NOT gate 43. Therefore, when the disable signal is received at the input line 41a, the power sharing line 7 is electrically coupled to the output line 41b in both the master device and the slave device.

[0091] FIG. 6A to FIG. 6C Shows various conditions Figure 3A The system 30 may reside in each of the control circuits 10a-10e of the semiconductor devices 4a-4e, but FIG. 6A to FIG. 6C The system is shown in various embodiments in different situations specific to a slave or master designated device.

[0092] Specifically, Fig. 6A shows the device designated as the master device Figure 3A System 30. Figure 6BThe system 30 is shown with an instruction in a slave device having a no operation (NOP) command from its command decoder 36 . Figure 6C The system 30 is shown with instructions from the device with a bank activate command from its command decoder 36. Unless otherwise specified, FIG. 6A to FIG. 6C Parts and Figure 3A Like numbered components shown are identical or substantially similar.

[0093] See also Fig. 6A , the system 30 may include first to third OR gates 42a-42c, and a NAND gate 44. Fig. 6A The system 30 represents a master device, so the die designator 34 can send a 0 to the NAND gate 44 so that the output from the NAND gate 44 is always 1 regardless of any signal received from the command decoder 36 through the first OR gate 42a. This output 1 keeps the output of the third OR gate 42c always 1, which keeps the master voltage regulator enabled by default. Therefore, the output of the OR logic gate 42c is Fig. 6A The system 30 is shown labeled VENABLE.

[0094] See also Figure 6B ,and Fig. 6A Similarly, the system 30 may include first to third OR gates 42a-42c and a NAND gate 44. Figure 6B The system 30 represents a slave device, so the die designator 34 can send a 1 to the NAND gate 44 so that when the signal received from its command decoder 36 through the first OR gate 42a is 1, the output from the NAND gate will be 0. When there is a NOP command, the command decoder 36 sends a 1 to the first OR gate 42a so that the output from the first OR gate 42a is 1. Therefore, the NAND gate 44 receives a 1 from the die designator and another 1 from the first OR gate 42a, and outputs a 0 to the third OR gate 42c. Therefore, unless the third OR gate receives a 1 from the second OR gate 42b, the slave voltage block is disabled. As shown in FIG. Fig. 6A As shown, in Figure 6B In the illustrated embodiment of , the output of OR logic gate 42c is 1 in this operating scenario and is labeled VENABLE.

[0095] See also Figure 6C ,and Fig. 6A and Figure 6BSimilarly, the system 30 may include first to third OR gates 42a-42c and a NAND gate 44. Because it is a system 30 of slave devices, the die designator 34 may send a 1 to the NAND gate 44 so that when the signal received from the command decoder 36 through the first OR gate 42a is 1, the output from the NAND gate will be 0. When there is a bank activation command (or any other command that requires a current load value above a threshold), the command decoder 36 sends a 0 to the first OR gate 42a and a 1 to the second OR gate 42b. Therefore, the third OR gate 42c receives a 1 from the second OR gate 42b and the NAND gate 44 and outputs a 1, thereby enabling the slave voltage block. As shown in FIG. Fig. 6A and Figure 6B As shown, in Figure 6C In the illustrated embodiment of , the output of OR logic gate 42c is 1 in this operating scenario and is labeled VENABLE.

[0096] Figure 7 A diagram of a system 50 for self-refresh mode (SRM) in a group of devices 4 a - 4 c connected by signal interconnects 6 is shown. Figure 7 Only three devices 4a-4c are shown. However, in some embodiments, the system 50 may include any number of devices that may be connected by signal interconnects 6. Each device 4a-4c may include a command decoder 36a-36c, a mode register 32a-32c, an AND gate 46a-46c, an oscillator 48a-48c, and a programmable delay generator 54a-54c.

[0097] exist Figure 7 In the illustrated embodiment of, the first device 4a is designated as the master device by the mode register 32a. The second device 4b and the third device 4c are designated as slave devices by the mode registers 32b, 32c. Each command decoder 36a-36c outputs the SRM command signal of 1 to the AND gate 46a-46c. Because the mode register of the master device 4a sends the signal of 1 to the AND gate 46a, the AND gate 46a outputs the oscillator enable signal of 1. However, for the slave devices 4b, 4c, the mode register sends 0 as a signal to the AND gates 46b, 46c, so that the output of the AND gates 46b, 46c is 0. Therefore, the first oscillator 48a is enabled, and the second oscillator 48b and the third oscillator 48c are disabled. Disabling from the oscillators 48b, 48c can be beneficial because they do not draw power. In some embodiments, the system 50 may also include switches 52a-52c between the oscillators 48a-48c and the programmable delay generators 54a-54c. In slave devices 4b, 4c, switches 52b, 52c may isolate oscillators 48a-48c and delay generators 54b, 54c. In some embodiments, switches 52a-52c may include N-channel gates or any high impedance driver.

[0098] The enabled first oscillator 48a outputs a refresh signal of 1 to the delay generators 54a-54c via the interconnect 6 through the switch 52a. In some embodiments, the programmable delay generators 54b, 54c may be omitted or disabled so that the master delay generator 54a sends an interleaved signal to each die 4a-4c via the interconnect 6. In such embodiments, the interconnect 6 may include multiple lines to transmit different signals to different devices. In some embodiments, the master device 4A may send a refresh signal with address information. The address information may include the timing of each refresh in the different devices 4a-4c.

[0099] Figure 8 Schematically illustrates logic for operation according to one embodiment. Command decoder 36 may send command signals to first OR gate 42a, second OR gate 42b, and / or AND gate 46. For example, command decoder 36 may send a self-refresh mode (SRM) command signal to AND gate 46. For a device designated as a master, the SRM command may enable SRM oscillator 48 and send a signal to programmable delay generator 54. In some embodiments, if the device is a slave, the oscillator may be disabled and may be decoupled from signal interconnect 6.

[0100] The programmable delay generator 54 can be started by a start refresh command originating in the master device. The programmable delay generator 54 can control the timing of the self-refresh of the device and can be programmed so that the refresh events of the tube cores in the module can be set deterministically. For example, the delay generator 54 can be programmed to ensure that the refresh events are spaced apart in the time domain to minimize power surges. The start refresh command from the master device can also send an enable signal to the first OR gate 42a. The enable signal enables the voltage regulator 20 and the charge pump 22.

[0101] In some embodiments, the regulated voltage from the voltage regulator 20 and the modified voltage from the charge pump 22 can be shared with other devices via the first power sharing line 7a and the second power sharing line 7b. If the device is designated as a master device by the mode register 32, the charge pump 22 can be enabled by default through the third OR gate 47. In some embodiments, a subset of the power demand commands can also enable the charge pump 22 through the third OR gate 47. One or more power demand commands can be generated by the signal interconnect 6 or in a manner similar to Figure 2 The positions of the first power sharing line 7a and the second power sharing line 7b are connected to other signal lines of the device.

[0102] The command decoder 36 may send signals for bank activation commands, power demand commands, and / or refresh commands. In contrast to the SRM command signals, these signals may not be sent to the AND gate 46. The signal may be sent to the second OR gate 42b. The signal may turn on the voltage regulator 20.

[0103] Fig. 9 A schematic side view of a module 2' is shown. The module 2' shown includes stacked semiconductor devices 4a'-4n' (e.g., memory dies) stacked vertically. The module 2' may include any number of semiconductor devices. In some embodiments, the stacked semiconductor devices 4a'-4n' may be identical. The semiconductor devices 4a'-4n' may be electrically coupled via interconnects (not shown).

[0104] In one aspect, a module is disclosed. The module includes a group of structurally identical dies, the group of structurally identical dies having a first die and a second die. The first die includes a first voltage block and the second die includes a second voltage block. The module also includes an interconnect that electrically connects the first die and the second die. The first voltage block is enabled in a first condition, wherein the second voltage block is disabled in the first condition. The first die and the second die are enabled in a second condition.

[0105] In one embodiment, the first voltage block and the second voltage block are operable to provide at least one of voltage regulation or voltage generation.

[0106] In one embodiment, the second die also includes a second control circuit.

[0107] In one embodiment, the module further includes a power interconnect configured to provide externally regulated power to the second die.

[0108] In one embodiment, the first voltage block includes a first linear voltage regulator and the second voltage block includes a second linear voltage regulator.

[0109] In one embodiment, the first voltage block includes a first charge pump and the second voltage block includes a second charge pump. The first die may be configured to provide an enable signal to the second die in the second condition to enable the second charge pump. The second voltage block may be disabled so that the second regulator is disabled and the second charge pump is enabled.

[0110] In one embodiment, the first die is vertically stacked with the second die.

[0111] In one embodiment, the set of structurally identical dies each include a memory circuit. The memory circuit may include a dynamic random access memory (DRAM).

[0112] In one embodiment, the first die includes a first plurality of voltage regulators and the second die includes a second plurality of voltage regulators. In a first condition, all voltage regulators of the first die may be enabled and at least some voltage regulators of the second die are disabled.

[0113] In one embodiment, the first condition is an inactive mode and the second condition is an active mode.

[0114] In one embodiment, the first voltage block provides power internally generated in the first voltage block to the second die in the first condition.

[0115] In one embodiment, the module also includes a fuse or anti-fuse configured to designate at least one of the dies as a primary die.

[0116] In one embodiment, the first die has a first control circuit configured to provide an enable signal to the second die through the interconnect in the second condition to enable the second voltage block. The second die may include a second control circuit configured to provide a control signal. A first value of the control signal may be used to enable the second voltage block and a second value of the control signal may be used to disable the second voltage block.

[0117] In one aspect, a module is disclosed. The module includes a plurality of memory dies that communicate with each other. At least one of the memory dies is designated as a master die and the remainder of the memory dies are designated as slave dies. In an inactive mode, a master voltage block included in the master die is enabled and a corresponding slave voltage block included in each of the slave dies is disabled. In an active mode, in one or more of the slave dies, the slave voltage block is enabled.

[0118] In one embodiment, in the active mode, the slave die enables the slave voltage block.

[0119] In one embodiment, the main voltage block includes a main linear voltage regulator and a main charge pump.

[0120] In one embodiment, each of the slave voltage blocks includes a slave linear voltage regulator and a slave charge pump.

[0121] In one embodiment, the memory die comprises a dynamic random access memory (DRAM) die.

[0122] In one embodiment, the master die and the slave die are designated by hardware.

[0123] In one embodiment, the memory die are identical in structure and the master die and the slave die are designated by software. The memory die may be configured as a master die by default and may be designated as a slave die by software. The memory die may be configured as a slave die by default and may be designated by software to be used as a master die.

[0124] In one aspect, a method of operating a group of structurally similar dies is disclosed, the group of structurally similar dies comprising a master die and a slave die connected to each other. The method includes enabling a first voltage block of the first die in an inactive mode. The method also includes disabling a second voltage block of the second die in the inactive mode. The method also includes transitioning from the inactive mode to an active mode, and enabling both the first voltage block and the second voltage block in the active mode.

[0125] In one embodiment, the method further includes operating the second die at a lower power in the inactive mode relative to the active mode.

[0126] In one embodiment, the method also includes using the first voltage block to generate a power supply voltage, and providing the power supply voltage from the first die to the second die in the inactive mode. The power supply voltage can be provided from the first die to the second die during the inactive mode to support operations in the second die. The first die and the second die can be connected by a power sharing line configured to transmit the power supply voltage from the first die to the second die. The method also includes electrically decoupling the power sharing line from the voltage block of the second die in the inactive mode. The method may also include, in the active mode, supplying a first internally generated power generated in the first die to a first circuit included in the first die, and supplying a second internally generated power generated in the second die to a second circuit included in the second die.

[0127] In one embodiment, the method further includes supplying voltage from the master die to the slave die in the inactive state.

[0128] In one embodiment, the method further includes sending an enable signal from the master die to the slave die to enable a portion of the slave voltage block.

[0129] In one aspect, a method of operating a group of structurally identical dies is disclosed, the group of structurally identical dies comprising a first die and a second die connected to each other. The method includes supplying a voltage from the first die to the second die in an inactive mode. The first die is in a high power mode and the second die is in a low power mode.

[0130] In one embodiment, the voltage is supplied from the first die to the second die during the inactive mode to support operations in the second die.

[0131] In one embodiment, the method further includes, in an active mode, supplying a first internally generated power source generated in the first die to a first circuit included in the first die, and supplying a second internally generated power source generated in the second die to a second circuit included in the second die. The voltage blocks of the first die and the second die are enabled in the active mode.

[0132] In one embodiment, the first die and the second die are connected by a power share line configured to transfer a voltage from the first die to the second die. The second die electrically decouples the power share line in the active mode.

[0133] In one aspect, a method of operating a group of identical dies is disclosed, the group of identical dies including a master die and a slave die connected to each other. The method includes supplying a control signal from the master die to the slave die. The control signal schedules a self-refresh operation between the slave dies.

[0134] In one embodiment, the control signal enables or disables a voltage block of the slave die.

[0135] In one embodiment, the group of identical dies includes a programmable delay generator.The method may also include scheduling, by the programmable delay generator, the timing of the self-refresh operation.

[0136] In one aspect, a module is disclosed. The module includes a plurality of memory dies that communicate with each other. At least one of the memory dies is designated as a master die and the rest of the memory dies are designated as slave dies. When the module is in an inactive mode, a master voltage block in the master die is enabled and a corresponding slave voltage block in the slave die is disabled. In the inactive mode, the voltage block in the master die is used as a voltage supply for the slave die.

[0137] In one aspect, a module is disclosed. The module includes a group of structurally identical dies, the group of structurally identical dies including a first die and a second die. In an inactive mode of the module, power consumption of the first die enables more voltage blocks than that of the second die.

[0138] In one embodiment, the first die and the second die are in a non-operational mode.

[0139] In one aspect, a method of operating a group of structurally identical dies is disclosed, wherein the group of structurally identical dies are each connected to each other and include a master die and two or more slave dies. The method includes providing a plurality of control signals from the master die to the two or more slave dies. The method also includes controlling a memory refresh operation of the two or more slave dies based on the plurality of control signals.

[0140] In one embodiment, the memory refresh operation includes scheduling a plurality of self-refresh operations among the two or more slave dies.

[0141] In one embodiment, the method further includes using the control signal to selectively enable or disable a plurality of voltage blocks of the slave die.

[0142] In one embodiment, scheduling the plurality of self-refresh operations further comprises programming delays of programmable delay generators of the two or more slave devices.

[0143] In one aspect, a module is disclosed. The module includes a plurality of semiconductor dies that communicate with each other and each include a memory. The plurality of semiconductor dies are divided into at least one main die and at least one slave die. The at least one main die includes a main voltage block, and the at least one slave die includes a slave voltage block. When the module is in an inactive mode, the main voltage block is enabled and the slave voltage block is disabled, and the main voltage block is configured to provide a power supply voltage to the at least one slave die.

[0144] In one embodiment, when the module is in active mode, both the master voltage block and the slave voltage block are enabled.

[0145] In one aspect, a module is disclosed. The module includes a group of structurally identical dies, the group of structurally identical dies including a first die and a second die electrically connected to each other. In an inactive mode of the module, the number of enabled voltage blocks of the first die is greater than the number of enabled voltage blocks of the second die.

[0146] In one embodiment, the first die and the second die are in at least one of a sleep state or a standby state in the inactive mode.

[0147] In one aspect, a module is disclosed. The module includes a group of structurally identical dies, the group of structurally identical dies including a first die having a first voltage block and a first control circuit and a second die having a second control circuit and a second voltage block. The module also includes an interconnect that electrically connects the first die and the second die. In a first condition, the first voltage block is enabled and the second voltage block is disabled. The first voltage block and the second voltage block are enabled in a second condition.

[0148] In one embodiment, the second control circuit is configured to provide a control signal. One value of the signal can be used to enable the second voltage block and a second value of the signal can be used to disable the second voltage block. When the second voltage block is enabled, the output of the second voltage block can provide voltage to the circuit in the second die. The first voltage generated by the first voltage block can be coupled to the interconnect to provide voltage to the circuit in the second die.

[0149] In one embodiment, the second voltage block in the second die includes a voltage control circuit coupled to a voltage generating circuit in the second die. The voltage control circuit can enable or disable the voltage generating circuit in the second die. The voltage generating circuit in the second die can provide voltage to a memory circuit in the second die. The voltage control circuit of the second die can be disabled by the second control circuit. The output of the voltage control circuit in the second die can be decoupled from the input of the voltage generating circuit in the second die. The input to the voltage generating circuit in the second die can be coupled to the output of the voltage control circuit in the first die. When the voltage generating circuit in the second die is enabled, the output of the voltage generating circuit in the second die can be decoupled from the output of the voltage generating circuit in the first die. The voltage generating circuit in the second die can be configured to be enabled by the control circuit in the second die. When the voltage generating circuit in the second die is disabled in an inactive mode, the output of the voltage generating circuit in the second die may be decoupled from the interconnect to provide voltage to the circuit in the second die. The output of the voltage generating circuit in the first die may be coupled to the interconnect to provide voltage to the circuit in the second die. The voltage generating circuit in the second die may be configured to be disabled by the second control circuit. The module may include a dynamic memory device. The activation of the voltage generating circuit in the second die may be configured to be enabled by a command received by the control circuit in the second die. The enable command received by the control circuit of the second die may be a refresh command. The enable command received by the control circuit of the second die may be a storage library activation command. The enable command received by the control circuit of the second die may be a refresh mode command.

[0150] In one embodiment, when the self-refresh timing and self-refresh control logic are enabled in the first die, the self-refresh timing and self-refresh control logic in the second die are disabled. The refresh control logic of the first die may send a refresh start command and send the refresh start command to the second die. The programmable delay generator in the second die may generate a refresh command based at least in part on the received refresh start command and the programmable time. The second die may enable a voltage generating circuit in the second die in response to the refresh command. The programmable time may be programmable based at least in part on a reconfigurable non-volatile memory. The second die may enable a voltage generating circuit in the second die in response to the refresh start command.

[0151] In one embodiment, the first control circuit and the second control circuit are defined at least in part based on fuses.

[0152] In one embodiment, the first control circuit and the second control circuit are defined at least in part based on a reconfigurable non-volatile memory.

[0153] In one embodiment, the interconnect includes a voltage bus configured to transmit a voltage between the dies.

[0154] In one embodiment, the configuration of the control circuitry of the first die and the second die may determine the response of the first voltage generating block and the second voltage generating block to commands received by the control circuitry.

[0155] In one embodiment, the first control circuit and the second control circuit are defined at least in part based on fuses.

[0156] In one embodiment, the first control circuit and the second control circuit are defined at least in part based on a reconfigurable non-volatile memory.

[0157] In one embodiment, the interconnect includes a voltage bus configured to transmit a voltage between the dies.

[0158] In one embodiment, the configuration of the control circuitry of the first die and the second die determines the response of the first voltage generating block and the second voltage generating block to commands received by the control circuitry.

[0159] In one aspect, a module is disclosed. The module includes a group of structurally identical dies. The group of structurally identical dies includes a first die having a first control circuit and a second die having a second control circuit. The module also includes an interconnect electrically connecting the first die and the second die. When the self-refresh timing and self-refresh control logic in the first die are enabled by the first control circuit, the self-refresh timing and self-refresh control logic in the second die are disabled by the second control circuit in the self-refresh mode.

[0160] In one embodiment, the self-refresh control logic of the first die is configured to send a refresh enable command to the second die through the interconnect.

[0161] In one embodiment, the programmable delay generator in the second die is configured to generate a local refresh command based at least in part on the received refresh enable command and a programmable time.

[0162] In one embodiment, refresh operations of the dynamic memory of the first die and refresh operations of the dynamic memory of the second die are staggered in time.

[0163] In one embodiment, the programmable time is defined at least in part based on fuses.

[0164] In one embodiment, the programmable time is defined at least in part based on data programmed in the reconfigurable non-volatile memory.

[0165] In one embodiment, the second die is configured to enable voltage generating circuitry in the second die in response to the refresh enable command.

[0166] In one embodiment, the first die includes an oscillator configured to generate the refresh enable command, wherein the second die includes an oscillator that is disabled when the oscillator of the first die is enabled.

[0167] A method for controlling the timing of self-refresh operations of multiple die is disclosed. The method includes communicating between a group of structurally identical die using an interconnect. The group of structurally identical die includes a first die having a first control circuit and a second die having a second control circuit. The method also includes disabling the self-refresh timing and self-refresh control logic in the second die using the second control circuit. The method also includes enabling the self-refresh timing and self-refresh control logic in the first die using the first control circuit when the self-refresh timing and the self-refresh control logic in the second die are disabled.

[0168] In one embodiment, the method further includes sending a refresh enable command from the self-refresh control logic of the first die to the second die through the interconnect.

[0169] In one embodiment, the method further comprises generating a local refresh command in the second die using a programmable delay generator of the second die in response to the refresh enable command. The method may further comprise interleaving a refresh operation of the dynamic memory of the first die with a refresh operation of the dynamic memory of the second die. The method may further comprise generating the local refresh command based on a programmable time.

[0170] In one embodiment, the method further includes enabling voltage generating circuitry in the second die in response to the refresh enable command.

[0171] In one embodiment, the method further includes generating the refresh enable command using an oscillator of the first die, and disabling an oscillator of the second die when the oscillator of the first die is enabled.

[0172] In one aspect, a module is disclosed. The module includes a group of die with identical structure, the group of die including a first die having a first circuit block and a second die having a second circuit block. The module also includes an interconnect electrically connecting the first die and the second die. The first circuit block is enabled in a first condition and the second circuit block is disabled in the first condition. The first circuit block and the second circuit block are enabled in a second condition.

[0173] In one embodiment, the first circuit block includes the self-refresh timing and self-refresh control logic of the first die, and wherein the second circuit block includes the self-refresh timing and self-refresh control logic of the second die. The first die may also include a first control circuit and the second die may also include a second control circuit. When the self-refresh timing and the self-refresh control logic in the first die are enabled by the first control circuit in the first condition, the self-refresh timing and the self-refresh control logic in the second die are disabled by the second control circuit. The self-refresh control logic of the first die may be configured to send a refresh start command to the second die through the interconnect.

[0174] In one embodiment, the first circuit block includes a first voltage block and the second circuit block includes a second voltage block. The first voltage block and the second voltage block are operable to provide at least one of voltage regulation or voltage generation.

[0175] Although disclosed in the context of certain embodiments and examples, it should be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses and their obvious modifications and equivalents. In addition, although several variations have been shown and described in detail, other modifications within the scope of the present disclosure will be apparent to those skilled in the art based on the present disclosure. It is also envisioned that various combinations or sub-combinations of specific features and aspects of the embodiments may be performed, and these combinations or sub-combinations still fall within the scope of the present invention. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the disclosed invention. Therefore, it is intended that the scope of the invention disclosed herein should not be limited by the above-mentioned specific disclosed embodiments, but should only be determined by a clear reading of the following aspects.

Claims

1. A module comprising: a group of dies with the same structure, the group of dies with the same structure comprising a first die having a first voltage block and a second die having a second voltage block; and an interconnect electrically connecting the first die and the second die, wherein the first voltage block is enabled in a first condition, wherein the second voltage block is disabled in the first condition, and Wherein the first die and the second die are enabled in a second state.

2. A module comprising: a plurality of memory dies in communication with each other, At least one of the memory dies is designated as a master die and the remainder of the memory dies are designated as slave dies, wherein in an inactive mode, a master voltage block included in the master die is enabled and a corresponding slave voltage block included in each of the slave die is disabled, and wherein in an active mode, in one or more of the slave die, the slave voltage block is enabled.

3. A method of operating a group of similar dies, the group of similar dies comprising a master die and a slave die connected to each other, the method comprising: The group is operated in an inactive state with a greater portion of a master voltage block enabled by the master die than a corresponding slave voltage block of the slave die.

4. A method for operating a group of die with the same structure, wherein the group of die with the same structure comprises a first die and a second die connected to each other, the method comprising: enabling a first voltage block of the first die in an inactive mode; disabling a second voltage block of the second die in the inactive mode; transitioning from said inactive mode to an active mode; as well as Both the first voltage block and the second voltage block are enabled in the active mode.

5. A module comprising: a plurality of semiconductor dies communicating with each other and each including a memory, the plurality of semiconductor dies being divided into at least one master die and at least one slave die; wherein the at least one master die comprises a master voltage block, and the at least one slave die comprises a slave voltage block; Wherein when the module is in an inactive mode, the master voltage block is enabled and the slave voltage block is disabled, and the master voltage block is configured to provide a power supply voltage to the at least one slave die.

6. A module comprising: A group of structurally identical dies, the group of structurally identical dies comprising a first die and a second die electrically connected to each other, wherein in an inactive mode of the module, the number of enabled voltage blocks of the first die is greater than the number of enabled voltage blocks of the second die.

7. A module comprising: A group of dies with the same structure, wherein the group of dies with the same structure includes a first die having a first voltage block and a first control circuit and a second die having a second control circuit and a second voltage block; and an interconnect electrically connecting the first die and the second die, wherein the first voltage block is enabled in a first condition, wherein the second voltage block is disabled in the first condition, and Wherein the first voltage block and the second voltage block are enabled in a second condition.

8. A module comprising: A group of tube dies with the same structure, wherein the group of tube dies with the same structure includes a first tube die having a first control circuit and a second tube die having a second control circuit; and an interconnect electrically connecting the first die and the second die, Wherein when the self-refresh timing and self-refresh control logic in the first die are enabled by the first control circuit, the self-refresh timing and self-refresh control logic in the second die are disabled by the second control circuit in the self-refresh mode.

9. A method of controlling the timing of self-refresh operations of a plurality of dies, the method comprising: communicating between a group of structurally identical dies using an interconnect, the group of structurally identical dies including a first die having a first control circuit and a second die having a second control circuit; using the first control circuit to enable self-refresh timing and self-refresh control logic in the first die; as well as The second control circuit is used to disable the self-refresh timing and self-refresh control logic in the second die when the self-refresh timing and the self-refresh control logic in the first die are enabled.

10. A module comprising: A group of dies with the same structure, wherein the group of dies with the same structure includes a first die having a first circuit block and a second die having a second circuit block; and an interconnect electrically connecting the first die and the second die, wherein the first circuit block is enabled in a first condition, wherein the second circuit block is disabled in the first condition, and The first circuit block and the second circuit block are enabled in a second condition.

Images