Improved predictive programming verification

Abstract

The invention relates to improved predictive programming verification. A memory array includes a plurality of memory cells. Control logic coupled to the memory array may cause a program voltage to be applied to a subset of the plurality of memory cells to be programmed to a specified logic level, wherein the specified logic level is associated with a set of logic levels. The control logic may cause a first program verify voltage associated with the set of logic levels to be applied to the memory cells. The control logic may decrement a count associated with the set of logic levels, where the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to a logic level in a predefined set of logic levels, and in response to determining that the count falls below a threshold, the set of logic levels is programmed to the subset of memory cells. A program operation of the subset of the plurality of memory cells is terminated.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to improved predictive program-verify operations. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, nonvolatile memory devices and volatile memory devices. In general, a host system may utilize a memory subsystem to store data at and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present application provides a memory device comprising: a memory array comprising a plurality of memory cells; and control logic operatively coupled to the memory array to perform operations comprising: during a programming operation, applying a programming voltage to a subset of a plurality of memory cells to be programmed to a specified logic level, wherein the specified logic level is associated with a set of logic levels; applying a first programming verification voltage associated with the set of logic levels to the subset of memory cells; in response to applying the first programming verification voltage, decrementing a count associated with the specified logic level, wherein the count indicates the number of remaining programming voltages to be applied for programming the subset of memory cells to a specified logic level in a predefined logic level group; and terminating the programming operation of the subset of the plurality of memory cells in response to determining that the count drops below a threshold.

[0004] In one aspect, the present application provides a method comprising: during a programming operation, applying a programming voltage to a subset of a plurality of memory cells to be programmed to a specified logic level, wherein the specified logic level is associated with a set of logic levels; applying a first programming verification voltage associated with the set of logic levels to the subset of memory cells; and in response to applying the first programming verification voltage, decrementing a count associated with the specified logic level, wherein the count indicates the number of remaining programming voltages to be applied for programming the subset of memory cells to the specified logic level in a predefined logic level group; and in response to determining that the count drops below a threshold, terminating the programming operation of the subset of the plurality of memory cells.

[0005] In yet another aspect, the present application provides a non-transitory computer-readable medium comprising executable instructions that, when executed by a processing device, cause the processing device to perform the following operations: during a programming operation, apply a programming voltage to a subset of a plurality of memory cells to be programmed to a specified logic level, wherein the specified logic level is associated with a set of logic levels; apply a first programming verification voltage associated with the set of logic levels to the subset of memory cells; and in response to applying the first programming verification voltage, decrement a count associated with the specified logic level, wherein the count indicates the number of remaining programming voltages to be applied for programming the subset of memory cells to a specified logic level in a predefined logic level group; and in response to determining that the count drops below a threshold, terminate the programming operation of the subset of the plurality of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1A An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 2 A diagram illustrating voltage threshold distribution grouping according to some embodiments of the present disclosure.

[0010] Figure 3 is a diagram of a program verification operation using an arithmetic algorithm according to an embodiment of the present disclosure.

[0011] Figure 4 A diagram illustrating voltage application during a program operation according to an embodiment of the present disclosure.

[0012] Figure 5 is a flow chart of an example method utilized in an improved system including program-verify operations using an arithmetic algorithm according to some embodiments of the present disclosure.

[0013] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure relate to improved predictive program verification operations. In particular, various aspects of the present disclosure relate to reducing the number of program verification pulses applied during program verification operations compared to other solutions. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1A Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0015] The memory subsystem may include a high-density non-volatile memory device, where data needs to be retained when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logic levels associated with the number of bits stored. The logic levels can be represented by binary values ​​(e.g., "0" and "1") or combinations of such values.

[0016] The memory device may include a plurality of memory cells arranged in a two-dimensional or three-dimensional grid. The memory cells may be formed on a silicon wafer in an array of columns and rows. A word line may refer to a conductive line coupled to a memory cell, which is used together with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. A block hereinafter refers to a unit of a memory device for storing data, and may include a group of memory cells. One or more blocks may be grouped together to form a separate partition (e.g., plane) of a memory device so as to allow concurrent operations on each plane. Each data block may include several sub-blocks, wherein each sub-block is defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. A memory page (also referred to herein as a "page") stores one or more bits of binary data corresponding to data received from a host system. In order to achieve high density, a string of memory cells in a non-volatile memory device may be constructed to include several memory cells that include pillars that at least partially surround a channel material. The memory cells may be coupled to access lines (which are often referred to as "word lines") that are often fabricated together with the memory cells to form a string array in a memory block. The compact nature of certain non-volatile memory devices, such as 3D flash NAND memory, means that word lines are common to many memory cells within a memory block.

[0017] During a programming operation on a non-volatile memory device, certain phases may be performed, including programming, program recovery, program verification, and program verification recovery. During a programming operation, a selected set of memory cells may be programmed by applying a programming voltage to one or more word lines. A high programming voltage may be applied during the programming phase, followed by a program recovery phase in which the nodes are discharged. Next, a verification voltage may be applied during the program verification phase, followed by a verification recovery phase. During the recovery phase, all signals on the word lines are ramped down to some lower voltage level.

[0018] In order to meet various operational and data reliability requirements, the threshold voltage distribution of programmed memory cells (e.g., the distribution of threshold voltages of a group of memory cells programmed to the same logic level) should conform to certain parameters, such as the distribution width (e.g., the difference between the maximum and minimum threshold voltages of a group of memory cells programmed to the same logic level). In addition, triple-level cell (TLC) and quad-level cell (QLC) memory devices have a larger number of logic levels (e.g., eight (8) and sixteen (16), respectively), and impose more stringent requirements on the width of the threshold voltage distribution.

[0019] During a programming operation, the control logic may apply a series of incrementally increasing programming pulses to the control gate of the programmed memory cell to gradually increase the memory cell charge level. A programming verification operation may be performed after applying each programming pulse. The programming verification operation may determine the threshold voltage of the memory cell resulting from the application of the programming pulse. In some examples, the programming verification operation may include storing a target threshold voltage in a page buffer coupled to each bit line (e.g., a target threshold voltage associated with a target logic level will be programmed to the memory cell). The programming verification operation may cause a series of ramp voltages to be applied to the control gate of the memory cell being verified. When a ramp voltage in the series of ramp voltages reaches the threshold voltage of the programmed memory cell, the memory cell turns on, and the sensing circuit system detects the current on the bit line coupled to the memory cell. Thus, the sensing circuit system may compare the current threshold voltage of the memory cell with the stored target threshold voltage. If the current threshold voltage is greater than or equal to the target threshold voltage, no additional programming pulses need to be applied.

[0020] Since some solutions apply a ramp voltage during the program verification operation after each programming pulse is applied, the program verification operation may be time consuming. As the number of bits stored by the memory cell increases, the program verification operation may take longer - for example, a program verification operation on a quad-level cell (QLC) may take longer than a program verification operation on a triple-level cell (TLC). For example, a program verification operation on a QLC memory cell may utilize multiple ramp voltages after each programming pulse is applied. The programming time may be the time a memory device takes to perform a programming operation. This may include the time it takes a non-voltage device to perform a program verification operation. Therefore, the programming time may be time consuming due to the time consuming program verification operation.

[0021] Aspects of the present disclosure address the above and other deficiencies by implementing a program verification operation that utilizes a predictive algorithm to reduce the number of program verification pulses applied. For example, a local media controller of a memory array may use a single program verification level voltage for a group of logic levels. The controller may group the logic levels into any number of groups based on a programming voltage step size (e.g., a Vpgm step size), a memory array size, a number of bits stored by a memory cell, a number of program pulses applied, a read window budget (RWB), etc. The controller may select a lowest program verification voltage level associated with each group determined—e.g., selecting a group verification voltage for each group determined. In addition, the memory device may store the number of remaining program pulses to be applied for programming the memory cell to a specified logic level in a page buffer coupled to a bit line associated with a programming operation (e.g., associated with a memory cell selected for the programming operation). For example, the controller may group the logic levels such that one of the selected groups includes four (4) logic levels.

[0022] In one example, the controller may initiate a programming operation to program the memory cell to one of sixteen logic levels - for example, to one of sixteen voltage threshold distributions. In one example, the controller may determine to group the logic levels into four (4) groups of logic levels, each group containing four (4) logic levels - for example, logic levels associated with logic levels '0000', '0001', '0010', and '0011' may be in a first logic level group, logic levels associated with logic levels '0100', '0101', '0110', '0111' may be in a second logic level group, and so on. Thus, the controller may begin the programming operation by programming the memory cell to a first logic level associated with the first group of logic levels. After causing a programming pulse associated with programming the memory cell to the first logic level to be applied, the controller may cause a programming verification pulse to be applied. In some embodiments, the programming verification pulse may be a group verification voltage determined for the first group - for example, the controller may cause the first group verification voltage to be applied. In addition to causing application of the programming pulses and application of the first set of verify voltages, the controller may decrement a count associated with each logic level in the first set of logic levels.

[0023] For example, the memory device stores information about a sequence of programming operations (e.g., the memory device may store code indicating a sequence to be performed during a programming operation). The programming sequence may indicate the number of programming pulses applied to program the memory cell to a respective logic level—e.g., one (1) programming pulse to program the memory cell to a first logic level; two (2) programming pulses to program the memory cell to a second logic level; three (3) programming pulses to program the memory cell to a third logic level; four (4) programming pulses to program the memory cell to a fourth logic level, etc. Based on this information, the controller may determine the number of programming pulses still to be applied to program the memory cell to the respective logic level. For example, the controller may determine that after applying the programming pulses and the first set of verify voltages, the controller may apply a second programming pulse to program the memory cell to a second logic level (associated with a second threshold voltage distribution), apply a third programming pulse to program the memory cell to a third logic level (associated with a third threshold voltage distribution), and apply a fourth programming pulse to program the memory cell to a fourth logic level (associated with a fourth threshold voltage distribution). Thus, the controller can determine that there is one (1) remaining programming pulse to program the memory cell to the second logic level, two (2) remaining programming pulses to program the memory cell to the third logic level, and three (3) remaining programming pulses to program the memory cell to the fourth logic level. The memory device can store corresponding counts (e.g., count one (1) for the second threshold voltage distribution, count two (2) for the third threshold voltage distribution, etc.) at a page buffer coupled to the bit line. The controller can decrement each corresponding count by one (1) after a subsequent programming pulse - for example, the controller can track the number of remaining programming pulses for memory cells to be programmed to the corresponding voltage threshold distribution.

[0024] For example, the controller may cause a second programming pulse to be applied, and cause the first set of verification voltages to be applied again after the second programming pulse. After applying the first set of verification voltages a second time, the controller may decrement the respective counts for each threshold voltage distribution—e.g., decrement the count associated with the second threshold voltage distribution to zero, decrement the count associated with the third threshold voltage distribution to one (1), and so on. In at least one embodiment, the controller may stop further programming of the memory cell when the respective voltage threshold distribution count of the memory cell is zero—e.g., stop programming the memory cell to be programmed to the second voltage threshold distribution when the count associated with the second threshold voltage distribution is zero. The controller may continue to cause programming pulses and the first set of verification voltages to be applied until each respective count of each threshold voltage distribution in the first set of threshold voltage distributions is zero (0). In such an example, the controller may then continue to program the memory cell to the second set of threshold voltage distributions in a similar manner.

[0025] By implementing an improved predictive program-verify operation, a memory device can reduce the number of program-verify pulses applied. This can reduce the overall power consumption of the system and reduce the overall programming time.

[0026] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0030] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0031] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of the like. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages that may refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-OR flash memory, electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to operate on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, the memory device 130 may represent a single die with some control logic (e.g., the local media controller 135) embodied thereon. In some embodiments, one or more components of the memory subsystem 110 may be omitted.

[0042] In one embodiment, the memory device 130 includes a program verification component 113 that can manage program verification operations on a non-volatile memory device (e.g., memory device 130) of the memory subsystem 110. For example, the program verification component 113 can store information about the number of logic levels and the corresponding set of verification voltages for each set of logic levels. The program verification component 113 can also store the number of remaining programming pulses for programming the memory cell to the logic level - for example, after applying the first set of verification voltages for each logic level in the corresponding group, the number of programming pulses to be applied to the memory cell to program the memory cell to the corresponding logic level. The number of remaining programming pulses can be referred to as a count - for example, each corresponding logic level can have a corresponding count. The program verification component 113 can predict when the memory cell is programmed to a specified logic level based on updating the count of each corresponding logic level - for example, when the corresponding count is zero (0), it is predicted that the memory cell has been programmed, indicating that no additional programming pulses should be applied. For example, the program verification component 113 can apply a first programming pulse and a first set of verification level voltages. The program verification component 113 may decrement a count associated with each respective logic level distribution (e.g., the number of programming pulses remaining after applying the first set of verification voltages) and stop further programming of the memory cells to the logic level associated with the count zero (0). In one embodiment, the program verification component 113 may continue this operation until all groups are programmed. For example, the program verification component 113 may store information indicating that the group includes two (2) or more logic levels. The program verification component 113 may also store information indicating that zero (0) programming pulses remain after the first set of verification voltages for the first logic level and one (1) programming pulse remains after the first set of verification voltages for the second logic level. Thus, after applying the first set of verification voltages, the program verification component 113 may stop further programming of the memory cells to be programmed to the first logic level. The program verification component 113 may then apply the second programming voltage and group verification level a second time and decrement the count associated with the second logic level—e.g., decrementing the count to zero (0) after applying the second programming pulse. Therefore, after the count is zero (0), the program verification component 113 can stop programming of memory cells to be programmed to the second logic level.

[0043] In some embodiments, the memory subsystem controller 115 includes at least a portion of the program verification component 113. For example, the memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the program verification component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the program verification component 113 and is configured to perform the functionality described herein. In such embodiments, the program verification component 113 may be implemented using hardware or as firmware, which is stored on the memory device 130 and executed by the control logic (e.g., the program verification component 113) to perform operations related to program recovery described herein.

[0044] Figure 1B is a first device in the form of a memory device 130 according to an embodiment and a memory subsystem (eg, Figure 1A 1 is a simplified block diagram of a second device in the form of a memory subsystem 110 of the present invention communicating with a memory subsystem controller 115 of the present invention. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical appliances, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device. The memory device 130 can include a memory subsystem controller 115 as described in reference to FIG. Figure 1A The programming verification component 113 is described.

[0045] Memory device 130 includes a memory cell array 104 that is logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1B In one embodiment, memory cell array 104 (ie, "memory array") may include a number of sacrificial memory cells for detecting the occurrence of read disturb in memory device 130, as described in detail herein.

[0046] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 160 to manage the input of commands, addresses, and data to memory device 130 and the output of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 160 and row decoding circuitry 108 and column decoding circuitry 109 to latch address signals prior to decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0047] The controller (e.g., the local media controller 135 inside the memory device 130) controls access to the memory cell array 104 in response to a command and generates status information of the external memory subsystem controller 115, that is, the local media controller 135 is configured to perform an access operation (e.g., a read operation, a program operation, and / or an erase operation) on the memory cell array 104. The local media controller 135 communicates with the row decoding circuit system 108 and the column decoding circuit system 109 to control the row decoding circuit system 108 and the column decoding circuit system 109 in response to an address.

[0048] The local media controller 135 also communicates with cache registers 172. The cache registers 172 latch incoming or outgoing data as directed by the local media controller 135 to temporarily store the data while the memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from the cache registers 172 to the data registers 170 for transmission to the memory cell array 104; the new data may then be latched in the cache registers 172 from the I / O control circuitry 160. During a read operation, data may be transferred from the cache registers 172 to the I / O control circuitry 160 for output to the memory subsystem controller 115; the new data may then be transferred from the data registers 170 to the cache registers 172. The cache registers 172 and / or the data registers 170 may form a page buffer of the memory device 130 (e.g., may form a portion thereof). The page buffer may further include a sensing device ( Figure 1B 104) to sense the data state of the memory cells of the memory cell array 104, for example by sensing the state of the data lines of the memory cells. The status register 122 can communicate with the I / O control circuitry 160 and the local memory controller 135 to latch the status information for output to the memory subsystem controller 115.

[0049] The memory device 130 receives control signals at the memory subsystem controller 115 from the local media controller 135 through the control link 132. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the nature of the memory device 130, additional or alternative control signals (not shown) may be further received via the control link 132. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 236, and outputs the data to the memory subsystem controller 115 via the I / O bus 236.

[0050] For example, a command may be received via input / output (I / O) pins [7:0] of the I / O bus 236 at the I / O control circuitry 160, and the command may then be written into the command register 124. An address may be received via input / output (I / O) pins [7:0] of the I / O bus 236 at the I / O control circuitry 160, and the address may then be written into the address register 114. Data may be received via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices at the I / O control circuitry 160, and the data may then be written into the cache register 172. The data may then be written into the data register 170 for use in programming the memory cell array 104.

[0051] In an embodiment, cache register 172 may be omitted and data may be written directly into data register 170. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although reference may be made to I / O pins, they may include any conductive node, such as a commonly used conductive pad or conductive bump, that enables electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115).

[0052] Those skilled in the art will appreciate that additional circuitry and signals may be provided and simplified. Figure 1B It should be appreciated that reference Figure 1B The functionality of the various block components described may not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1BAlternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1B Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0053] Figure 2 A diagram 200 illustrating an operation utilizing improved predictive program verification according to some embodiments of the present disclosure. In one embodiment, diagram 200 may illustrate one possible grouping of threshold voltage distributions associated with a specified logic level (e.g., distributions associated with a particular program verify (PV) voltage). It should be noted that the number of threshold voltage distributions shown in diagram 200 and / or the number of groups shown are for illustrative purposes only and are one example of many possibilities. That is, diagram 200 may illustrate any number of threshold voltage distributions (e.g., two (2), four (4), eight (8), sixteen (16), thirty-two (32), etc.) and any number of groups 210 (e.g., two (2), three (3), four (4), five (5), six (6), seven (7), eight (8), etc.). In some embodiments, diagram 200 may illustrate threshold voltages associated with a quad level cell (QLC). In other embodiments, the diagram 200 may illustrate threshold voltage distributions for a multi-level cell (MLC), a triple-level cell (TLC), a penta-level cell (PLC), etc. In this embodiment, the diagram 200 illustrates sixteen threshold voltage distributions (e.g., threshold voltage distributions 205 - a through 205 - p), four (4) groups 210 (e.g., groups 210 - a through 210 - d), where each group 210 has a corresponding group verification voltage 215.

[0054] In one embodiment, a memory device (e.g., as shown in reference Figure 1AThe control logic of the described memory device 130 may group specified voltage levels (e.g., their corresponding threshold voltage distributions) into groups 210. In some embodiments, the control logic may place the logic levels (e.g., corresponding threshold voltage distributions) into groups based on the programming voltage step size (e.g., Vpgm step size), the memory array size, the number of bits stored by the memory cells, the number of programming pulses applied, the read window budget (RWB), etc. - for example, based on memory cells storing four (4) bits, the memory device may have a larger number of groups to increase the read window budget, or a smaller number of groups. In the example shown in diagram 200, the control logic may select four (4) groups, each group having four (4) threshold voltage distributions. For example, group 210-a may include logic levels associated with threshold voltage distribution 205-a, threshold voltage distribution 205-b, threshold voltage distribution 205-c and threshold voltage distribution 205-d, while group 210-b may include logic levels associated with threshold voltage distribution 205-e, threshold voltage distribution 205-f, threshold voltage distribution 205-g and threshold voltage distribution 205-h, etc. - for example, group 210-c may include threshold voltage distributions 205-i to 205-l, and group 210-d may include threshold voltage distributions 205-m to group 210-p. It should be noted that each group 210 may include any number of threshold voltage distributions 205, and each group may include a different number of threshold voltages - for example, the group 210 may include one (1), two (2), three (3), four (4), five (5), six (6), seven (7), eight (8), etc. threshold voltage distributions 205.

[0055] In some embodiments, the control logic may select or program a group verification voltage 215 for each selected group 210. In some embodiments, the group verification voltage 215 may be a minimum (e.g., minimum in magnitude) verification voltage 215 for the group. For example, group verification voltage 215-a, group verification voltage 215-b, group verification voltage 215-c, and group verification voltage 215-d may be verification voltages having minimum magnitudes for each respective group 210—e.g., group verification voltage 215-b may be the minimum verification voltage applied to group 210-b during a program verification operation. In at least one embodiment, the memory device may cause the group verification voltage 215 to be applied for at least each program verification operation associated with the respective group 210-b. For example, the memory device may cause the group verification voltage 215-b to be applied for each program verification operation associated with the group 210-b. Reference Figures 3 to 5 Additional details regarding applying group verify voltage 215 for each program verify operation associated with group 210 are described.

[0056] In some embodiments, the control logic may also store the number of programming pulses remaining for the corresponding threshold voltage distribution 205 after applying the group verification voltage 215, as shown in FIG. Figure 3 Thus, after storing a plurality of threshold voltage distributions, determining which threshold voltage distribution 205 is in group 210, and information about the number of remaining programming pulses, the control logic of the memory device can perform a program verification operation.

[0057] Figure 3 A diagram 300 is illustrated for improved predictive programming verification operations according to some embodiments of the present disclosure. In one embodiment, the diagram 300 may include a Figure 2 The group 210-b described. It should be noted that Figure 300 may show one possible grouping of logic levels and their corresponding threshold voltage distributions (e.g., distributions associated with a particular program verify (PV) voltage). It should be noted that the number of threshold voltage distributions shown in Figure 300 is for illustrative purposes only and is one example of many possibilities. That is, Figure 300 may illustrate any number of threshold voltage distributions (e.g., two (2), four (4), eight (8), sixteen (16), thirty-two (32), etc.). In some embodiments, Figure 300 may illustrate threshold voltages associated with a quad-level cell (QLC). In other embodiments, Figure 300 may illustrate threshold voltage distributions for a multi-level cell (MLC), a triple-level cell (TLC), a penta-level cell (PLC), etc. In this embodiment, Figure 300 illustrates group 210-b having four (4) threshold voltage distributions 205-e to 205-h. In some embodiments, group 210-b may include as described in reference Figure 2 Depicted group verification voltage 215-b.

[0058] In some embodiments, the control logic of the memory device may determine the number of programming pulses that remain to be applied after the group verify voltage 215 to program the memory cell to the corresponding logic level. For example, after applying the group verify voltage 215-b to the group 210-b, the control logic may determine the number of programming pulses remaining (e.g., still to be applied) for each logic level. In one embodiment, the control logic may determine the number of remaining programming pulses based on a programming sequence stored on the memory device (e.g., a sequence indicating which programming voltages to apply to program all memory cells to the corresponding logic state) - for example, based on a stored programming sequence indicating the number of programming pulses applied in each programming operation. In some embodiments, the programming sequence may also enable the control logic to determine when the memory cell is programmed into a threshold voltage distribution 205 associated with the logic level - for example, the control logic may determine that the memory cell is programmed into the threshold voltage distribution 205 after applying an "n" number of programming pulses, where "n" is based on the logic level and the corresponding threshold voltage level. In some embodiments, the control logic is configured to store the information in a page buffer coupled to the bit line connected to the memory cell being programmed. For example, the control logic may cause the group verify voltage 215-b to be applied and determine, based on the programming sequence, that an additional prediction pulse 305-a should be applied to program the memory cell within the threshold voltage distribution 205-f. In some embodiments, the control logic may also determine that after programming the memory cell to the threshold voltage distribution 205-f, an additional prediction pulse 305-b is required to program the memory cell to the logic level associated with the threshold voltage distribution 205-g. In one embodiment, after programming the memory cell to the threshold voltage distribution 205-g, the control logic may determine that an additional prediction pulse 305-c is required to program the memory cell to the logic level associated with the threshold voltage distribution 205-h. Thus, the memory device may store the following information shown in Table 1:

[0059]

[0060] Table 1

[0061] In some embodiments, the control logic may store the information shown in Table 1 in a page buffer coupled to the bit lines. In some embodiments, the control logic may store the bits corresponding to the numbers shown in Table 1 - for example, storing bits '00' corresponding to the number zero (0), storing bits '01' corresponding to the number one (1), storing bits '10' corresponding to the number two (2), and storing bits '11' corresponding to the number three (3). It should be noted that Table 1 illustrates one possible example, and other examples are possible. In other embodiments, the number of remaining programming pulses may be different - for example, the number of remaining programming pulses of the threshold voltage distribution 205-f to the threshold voltage distribution 205-h may be greater than or equal to one (1), two (2), three (3), four (4), five (5), six (6), seven (7), eight (8), etc. Additionally, there may be any number of additional prediction pulses 305 between two threshold voltage distributions 205—for example, there may be one (1), two (2), three (3), four (4), five (5), six (6), seven (7), eight (8), etc. programming pulses between two threshold voltage distributions.

[0062] In some embodiments, when a specified logic level is associated with a count of zero (0), the control logic may stop programming certain memory cells - e.g., stop applying additional programming pulses to memory cells to be programmed to a logic level associated with a threshold voltage distribution 205-a after applying the group verify voltage 215-b. In some embodiments, the control logic may also decrement a count (e.g., the number of remaining programming pulses associated with each respective threshold voltage distribution 205) after applying a programming pulse and a subsequent group verify voltage - e.g., after each application of a programming pulse after applying the group verify voltage 215-b. In one embodiment, the control logic may cause a first programming pulse and a second group verify voltage 215-b to be applied after applying the group verify voltage 215-b, and decrement each count corresponding to a respective logic level of a threshold voltage distribution by one (1). For example, the count associated with the logic level associated with threshold voltage distribution 205-f is decremented to zero (0), the count associated with the logic level associated with threshold voltage distribution 205-g is decremented to one (1), and the count associated with the logic level associated with threshold voltage distribution 205-h is decremented to two (2) - e.g., changing bit '01' to '00' for threshold voltage distribution 205-f, changing bit '10' to '01' for threshold voltage distribution 205-g, and changing bit '11' to '10' for threshold voltage distribution 205-h. The control logic may continue similar operations until a memory cell intended to be programmed to a threshold voltage distribution 205 in group 210 is programmed - e.g., until a memory cell is programmed to threshold voltage distribution 205-h of group 210-b. The control logic may use similar operations for other groups (eg, groups 210 - a , 210 - c , and 210 - d as described with reference to FIG. 1 ).

[0063] Figure 4 400 is a diagram illustrating application of programming pulses and program verification voltages according to some embodiments of the present disclosure. In one embodiment, the operations referenced by diagram 400 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the operations of diagram 400 are performed by Figure 1A and Figure 1B The local media controller 135 or the programming verification component 113 executes.

[0064] During a programming operation performed on a non-volatile memory device such as memory device 130, certain voltages may be applied to the memory cells to increase their threshold charge—for example, programming voltage 405 may be incrementally ramped up to increase the memory threshold voltage to a target voltage threshold. The programming operation may include certain phases, including programming, program recovery, program verification, and program verification recovery. Diagram 400 may also show a program verification voltage applied after the corresponding programming voltage 405. As shown in FIG. Figures 2 to 3 As described, memory devices can group threshold voltage distributions together and use one group verification voltage for the respective groups. Diagram 400 illustrates an example of four (4) program verification voltages 410 being applied—e.g., program verification voltage 410-a, program verification voltage 410-b, program verification voltage 410-c, and program verification voltage 410-d. In some embodiments, the four (4) program verification voltages 410 can correspond to four groups (e.g., as shown in reference Figure 2 It should be noted that this is only one example and any number of groups (and corresponding program verify voltages 410) are possible, as shown in FIG. Figure 2 and 3 Additionally, diagram 400 illustrates an embodiment in which 21 programming voltages 405 are applied to program a memory cell to one of sixteen (16) distributions. It should be noted that any number of programming pulses may be applied (e.g., any number of programming pulses greater than 16 for 16 distributions), and that there may be any number of voltage threshold distributions - e.g., the timing diagrams for MLC, TLC, and PLC memory cells may differ from the illustrated diagram 400.

[0065] In one embodiment, the control logic of the memory device may cause an initial programming voltage 405-a to be applied. In some embodiments, the control logic may then apply a first set of verification voltages (e.g., program verification voltage 410-a) after programming voltage 405-a. In some embodiments, the control logic may also decrement a count associated with each respective logic level associated with a threshold voltage distribution of the group associated with program verification voltage 410-a, as described with reference to FIG. Figure 3 4. As described above. After each subsequent programming voltage 405, the control logic may continue to apply slightly ramped (e.g., incrementally larger) programming voltages 405 and program verification voltages 410-a until all memory cells associated with the first group are programmed. In such embodiments, the control logic may cause the next group of program verification voltages 410 to be applied—for example, the control logic may cause program verification voltage 410-b to be applied after programming memory cells to all logic levels associated with the threshold voltage distribution of the first group. The control logic may continue to follow similar operations until all programming voltages 405-u are applied.

[0066] In at least one embodiment, the control logic may apply two or more program verification voltages 410 after the corresponding programming voltage 405. For example, the control logic may cause program verification voltage 410-a and program verification voltage 410-b to be applied after programming voltage 405-e. In at least one embodiment, program verification voltage 410-b may ensure that each memory cell in the first group is programmed - for example, program verification voltage 410-b may exceed the target voltage of each memory cell in the first group. Thus, the control logic may ensure that the predicted number of programming pulses is sufficient to program the memory cells to a set of logic levels. The control logic may similarly cause program verification voltage 410-b and program verification voltage 410-c to be applied after programming voltage 405-i, and cause program verification voltage 410-c and program verification voltage 410-d to be applied after programming voltage 405-m. In some embodiments, the control logic may avoid applying any program verification voltage after the corresponding programming voltage. For example, the control logic may avoid applying any program verification voltage 410 after applying programming voltage 405-r. In some embodiments, the number of program verify voltages 410 applied after the corresponding program voltage may depend on the width of the voltage threshold distribution or read window budget (RWB) of the memory device.

[0067] Figure 5 5 is a flowchart of an example method for implementing an improved program verification operation with an arithmetic algorithm according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1A The local media controller 135 or programming verification component 113 of the present invention is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0068] Prior to operation 505, a programming operation may be initiated on the memory array. For example, processing logic (e.g., Figure 1A The program verification component 113 of the embodiment of the present invention can initiate a programming operation on the memory array, wherein the memory array includes memory cells that can be programmed to one or more logic levels (e.g., as shown in the reference Figure 22. In at least one embodiment, the memory cell is a quad level cell (QLC) having sixteen (16) threshold voltage distributions.

[0069] At operation 505, during a programming operation, a programming voltage is applied to a subset of the plurality of memory cells to be programmed to a specified logic level. For example, during a programming operation, processing logic may cause a programming voltage to be applied to a subset of the plurality of memory cells to be programmed to a specified logic level, where the specified logic level is associated with a set of logic levels. For example, processing logic may cause programming voltage 405-a to be applied to program the memory cells to a first logic level (e.g., a logic level associated with threshold voltage distribution 205-a). In some embodiments, processing logic may ramp up the programming voltage throughout the programming operation—e.g., incrementally increase the programming voltage throughout the programming operation, as described with reference to FIG. Figure 4 For example, the processing logic may cause a second programming voltage to be applied to a memory cell to be programmed to a second specified logic level in the set of logic levels. In such an example, the second programming voltage may be greater than the programming voltage. Figure 2 As described, control logic can select a logic level group and apply a single program verify voltage to program the memory cell to each logic level in the logic level group - e.g., creating groups 210-a through 210-d. In some embodiments, control logic can select a group based on a programming voltage step size (e.g., a Vpgm step size), a memory array size, a number of bits stored by a memory cell, a number of program pulses applied, a read window budget (RWB), etc.

[0070] At operation 510, a first program verification voltage associated with the set of logic levels is applied to a subset of memory cells. For example, processing logic may apply a first program verification voltage associated with the set of logic levels to a subset of memory cells—e.g., causing group verification voltage 215-a to be applied, as described with reference to FIG. Figure 2 Described. Reference Figure 2As described above, processing logic may apply the same first program verify voltage to each logic level in the set of logic levels. Thus, in response to causing the second program voltage to be applied, processing logic may cause the first program verify voltage associated with the first set of logic levels to be applied to the memory cells. In some embodiments, processing logic may continue to apply the first program verify voltage until all memory cells to be programmed to the first set of logic levels are programmed to the first set of logic levels. In such embodiments, processing logic may then apply a second program verify voltage associated with the second set of logic levels—for example, applying group verify voltage 215-b to group 210-b, as described above with reference to FIG. Figure 2 and 3 described.

[0071] At operation 515, in response to applying the first program verify voltage, a count associated with the specified logic level is decremented. For example, the processing logic may decrement a count associated with the specified logic level, wherein the count indicates the number of remaining programming voltages to be applied for programming the subset of memory cells to the specified logic level in the predefined logic level group. In at least one embodiment, the count indicates the number of remaining programming voltages to be applied before the memory cells are programmed to the corresponding logic level—for example, the count may refer to the number of programming pulses still to be applied to the memory cells to program the memory cells to the corresponding logic level, as described in reference to FIG. Figure 3 In response to applying the first program verify voltage, the processing logic may also decrement a count associated with a corresponding logic level in the first set of threshold logic levels. In at least one embodiment, the count associated with each corresponding logic level in the first set of logic levels is stored in a page buffer that is coupled to the bit lines connected to the subset of memory cells. In some embodiments, in response to applying the first program verify voltage, the processing logic may decrement a count associated with a second threshold logic level of the first set of logic levels—for example, where the count indicates the number of remaining programming voltages to be applied before the memory cell is programmed to the second logic level.

[0072] At operation 520, in response to determining that the count falls below a threshold, a programming operation of a subset of the plurality of memory cells is terminated. For example, in response to decrementing the count, the processing logic may determine that the count satisfies the threshold. For example, the processing logic may determine that the count is at zero (0), as described in reference to FIG. Figure 3As described. In some embodiments, the processing logic may determine that the count fails to meet a threshold value—e.g., the count is greater than zero (0). In such embodiments, the processing logic may continue to program the memory cells associated with the corresponding logic level—e.g., continue to apply the programming voltage to the memory cells to be programmed to the logic level associated with the corresponding threshold voltage distribution. For example, during a programming operation, the processing logic may cause a second programming voltage to be applied to a second subset of a plurality of memory cells to be programmed to a second specified logic level, wherein the second specified logic level is associated with a second group of logic levels. The processing logic may then cause a second programming verification voltage associated with the second group of logic levels to be applied to the second subset of the plurality of memory cells. In at least one embodiment, in response to applying the second programming verification voltage, the processing logic may decrement a second count associated with the second specified logic level, wherein the second count indicates a second number of remaining programming voltages to be applied to the second subset of memory cells to be programmed to the second specified logic level in the second group of logic levels. In some embodiments, in response to determining that the count exceeds the second threshold value, the processing logic may continue to perform a programming operation on the second subset of the plurality of memory cells. In one embodiment, in response to determining that the count satisfies the threshold, processing logic may terminate the programming operation of the subset of memory cells—e.g., processing logic may inhibit further programming of the subset of memory cells. In some embodiments, processing logic may predict that a memory cell is programmed to a corresponding logic level based on the count being zero rather than ramping up a program verify voltage and comparing the current threshold voltage to a target threshold voltage.

[0073] In some embodiments, each respective logic level is associated with a different program verification level, and the first program verification voltage associated with the first group has a minimum magnitude of a different program verification level. Figure 2As described, each logic level associated with a corresponding threshold voltage distribution may have one or more different associated program verify levels. However, for each group 210, a lowest program verify level voltage is selected, e.g., group verify voltage 210-b of group 210-b is lower than the voltages of the program verify levels associated with the remaining logic levels. In at least one embodiment, there are at least two or more groups of logic levels—e.g., there may be two (2) groups, three (3) groups, four (4) groups, five (5) groups, six (6) groups, seven (7) groups, eight (8) groups, etc. In some embodiments, a second group of logic levels is associated with a second program verify voltage that is greater than the first program verify voltage—e.g., group verify voltage 215-d may be greater than group verify voltage 215-c, group verify voltage 215-c may be greater than group verify voltage 215-b, and group verify voltage 215-b may be greater than group verify voltage 215-a. In some embodiments, the gap between the first program verification voltage and the second program verification voltage is based on a step size between two or more programming voltages - for example, the gap between group verification voltage 215-a and group verification voltage 215-b can be based on a step size between a programming voltage associated with group 210-a and a programming voltage associated with group 210-b. Alternatively, since the group can be selected based on the programming voltage step size, the selected group verification voltage can also be based on the programming voltage step size. In at least one embodiment, in response to causing the first program verification voltage to be applied, the processing logic can decrement a count associated with each of the logic levels. In at least one embodiment, the number of logic levels in the set of logic levels is equal to the number of logic levels in the second set of logic levels.

[0074] In at least one embodiment, processing logic may cause a second programming voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logic level, wherein the second logic level is associated with the set of logic levels. In such embodiments, processing logic may cause a first programming verification voltage associated with the set of logic levels to be applied to the second subset of the plurality of memory cells. Additionally, in response to applying the first programming verification voltage, processing logic may decrement a second count associated with the second specified logic level, wherein the second count indicates the number of remaining programming voltages to be applied to program the second subset of memory cells to the second specified logic level in the set of predefined logic levels. In one embodiment, in response to determining that the count drops below a second threshold, processing logic may terminate the programming operation of the second subset of the plurality of memory cells.

[0075] Figure 6An example machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., the host system 120 of FIG. 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem 110 of FIG. 1 ) or may be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the program verification component 113 of FIG. 1 to perform operations). In one embodiment, the program verification component 113 is configured to track the number of voltage threshold distribution groups. For example, the program verification component 113 may store the number of programming pulses remaining for each respective voltage threshold distribution after applying the respective set of verification levels. The program verification component 113 may then decrement the number (e.g., count) associated with each respective voltage threshold distribution group and inhibit programming of memory cells that are programmed to the voltage threshold distribution associated with a count of zero (0), as described with reference to FIGS. 1-5 . In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. In a peer-to-peer (or distributed) network environment, the machine may operate in the capacity of a server or a client machine in a client-server network environment, or in a cloud computing infrastructure or environment.

[0076] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0077] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0078] Processing device 602 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 to communicate via a network 620.

[0079] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 404 may correspond to the memory subsystem 110 of FIG. 1 .

[0080] In one embodiment, the instructions 626 include instructions to implement functionality corresponding to the voltage applying component 113 to perform programming operations for the processing device 602. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0081] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0082] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0083] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. Structures for a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0085] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0086] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory device, comprising: a memory array comprising a plurality of memory cells; and control logic operatively coupled to the memory array to perform operations including: causing a programming voltage to be applied to a subset of the plurality of memory cells to be programmed to a specified logic level during a programming operation, wherein the specified logic level is associated with a set of logic levels; causing a first program verify voltage associated with the set of logic levels to be applied to the subset of memory cells; responsive to applying the first program verify voltage, decrementing a count associated with the designated logic level, wherein the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to the designated logic level in a predefined set of logic levels; and In response to determining that the count has fallen below a threshold, the programming operation of the subset of the plurality of memory cells is terminated.

2. The memory device of claim 1 , wherein the operations further comprise: causing a second programming voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logic level, wherein the second logic level is associated with the set of logic levels; causing the first program verify voltage associated with the set of logic levels to be applied to the second subset of the plurality of memory cells; responsive to applying the first program verify voltage, decrementing a second count associated with the second designated logic level, wherein the second count indicates a number of remaining programming voltages to be applied for programming the second subset of memory cells to the second designated logic level in the predefined set of logic levels; and In response to determining that the count falls below a second threshold, the programming operation of the second subset of the plurality of memory cells is terminated.

3. The memory device of claim 1, wherein the count associated with the specified logic level is stored in a page buffer coupled to a bit line connected to the subset of memory cells.

4. The memory device of claim 1, wherein each respective logic level is associated with a different program verify level, and the first program verify voltage associated with the set of logic levels has a minimum magnitude of the different program verify levels.

5. The memory device of claim 1, wherein the operations comprise: In response to causing the first program verify voltage to be applied, a count associated with each of the logic levels in the predefined logic level group is decremented.

6. The memory device of claim 1, wherein the operations further comprise: causing a second programming voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logic level during the programming operation, wherein the second specified logic level is associated with a second set of logic levels; causing a second program verify voltage associated with the second set of logic levels to be applied to the second subset of the plurality of memory cells; responsive to applying the second program verify voltage, decrementing a second count associated with the second designated logic level, wherein the second count indicates a second number of remaining programming voltages to be applied to the second subset of memory cells to be programmed to the second designated logic level in the second set of logic levels; and Responsive to determining that the count exceeds a second threshold, continuing the programming operation of the second subset of the plurality of memory cells.

7. The memory device of claim 6, wherein a number of logic levels in the set of logic levels is equal to a number of logic levels in the second set of logic levels.

8. The memory device of claim 1, wherein the memory cell is a quad-level cell (QLC).

9. A method comprising: During a programming operation, causing a programming voltage to be applied to a subset of a plurality of memory cells to be programmed to a specified logic level, wherein the specified logic level is associated with a set of logic levels; causing a first program verify voltage associated with the set of logic levels to be applied to the subset of memory cells; and responsive to applying the first program verify voltage, decrementing a count associated with the designated logic level, wherein the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to the designated logic level in a predefined set of logic levels; and In response to determining that the count has fallen below a threshold, the programming operation of the subset of the plurality of memory cells is terminated.

10. The method according to claim 9, further comprising: causing a second programming voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logic level, wherein the second logic level is associated with the set of logic levels; causing the first program verify voltage associated with the set of logic levels to be applied to the second subset of the plurality of memory cells; responsive to applying the first program verify voltage, decrementing a second count associated with the second designated logic level, wherein the second count indicates a number of remaining programming voltages to be applied for programming the second subset of memory cells to the second designated logic level in the predefined set of logic levels; and In response to determining that the count falls below a second threshold, the programming operation of the second subset of the plurality of memory cells is terminated.

11. The method of claim 9, wherein the count associated with the specified logic level is stored in a page buffer coupled to a bit line connected to the subset of memory cells.

12. The method of claim 9, wherein each respective logic level is associated with a different program verify level, and the first program verify voltage associated with the set of logic levels has a minimum magnitude of the different program verify levels.

13. The method according to claim 9, further comprising: In response to causing the first program verify voltage to be applied, a count associated with each of the logic levels in the predefined logic level group is decremented.

14. The method according to claim 9, further comprising: causing a second programming voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logic level during the programming operation, wherein the second specified logic level is associated with a second set of logic levels; causing a second program verify voltage associated with the second set of logic levels to be applied to the second subset of the plurality of memory cells; responsive to applying the second program verify voltage, decrementing a second count associated with the second designated logic level, wherein the second count indicates a second number of remaining programming voltages to be applied to the second subset of memory cells to be programmed to the second designated logic level in the second set of logic levels; Responsive to determining that the count exceeds a second threshold, continuing the programming operation of the second subset of the plurality of memory cells. 15 . The method of claim 14 , wherein the number of logic levels in the set of logic levels is equal to the number of logic levels in the second set of logic levels.

16. The method of claim 9, wherein the memory cell is a quad-level cell (QLC).

17. A non-transitory computer-readable medium comprising executable instructions that, when executed by a processing device, cause the processing device to: During a programming operation, causing a programming voltage to be applied to a subset of a plurality of memory cells to be programmed to a specified logic level, wherein the specified logic level is associated with a set of logic levels; causing a first program verify voltage associated with the set of logic levels to be applied to the subset of memory cells; and responsive to applying the first program verify voltage, decrementing a count associated with the designated logic level, wherein the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to the designated logic level in a predefined set of logic levels; and In response to determining that the count has fallen below a threshold, the programming operation of the subset of the plurality of memory cells is terminated.

18. The non-transitory computer-readable medium of claim 17, further comprising executable instructions that, when executed by a processing device, cause the processing device to: causing a second programming voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logic level, wherein the second logic level is associated with the set of logic levels; causing the first program verify voltage associated with the set of logic levels to be applied to the second subset of the plurality of memory cells; responsive to applying the first program verify voltage, decrementing a second count associated with the second designated logic level, wherein the second count indicates a number of remaining programming voltages to be applied for programming the second subset of memory cells to the second designated logic level in the predefined set of logic levels; and In response to determining that the count falls below a second threshold, the programming operation of the second subset of the plurality of memory cells is terminated.

19. The non-transitory computer-readable medium of claim 17, wherein the count associated with the specified logic level is stored in a page buffer coupled to a bit line connected to the subset of memory cells.

20. The non-transitory computer readable medium of claim 17, wherein each respective logic level is associated with a different program verify level, and the first program verify voltage associated with the set of logic levels has a minimum magnitude of the different program verify levels.

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