Voltage scaling based on error rate fluctuations

Abstract

The invention relates to voltage scaling based on error rate fluctuations. A method includes determining a target total bit error rate (BER); calculating a target channel BER based on the target total BER; and training a channel according to the compute target channel BER by: transmitting a slave data physical input / output PHY I / O to a memory device through the channel in a loop; transmitting test data from the memory device to the PHY I / O over the channel in the loop, where the data is cycled from the memory device and returned to the PHY I / O without writing to or reading from the memory device; determining an actual channel BER based on the data transmitted to and received from the memory device; comparing the actual channel BER with the calculated target channel BER; and adjusting a voltage value based on the comparison.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to voltage scaling based on error rate fluctuations. Background Art

[0002] The memory system may include a memory subsystem, which may include one or more memory devices that store data, digital logic, and associated voltage control. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices and the voltage control may change the voltage during operation of the digital logic. Summary of the invention

[0003] In one aspect, the present disclosure provides a method for scaling voltage based on fluctuations in a bit error rate (BER), comprising: determining a target overall BER; calculating a target channel BER based on the target overall BER; and training a channel according to the calculated target channel BER by: transmitting data from a physical input / output (PHY I / O) to a memory device through the channel in a loop; transmitting the data from the memory device to the PHY I / O through the channel in the loop, wherein the data circulates from the PHY I / O to the memory device and back to the PHY I / O; determining an actual channel BER based on the data transmitted to the memory device and the data received from the memory device; comparing the actual channel BER to the calculated target channel BER; and adjusting a voltage value associated with the channel based on the comparison between the actual channel BER and the calculated target channel BER.

[0004] On the other hand, the present disclosure provides an apparatus for voltage scaling, comprising: a physical input / output (PHY I / O), wherein the PHY I / O is configured to: send data to a memory device through a channel; and receive the data from the memory device through the channel; and a processor coupled to the PHY I / O, wherein the processor is configured to: determine an actual channel bit error rate (BER) based on the data sent to the memory device and the data received from the memory device; and control adjustment of a voltage value in response to the determination of the actual channel BER.

[0005] On the other hand, the present disclosure provides a system for scaling voltage, comprising: a memory device; a physical input / output (PHY I / O), wherein the PHY I / O is configured to: transmit test data to the memory device via a channel; and receive the test data from the memory device via the channel; and a processor coupled to the PHY I / O, wherein the processor is configured to: determine an actual bit error rate (BER) associated with the channel based on the transmitted test data and the received test data; determine a temperature and a voltage value associated with the channel; and control adjustment of the voltage value associated with the channel based on the actual channel BER, the channel temperature, and the channel voltage value. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example apparatus for voltage scaling based on error rate fluctuations according to some embodiments of the present disclosure is described.

[0009] Figure 3 A diagram illustrating an example method for voltage scaling based on error rate fluctuations according to some embodiments of the present disclosure.

[0010] Figure 4 An example system including a memory device and a PHY I / O according to some embodiments of the present disclosure is described.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to voltage scaling based on error rate fluctuations, and in particular, to a memory subsystem including circuitry (e.g., voltage scaling circuitry) for performing voltage scaling based on error rate fluctuations. Voltage scaling can be used to match system power consumption to desired performance. Error rates associated with a system (e.g., a computing system) can be monitored to determine settings for voltage values. Dynamic voltage scaling is a technique that aims to reduce system power consumption by dynamically adjusting the voltage of the system. This can take advantage of the fact that systems typically have nominal voltage settings. Dynamic voltage scaling that increases voltage can be referred to as overvoltage, while dynamic voltage scaling that decreases voltage can be referred to as undervoltage. Undervoltage can be performed to save power (particularly in computing systems such as laptops and other mobile devices, where energy comes from batteries and is therefore limited) or, in some cases, to improve the reliability of the computing system.

[0013] The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Figure 1 and others to describe examples of storage devices and memory modules. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0014] During operation of a computing system, data incurs errors when being transmitted to and / or from a device and / or due to the inherent characteristics of the device. For example, a fiber optic receiver or radio delivering data to a controller may have a certain percentage of the transmitted data corrupted. In one embodiment, a memory device including a memory subsystem may experience a certain percentage of data corruption in the data transmitted to and from the memory device. In addition, due to the inherent behavior of the memory device (e.g., voltage drift, read / write interference, and / or memory cell degradation, etc.), the memory device (i.e., such as a NAND memory device) may introduce errors (e.g., flipped bits) to the data stored thereby. As a result, the execution of a read operation may return a bit from the memory cell (e.g., a NAND memory cell) that is different from the bit written to the memory cell. For example, a logical "0" written to a memory cell may be read as a logical "1", or vice versa. The error rate exhibited by the memory device (e.g., a bit error rate of the memory device and / or a signal-to-noise ratio of the memory device) may fluctuate over time due to factors such as temperature, memory device aging, memory device utilization, or workload.

[0015] For example, because current is used to provide power to the memory subsystem, the memory subsystem may exhibit temperature fluctuations during operation. Such fluctuations may become more significant based on the type of workload to which the memory subsystem is subjected. For example, some types of workloads that may be characterized by a high amount of operations may cause greater temperature fluctuations within the memory subsystem than workloads characterized by a low amount of operations, resulting in higher memory device error rates. Furthermore, the memory subsystem may experience temperature fluctuations based on the environment in which the memory subsystem is deployed. Additionally, over time and in use, the quality of the memory subsystem may degrade, resulting in higher error rates and greater susceptibility to temperature and workload changes.

[0016] In addition, when the memory subsystem interacts with the host system via a channel (or other interface, communication bus, etc.), errors (e.g., bit error rate of the channel, signal-to-noise ratio of the channel) are encountered on the channel. Channel errors may depend on (but are not limited to) temperature, aging, voltage stability, and / or frequency changes (e.g., speed) of the memory subsystem and / or the environment. As a general rule, the faster the channel, the higher the bit error rate (BER), and therefore, the slower the channel, the lower the BER. In addition, tolerances within the system can affect the channel error rate. For example, as non-limiting examples, on-chip and off-chip terminations, set I / O slopes and drive strengths, internal PLL / DLL jitter requirements, tolerances within internal analog and digital power supplies can affect the channel error rate. Therefore, the system experiences a total BER, which is equal to the sum of the BER of the memory device (e.g., errors introduced during operation of the memory device) and the BER encountered via the channel (e.g., errors introduced due to data crossing the channel). When the memory device BER is very small, the above tolerances can be relaxed or the voltage of the system can be reduced, thereby intentionally allowing more errors to be encountered across the channel, resulting in lower precision required in components used in the system, reduced resources (such as reduced power consumption) and / or reduced cost.

[0017] However, memory device BER may sometimes be significant and thus channel BER mitigation is desirable. Channel BER may be mitigated in a number of non-limiting ways (e.g., tightening tolerances in the system, manipulating I / O slew rates, termination, internal biasing, reducing speed or adjusting drive strength, pull-up / pull-down, attenuation / gain, clocking frequency and / or rate, etc.). In some embodiments, channel BER may be mitigated by operating the channel at or above a specific voltage value, which may be referred to as the "nominal voltage value" of the channel (or interface, bus, etc.). For example, channel BER may vary depending on the voltage value supplied to the system. For example, the greater the voltage supplied to the system (e.g., to the channel), the lower the channel BER. Given sufficiently high voltages and therefore low channel BER, some approaches may result in a total BER (the sum of the BERs of the memory device and the channel) that is better than a target BER at which the system can operate adequately (e.g., store data or otherwise operate as designed). However, due to operating better than the target total BER (e.g., at a relatively high voltage), such approaches may result in reduced overall efficiency of the system, increased power consumption, and / or increased thermal load experienced by the memory subsystem or its components.

[0018] Aspects of the present disclosure address the above and other deficiencies by determining whether a system is operating above, below, or within a threshold amount of a target overall BER and / or above, below, or within a threshold amount of a target channel BER. For example, embodiments herein may allow for dynamic control of channel BER to reduce power consumption within a memory subsystem without negatively impacting the performance of memory devices (e.g., NAND memory devices) utilized by the memory subsystem.

[0019] For example, some embodiments herein transmit data to a PHY I / O (e.g., a physical input / output (PHY I / O)) of a memory device, write data to the memory device, generate a bit string including data read from the memory device, transmit the bit string to the PHY I / O of the device via a channel (e.g., such as an Open NAND Flash Interface (ONFI) channel), and determine an actual overall BER.

[0020] In addition, some embodiments herein include: training logic for transmitting test data to a memory device via a channel in a loop and receiving test data from the memory device without reading the test data or writing the test data to the memory; determining an actual channel BER from the loop data; in response to the actual total BER being associated with the actual channel BER in the data structure within a threshold period, adjusting a voltage value associated with the channel; or in response to the actual total BER not being associated with the actual channel BER in the data structure or not being associated in the data structure within a threshold period, calculating a difference between the actual total BER and the actual channel BER to determine the actual memory device BER, calculating a target channel BER based on the difference between the target total BER and the actual memory device BER, comparing the actual channel BER to the calculated target channel BER, and adjusting a voltage value associated with the channel based on the comparison. Thus, the voltage value may be adjusted to a level that improves the efficiency of the system and still continues to produce an acceptable actual total BER. That is, embodiments herein may adjust the voltage value to mitigate (e.g., reduce) the difference between the actual total BER and the target total BER and / or the difference between the actual channel BER and the calculated target channel BER, thereby improving the efficiency of the system. However, the examples are not limited in this regard and tolerances in the system, manipulation of I / O slew rates, termination, internal biasing, speed, drive strength, pull-up / pull-down, attenuation / gain, clocking frequency and / or rate may be manipulated and / or adjusted to mitigate (or further mitigate in conjunction with voltage adjustments) the difference between the actual overall BER and the target overall BER and / or the difference between the actual channel BER and the calculated target channel BER.

[0021] In some embodiments, the temperature associated with the channel may be monitored by a temperature sensor coupled to the channel (e.g., circuitry associated with the ONFI interface). When the actual total BER described above is less than or greater than the target total BER and / or the actual channel BER is less than or greater than the calculated target channel BER, the amount of power provided to the various components of the memory subsystem may be adjusted. Adjusting the power may change the actual channel BER and, in turn, the actual total BER. In some embodiments, the efficiency of the system may be improved while still operating within the target total BER. In addition, the channel temperature and the adjusted voltage value may be associated with the actual total BER and / or the actual channel BER and may be stored in a data structure for future reference. For example, the data structure may be a database and / or a lookup table, but examples are not limited thereto. In addition, the current date and time may be associated with the channel temperature, the adjusted voltage value, and the actual total BER and / or the actual channel BER and stored in the data structure.

[0022] Figure 1An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a memory device, a memory module, or a mixture of a memory device and a memory module. Examples of memory devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120, for example, uses the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130) when the memory subsystem 110 is coupled to the host system 120 through a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices, such as memory device 130, include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130, 140 may include one or more arrays of memory cells. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0031] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as, for example, read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), name spaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140 and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode addresses to access the memory device 130 and / or the memory device 140.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] The memory subsystem 110 may also include voltage scaling circuitry 113. Figure 1 1 to avoid obscuring the diagram, but the voltage scaling circuitry 113 may include various circuitry to facilitate adjusting the voltage in response to a comparison between a target overall BER and an actual overall BER and / or a comparison between a calculated target channel BER and an actual channel BER. For example, execution of a read operation of the memory device 130 may return a bit from a memory cell (e.g., a NAND memory cell) that is different from the bit written to the memory cell. For example, a logical "0" written to a memory cell of the memory device 130 may be read as a logical "1", or vice versa. Additionally, during the transfer of data between the memory device PHY I / O 121 and the memory subsystem controller PHY I / O 123 or a host device, the channel through which the bit string is transferred may result in errors. Thus, in addition to the actual BER of the channel, the actual overall BER may also include the actual BER of the memory device 130. The actual total BER may be determined based on data sent and written to and read and received from memory device 130 and the actual channel BER may be determined based on test data sent to and received from memory device 130 in the loop and not written to or read from memory device 130. In addition, the actual memory device BER may be calculated based on the difference between the actual total BER and the actual channel BER, as discussed further below. In addition, it should be appreciated that memory subsystem controller PHY I / O 123 and memory device PHY I / O 121 may generally be input / output (I / O) devices of the physical (PHY) layer of the OSI being calculated. In some embodiments, PHY I / O 121 and 123 may be ONFI interfaces, but embodiments are not limited thereto.

[0039] Additionally, the memory subsystem 110 may include training logic 122. Figure 11 so as not to obscure the figure, but the training logic 122 may include various circuit systems to facilitate training the channel voltage based on a comparison between a target overall BER and an actual overall BER and / or a comparison between a target channel BER and an actual channel BER and temperature, voltage, and other parameters associated with the channel, as further described herein.

[0040] In some embodiments, voltage scaling circuitry 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that may allow voltage scaling circuitry 113 to program and / or execute operations to selectively perform regulation of voltage.

[0041] In some embodiments, the memory subsystem controller 115 includes at least a portion of the voltage scaling circuitry 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the voltage scaling circuitry 113 is part of a host system 120, an application, or an operating system.

[0042] In a non-limiting example, a device (e.g., computing system 100) may include memory subsystem voltage scaling circuitry 113. Memory subsystem voltage scaling circuitry 113 may reside on memory subsystem 110. As used herein, the term "resides on" refers to something being physically located on a particular component. For example, memory subsystem voltage scaling circuitry 113 "resides on" memory subsystem 110 refers to a condition in which the hardware circuitry, including memory subsystem voltage scaling circuitry 113, is physically located on memory subsystem 110. The term "resides on" may be used interchangeably with other terms herein, such as "deployed on" or "located on."

[0043] The memory subsystem voltage scaling circuitry 113 may be configured to adjust the voltage and / or control the adjustment of the voltage. The voltage may be adjusted based on the actual overall BER. For example, data may be sent from the PHY I / O 123 of the memory subsystem controller 115 to the PHY I / O 121 of the memory device 130 through a channel. A bit string including data read from the memory device 130 may be generated by the memory device 130. The bit string including data read from the memory device 130 may be received by the memory subsystem controller PHY I / O 123 through a channel. The memory subsystem controller 115 may control the transmission of the bit string generated by the memory device 130 to the PHY I / O 123 of the memory subsystem 110.

[0044] As will be further described herein, the decoder (e.g., Figure 2225) to determine the actual total BER from the received bit string. In some embodiments, the memory subsystem voltage scaling circuitry 113 may adjust the voltage in response to a comparison between the actual total BER and a determined target total BER. For example, in a situation where the actual total BER is greater than the target total BER, increasing the voltage may reduce the actual channel BER and thereby reduce the actual total BER (e.g., because the actual total BER is equal to the sum of the channel BER and the memory device BER). Conversely, in a situation where the actual total BER is less than the target total BER, reducing the voltage may increase the actual channel BER, thereby increasing the actual total BER. Furthermore, in a situation where the actual total BER is at or equal to the target total BER (or within a threshold of the target total BER), maintaining the voltage may maintain the actual channel BER and the actual total BER.

[0045] In some embodiments, the memory subsystem voltage scaling circuitry 113 may be configured to adjust the voltage and / or control the adjustment of the voltage based on the actual channel BER. For example, the memory device 130 may include loopback logic 133. In some embodiments, the loopback logic 133 may be coupled to the memory device PHY I / O 121. Test data may be sent to the memory device 130 and received back from the memory device 130 in a loop. That is, the test data may be sent to the memory device 130 and received from the memory device 130 without reading or writing the test data to the memory device 130. As the looped test data traverses the channel, the actual channel BER may be determined based on a number of errors encountered by the looped test data. For example, using the training logic 222, the test data sent to the memory device 130 may be compared with the test data received back from the memory device 130 in the loop. However, the example is not limited thereto and in some embodiments, the test data may be determined based on a number of errors encountered while traversing the channel (e.g., which are detected by a decoder of the processor 117 coupled to the memory subsystem 110 (e.g., the processor 117 of the memory subsystem 110)). Figure 2 The decoder 225 described in (225) is corrected) to determine the actual channel BER.

[0046] In some embodiments, a processor 117 coupled to a PHY I / O 123 of a memory subsystem controller 115 may be configured to calculate an actual BER for at least one of the memory components of the memory subsystem 110. The actual memory device BER may be based on a difference between the actual total BER and the actual channel BER. In some embodiments, the memory subsystem controller PHY I / O 123 (e.g., a processor 117 coupled to the PHY I / O 123) may be further configured to calculate a target channel BER based on a difference between the target total BER and the actual memory device BER. The actual channel BER may be compared to the calculated target channel BER to determine whether the actual channel BER is below, above, or at the calculated target channel BER. Thus, a voltage may be adjusted (i.e., altered to increase or decrease a voltage value) in response to a comparison between the actual channel BER and the calculated target channel BER, as further described herein. Furthermore, the actual channel BER may be associated with the actual total BER and / or the actual memory device BER and the calculated target channel BER and stored in a data structure. Additionally, the current date or the current date and time when the actual overall BER and the actual channel BER were determined may be further associated with the calculated target channel BER and stored in the data structure.

[0047] For example, in some embodiments, the memory subsystem controller PHY I / O 123 (e.g., the processor 117 coupled to the PHY I / O 123) may be configured to cause the voltage value to be scaled down based on a determination that the actual channel BER is below a threshold of a target channel BER. In some embodiments, the memory subsystem controller PHY I / O 123 (e.g., the processor 117 coupled to the PHY I / O 123) may be configured to cause the voltage value to be scaled up based on a determination that the actual channel BER is above a threshold of a target channel BER. In some embodiments, the memory subsystem controller PHY I / O 123 (e.g., the processor 117 coupled to the PHY I / O 123) may be configured to cause the voltage value to be maintained (i.e., remain unchanged) based on a determination that the actual channel BER is within a threshold of a target channel BER.

[0048] By determining a comparison between the actual total BER and the target total BER and / or the actual channel BER and the calculated target channel BER and scaling the supply voltage based on the comparison, the actual channel BER may be adjusted to result in an overall adjustment of the actual total BER (e.g., to maintain the actual total BER within a threshold amount of the target total BER). Adjusting the actual channel BER as described herein may allow the system to operate at an acceptable error rate (e.g., the target total BER) with a minimum supply voltage, thereby improving the efficiency of the system and thereby providing an improvement in the overall functionality of the computing system in which aspects of the present disclosure are employed. Although examples of adjusting the actual channel BER by scaling or adjusting the supply voltage are described herein, examples of adjusting the actual channel BER are not limited thereto, but may include or further include altering other factors, such as tightening tolerances of the system, manipulation of I / O slew rates, termination, internal biasing, reducing speed or adjusting drive strength, pull-up / pull-down, attenuation / gain, clocking frequency and / or rate, etc.

[0049] Figure 2 An example device 200 for voltage scaling based on error rate fluctuations is illustrated in accordance with some embodiments of the present disclosure. The device may include a physical input / output (PHY I / O) 223. The PHY I / O 223 may include training logic 222 and may be coupled to a processor 217, a decoder 225 (e.g., a low density parity check (LDPC) decoder), a temperature sensor 229, and / or a voltage regulator 227. The processor 217 may include a data structure 226 for storing data and retrieving stored data.

[0050] In some embodiments, the actual overall BER of the memory subsystem 210 may be determined. For example, the PHY I / O 223 may send data information to the PHY I / O 221 of the memory device 130 of the memory subsystem 210 of the apparatus 200. The sent data may be written to the memory device 130. The memory device 130 may then send the data information read from the memory device 130 from the PHY I / O 221 of the memory device 130 to the PHY I / O 223. The data information may be included in a bit string and in some embodiments, the processor 217 coupled to the PHY I / O 223 may receive the bit string including the data information. For example, the PHY I / O 223 may be coupled to the PHY I / O 221 of the memory device 130 via the channel 224. Thus, the PHY I / O 223 may receive the bit string from the memory device 130 via the channel 224. In a less limiting example, the bit string may be received via a channel associated with an Open NAND Flash Interface (ONFI) interface, bus, or similar set of channels configured to facilitate data transfer, such as between PHY I / O 223 and memory device 130 .

[0051] The bit string may include a codeword. A codeword may include host data (e.g., user data, etc.) and / or elements of an error correction code. In general, a "codeword" refers to a bit string containing a predetermined number of bits, which may include data (e.g., a payload), error correction bits (e.g., a parity check), a header (e.g., one or more bits describing the purpose of the bit string), and / or an address locator (e.g., an address to which the bit string is to be written or from which it is to be retrieved).

[0052] Utilizing decoder 225, processor 217 may be configured to determine the actual total BER based on data sent from PHY I / O 223 and written to memory device 130 and data read and received from memory device 130 by PHY I / O 223. Due to errors in memory device 130 and errors encountered when transmitting and receiving data through channel 224, the received data information may be different from the transmitted data information. For example, decoder 225 may be coupled to PHY I / O 223 and / or memory device 130. Decoder 225 may be a low density parity check (LDPC) decoder 225 configured to decode codewords, which may include firmware and / or hardware. Decoding the codewords may be part of a read operation. Decoded data generated from decoding the codewords may be used to determine the total number of actual errors received from memory device 130 and encountered through channel 224. For example, execution of a read operation may return bits from a memory cell (e.g., a NAND memory cell) that are different from the bits written to the memory cell. For example, a logic "0" written to a memory cell may be read as a logic "1", or vice versa. Additionally, during the transmission of data between PHY I / O 221 and PHY I / O 223 of memory device 130, channel 224 through which the bit string is transmitted may cause errors. Therefore, in addition to the actual BER of channel 224, the actual total BER may also include the actual BER of memory device 130.

[0053] In some embodiments, the training logic 222 may be used to determine the actual channel BER. For example, the training logic 222 may be coupled to the PHY I / O 223 and the memory device 130 may include loopback logic 233 coupled to the memory device PHY I / O 221. Test data information (e.g., test data for training a channel) may be sent from the PHY I / O 223 to the PHY I / O 221 of the memory device 130 using the training logic 222 and received from the PHY I / O 221 of the memory device 130 back to the PHY I / O 223 using the loopback logic 233 without being written to or read from the memory device 130 (e.g., the test data may be sent in a loop). In some embodiments, the processor 217 coupled to the PHY I / O 223 may send and receive data information via the channel 224 (e.g., received via the channel 224 associated with an Open NAND Flash Interface (ONFI) interface, bus, or similar set of channels configured to facilitate data transfer). The training logic 222 may be used to compare the transmitted test data to the received test data to determine the actual channel BER based on a certain number of errors encountered by the test data as it traverses the channel 224 .

[0054] Thus, decoder 225 coupled to PHY I / O 223 and processor 217 may be used to determine an actual overall BER based on data sent and written to, and read and received from, memory device 130. Furthermore, utilizing training logic 222 coupled to PHY I / O 223 and processor 217 and loopback logic 233 of PHY I / O 221 coupled to memory device 130, an actual channel BER may be determined based on test data that is looped to memory device 130 and not written to or read from memory device 130. PHY I / O 223, such as processor 217 coupled to PHY I / O 223, may be further used to calculate an actual memory device BER based on a difference between the actual overall BER and the actual channel BER.

[0055] In some embodiments, PHY I / O 223 (e.g., processor 217 coupled to PHY I / O 223) may thus control adjustment of the voltage value based on the actual overall BER and / or the actual channel BER. For example, the voltage value may be adjusted based on a comparison between a target overall BER and the actual overall BER. The voltage value may be associated with channel 224, so adjusting the voltage value may change (e.g., increase or decrease) the actual BER of channel 224, thereby altering the actual overall BER, since the actual overall BER is composed of the sum of the actual channel BER and the actual memory device BER.

[0056] In addition, the voltage value may be adjusted based on a comparison between a calculated target channel BER (e.g., the difference between a target overall BER and an actual memory device BER) and the actual channel BER. In some embodiments, the actual overall BER and the actual channel BER may be associated with the target channel BER and stored in a data structure and thus the voltage value may be adjusted based on a comparison between the actual channel BER stored in the data structure and the target channel BER (associated with the actual overall BER and the actual channel BER). In addition, the date or date and time at which the actual overall BER and the actual channel BER were determined may be associated with the target channel BER and stored in the data structure. The voltage value may be adjusted based on the date or date and time at which the actual overall BER and the actual channel BER are stored in the data structure not exceeding a threshold period of time (e.g., 1 week, 1 month, 3 months, 6 months, etc.).

[0057] As previously described, a voltage value may be associated with a channel 224, so adjusting the voltage value may change (e.g., increase or decrease) the actual BER of the channel 224. As will be described in further detail herein, adjusting the voltage value by cycling test data between the PHY I / O 223 and the PHY I / O 221 of the memory device 130 and then comparing the calculated target channel BER to the actual channel BER may be referred to as training the channel according to the calculated target channel BER. The training logic 222 coupled to the PHY I / O 223 and utilizing the processor 217 may include various circuitry to facilitate training the channel voltage according to the calculated target channel BER.

[0058] For example, processor 217 may be configured to calculate a target channel BER based on a difference between a target total BER and an actual memory device BER. Thus, due to fluctuations in the error rate of memory device 130, calculating the target channel BER may be dynamic (e.g., may occur during normal operation of the memory device). For example, when the actual BER of memory device 130 is almost error-free (i.e., a low error rate), the difference between the target total BER and the actual memory device BER may be close to the value of the target total BER. Thus, the voltage value may be reduced, thereby allowing a higher error rate across channel 224. However, as memory device 130 degrades over time, the actual error rate of memory device 130 may increase. Thus, as the actual BER of memory device 130 increases closer to the target total BER (i.e., toward a high error rate), the difference between the target total BER and the actual memory device BER may decrease, thereby reducing the calculated target channel BER. Thus, the voltage value may be increased to minimize the actual BER encountered by channel 224. In this way, the actual total BER may be maintained at or close to the target total BER and the actual channel BER may be maintained at or close to the dynamically calculated target channel BER.

[0059] In other words, the BER of the memory device 130 may fluctuate throughout the life of the memory device 130 due to various circumstances such as fluctuations in temperature, the type of workload, and degradation of the memory subsystem, but examples are not limited thereto. Thus, the actual total BER (e.g., a combination of the actual BER of the channel 224 and the actual BER of the memory device 130) will fluctuate due to the changing number of errors exhibited by the memory device 130 throughout the life and operation of the memory device 130. Thus, the difference between the target total BER and the actual memory device BER will change depending on various aspects of the operation within the memory subsystem 210. In order to adapt to these changes in order to maintain optimal efficiency and produce an acceptable actual total BER, the processor 217 may be configured to determine changes in the calculated target channel BER (e.g., an acceptable BER for the channel 224) by retraining the channel, as further described herein. Thus, changes in the calculated target channel BER may be derived from changes in the actual total BER caused by fluctuations in the memory device BER. In this way, the calculated target channel BER may be a roaming or dynamic value.

[0060] In some embodiments, the PHY I / O 223 may be further coupled to a voltage regulator 227. The processor 217 may be configured to control the adjustment of the voltage value by using the voltage regulator 277 in response to a comparison between the actual total BER and the target total BER and / or between the actual channel BER and the calculated target channel BER by changing the voltage value from a first voltage value to a second voltage value. As described above, when the memory device BER fluctuates over time and operation, the calculated target channel BER may change. Therefore, the processor 217 may be configured to further control the voltage value in response to the comparison between the actual channel BER and the dynamic target channel BER. In other words, the voltage value may depend on the actual total BER and may be adjusted as the actual total BER fluctuates in order to achieve the optimal BER target of the channel 224. Adjusting the voltage value may mitigate or reduce the difference between the actual total BER and the target total BER and / or between the actual channel BER and the calculated target channel BER. In addition, the voltage value may depend on the actual channel BER and may be adjusted as the actual total BER fluctuates in order to achieve the optimal BER target of the channel 224. Adjusting the voltage value may mitigate or reduce the difference between the actual channel BER and the calculated target channel BER and, as will be described in greater detail below, may be further adjusted based on training and / or retraining the channel 224 according to the calculated target channel BER.

[0061] For example, in an embodiment where channel 224 is provided as part of an ONFI bus (e.g., an interface), the ONFI bus may operate at a nominal voltage value associated with the ONFI bus. This nominal voltage value may produce a minimum channel BER, however, as discussed herein, the nominal voltage value may be greater than required to operate the memory subsystem 210 while maintaining an actual total BER within an acceptable error threshold or error threshold range. In a situation where the actual channel BER is lower than the calculated target channel BER (and therefore, the actual total BER is lower than the target total BER), the system operates at a higher or "better than" required state rather than a state required to maintain an acceptable total BER (e.g., target total BER). Reducing the voltage value may result in an increase in the actual channel BER. However, in this example, the increase in the actual channel BER is acceptable because the actual channel BER is lower than the calculated target channel BER and therefore the actual total BER is lower than the target total BER. The voltage value may be reduced, thereby reducing power consumption and adverse thermal effects on the memory subsystem 210 while improving the efficiency of the memory subsystem 210.

[0062] For example, the first voltage value may be a nominal voltage value associated with the ONFI bus and the second voltage value may be less than the first voltage value. In the case where the actual channel BER is lower than the lower limit value of the threshold range for calculating the target channel BER, the processor 217 may be configured to cause the voltage regulator 227 to adjust the voltage value from the first voltage value (nominal ONFI bus voltage value) to the second voltage value (less than the nominal voltage value). In the case where the actual channel BER is still lower than the lower limit value of the threshold range for calculating the target channel BER after the voltage value is adjusted from the first voltage value to the second voltage value, the processor 217 may be configured to cause the voltage regulator 227 to adjust the voltage value by changing the voltage value from the second voltage value to a third voltage value, the third voltage value being less than the first voltage value and less than the second voltage value. Thus, the voltage value may be adjusted to reduce the difference between the actual total BER and the target total BER and / or between the actual channel BER and the calculated target channel BER.

[0063] Although three voltage values ​​are described, the scope of the present disclosure further contemplates the use of more than three voltage values ​​to provide additional fine tuning of the voltage value selected during operation of the memory subsystem 210. Furthermore, it is contemplated within the scope of the present disclosure that the voltage value may be dynamically altered based on the actual channel BER. In the event that the actual channel BER is above the upper value of the threshold range for calculating the target channel BER, the processor 217 may be configured to cause the voltage regulator 227 to adjust the voltage value. For example, increasing the voltage value from the third voltage value to the second voltage value, increasing the voltage value from the second voltage value to the nominal voltage value, and so on, may reduce the difference between the actual overall BER and the target overall BER and / or between the actual channel BER and the calculated target channel BER.

[0064] In the case where the actual channel BER is equal to or within a threshold range of the calculated target channel BER (and therefore, the actual overall BER is equal to or within a threshold range of the target overall BER), the processor 217 may be configured to cause the voltage regulator 227 to maintain the voltage value.

[0065] The PHY I / O 223 may be further coupled to a temperature sensor 229. The processor 217 may be configured to monitor the temperature detected by the temperature sensor 229 and associated with the memory subsystem 210. As previously described above, the memory subsystem 210 may exhibit temperature fluctuations during operation. Such fluctuations may become more significant based on the type of workload to which the memory subsystem 210 is subjected. For example, a high operating volume may cause greater temperature fluctuations, resulting in a higher memory device BER, compared to a workload with a low operating volume. In addition, the memory subsystem 210 may experience temperature fluctuations based on the environment in which the memory subsystem 210 is deployed. In addition, over time and in use, the quality of the memory subsystem 210 may degrade, resulting in higher error rates and greater susceptibility to temperature and workload changes. The temperature may be monitored by the temperature sensor 229 to detect such temperature fluctuations.

[0066] Thus, the actual total BER associated with channel 224 fluctuates with temperature fluctuations associated with memory subsystem 210. In situations where the temperature increases, different BERs may be encountered when transmitting data across channel 224. For example, a temperature increase of a specific amount (e.g., 5 degrees, 10 degrees, 15 degrees, etc.) may increase the actual BER of channel 224 sufficiently to cause the actual channel BER to exceed the upper limit of the threshold range for calculating the target channel BER. Therefore, processor 217 may be configured to cause voltage regulator 227 to increase the voltage value, thereby reducing the channel BER. In situations where the temperature decreases, different BERs may be encountered when transmitting data across channel 224. For example, a temperature decrease of a specific amount (e.g., 5 degrees, 10 degrees, 15 degrees, etc.) may reduce the actual BER of channel 224 sufficiently to cause the actual channel BER to drop below the lower limit of the threshold range for calculating the target channel BER. Therefore, processor 217 may be configured to cause voltage regulator 227 to reduce the voltage value, thereby increasing the actual channel BER. In addition, the actual total BER associated with memory device 130 fluctuates with temperature fluctuations associated with memory subsystem 210. In situations where the temperature increases or decreases by a certain amount (e.g., 5 degrees, 10 degrees, 15 degrees, etc.), the actual memory device BER may fluctuate enough to alter the actual overall BER and the calculation between the target overall BER and the actual memory device BER, causing the calculated target channel BER to change.

[0067] Thus, the processor 217 may be configured to train and / or retrain the channel 224 based on fluctuations in temperature to cause the voltage regulator 227 to increase or decrease the voltage value. For example, in response to the temperature increasing or decreasing by a particular amount (e.g., 5 degrees, 10 degrees, 15 degrees, etc.), the processor 217 may be configured to cause test data to be sent from the PHY I / O 223 to the PHY I / O 221 of the memory device 130 and looped back from the PHY I / O 221 of the memory device 130 to the PHY I / O 223. Using the training logic 222, the processor 217 may be further configured to determine the difference (e.g., errors encountered) between the data sent from the PHY I / O 223 to the PHY I / O 221 of the memory device 130 and the data received from the PHY I / O 221 of the memory device 130 to the PHY I / O 223. Since data travels between PHY I / O 223 and PHY I / O 221 of memory device 130 twice, once from PHY I / O 223 to PHY I / O 221 of memory device 130 and once from PHY I / O 221 of memory device 130 to PHY I / O 223, the actual BER determined by processor 217 may be divided in half to determine the actual channel BER (e.g., the error rate encountered by channel 224).

[0068] Training the channel 224 according to the calculated target channel BER may supply a voltage value that maintains the actual channel BER within a threshold range of the calculated target channel BER. Training the channel 224 according to the calculated target channel BER may minimize instances where the actual total BER of the memory subsystem 210 exceeds the target total BER. In some embodiments, the PHY I / O 223 (e.g., the processor 217 coupled to the PHY I / O 223) may be configured to determine a temperature and voltage value associated with the channel 224 and associate the temperature and voltage value with the actual channel BER. The PHY I / O 223 (e.g., the processor 217 coupled to the PHY I / O 223) may be further configured to store the temperature, the actual channel BER, and the voltage value. The processor 217 may store the temperature, the actual channel BER, and the voltage value in a data structure 226. The processor 217 may be further configured to store the date and time at which the training or retraining of the channel was performed and may associate the date and time with the temperature, the actual channel BER, and / or the voltage value as further described herein.

[0069] Thus, in situations where the temperature detected by the temperature sensor 229 and monitored by the processor 217 fluctuates by a particular amount (e.g., 5 degrees, 10 degrees, 15 degrees, etc.), the processor 217 may be configured to query the data structure 226. For example, a change in temperature may significantly alter the actual channel BER and / or the actual memory device BER sufficiently to cause the actual channel BER to exceed a threshold range for calculating a target channel BER and / or cause the actual total BER to exceed a threshold range for a target total BER. Thus, in response to a significant change in temperature (e.g., 5 degrees, 10 degrees, 15 degrees, etc.) determined based on utilization of the temperature sensor 229, the processor 217 may be configured to determine a temperature associated with the channel 224. The processor 217 may further be configured to compare the temperature associated with the channel 224 to the temperature stored in the data structure 226.

[0070] In response to the temperature associated with the channel 224 not matching the temperature stored in the data structure 226, the processor 217 may be configured to retrain the channel 224 according to the calculated target channel BER. For example, the PHY I / O 223 may send data to the PHY I / O 221 of the memory device 130 over the channel 224 and receive data back from the PHY I / O 221 of the memory device 130 without writing the data to the memory device 130 or reading the data from the memory device 130. The data may be test data sent in a loop between the PHY I / O 223 coupled to the training logic 222 and the PHY I / O 221 coupled to the loopback logic 233 of the memory device 130. The processor 217 associated with the PHY I / O 223 may determine the actual channel BER based on errors encountered by the test data as it traverses the channel and in response, the processor 217 may control the adjustment of the voltage value associated with the channel 224, as previously described. Processor 217 may be further configured to determine a voltage value associated with channel 224, associate the temperature and adjusted voltage value with the actual channel BER, and store the temperature, actual channel BER, and voltage value in data structure 226. Processor 217 may be further configured to associate and store the current date or the current date and time with the temperature, actual channel BER, and voltage value.

[0071] In response to the temperature associated with the channel 224 matching the temperature stored in the data structure 226, the processor 217 may be configured to determine the date or date and time at which the temperature was stored. For example, the processor 217 may be configured to associate the date or date and time at which the training or retraining was performed with the temperature, actual channel BER, and voltage values ​​and store in the data structure 226. In response to the date or date and time at which the training or retraining was completed / stored exceeding a threshold period (e.g., 1 week, 1 month, 3 months, 6 months, etc.), the processor 217 may be further configured to retrain the channel 224. Thus, the processor 217 may be configured to retrain the channel 224 due to changes in temperature and potential degradation of the memory subsystem 210 over time.

[0072] In response to the temperature associated with channel 224 matching the temperature stored in data structure 226 and the date or date and time at which the temperature was stored (e.g., training or retraining of channel 224 was performed) not exceeding a threshold period (e.g., 1 week, 1 month, 3 months, 6 months, etc.), processor 217 may be further configured to adjust the voltage value based on the voltage value associated with the temperature, actual channel BER, and date or date and time in data structure 226. In this way, retraining is not completed and the voltage value may be adjusted based on previously stored training data, resulting in a more time-efficient adjustment of the voltage value.

[0073] In an illustrative, non-limiting example, the memory subsystem 210 is capable of adjusting the PHY I / O voltage value. For example, the system may be booted. When the system boots up, the processor 217 of the PHY I / O 223 may be configured to train the channel 224 using the training logic 222 for a calculated target channel BER associated with the target overall BER. For example, the target overall BER may be approximately 2E-4 (2×10 -4 ). 2E-4(2×10 -4 ) is similar to about 8 errors in a codeword of about 40K bits and is therefore detectable. -4 ) with a target total BER of 1E-6 (1×10 -6) can save power and improve the efficiency of the memory subsystem 210 without negatively affecting the performance of the memory device 130 (e.g., a NAND memory device). This is because the memory device 130 may introduce an amount of errors below a threshold error rate (e.g., the memory device 130 generally provides data with a minimum number of errors associated therewith) and therefore the introduction of some additional errors by the channel 224 is acceptable, particularly due to the benefits of reduced power consumption, higher or "better" thermal performance, etc., which may be experienced by the memory subsystem 210 due to the reduction in the voltage value applied to the PHY I / O 223. Continuing with this example, utilizing the training logic 222, the processor 217 may be configured to record / store the training, including the voltage value, temperature, and date and time at which the training was performed. The temperature sensor 229 may detect the temperature and the processor 217 may monitor the detected temperature for changes in a particular amount (e.g., 5 degrees, 10 degrees, 15 degrees, etc.). Although 5 degrees, 10 degrees, 15 degrees, etc. are mentioned herein, the examples are not limited thereto and the processor 217 may be configured to monitor any temperature value change or range of changes.

[0074] When the monitored temperature changes by more than a certain amount (e.g., 5 degrees, 10 degrees, 15 degrees, etc.), the processor 217 may query the data structure 226 for the new temperature and the training parameters associated with the new temperature. If the training and voltage value data is not already stored in the data structure 226, the processor 217 may be configured to record / store the training and voltage values ​​and use the training and voltage values ​​to tune the voltage regulator 227. If the training and voltage data was previously stored in the data structure 226 but the data storage exceeds a threshold period (e.g., 1 week, 1 month, 3 months, 6 months, etc.), the processor 217 may be configured to overwrite the updated data to the data structure 226. If the training and voltage data was previously stored in the data structure 226 within a threshold period (e.g., 1 week, 1 month, 3 months, 6 months, etc.), the processor 217 may be configured to load the existing training parameters and voltage values ​​into the PHY I / O 223 and the voltage regulator 227, respectively. Therefore, the processor 217 and the voltage regulator 227 can maintain a temperature range of about 2E-4 (2×10 -4 ). Although 1 week, 1 month, 3 months, 6 months, etc. are mentioned herein, examples are not limited thereto and processor 217 may be configured to monitor any date or date range. In addition, although about 2E-4 (2×10 -4 ), but examples of target total BER are not limited to these.

[0075] Figure 3An example method 340 for voltage scaling based on error rate fluctuations according to some embodiments of the present disclosure is described. The method 340 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 340 is performed by Figure 2 The memory subsystem circuit system 210 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0076] At operation 341, a target overall BER may be determined. The target overall BER may be a BER where maximum power savings and efficiency may be experienced without exceeding an acceptable practical overall error rate for the memory subsystem. Figure 2 The processor 217 may be configured to determine a target overall BER. For example, the target overall BER of the memory subsystem may be 2E-4 or 2×10 -4 , but the examples are not limited thereto.

[0077] At operation 343, a target channel BER may be determined. The target channel BER may be calculated based on a target overall BER (e.g., 2E-4 or 2×10 -4 ) and the actual memory device BER to determine the calculated target channel BER. The actual memory device BER may be determined based on the difference between the actual total BER and the actual channel BER, as will be further described.

[0078] For example, in some embodiments, the communication may be performed via a channel (eg Figure 2 Channel 224) transfers data from Figure 2 The PHYI / O 223 is transmitted to Figure 2 The memory device 130 (e.g., to Figure 2 The actual overall BER can be determined by using the PHY I / O 221 of the memory device 130 of the memory device 130 and writing the data to the memory device. A bit string including the data read from the memory device can be generated and the bit string can be transmitted from the memory device back to the PHY I / O through the channel. In some embodiments, the data read from the memory device can include one codeword. In addition, the data read from the memory device can include multiple codewords (e.g., 5, 10, etc.). Figure 2The decoder 225 of the memory device decodes the codeword to determine the actual total BER based on the errors in the data read and received from the memory device and corrected by the decoder. The actual total BER may include any errors in the data caused by the memory device and encountered by the channel.

[0079] In some embodiments, the training logic circuitry (e.g., Figure 2 The training logic 222 of the memory device 200 transmits test data from the PHY I / O to the memory device (e.g., to the PHY I / O of the memory device) through the channel and back from the memory device to the PHY I / O to determine the actual channel BER. For example, the memory device may include loopback logic (e.g., Figure 2 The loopback logic 233 may include circuitry that causes test data received by the memory device to be looped back to the PHY I / O without being written to or read from the memory device. Thus, the test data traverses the channel once from the PHY I / O to the memory device and again from the memory device to the PHY I / O. As a result, the test data may encounter errors while traversing the channel. Training logic may be used to determine the actual channel BER based on the number of errors in the looped test data encountered by traversing the channel. In some embodiments, since the test data traverses the channel twice (once to the memory device and once from the memory device), the number of errors may be divided in half to determine the actual channel BER.

[0080] The actual channel BER and the actual total BER may be queried in the data structure to determine the target channel BER. For example, the actual channel BER and the actual total BER may have been previously stored in the data structure and associated with the target channel BER. In instances where the actual channel BER and the actual total BER are not associated with the target channel BER and stored in the data structure or the period during which the actual channel BER and the actual total BER are stored in the data structure exceeds a threshold period, the actual channel BER may be used together with the actual total BER to calculate the actual BER of the memory device. In other words, the actual memory device BER may be calculated from the difference between the actual total BER (determined from data sent and written to the memory device and read and received from the memory device) and the actual channel BER (determined from test data that circulates between the PHY I / O and the memory device and is not written to the memory device or read from the memory device). The actual BER of the memory device may be used together with the target total BER to calculate the target channel BER. Thus, the target channel BER may be calculated from the difference between the target total BER and the actual memory device BER. The calculated target channel BER may be associated with the actual total BER, the actual channel BER, and the current date or the current date and time and stored in the data structure for future use. Thus, in some embodiments, because the target channel BER may be stored in a data structure, future voltage adjustments may be performed without recalculating the actual memory device BER and the target channel BER, thereby minimizing the workload of the system 410, saving time, and improving efficiency.

[0081] At operation 345, the channel may be trained according to the calculated target channel BER. For example, data may be transmitted from the PHY I / O to the memory device through the channel using training logic and received back from the memory device by the PHY I / O using loopback logic. As previously described, the data may be test data sent in a loop between the PHY I / O and the memory device. For example, the test data may not be written to the memory device or read from the memory device. In this way, the test data may be used to calculate the actual channel BER. The actual channel BER may be compared to the calculated target channel BER. In some embodiments, based on the comparison between the actual channel BER and the calculated target channel BER, the actual channel BER may be compared to the calculated target channel BER by changing the voltage regulator (e.g., Figure 2 The voltage value associated with the channel is adjusted by using the voltage value associated with the voltage regulator 227).

[0082] Additionally, the temperature associated with the channel may be detected by a temperature sensor (eg, Figure 2 The temperature and voltage values ​​associated with the channel may be determined and the channel temperature and channel voltage values ​​may be associated with the actual channel BER. The actual channel BER and the channel temperature and channel voltage values ​​associated with the actual channel BER may be stored in a processor coupled to the PHY I / O. Figure 2 In data structure 226.

[0083] As previously described, fluctuations in temperature may result in fluctuations in the BER encountered by the memory subsystem. For example, the channel BER may increase or decrease based on changes in temperature. In some embodiments, a temperature associated with a channel may be monitored and in response to a change in a monitored temperature value exceeding a threshold, a data structure may be queried for information associated with the monitored temperature value. In response to the information associated with the monitored temperature value not being in the data structure, the channel may be retrained in accordance with the calculated target channel BER. Additionally, in response to the information associated with the monitored temperature value being in the data structure, a date or date and time at which the information was stored in the data structure may be determined. In response to the date or date and time at which the information was stored exceeding a threshold period, the channel may be retrained in accordance with the calculated target channel BER.

[0084] Figure 4 The present disclosure describes a method including a memory device (eg, Figure 2 Memory device 130) and PHY I / O (e.g. Figure 2 4. Example system 410 of PHY I / O 223 of FIG. Figure 2 The PHY I / O 221 of the memory device 130 can be connected via a channel (e.g. Figure 2 224) coupled to the PHY I / O and the processor (e.g. Figure 2 processor 221).

[0085] At operation 471 of system 410, the PHY I / O may be configured to transfer data to the memory device. The PHY I / O may transfer data to the memory device via a channel. The channel may be a communication bus such as an ONFI bus, but examples are not limited thereto. During training of the channel according to calculating the target channel BER, data may be sent to the memory device.

[0086] At operation 473 of system 410, the PHY I / O may be configured to receive data from the memory device via the channel. During training of the channel according to calculating the target channel BER, data may be sent from the memory device to the PHY I / O. The data transmitted from the PHY I / O to the memory device and received by the PHY I / O from the memory device may be test data sent in a loop between the PHY I / O and the memory device. For example, the PHY I / O may be coupled to training logic (e.g., Figure 2 training logic 222) and the memory device may include loopback logic (e.g. Figure 2Thus, data may be transferred across the channel a first time from the PHY I / O to the memory device and a second time from the memory device to the PHY I / O in the loop, and test data is not written to or read from the memory device.

[0087] At operation 475 of system 410, a processor coupled to the PHY I / O may be configured to determine an actual channel BER. The actual channel BER may be determined based on errors encountered by the test data as it is sent from the PHY I / O to the memory device via the channel and received by the PHY I / O from the memory device via the channel. Using training logic, the processor may determine a number of errors encountered by the test data as it traverses the channel. Thus, the test data passes across the channel twice. Thus, the number of errors may be divided in half to determine the actual channel BER.

[0088] At operation 477 of system 410, a processor coupled to the PHY I / O may be configured to determine a temperature associated with the channel. The temperature may be determined by Figure 2 The processor may be further configured to monitor the temperature detected by the temperature sensor. In some embodiments, the processor may be further configured to compare the determined temperature associated with the channel with a previously stored temperature, as further described herein. The processor may be further configured to determine a voltage value (i.e., voltage output) of the voltage regulator. The voltage value may be associated with the channel. Thus, the voltage value of the channel may be determined by Figure 2 The voltage regulator 227 of the embodiment of the present invention is set and adjusted as further described herein. Adjusting the voltage value can change the number of errors encountered by data when it is transmitted through the channel.

[0089] The processor may be further configured to store the temperature, the actual channel BER, the determined voltage value, and the current date or the current date and time. The temperature, the actual channel BER, the determined voltage value, and the current date or the current date and time may be stored in Figure 2 For example, the processor may be configured to associate the temperature with the actual channel BER and the determined voltage value and store the associated temperature, actual channel BER, voltage value, and current date or current date and time in the data structure in response to the temperature associated with the channel not being previously stored in the data structure.

[0090] In some embodiments, the processor may be configured to determine a date or a date and time that the temperature was stored in the data structure in response to the temperature associated with the channel being previously stored in the data structure. The processor may be further configured to retrain the channel in response to the date or a date and time that the temperature was stored in the data structure exceeding a threshold period. In response to retraining the channel, the processor may be configured to associate the temperature with the actual channel BER and the determined voltage value and store the associated temperature, actual channel BER, voltage value, and current date or current date and time in the data structure.

[0091] As previously described, changes in temperature may result in changes in the number of errors encountered by the channel and / or from the memory devices of the system 410. For example, a significant change in temperature (i.e., a threshold of 5 degrees, 10 degrees, 15 degrees, etc.) may result in an increase or decrease in the number of errors in the system 410. In some embodiments, the processor may be configured to monitor the temperature associated with the channel via a temperature sensor. In response to an increase or decrease in temperature exceeding a threshold, the processor may be further configured to control the adjustment of a voltage value associated with the channel. For example, in response to an increase or decrease in temperature exceeding a threshold, the processor may be configured to query a data structure to determine whether the increase or decrease in temperature is stored in the data structure and the date or date and time at which the increase or decrease in temperature was stored in the data structure. In response to determining that the increase or decrease in temperature is not stored in the data structure or the date or date and time at which the increase or decrease in temperature is stored exceeds a threshold period, the processor may be configured to retrain the channel, as previously detailed.

[0092] In some embodiments, in response to determining that the increased or decreased temperature is stored in the data structure and the date does not exceed the threshold period, the processor may be configured to control the adjustment of the voltage value according to the voltage value in the data structure associated with the increased or decreased temperature. For example, the processor may be configured to control the voltage regulator to cause the voltage value to increase in response to the actual channel BER associated with the increased or decreased temperature in the data structure being higher than the upper limit value of the threshold range from the calculated target channel BER. In addition, the processor may be configured to control the voltage regulator to cause the voltage value to decrease in response to the actual channel BER associated with the increased or decreased temperature in the data structure being less than the lower limit value of the threshold range from the calculated target channel BER. In addition, the processor may be configured to control the voltage regulator to cause the voltage value to remain unchanged in response to the actual channel BER associated with the increased or decreased temperature in the data structure being within the threshold range of the calculated target channel BER. Thus, in some embodiments, since the temperature was previously stored in the data structure within the threshold period, the voltage can be adjusted without retraining the channel, thereby minimizing the workload of the system 410, saving time and improving efficiency. At operation 479 of system 410, a processor coupled to the PHY I / O may be configured to control the adjustment of a voltage value associated with a channel. In some embodiments, the processor coupled to the PHY I / O may be configured to calculate a target channel BER. The processor may be further configured to compare the calculated target channel BER with the actual channel BER. Based on the comparison between the calculated target channel BER and the actual channel BER, the processor may be configured to control the adjustment of a voltage value associated with the channel. For example, the processor may be configured to control the adjustment of the voltage value to minimize the difference between the actual channel BER and the calculated target channel BER. As an example, the voltage value may be increased or decreased to change the actual BER encountered by channel 224. The processor may control the adjustment of the voltage value by controlling a voltage output from a voltage regulator, wherein the voltage output from the voltage regulator is a voltage value associated with the channel.

[0093] Furthermore, in some embodiments, the processor may be configured to calculate the actual BER of the memory device 130. The processor may be configured to calculate the actual memory device BER based on the difference between the actual overall BER and the actual channel BER. For example, the PHY I / O may be configured to transmit data to the memory device and receive a bit string including data read from the memory device. The PHY I / O may receive a bit string including data read from the memory device via a channel. The bit string may include data previously transmitted from the PHY I / O to the memory device and any errors introduced into the data by the memory device and encountered through the channel. Using a decoder (e.g., Figure 2The processor may be further configured to determine the actual total BER based on a number of errors induced by the memory device and encountered when transmitted through the channel that are corrected by the decoder. Thus, the processor may be configured to determine the actual total BER. Therefore, the actual memory device BER may be calculated based on the difference between the actual total BER and the actual channel BER.

[0094] The processor may be further configured to calculate a target channel BER based on a difference between the target overall BER and the actual memory device BER. The processor may be further configured to associate the calculated target channel BER and the current date or the current date and time with the target overall BER and the actual channel BER (and / or the actual memory device BER) and store the association in a data structure for future reference. As previously described, the processor may be configured to compare the actual channel BER to the calculated target channel BER and control the adjustment of a voltage value associated with the channel based on the comparison. Thus, the processor may adjust the voltage value by controlling a voltage output from a voltage regulator, wherein the voltage output from the voltage regulator is the voltage value associated with the channel.

[0095] Figure 5 is a block diagram of an example computer system 500 in which embodiments of the present disclosure may operate. For example, Figure 5 An example machine illustrating a computer system 500 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110) or can be used to perform operations of the controller (for example, to execute an operating system to execute a corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0096] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0097] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 518, which communicate with each other via a bus 530.

[0098] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device 502 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0099] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0100] In one embodiment, instructions 526 include instructions for implementing instructions corresponding to voltage scaling circuitry 113 and PHY I / O (eg, Figure 1The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0101] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally considered here to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0102] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0103] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0104] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure described herein may be implemented using various programming languages.

[0105] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0106] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be understood that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for scaling a voltage based on fluctuations in a bit error rate (BER), comprising: Determine target overall BER; calculating a target channel BER based on the target overall BER; and The channel is trained (224) according to the calculated target channel BER by: transmitting data from a physical input / output PHY I / O (123, 223) to a memory device (130) through the channel in a loop; transmitting the data from the memory device to the PHY I / O through the channel in the loop, wherein the data circulates from the PHY I / O to the memory device and back to the PHY I / O; determining an actual channel BER based on the data transmitted to the memory device and the data received from the memory device; comparing the actual channel BER with the calculated target channel BER; and A voltage value associated with the channel is adjusted based on the comparison between the actual channel BER and the calculated target channel BER.

2. The method of claim 1, wherein calculating the target channel BER comprises: Determine the actual overall BER; calculating an actual memory device BER based on a difference between the actual overall BER and the actual channel BER; and The target channel BER is calculated based on a difference between the target overall BER and the actual memory device BER.

3. The method according to claim 1, further comprising: determining a temperature associated with the channel; determining the voltage value associated with the channel; correlating the channel temperature and the channel voltage value with the actual channel BER; and The actual channel BER and the channel temperature and channel voltage values ​​associated with the actual channel BER are stored.

4. The method according to any one of claims 1 to 2, further comprising: monitoring a temperature value associated with the channel; querying a data structure (226, 518) for information associated with the monitored temperature value in response to a change in the monitored temperature value exceeding a threshold; and The channel is retrained according to the calculated target channel BER in response to information associated with the monitored temperature value not being in the data structure.

5. The method according to any one of claims 1 to 2, further comprising: monitoring a temperature value associated with the channel; querying a data structure for information associated with the monitored temperature value in response to a change in the monitored temperature value exceeding a threshold; determining a date at which the information associated with the monitored temperature value was stored in the data structure in response to the information associated with the monitored temperature value being in the data structure; and The channel is retrained according to the calculated target channel BER in response to the date exceeding a threshold period.

6. The method according to any one of claims 1 to 2, wherein adjusting the voltage value comprises: Calculating a difference between the actual channel BER and the calculated target channel BER; and The voltage value is adjusted to reduce the difference between the actual channel BER and the calculated target channel BER by: increasing the voltage value in response to the actual channel BER being higher than an upper limit value from a threshold range of the calculated target channel BER; reducing the voltage value in response to the actual channel BER being less than a lower limit value from the threshold range of the calculated target channel BER; and The voltage value is maintained in response to the actual channel BER being within the threshold range from the calculated target channel BER.

7. A device (100, 200) for voltage scaling, comprising: A physical input / output (PHYI / O) (123, 223), wherein the PHYI / O is configured to: sending the data to the memory device (130) via the channel (224); and receiving the data from the memory device via the channel; and a processor (117, 217, 502) coupled to the PHY I / O, wherein the processor is configured to: determining an actual channel bit error rate (BER) based on the data sent to the memory device and the data received from the memory device; and Adjustment of the voltage value is controlled in response to the determining the actual channel BER.

8. The apparatus of claim 7, wherein the processor is further configured to: calculating an actual BER of the memory device; Determine target overall BER; calculating a target channel BER based on a difference between the target overall BER and the actual memory device BER; and Adjustment of the voltage value is controlled based on a difference between the actual channel BER and the calculated target channel BER.

9. The apparatus of claim 7, wherein the processor is further configured to: determining temperature and voltage values ​​associated with the channel; correlating the temperature and the voltage value with the actual channel BER; and The temperature, the actual channel BER, and the voltage value are stored.

10. The apparatus of claim 7, wherein the processor is further configured to: determining a temperature associated with the channel; comparing the temperature associated with the channel to a stored temperature; In response to the temperature associated with the channel not matching a storage temperature: determining the voltage value associated with the channel; correlating the temperature and the voltage value with the actual channel BER; and storing the temperature, the actual channel BER and the voltage value; and In response to the temperature matching the storage temperature: determining a date and time for storing the storage temperature; In response to the date and time exceeding a threshold period: determining the voltage value; and correlating the temperature and the voltage value with the actual channel BER; and The temperature, the actual channel BER, the voltage value, and the current date and time are stored.

11. A system (110, 210, 410, 500) for scaling voltage, comprising: a memory device (130); A physical input / output (PHYI / O) (123, 223), wherein the PHYI / O is configured to: transmitting the test data to the memory device via a channel (224); and receiving the test data from the memory device via the channel; and a processor (117, 217, 502) coupled to the PHY I / O, wherein the processor is configured to: determining an actual bit error rate (BER) associated with the channel based on the transmission test data and the reception test data; determining temperature and voltage values ​​associated with the channel; and Adjustment of the voltage value associated with the channel is controlled based on the actual channel BER, the channel temperature, and the channel voltage value.

12. The system of claim 11, wherein the processor is further configured to: Calculate the target channel BER; calculating a difference between the actual channel BER and the calculated target channel BER; and Adjustment of the voltage value is controlled based on the difference between the actual channel BER and the calculated target channel BER.

13. The system of claim 11, wherein in response to determining the temperature associated with the channel, the processor is further configured to: comparing the determined temperature to a temperature stored in a data structure (226, 518); In response to the temperature not being stored in the data structure: correlating the temperature with the actual channel BER and the voltage value; and storing the associated temperature, the actual channel BER, the voltage value, and a current date in the data structure; and In response to the temperature matching a stored temperature in the data structure: determining a date on which the temperature was stored in the data structure; and In response to the date exceeding a threshold period: correlating the temperature with the actual channel BER and the voltage value; and The associated temperature, the actual channel BER, the voltage value, and a current date are stored in the data structure.

14. The system of claim 11, wherein the processor is further configured to: monitoring the temperature associated with the channel and adjusting the voltage value associated with the channel in response to an increase or decrease in the temperature exceeding a threshold; determining whether the increased or decreased temperature is stored in a data structure and the date the increased or decreased temperature was stored in the data structure; and In response to the increased or decreased temperature being stored in the data structure and the date not exceeding a threshold period, controlling the adjustment of the voltage value in response to the actual channel BER associated with the increased or decreased temperature being: By increasing the voltage value to be higher than an upper limit value from a threshold range for calculating the target channel BER; and The voltage value is reduced to fall below a lower limit value of the threshold range from the calculated target channel BER.

15. The system of claim 11, wherein the processor is further configured to: monitoring the temperature associated with the channel and adjusting the voltage value associated with the channel in response to an increase or decrease in the temperature exceeding a threshold; determining whether the increased or decreased temperature is stored in a data structure and the date the increased or decreased temperature was stored in the data structure; and In response to the increased or decreased temperature being stored in the data structure and the date not exceeding a threshold period, controlling adjustment of the voltage value in response to the actual channel BER associated with the increased or decreased temperature by maintaining the voltage value within a threshold range of a calculated target channel BER.

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