Thin wafer, method for manufacturing thin wafer, laminated semiconductor device, and method for manufacturing laminated semiconductor device

Abstract

The invention relates to a thin wafer, a manufacturing method thereof, a laminated semiconductor device and a manufacturing method thereof. A wafer may include a substrate, a device layer, and a polishing stop layer. The substrate may have a first surface and a second surface opposite each other. A device layer may be formed on the first surface of the substrate. The device layer may include a plurality of conductive patterns. A polishing stop layer is formed at a selected portion of the substrate. The polishing stop layer may include an insulating trench having a depth corresponding to a thickness of the substrate.

Description

Technical Field

[0001] Various embodiments generally relate to semiconductor technology. Background Art

[0002] A stacked semiconductor device may include at least two wafers (or at least two semiconductor dies) that are vertically stacked.

[0003] In order to reduce the size of a stacked semiconductor device and a signal transmission path in the stacked semiconductor device, a thinning process may be performed on a wafer (or a semiconductor die).

[0004] The thinning process may include bonding the wafers to one another, for which purpose the back side of at least one of the wafers is polished.

[0005] Therefore, this polishing operation is one of the most important operations performed to form a stacked type semiconductor device. Summary of the invention

[0006] Example embodiments provide a thin wafer having a uniform thickness.

[0007] Example embodiments also provide a method of manufacturing the thin wafer.

[0008] Example embodiments also provide a stacked semiconductor device including the above-mentioned thin wafer.

[0009] Example embodiments also provide a method of manufacturing the above-mentioned stacked semiconductor device.

[0010] According to example embodiments, a thin wafer may be provided. The thin wafer may include a thin substrate, a device layer, and a polishing stop layer. The thin substrate may have a first surface and a second surface opposite to each other. The device layer may be formed on the first surface of the thin substrate. The device layer may include a plurality of conductive patterns. The polishing stop layer is formed at a selected portion of the thin substrate. The polishing stop layer may include an insulating groove having a depth corresponding to the thickness of the thin substrate.

[0011] In example embodiments, the thin wafer may further include a plurality of conductive structures. The conductive structures may be formed by the thin substrate. The conductive structures may be electrically connected to electrodes of the device layer.

[0012] In example embodiments, a polish stop layer may be located between adjacent conductive structures.

[0013] In example embodiments, the thin substrate may include a plurality of die regions and scribe lanes for defining the die regions. The selected portion may be at least one of the scribe lanes and the die regions.

[0014] In example embodiments, the thin substrate may include a pattern concentration region and a dummy region. The selected portion may be at least one of the pattern concentration region and the dummy region.

[0015] In example embodiments, the polishing stop layers may be arranged symmetrically to each other on the entire surface of the thin substrate.

[0016] According to example embodiments, a method for manufacturing a thin wafer may be provided. In the method for manufacturing a thin wafer, a semiconductor substrate may be provided. The semiconductor substrate may have a front surface and a bottom surface spaced apart from each other by a first thickness. A polishing stop layer is formed by the front surface of the semiconductor substrate. The polishing stop layer may have a first depth less than the first thickness. An isolation layer may be formed at the semiconductor substrate having the polishing stop layer. The isolation layer may have a second depth shallower than the first depth. A device layer may be formed on the front surface of the semiconductor substrate having the polishing stop layer and the isolation layer. The bottom surface of the semiconductor substrate may be polished until the polishing stop layer may be exposed to form a thin wafer.

[0017] In example embodiments, the first depth may be about 0.1% to about 2% of the first thickness.

[0018] According to example embodiments, a method for manufacturing a stacked semiconductor device may be provided. In the method for manufacturing a stacked semiconductor device, a first device layer and a first bonding layer may be sequentially formed on a first substrate having a plurality of polishing stop layers to provide a first wafer. A second device layer and a second bonding layer may be sequentially formed on a second substrate to provide a second wafer. The first wafer may be stacked on the second wafer so that the first bonding layer and the second bonding layer face each other, thereby exposing the bottom surface of the first substrate. The first bonding layer of the first wafer and the second bonding layer of the second wafer may be mixed and bonded to each other. The bottom surface of the first substrate may be polished until the polishing stop layer may be exposed to form a thin substrate. The polishing stop layer may include a groove containing an insulating material. The depth of the groove may be less than the thickness of the first substrate.

[0019] According to example embodiments, a stacked semiconductor device may be provided. The stacked semiconductor device may include a first wafer and a second wafer. The first wafer may include a first substrate and a first bonding layer on the first substrate. The second wafer may include a second substrate and a second bonding layer on the second substrate. The second bonding layer may be hybrid bonded to the first bonding layer. The first substrate may include a plurality of first polishing stop layers. The first polishing stop layer may have an insulating groove structure having a depth corresponding to a thickness of the first substrate.

[0020] Therefore, according to example embodiments, a polishing stop layer having an insulating trench structure may be formed in a semiconductor substrate. The polishing stop layers may be arranged symmetrically to each other on the entire surface of the semiconductor substrate. Alternatively, the polishing stop layer may be arranged in an area with a fast polishing speed, an area with a low pattern density, or an adjacent conductive structure to improve polishing uniformity. Therefore, the improvement in polishing uniformity may provide a thin substrate having a uniform thickness without damaging a semiconductor substrate, a thin wafer, and a conductive member in a stacked semiconductor device including the thin wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and another aspect, features and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 is a cross-sectional view showing a thin wafer according to an example embodiment;

[0023] Figure 2A is a plan view showing a thin wafer according to an example embodiment;

[0024] Figure 2B It is shown Figure 2A an enlarged plan view of portion "A" in FIG.

[0025] Figure 3A and Figure 3B is a plan view showing a polishing stop layer according to an example embodiment;

[0026] Figure 4 It is along Figure 3A A cross-sectional view taken along line IV-IV';

[0027] Figures 5 to 8 is a cross-sectional view showing a method of manufacturing a thin wafer according to an example embodiment;

[0028] Figures 9 to 11 is a cross-sectional view showing a method of manufacturing a stacked semiconductor device according to an example embodiment; and

[0029] Fig.12 is a cross-sectional view showing a stacked semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0030] Although some implementations of the disclosed technology will be discussed, the disclosed technology may be implemented in a variety of ways beyond the details of the examples described herein.

[0031] Figure 1 is a cross-sectional view showing a thin wafer according to an example embodiment.

[0032] Reference Figure 1, the thin wafer TW of the example embodiment may include a thin substrate 110 and a device layer 170. In some implementations, the thin substrate 110 may include a bulk wafer or a bulk substrate (or a portion of a bulk wafer or a portion of a bulk substrate) as a semiconductor material wafer that can be used to manufacture integrated circuits. In some implementations, the thin substrate 110, the thin wafer TW including the thin substrate 110, and the "wafer" may be a resulting device or structure that performs at least one of a front end of line (FEOL) process and a back end of line (BEOL) process.

[0033] The thin substrate 110 may include one or more semiconductor materials, and the thin substrate 110 may be used to manufacture integrated circuits. For example, the thin substrate 110 may include silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium, arsenic, and a combination of two or more of the materials listed above. In example embodiments, the semiconductor material may include silicon.

[0034] In example embodiments, the thin substrate 110 may include a semiconductor material such as silicon, carbon, germanium, silicon germanium, germanium tin, a combination thereof, etc. The thin substrate 110 may include at least one of silicon, germanium, gallium, arsenic, and phosphorus.

[0035] The thin substrate 110 may include a first surface S1 and a second surface S2 opposite to each other. The first surface S1 and the second surface S2 may be spaced apart from each other by a thickness ds of the thin substrate 110. The thickness ds of the thin substrate 110 may be thinner than that of the bulk wafer. In example embodiments, the thickness of the thin substrate 110 may be about 0.8 μm to about 16 μm.

[0036] The thin substrate 110 may include at least one polishing stopper or polishing stop layer 130. In some implementations, the term "polishing stop layer" may be used to indicate a layer for slowing down or stopping a chemical mechanical polishing process. The polishing stop layer 130 may have a groove structure having a depth corresponding to a thickness ds of the thin substrate 110. Therefore, the polishing stop layer 130 may have a structure formed in the thin substrate 110. The polishing stop layer 130 having a depth ds may have various shapes.

[0037] The polishing stop layer 130 may be an insulating trench filled with an insulating material, such as silicon oxide, silicon nitride, an organic insulating material, or the like.

[0038] The polish stop layer 130 may be disposed in a selected portion of the thin substrate 110 .

[0039] In example embodiments, the polishing stop layer 130 may be symmetrically located at regions in the thin substrate 110. The polishing stop layer 130 may be uniformly arranged in a selected portion of the thin substrate 110.

[0040] Furthermore, the number of polishing stop layers 130 in a region of a thin wafer having a fast polishing speed may be greater than the number of polishing stop layers 130 in a region of a thin wafer having a slow polishing speed.

[0041] Therefore, the bulk wafer may be planarized by performing a polishing operation using the polishing stop layer 130 having an insulating trench structure to slow down or stop the polishing operation, thereby forming the thin substrate 110 having the planarized second surface S2.

[0042] The thin substrate 110 according to example embodiments may further include a conductive structure 150 in the thin substrate 110 . The conductive structure 150 may be formed in the thin substrate 110 .

[0043] The conductive structure 150 may include a conductive via 152 and a sidewall insulating layer 154. The conductive via 152 may include a conductive material.

[0044] The conductive via 152 may couple between an electrical component on the first surface S1 of the thin substrate 110 and an electrical component on the second surface S2 of the thin substrate 110 .

[0045] A sidewall insulating layer 154 may be interposed between the conductive via 152 and the thin substrate 110 to electrically isolate the conductive via 152 from the thin substrate 110 .

[0046] For example, the height of the conductive structure 150 may be similar to or substantially the same as the thickness ds of the thin substrate 110 .

[0047] The thin wafer TW according to example embodiments may further include a device layer 170 . For example, the device layer 170 may be formed on the first surface S1 of the thin substrate 110 .

[0048] The device layer 170 may include at least one electrode and an interconnect layer (or interconnect).

[0049] For example, device layer 170 may include active components and / or passive components.

[0050] Furthermore, the device layer 170 may include at least one of a transistor, a memory, a capacitor, an inductor, a resistor, a switch, an integrated circuit, an amplifier, an optoelectronic component, and other electronic components and a plurality of interconnection layers connected therebetween.

[0051] Alternatively, the device layer 170 may include at least one of a memory component having a plurality of memory cells and a logic / driver component for driving the memory component. The memory component may include a plurality of memory cells arranged two-dimensionally or three-dimensionally.

[0052] Electrodes of elements in the device layer 170 or an interconnection layer connected to the electrodes may be electrically connected to the conductive structure 150 exposed through the first surface S1 .

[0053] Although not depicted in the drawings, external terminals or bonding pads may be formed on the conductive structure 150 exposed through the second surface S2 of the thin substrate 110 .

[0054] Figure 2A is a plan view showing a thin wafer according to an example embodiment, Figure 2B It is shown Figure 2A An enlarged plan view of portion "A" in FIG.

[0055] Reference Figure 2A and Figure 2B , the thin wafer TW may include a substrate having a plurality of dies 10. The dies 10 may be divided by scribe lines SL on the substrate. Figure 2A and Figure 2B It can be shown that it can be formed Figure 1 The upper surface of the thin wafer TW of the device layer 170 in the device layer 170 may not be shown in Figure 2A and Figure 2B In addition, the substrate may correspond to Figure 1 The thin substrate 110 in the embodiment of the present invention.

[0056] The device layers on the die 10 may include active components, passive components, interconnect layers, memory components, and logic / driver components. The device layers on the scribe lanes SL may include test patterns and alignment keys.

[0057] For example, scribe street SL may include polishing stop layer region 130b including at least one polishing stop layer 130. In addition, die 10 may include at least one polishing stop layer region 130b including at least one polishing stop layer 130. Polishing stop layers 130 in polishing stop layer regions 130a and 130b may include various shapes.

[0058] In example embodiments, the polishing stop layer 130 in the polishing stop layer region 130a may have various shapes and may be spaced apart from each other by a gap. The polishing stop layer 130 in the polishing stop layer region 130a may overlap at least one of a test pattern and an alignment key formed at the scribe street SL. Alternatively, the polishing stop layer 130 in the polishing stop layer region 130a may be disposed between the test pattern and the alignment key disposed at the scribe street SL.

[0059] The polishing stop layer region 130b of the die 10 may be located in at least one of the pattern concentration region PA and the dummy region PD. For example, the pattern concentration region PA is a region of the die 10 where a plurality of circuit patterns are distributed, and the density of the plurality of circuit patterns in the pattern concentration region PA is higher than a set density. The dummy region PD is a region of the die 10 where a plurality of circuit patterns are distributed, and the density of the plurality of circuit patterns is lower than a set density.

[0060] For example, the pattern concentration area PA may be a portion of the substrate corresponding to a region where circuit patterns are densely distributed (eg, a memory cell array). The dummy area PD may be a portion of the substrate corresponding to a region where circuit patterns are roughly distributed (eg, a logic circuit region or a peripheral circuit region).

[0061] A relatively large number of conductive structures 150 may be integrated in the die 10 corresponding to the pattern concentration area PA (eg, in a thin substrate). A relatively small number of conductive structures 150 may be integrated in the die 10 corresponding to the dummy area PD (eg, in a thin substrate).

[0062] In example embodiments, the polishing stop layer 130 in the polishing stop layer region 130 b may not contact the conductive structure 150 in the polishing stop layer region 130 b .

[0063] Alternatively, the polishing stop layer region 130b may be located in the dummy region PD. The polishing stop layer 130 may be uniformly distributed in the polishing stop layer region 130b.

[0064] In addition, the polishing stop layer region 130b may be located in the pattern concentration region PA. The size of the polishing stop layer 130 in the pattern concentration region PA may be smaller than the size of the polishing stop layer 130 in the dummy region PD and the scribe lane SL.

[0065] At least one polishing stop layer 130 in the polishing stop layer regions 130a and 130b may be located between adjacent conductive structures 150. In some implementations, the polishing stop layer 130 in the pattern concentration area PA may be located between adjacent conductive structures 150 to cut off signal interference between the conductive structures 150.

[0066] Figure 3A and Figure 3B is a plan view showing a polishing stop layer according to an example embodiment, Figure 4 It is along Figure 3A A cross-sectional view taken along line IV-IV'.

[0067] Reference Figure 3A , the polishing stop layer 131 according to example embodiments may be disposed between adjacent conductive structures 150 .

[0068] In an example implementation, if Figure 3A As shown, the polish stop layer 131 may have a grid shape configured to separate the plurality of conductive structures 150 into individual conductive structures 150 .

[0069] Reference Figure 3B , the plane structure of the polishing stop layer 131 may have a dotted line shape or a dot shape between the conductive structures 150 .

[0070] As the integration density or integration level of semiconductor integrated circuit devices increases, the density of the conductive structures 150 in the thin substrate 110 may also increase. In some implementations, the conductive vias 152 corresponding to the actual conductive material of the conductive structures 150 are electrically isolated by the thin substrate 110 and the sidewall insulating layer 154, and thus when the conductive structures 150 may be densely distributed, the signals generated by the conductive structures may be interfered by other signals generated by adjacent conductive structures 150, thereby degrading the electrical characteristics of the semiconductor integrated circuit device.

[0071] In example embodiments, the polishing stop layer 131 including an insulating material may be interposed between densely or closely arranged conductive structures 150. Therefore, signal interference between the conductive structures 150 may be reduced by the polishing stop layer 131.

[0072] Figures 5 to 8 is a cross-sectional view illustrating a method of manufacturing a thin wafer according to an example embodiment.

[0073] In some implementations, the semiconductor substrate sub may include a bulk wafer or a bulk semiconductor substrate including a semiconductor material.

[0074] Reference Figure 5 , the semiconductor substrate sub may have a first thickness d1. The semiconductor substrate sub may have a front surface FS and a bottom surface BS opposite to each other. The front surface FS and the bottom surface BS may be spaced apart from each other by a first thickness d1.

[0075] Reference Figure 6 At least one first trench t may be formed at a selected portion of the semiconductor substrate sub. The first trench t may have a depth ds from the front surface FS of the semiconductor substrate sub. The first depth ds may determine Figure 1 The first trench t may be formed to have a depth corresponding to a desired thickness of the thin substrate 110 .

[0076] For example, the first depth ds may be less than the first thickness d1. In example embodiments, the first depth ds of the first trench t may be about 0.1% to about 2% of the first thickness d1. For example, when the first thickness d1 may be about 800 μm, the first depth ds may be about 0.8 μm to about 16 μm, particularly about 5 μm to about 10 μm.

[0077] The selected portion may be at least one of: a portion of the semiconductor substrate sub where the die 10 is to be formed; or a portion of the semiconductor substrate sub where the scribe lane SL is to be formed. For example, the first trench t includes a plurality of first trenches t. The plurality of first trenches t may be formed in the selected portion of the semiconductor substrate sub, and the plan view and cross-sectional view of the first trench t may have various shapes. In some implementations, in a plan view, the first trenches t may be symmetrically arranged on the surface of the semiconductor substrate sub.

[0078] Reference Figure 7 , the first trench t may be filled with an insulating material to form a polishing stop layer 130. For example, the insulating material may include at least one of silicon oxide, silicon nitride, or an organic insulating material, but the disclosed technology is not limited thereto.

[0079] Subsequently, an isolation layer ISO forming process and a well forming process may be performed on the semiconductor substrate sub.

[0080] The isolation layer ISO may have a shallow trench isolation (STI) structure. For example, a second trench ST may be formed in the semiconductor substrate sub. The depth of the second trench ST may be shallower than the first depth ds of the first trench t of the polishing stop layer 130. The second trench ST may be filled with an insulating material to form the isolation layer ISO.

[0081] In example embodiments, a process of filling the first trench t with an insulating material and a process of filling the second trench ST with an insulating material may be performed simultaneously. For example, the first trench t and the second trench ST may be formed at the semiconductor substrate sub. The first trench t and the second trench ST may be filled with an insulating material at the same time to form a polishing stop layer 130 and an isolation layer ISO.

[0082] Then, a device layer 170 may be formed on the front surface FS of the semiconductor substrate sub. As described above, the device layer 170 may include active elements and / or passive elements. Figure 7 As shown, multiple interconnection layers M can be formed.

[0083] In example embodiments, a FEOL process and a BEOL process may be performed on the device layer 170 .

[0084] Reference Figure 8 , the bottom surface BS of the semiconductor substrate sub may be polished to form a thin substrate 110 having a first depth ds.

[0085] In some implementations, the semiconductor substrate sub may be placed so that the bottom surface BS of the semiconductor substrate sub faces an upward direction. The bottom surface BS of the semiconductor substrate sub may be polished until the bottom of the polishing stop layer 130 is exposed. Since the depth (e.g., the first depth ds) of the polishing stop layer 130 may be about 0.1% to about 2% of the first thickness d1 of the semiconductor substrate sub, the portion of the semiconductor substrate sub removed by polishing may be about 98% to about 99.9% of the first thickness t1 of the semiconductor substrate sub. For example, a chemical mechanical polishing (CMP) process may be performed on the semiconductor substrate sub, but the disclosed technology is not limited thereto.

[0086] For example, since the polishing stop layer 130 may be symmetrically arranged on the surface of the semiconductor substrate sub, the bottom surface BS of the semiconductor substrate sub may be polished (or removed) at a uniform polishing speed with respect to the entire bottom surface BS of the semiconductor substrate sub.

[0087] In example embodiments, when a specific portion of the semiconductor substrate sub is relatively quickly polished, the polishing stop layer 130 may be densely arranged in the specific portion to control the polishing speed of the semiconductor substrate sub.

[0088] The thin substrate 110 may be formed through the above-described process. The first surface S1 of the thin substrate 110 may correspond to the front surface FS of the semiconductor substrate sub. The second surface S2 of the thin substrate 110 may be exposed.

[0089] The conductive structure 150 may be formed in the thin substrate 110. In an example embodiment, a hole may be formed in the thin substrate 110. At least one of the interconnect layer M in the device layer 170 or the conductive region in the thin substrate 110 may be exposed through the hole. A sidewall insulating layer 154 may be formed on the sidewall of the hole. The hole may be filled with a conductive material to form a conductive via 152 to form the thin wafer TW. In an example embodiment, the conductive structure 150 may be formed after polishing the semiconductor substrate sub. Alternatively, the conductive structure 150 may be formed before polishing the semiconductor substrate sub or in other processes.

[0090] Although not depicted in the drawings, external terminals such as bonding pads may be formed on the conductive structure 150 exposed through the second surface S2 .

[0091] Figures 9 to 11 is a cross-sectional view showing a method of manufacturing a stacked semiconductor device according to an example embodiment, Fig.12 is a cross-sectional view showing a stacked semiconductor device according to an example embodiment.

[0092] Reference Fig. 9, a first wafer W1 and a second wafer W2 may be prepared. The first wafer W1 and the second wafer W2 may include semiconductor substrates sub1 and sub2 and device layers DL1 and DL2 on the semiconductor substrates sub1 and sub2, respectively.

[0093] The type and thickness of the first substrate sub1 of the first wafer W1 and the type and thickness of the second substrate sub2 of the second wafer W2 may be the same, but the disclosed technology is not limited thereto.

[0094] At least one of the first substrate sub1 or the second substrate sub2 may include a polishing stop layer 230. In example embodiments, the polishing stop layer 230 may be formed in the first substrate sub1. In some implementations, the polishing stop layer 230 may be formed in the first substrate sub1 and the second substrate sub2 in the same manner. In some implementations, the polishing stop layer 230 may be formed in a selected portion of the first substrate sub1 to have a Figures 5 to 7 The insulating trench structure shown. The depth of the polishing stop layer 230 may be about 0.1% to about 2% of the thickness of the first substrate sub1. The polishing stop layer 230 may have various widths and plane shapes that vary based on the integration degree of the device layer DL1 of the first wafer W1 and the polishing speed obtained in the previous polishing process.

[0095] In an implementation, the first device layer DL1 of the first wafer W1 and the second device layer DL2 of the second wafer W2 may have substantially the same structure. In another implementation, the first device layer DL1 of the first wafer W1 and the second device layer DL2 of the second wafer W2 may have different structures.

[0096] For example, at least one of the first device layer DL1 or the second device layer DL2 may include a memory component ME and / or a logic / driver component PE. In example embodiments, the first device layer DL1 and the second device layer DL2 may all include a memory component ME and a logic / driver component PE, but the disclosed technology is not limited thereto.

[0097] For example, the memory element ME may include a plurality of DRAM memory cells having cell capacitors CAP.The logic / driver element PE may include circuitry for performing memory operations of the DRAM memory cells.

[0098] exist Fig. 9 In the embodiment, the memory component ME and the logic / driver component PE may be arranged horizontally in parallel with each other, but the disclosed technology is not limited thereto. Alternatively, the memory component ME and the logic / driver component PE may be stacked vertically.

[0099] In example embodiments, the memory element ME may correspond to a pattern concentration region. The logic / driver element PE may include a dummy region.

[0100] Reference Fig.10 , a first bonding layer 250 may be formed on the first device layer DL1 , and a second bonding layer 260 may be formed on the second device layer DL2 .

[0101] The first bonding layer 250 may include a plurality of first bonding pads 252 and a first bonding insulating layer 254. The first bonding pads 252 may be connected to an electrode in the first device layer DL1 or a conductive pattern such as an interconnect layer directly or indirectly connected to the electrode. The first bonding insulating layer 254 may electrically isolate the first bonding pads 252 from each other.

[0102] The second bonding layer 260 may include a plurality of second bonding pads 262 and a second bonding insulating layer 264. The second bonding pads 262 may be connected to an electrode in the second device layer DL2 or a conductive pattern such as an interconnect layer or an interconnect directly or indirectly connected to the electrode. The second bonding insulating layer 264 may electrically isolate the second bonding pads 262 from each other.

[0103] The first wafer W1 may be placed such that the first bonding layer 250 of the first wafer W1 faces the second bonding layer 260 of the second wafer W2. The first wafer W1 may then be stacked on the second wafer W2.

[0104] In example embodiments, when the first wafer W1 may be stacked on the second wafer W2, the memory component ME of the first device layer DL1 may correspond to the memory component ME of the second device layer DL2, and the logic / driver component PE of the first device layer DL1 may correspond to the logic / driver component PE of the second device layer DL2. Therefore, the first bonding layer 250 and the second bonding layer 260 may contact each other. The bottom surface of the first wafer W1 may be exposed upward.

[0105] The first bonding layer 250 of the first wafer W1 and the second bonding layer 260 of the second wafer W2 may be hybrid-bonded to each other. Therefore, the first wafer W1 may be stacked on the second wafer W2.

[0106] Reference Fig.11 , the bottom surface of the first wafer W1 may be polished until the bottom surface of the polishing stop layer 230 may be exposed to form a thin substrate T-sub1.

[0107] The conductive structure 270 may be formed in the thin substrate T-sub. The conductive structure 270 may be formed in the thin substrate T-sub. The conductive structure 270 may be a vertical signal transmission wiring configured to transmit an external signal to an electrode of the first device layer DL1 or an interconnection layer connected to the electrode after receiving an external signal. The conductive structure 270 may be formed by the above-described process based on the example embodiment or by a through silicon via (TSV) formation process.

[0108] In example embodiments, the conductive structure 270 may be located between the polishing stop layers 230. Since the polishing stop layer 230 including an insulating material may be placed between densely arranged conductive structures 270, signal interference between adjacent conductive structures 270 may be reduced.

[0109] For example, any conductive structures 270 electrically connected to the region corresponding to the memory element ME (eg, conductive patterns in the memory element ME) may be relatively densely arranged. To reduce signal interference between densely arranged conductive structures 270 , the conductive structures 270 may be located between insulating polishing stop layers 230 .

[0110] Alternatively, if Fig.12 As shown, the second substrate sub2 may further include a plurality of polishing stop layers 231 having an insulating trench shape. Therefore, the second substrate sub2 may be polished using the polishing stop layers 231 to form a thin substrate T-sub2 for the second wafer W2.

[0111] For example, at least one conductive structure 271 in a pattern concentration region of the second device layer DL2 (eg, a region corresponding to the memory element ME of the second device layer DL2 ) may also be disposed between the polishing stop layers 231 .

[0112] In example embodiments, a polishing stop layer having an insulating groove structure may be formed in a semiconductor substrate. In one example, the polishing stop layer may be symmetrically arranged on the surface of the semiconductor substrate. In another example, the polishing stop layer may be arranged in a region having a fast polishing speed. In another example, the polishing stop layer may be arranged in a region having a slow pattern density. In another example, the polishing stop layer may be arranged between adjacent conductive structures. Therefore, the polishing uniformity of the semiconductor substrate may be improved. Therefore, by improving the polishing uniformity, a thin substrate, a thin wafer, and a stacked semiconductor device may be manufactured without damaging the conductive member in the semiconductor substrate.

[0113] Although various embodiments of the disclosed technology related to memory systems, data processing systems, and operations thereof are described above, variations and enhancements of the disclosed embodiments and other embodiments may be made based on what is disclosed and / or illustrated in this patent document.

[0114] Cross-reference to related applications and priority claim

[0115] This patent document claims priority to and the benefit of Korean Application No. 10-2023-0106941, filed on August 16, 2023, which is hereby incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. A wafer, comprising: a substrate including a first surface and a second surface opposite to each other; a polishing stop layer formed in a selected portion of the substrate, the polishing stop layer comprising one or more insulating trenches, each of the insulating trenches being filled with an insulating material and having a depth corresponding to a thickness of the substrate; as well as A device layer is supported by the substrate and includes a plurality of conductive patterns for electrically connecting different circuit elements in the substrate. 2 . The wafer of claim 1 , further comprising a plurality of conductive structures formed in the substrate and electrically connected to at least one of the conductive patterns of the device layer.

3. The wafer according to claim 2, wherein: The polish stop layer is located between adjacent conductive structures of the plurality of conductive structures.

4. The wafer according to claim 2, wherein: The polishing stop layer has a grid shape that separates the plurality of conductive structures into individual conductive structures.

5. The wafer according to claim 1, wherein: The substrate includes a plurality of die regions and scribe lanes for defining the plurality of die regions, and the selected portion of the substrate includes at least one of the scribe lanes or the die regions.

6. The wafer according to claim 1, wherein: The substrate includes a pattern concentration area and a dummy area, and the selected portion of the substrate is at least one of the pattern concentration area or the dummy area, wherein a plurality of circuit patterns are distributed in the pattern concentration area and the dummy area, and a density of the plurality of circuit patterns in the pattern concentration area is higher than a predetermined density, and a density of the plurality of circuit patterns in the dummy area is lower than the predetermined density. 7 . The wafer according to claim 1 , further comprising an isolation layer formed in the substrate from the first surface of the substrate, the isolation layer having a depth shallower than a depth of the polishing stop layer.

8. A method for manufacturing a wafer, the method comprising the following steps: forming a semiconductor substrate including a front surface and a bottom surface spaced apart from the front surface by a first thickness; forming a polish stop layer in the semiconductor substrate from the front surface of the semiconductor substrate, the polish stop layer having a first depth less than the first thickness; forming an isolation layer in the semiconductor substrate including the polishing stop layer formed in the semiconductor substrate, the isolation layer having a second depth less than the first depth; forming a device layer over the front surface of the semiconductor substrate including the polishing stop layer and the isolation layer formed in the semiconductor substrate; as well as The bottom surface of the semiconductor substrate is polished until the polishing stop layer is exposed.

9. The method according to claim 8, wherein: The step of forming the polishing stop layer comprises the following steps: forming a first trench having a first depth in a selected portion of the semiconductor substrate; and The first trench is filled with an insulating material.

10. The method according to claim 9, wherein: The first depth is 0.1% to 2% of the first thickness.

11. The method according to claim 8, wherein: The step of forming the isolation layer comprises the following steps: forming a second trench in the semiconductor substrate having a second depth from the front surface of the semiconductor substrate; and The second trench is filled with an insulating material.

12. The method according to claim 8, wherein: The step of forming the polishing stop layer and the isolation layer comprises the following steps: forming a first trench having a first depth in a selected portion of the semiconductor substrate; forming a second trench having a second depth in a region of the semiconductor substrate where the isolation layer is to be formed; and The first trench and the second trench are filled with an insulating material.

13. The method according to claim 8, further comprising the steps of: A plurality of conductive structures are formed in the substrate between the polish stop layers.

14. A method for manufacturing a stacked semiconductor device, the method comprising the following steps: forming a first wafer by forming a first device layer and a first bonding layer over a first substrate including a plurality of polish stop layers; forming a second wafer by forming a second device layer and a second bonding layer over a second substrate; stacking the first wafer on the second wafer such that the first bonding layer faces the second bonding layer and a bottom surface of the first substrate is exposed; performing hybrid bonding to attach the first bonding layer of the first wafer to the second bonding layer of the second wafer; as well as polishing the exposed bottom surface of the first wafer until the polishing stop layer is exposed, Wherein, the polishing stop layer includes an insulating groove having a depth less than a thickness of the first substrate.

15. The method according to claim 14, wherein: The method further comprises the following steps: before forming the first device layer and the first bonding layer, forming the polishing stop layer in the first substrate, Wherein, the step of forming the polishing stop layer comprises the following steps: forming a plurality of grooves on the front surface of the first substrate, the depth of each of the grooves being less than the thickness of the first substrate; and The trench is filled with an insulating material.

16. The method according to claim 14, wherein: The depth of the polishing stop layer is 0.1% to 2% of the thickness of the first substrate.

17. The method according to claim 14, wherein: Each of the first device layer and the second device layer includes a plurality of interconnect layers, wherein the first bonding layer comprises a plurality of first bonding pads and a first bonding insulating layer, the plurality of first bonding pads are connected to the interconnect layer of the first device layer, the first bonding insulating layer electrically insulates the first bonding pads from each other, and The second bonding layer includes a plurality of second bonding pads and a second bonding insulation layer, wherein the plurality of second bonding pads are connected to electrodes of the second device layer, and the second bonding insulation layer electrically insulates the second bonding pads from each other.

18. The method according to claim 17, wherein: The step of hybrid bonding the first wafer to the second wafer comprises the following steps: directly bonding the first bonding insulating layer to the second bonding insulating layer; and The first bonding pad is directly bonded to the second bonding pad.

19. The method according to claim 14, further comprising the steps of: A plurality of conductive structures penetrating the first substrate or the second substrate are formed.

20. The method according to claim 19, wherein: The polishing stop layer is located between adjacent conductive structures.

21. A stacked semiconductor device, comprising: A first wafer, the first wafer comprising a first substrate and a first bonding layer disposed on the first substrate; as well as a second wafer including a second substrate and a second bonding layer disposed on the second substrate to be attached to the first bonding layer using hybrid bonding, The first substrate includes a plurality of first polishing stop layers, each of which includes one or more insulating trench structures, and the one or more insulating trench structures are filled with insulating material and have a depth corresponding to the thickness of the first substrate.

22. The stacked semiconductor device according to claim 21, in, The first bonding layer includes a plurality of first bonding pads connected to the interconnection layer of the first device layer and a first bonding insulation layer, the first bonding insulation layer is located between the first bonding pads, and The second bonding layer includes a plurality of second bonding pads and a second bonding insulation layer, the plurality of second bonding pads are in contact with the first bonding pads, and the second bonding insulation layer is located between the second bonding pads.

23. The stacked semiconductor device according to claim 21, in, The first wafer further includes a first device layer including a plurality of first conductive patterns electrically connecting different circuit elements in the first wafer, and The second wafer further includes a second device layer, and the second device layer includes a plurality of second conductive patterns electrically connecting different circuit elements in the second wafer.

24. The stacked semiconductor device according to claim 23, in, The first substrate further includes a plurality of first conductive structures formed in the first substrate and electrically connected to at least one of the first conductive patterns, and Wherein, at least one of the first conductive structures is located between the first polishing stop layers.

25. The stacked semiconductor device according to claim 24, wherein: The first device layer includes a pattern concentration area and a dummy area, and the first conductive structure between the first polishing stop layer is electrically connected to the first conductive pattern in the pattern concentration area, wherein a plurality of circuit patterns are distributed in the pattern concentration area and the dummy area, and a density of the plurality of circuit patterns in the pattern concentration area is higher than a predetermined density, and a density of the plurality of circuit patterns in the dummy area is lower than the predetermined density.

26. The stacked semiconductor device according to claim 23, wherein: The second substrate includes a plurality of second polishing stop layers and a plurality of second conductive structures, the depth of each second polishing stop layer corresponds to the thickness of the second substrate, and the second conductive structure is formed in the second substrate and electrically connected to at least one of the second conductive patterns.

27. The stacked semiconductor device according to claim 26, wherein: The second substrate includes a pattern concentration area and a dummy area, and the second conductive structure between the second polishing stop layers is electrically connected to the second conductive pattern in the pattern concentration area of ​​the second device layer.

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