Semiconductor device and forming method thereof

Abstract

The method comprises the following steps: forming a first bonding pad along a wafer; bonding a first die to the first set of first bond pads, the first die being electrically connected to the wafer; depositing a gap filling dielectric over the wafer and around the first die; forming an opening in the gap filling dielectric; forming a first active through-via in physical contact with the second set of first bond pads and a first dummy through-via in physical contact with the third set of first bond pads, the first active through-via being electrically connected to the wafer, the first dummy through-via being electrically isolated from the wafer; forming a second bond pad along the first die, the first active through-via, and the first dummy through-via; and a first active via bonding the second die to the first die and to the first active through-via. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the demand for smaller and more creative packaging technologies for semiconductor dies has emerged. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, including: forming a first bonding pad along a wafer; bonding a first die to a first group of the first bonding pads, the first die being electrically connected to the wafer; depositing a gap-filling dielectric above the wafer and around the first die; forming an opening in the gap-filling dielectric to expose a second group of the first bonding pads and a third group of the first bonding pads; forming a first active through-via physically contacting the second group of the first bonding pads and a first pseudo through-via physically contacting the third group of the first bonding pads, the first active through-via being electrically connected to the wafer, and the first pseudo through-via being electrically isolated from the wafer; forming a second bonding pad along the back side of the first die, the upper surface of the first active through-via, and the upper surface of the first pseudo through-via; and bonding the second die to the first die and the first active through-via of the first active through-via.

[0004] Other embodiments of the present application provide a semiconductor device, including: a first top die bonded to a bottom die, a first bonding pad electrically connecting the first top die to the bottom die; a first active through-via located above the bottom die, a second bonding pad electrically connecting the first active through-via to the bottom die; a first dummy through-via located above the bottom die, the first dummy through-via being in physical contact with a third bonding pad; and a dielectric layer sealing the first top die, the first active through-via and the first dummy through-via.

[0005] Some other embodiments of the present application provide a semiconductor device, comprising: a first die level, the first die level including a first die; a second die level, the second die level including: a second die; a first active through-via; and a first pseudo through-via, wherein in a first plan view, the first pseudo through-via includes a discontinuous frame around the second die; and a first bonding structure, between the first die level and the second die level, the first bonding structure electrically connecting the first die to the second die, the first bonding structure electrically connecting the first die to the first active through-via. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A and Figure 1B is a cross-sectional view of an integrated circuit die according to various embodiments.

[0008] Figures 2 to 15 is a cross-sectional view of an intermediate stage in the fabrication of a die structure according to some embodiments.

[0009] Fig.16 is a cross-sectional view of an intermediate stage in the fabrication of an integrated circuit package in accordance with some embodiments.

[0010] FIG. 17A to FIG. 17K is a plan view of an intermediate stage in the fabrication of a die structure according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing the different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] The disclosed embodiments provide embodiments for forming a die structure including one or more integrated circuit dies, active through vias, and pseudo through vias. The die structure can be incorporated into an integrated circuit package, such as an integrated system on chip (SoIC) device, but other types of devices or packages can be formed. Pseudo through vias provide various benefits, such as heat dissipation between electrically connected elements, and can be formed simultaneously with active through vias. The resulting semiconductor device can be manufactured to have a greater yield and improved performance.

[0014] Figure 1A and Figure 1B Components are shown that will be combined to form a die structure that may be part of an integrated circuit package according to various embodiments. Figure 1A An integrated circuit die is shown that may be singulated from the wafer and used as the top die of the die structure. Figure 1B An integrated circuit die is shown that may remain in wafer form and serve as a bottom die of the die structure.

[0015] Figure 1A 5 is a cross-sectional view of an integrated circuit die 50. The integrated circuit die 50 will be bonded to other dies in subsequent processing to form a die structure. The integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), etc.), a bridge die (e.g., a local silicon interconnect (LSI)), a power management die (e.g., a power management integrated circuit (PMIC)), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP)), a front-end die (e.g., an analog front end (AFE)), etc. or a combination thereof.

[0016] The integrated circuit die 50 can be formed in a wafer that may include different device regions that are segmented to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, which can be a doped or undoped silicon substrate or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., Figure 1A upward-facing surface) and non-active surfaces (e.g. Figure 1A Surfaces facing downward in the semiconductor substrate 52). Devices (not shown separately) may be formed in and / or on the active surface of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, inductors, resistors, etc.). The inactive surface may be free of devices.

[0017] The interconnect structure 54 is disposed above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices of the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. The dielectric layer may be, for example, a low-k dielectric layer. The metallization layer may include conductive vias and / or wires to interconnect the devices of the semiconductor substrate 52. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. The metallization layer of the interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

[0018] Optionally, the conductive via 56 extends into the interconnect structure 54 and / or the semiconductor substrate 52. The conductive via 56 is electrically coupled to the metallization layer of the interconnect structure 54. As an example of forming the conductive via 56, a groove can be formed in the interconnect structure 54 and / or the semiconductor substrate 52 by, for example, etching, milling, laser technology, a combination thereof, etc. A thin barrier layer can be conformally deposited in the groove, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, etc. The barrier layer can be formed of an oxide, a nitride, a combination thereof, etc. A conductive material can be formed over the barrier layer and in the groove. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, etc. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, etc. Excess conductive material and the barrier layer are removed from the surface of the interconnect structure 54 or the semiconductor substrate 52 by, for example, chemical mechanical polishing (CMP). The remaining portion of the barrier layer and the conductive material located in the groove forms the conductive via 56. After its initial formation, the conductive via 56 may be buried in the semiconductor substrate 52. The semiconductor substrate 52 may be thinned in subsequent processing to expose the conductive via 56 at the inactive surface of the semiconductor substrate 52. After the exposure process, the conductive via 56 is a through substrate via (TSV) extending through the semiconductor substrate 52, such as a through silicon via.

[0019] The dielectric layer 62 is located above the interconnect structure 54 at the front side of the integrated circuit die 50. The dielectric layer 62 can be formed of: an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, etc.; a nitride such as silicon nitride, etc.; a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymer, etc.; a combination thereof; etc. The dielectric layer 62 can be formed, for example, by CVD, spin coating, lamination, etc. Optionally, one or more passivation layers (not shown separately) are disposed between the dielectric layer 62 and the interconnect structure 54.

[0020] The die connector 64 extends through the dielectric layer 62. The die connector 64 may include conductive pillars, pads, etc. that may be made into external connections. In some embodiments, the die connector 64 includes a bonding pad (e.g., a metal pad) at the front side of the integrated circuit die 50, and includes a bonding pad via that connects the bonding pad to the upper metallization layer of the interconnect structure 54. In such embodiments, the die connector 64 (including the bonding pad and the bonding pad via) may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The die connector 64 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc., which may be formed, for example, by plating, etc.

[0021] Optionally, a chip probe (CP) test may be performed on the integrated circuit die 50. For example, a chip probe may be attached to a test pad (not separately shown). The chip probe test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Thus, only the subsequently processed integrated circuit die 50 (which is a KGD) is packaged, and the die that fails the chip probe test is not packaged.

[0022] Figure 1B 70 (e.g., an integrated circuit wafer 70). The integrated circuit die 50 will be bonded to the integrated circuit die 70 in subsequent processing to form a die structure. The integrated circuit die 70 can be a logic die (e.g., a CPU, a GPU, a SoC, an AP, a microcontroller, etc.), a memory die (e.g., a DRAM, a SRAM, etc.), a bridge die (e.g., an LSI), a power management die (e.g., a PMIC), an RF die, an interface die, a sensor die, a MEMS die, a signal processing die (e.g., a DSP), a front-end die (e.g., an AFE), etc., or a combination thereof.

[0023] The integrated circuit die 70 may be formed in a wafer that may include different device regions 70D. However, according to some embodiments, the different device regions 70D may remain undivided to form multiple integrated circuit dies 70 within the wafer form. The integrated circuit die 70 may be processed according to an applicable manufacturing process to form an integrated circuit. The integrated circuit die 70 may include a substrate 72 formed of a material similar to that described above in conjunction with the semiconductor substrate 52 and an interconnect structure 74 formed similarly to that described above in conjunction with the interconnect structure 54. It should be noted that the integrated circuit die 70 may not include conductive vias like the conductive vias 56 of the integrated circuit die 50. However, in other embodiments, the integrated circuit die 70 may include similar conductive vias that may be used for backside wiring and / or external electrical connections.

[0024] In some embodiments, a bonding structure 80 is formed along the front side of the integrated circuit die 70. The bonding structure 80 is formed above the interconnect structure 74 of the integrated circuit die 70 and will be used for subsequent bonding processes. The bonding structure 80 includes a bonding layer 82 formed of a dielectric material, which may be an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, etc., which may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The bonding structure 80 also includes a bonding pad 84 (e.g., a metal pad) formed in the bonding layer 82. The bonding pad 84 is electrically connected to the interconnect structure 74. For example, the bonding pad 84 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The bonding pad 84 may be formed by a conductive material, such as a metal, such as copper, aluminum, etc., which may be formed by, for example, plating, etc. In some embodiments, a planarization process is performed on the bonding pad 84 and the bonding layer 82, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. After the planarization process, the surfaces of the bonding pad 84 and the bonding layer 82 are substantially coplanar (within process variations). As shown, the bonding pad 84 may include a pad portion and a through-hole portion connecting the pad portion to the interconnect structure 74.

[0025] Figures 2 to 16 is a tube core structure 100 according to some embodiments (see Fig.15 ). The die structure 100 is a cross-sectional view of an intermediate stage in the manufacture of an integrated circuit die 70. The die structure 100 is a stack of integrated circuit dies (including the integrated circuit die 70, the first integrated circuit die 50A and the second integrated circuit die 50B). The die structure 100 is formed by bonding the integrated circuit dies 50 together on the device regions 70D of the integrated circuit die 70. The device regions 70D are segmented to form the die structure 100. The processing of one device region 70D of the integrated circuit die 70 is shown, but it should be understood that any number of device regions 70D (e.g., along the integrated circuit dies 70 in wafer form) can be processed simultaneously to form any number of die structures 100.

[0026] The die structure 100 is an assembly that can be subsequently packaged to form an integrated circuit package (see Fig.16 ). The integrated circuit die of the die structure 100 may be a heterogeneous die. Packaging the die structure 100 instead of individually packaging the die may allow the heterogeneous die to be integrated to have a small footprint. The die structure 100 may be a system on integrated chip (SoIC) device, but may form other types of devices.

[0027] exist Figure 2, one or more first integrated circuit dies 50A (e.g., the first layer of the top die of the die structure 100) are attached to the integrated circuit die 70 (e.g., the bottom die of the die structure 100) in a face-down manner so that the front side of the first integrated circuit die 50A is attached to the bonding structure 80 (e.g., the bonding layer 82 and the bonding pad 84) along the integrated circuit wafer 70. The dielectric layer 62A and the die connector 64A of the first integrated circuit die 50A are attached to the bonding structure 80. The first integrated circuit die 50A can be placed by, for example, a pick and place process. In the illustrated embodiment, two first integrated circuit dies 50A are placed in the device area 70D, but any desired number of first integrated circuit dies 50A can be placed in the device area 70D. The first integrated circuit die 50A can be a logic device, such as a CPU, a GPU, a SOC, a microcontroller, etc.

[0028] As discussed above, the integrated circuit die 70 may be a wafer, such that multiple die structures 100 may be formed simultaneously on multiple separate integrated circuit dies 70 .

[0029] The first integrated circuit die 50A can be attached by bonding the first integrated circuit die 50A to the bonding structure 80. As described above, the bonding structure 80 is located on the front side of the integrated circuit die 70.

[0030] For example, the dielectric layer 62A of the first integrated circuit die 50A is directly bonded to the bonding layer 82 by dielectric-to-dielectric bonding without using any adhesive material (e.g., a die attach film). The die connector 64A of the first integrated circuit die 50A is directly bonded to the bonding pad 84 by metal-to-metal bonding without using any eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the first integrated circuit die 50A against the bonding layer 82. The pre-bonding is performed at low temperatures, such as about room temperature, and after the pre-bonding, the dielectric layer 62A is bonded to the bonding layer 82. The bonding strength is then improved in a subsequent annealing step, wherein the bonding layer 82, the bonding pad 84, the dielectric layer 62A, and the die connector 64A are annealed. After annealing, a direct bond, such as a melt bond, is formed to bond the bonding layer 82 to the dielectric layer 62A. For example, the bonding may be a covalent bond between the material of the bonding layer 82 and the material of the dielectric layer 62A. The bonding pads 84 can be connected to the die connector 64A in a one-to-one correspondence. The bonding pads 84 and the die connector 64A can be in physical contact after pre-bonding, or can be expanded to physical contact during annealing. In addition, during annealing, the materials (e.g., copper) of the bonding pads 84 and the die connector 64A mix, thereby also forming a metal-to-metal bond. Therefore, the resulting bond between the first integrated circuit die 50A, the bonding layer 82, and the bonding pads 84 includes a dielectric-to-dielectric bond and a metal-to-metal bond.

[0031] exist Figure 3 In the embodiment of the present invention, a buffer layer 106 is deposited over the integrated circuit die 70 and around the first integrated circuit die 50A. The buffer layer 106 is a liner layer on which the upper gap-fill dielectric will be formed. The buffer layer 106 can protect the first integrated circuit die 50A and the integrated circuit die 70 from damage during subsequent processes (such as forming the gap-fill dielectric).

[0032] The buffer layer 106 may be formed of a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, aluminum nitride, gallium nitride, zinc oxide, a combination thereof, etc. The buffer material may be formed by: a sputtering process, such as physical vapor deposition (PVD); a chemical deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.; a spraying process; etc.

[0033] A gap-fill dielectric 108 is then formed on the buffer layer 106. The gap-fill dielectric 108 and the buffer layer 106 are located around and between the first integrated circuit die 50A in the device region 70D above the integrated circuit die 70. Initially, the gap-fill dielectric 108 and the buffer layer 106 may bury or cover the first integrated circuit die 50A such that top surfaces of the gap-fill dielectric 108 and the buffer layer 106 are located above a top surface of the first integrated circuit die 50A.

[0034] The gap-fill dielectric 108 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, aluminum nitride, gallium nitride, zinc oxide, boron nitride, beryllium oxide, combinations thereof, and the like. The gap-fill dielectric 108 may be formed by: a sputtering process such as physical vapor deposition (PVD); a chemical deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like; a spraying process; and the like. The gap-fill dielectric 108 may be formed by depositing the gap-fill dielectric 108 by a spraying process or by a chemical deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In some embodiments, the materials of the buffer layer 106 and the gap-fill dielectric 108 may be selected to have different etching selectivities so that the buffer layer 106 serves as an etching stop layer during a subsequent etching step.

[0035] exist Figure 4 In the process, a removal process is performed to make the top surface of the gap-fill dielectric 108 and the buffer layer 106 flush with the non-active (e.g., backside) surface of the first integrated circuit die 50A. In some embodiments, a planarization process is utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. After the planarization process, the gap-fill dielectric 108, the buffer layer 106, and the surface of the first integrated circuit die 50A (including the semiconductor substrate 52A) are substantially coplanar (within process variations). The conductive via 56A of the first integrated circuit die 50A can remain buried by the semiconductor substrate 52A after the removal process.

[0036] According to some embodiments, the semiconductor substrate 52A is then thinned to expose the conductive via 56A. Portions of the gap-fill dielectric 108 and the buffer layer 106 may also be removed by the thinning process. The thinning process may be, for example, a grinding process, CMP, an etch-back process, a combination thereof, etc., which is performed at the back side of the first integrated circuit die 50A.

[0037] exist Figure 5In the embodiment of the present invention, an etching process is performed to form an opening 110 that exposes some of the bonding pads 84 (such as bonding pads 84 that do not have the first integrated circuit die 50A directly attached). The opening 110 can be formed using any suitable process, such as photolithography and etching. For example, the opening 110 can be formed by etching, milling, laser technology, a combination thereof, etc. The etching process may include one or more isotropic etching and / or anisotropic etching processes. For example, a first etching process can be used to form the opening 110 to expose the buffer layer 106, and a second etching process can be used to extend the opening 110 to expose the bonding pad 84 below.

[0038] As discussed in more detail below, the openings 110 may have various shapes and sizes. For example, some of the openings 110A will be used for active through vias, while other openings 110B will be used for dummy through vias. Thus, the openings 110A and the openings 110B may have the same, similar, or different shapes and the same, similar, or different sizes.

[0039] exist Figure 6 , the opening 110 is filled with a conductive material to form a through via 156A / 158A. The through vias 156A / 158A include active through vias 156A and dummy through vias 158A. The active through via 156A will be electrically connected to other integrated circuits of the die structure (e.g., the integrated circuit die 50 / 70). The dummy through via 158A will be electrically isolated from the integrated circuits of the die structure (e.g., the integrated circuit die 50 / 70 and the active through via 156A). In some embodiments, the dummy through via 158A can be connected to conductive elements on some of the integrated circuit dies 50 / 70 or to some of the integrated circuit dies 50 / 70, however, so that the dummy through via 158A remains electrically isolated from the integrated circuits within those integrated circuit dies 50 / 70. For simplicity, the active through via 156A and the dummy through via 158A can be electrically isolated from the integrated circuits within the die dies 50 / 70. Figure 6 The various layouts shown in the figure are formed with different cross sections. For example, FIG. 17A to FIG. 17K It should be noted that by forming the openings 110 and through vias 156A / 158A at this portion of the process, it is ensured that the buffer layer 106 and gap fill dielectric 108 can be formed without cracks, without seams, and at a higher deposition rate and yield.

[0040] According to some embodiments, a thin barrier layer may be conformally deposited in the opening 110, such as by CVD, ALD, PVD, thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, a nitride, combinations thereof, and the like. A conductive material may be formed over the barrier layer and in the opening 110. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, and the like, or alloys or combinations thereof. Excess conductive material and the barrier layer are removed from the surface of the gap-fill dielectric 108 and the buffer layer 106 by, for example, CMP. The remaining portions of the barrier layer and the conductive material in the opening 110 form through vias 156A / 158A.

[0041] exist Figure 7 In the embodiment of the present invention, the semiconductor substrate 52A is recessed to expose the upper portion of the sidewalls of the conductive via 56A and the through vias 156A / 158A. The recessing can be performed by an etching process, such as dry etching, wet etching, or a combination thereof. After the recessing, the conductive via 56A protrudes from the inactive surface of the semiconductor substrate 52A, and the through vias 156A / 158A protrude from the upper surface of the gap-fill dielectric 108 and the buffer layer 106.

[0042] In addition, a bonding layer 122 is then formed on the back side of the gap-filling dielectric 108, the buffer layer 106, and the first integrated circuit die 50A. The bonding layer 122 is located around the portion of the sidewalls of the conductive via 56A and the through-via 156A / 158A. The bonding layer 122 can bury or cover the conductive via 56A and the through-via 156A / 158A so that the top surface of the bonding layer 122 is located above the surface of the conductive via 56A and the through-via 156A / 158A. The bonding layer 122 will be used for subsequent bonding processes and can help the conductive via 56A and the through-via 156A / 158A to be electrically isolated from each other, thereby avoiding short circuits. The bonding layer 122 is formed by a dielectric material. The dielectric material can be an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, etc., which can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0043] exist Figure 8In the embodiment of the present invention, a bonding pad 124 (e.g., a metal pad) is formed in the bonding layer 122. The bonding layer 122 and the bonding pad 124 may be collectively referred to as a bonding structure 120. The bonding pad 124 is connected to the conductive via 56A and the through-via 156A / 158A. For example, the bonding pad 124 may be formed to have an electrical connection to the active through-via 156A, and may also or may not be formed to have an electrical connection to the pseudo through-via 158A. The bonding pad 124 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The bonding pad 124 may be formed of a conductive material, such as a metal, such as copper, aluminum, etc., which may be formed by, for example, plating, etc. In some embodiments, a planarization process, such as CMP, an etch-back process, a combination thereof, etc., is performed on the bonding pad 124 and the bonding layer 122. After the planarization process, the surfaces of the bonding pad 124 and the bonding layer 122 are substantially coplanar (within process variations).

[0044] exist Fig. 9 , a second integrated circuit die 50B (e.g., a second layer of the top die of the die structure 100) is attached to a first integrated circuit die 50A (e.g., a first layer of the top die of the die structure 100) via a bonding structure 120 (e.g., a bonding layer 122 and a bonding pad 124) such that a front side of the second integrated circuit die 50B faces a back side of the first integrated circuit die 50A. In the illustrated embodiment, one second integrated circuit die 50B is attached over and electrically connected to the first integrated circuit die 50A and some of the through vias 156A / 158A, but any desired number of second integrated circuit dies 50B may be attached over each first integrated circuit die 50A. The second integrated circuit die 50B may be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The second integrated circuit die 50B may be a logic device, such as a CPU, a GPU, a SOC, a microcontroller, or the like.

[0045] As shown, the second integrated circuit die 50B may have connections to some of the active through vias 156A and / or the dummy through vias 158A. In such an embodiment, the second integrated circuit die 50B may be electrically connected to the active through vias 156A. Although the elements of the second integrated circuit die 50B may similarly have electrical connections to the dummy through vias 158A, these elements may also be dummy elements within the second integrated circuit die 50B. Therefore, those dummy through vias 158A remain electrically isolated from the integrated circuits of the second integrated circuit die 50B, and therefore remain electrically isolated from the electrically connected elements of the die structure 100 (e.g., the integrated circuit die 50 / 70 and the active through vias 156A).

[0046] The second integrated circuit die 50B can be attached to the bonding structure 120 (e.g., the bonding layer 122 and the bonding pad 124) by placing the second integrated circuit die 50B on the bonding layer 122 and the bonding pad 124; and then bonding the second integrated circuit die 50B to the first integrated circuit die 50A via the bonding layer 122 and the bonding pad 124. The second integrated circuit die 50B can be placed by, for example, a pick and place process. As an example of a bonding process, the second integrated circuit die 50B can be bonded to the bonding layer 122 and the bonding pad 124 by dielectric to dielectric and metal to metal bonding.

[0047] For example, the dielectric layer 62B of the second integrated circuit die 50B is directly bonded to the bonding layer 122 by dielectric-to-dielectric bonding without using any adhesive material (e.g., a die attach film). The die connector 64B of the second integrated circuit die 50B is directly bonded to the bonding pad 124 by metal-to-metal bonding without using any eutectic material (e.g., solder). The bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the second integrated circuit die 50B against the bonding layer 122. The pre-bonding is performed at low temperatures, such as about room temperature, and after the pre-bonding, the dielectric layer 62B is bonded to the bonding layer 122. The bonding strength is then improved in a subsequent annealing step, in which the bonding layer 122, the bonding pad 124, the dielectric layer 62B, and the die connector 64B are annealed. After annealing, a direct bond, such as a fusion bond, is formed to bond the bonding layer 122 to the dielectric layer 62B. For example, the bonding can be a covalent bonding between the material of the bonding layer 122 and the material of the dielectric layer 62B. The bonding pad 124 is connected to the die connector 64B in a one-to-one correspondence. The bonding pad 124 and the die connector 64B can be in physical contact after pre-bonding, or can be expanded to physical contact during annealing. In addition, during annealing, the materials (e.g., copper) of the bonding pad 124 and the die connector 64B are mixed, thereby also forming a metal-to-metal bond. Therefore, the resulting bonding between the second integrated circuit die 50B, the bonding layer 122 and the bonding pad 124 includes a dielectric-to-dielectric bond and a metal-to-metal bond.

[0048] As shown, the second integrated circuit die 50B includes a conductive via 56B. However, in some embodiments (not specifically shown), the second integrated circuit die 50B may not include the conductive via 56B, and external connections to the die structure 100 may be formed through the integrated circuit die 70. The die structure 100 shown includes three integrated circuit die layers (e.g., the integrated circuit die 70, one or more first integrated circuit dies 50A, and one or more second integrated circuit dies 50B). In embodiments where the conductive via 56B is excluded from the second integrated circuit die 50B, the second integrated circuit die 50B is the upper layer in the die structure 100, and external electrical connections are subsequently formed along the integrated circuit die 70. In other embodiments (not specifically shown), the die structure 100 may include more than three integrated circuit die layers, such as more than two integrated circuit die 50 layers attached to the integrated circuit die 70. Conversely, the die structure 100 may include two integrated circuit die layers, such as one integrated circuit die 50 layer attached to the integrated circuit die 70.

[0049] exist Fig.10, a buffer layer 126 is deposited over the first integrated circuit die 50A and through vias 156A / 158A and around the second integrated circuit die 50B. Buffer layer 126 is a liner layer on which the upper gap-fill dielectric will be formed. Buffer layer 126 can protect the second integrated circuit die 50B and the underlying conductive components from damage when the gap-fill dielectric is subsequently formed. Buffer layer 126 can be formed of one of the candidate materials and formed by one of the candidate methods described above in conjunction with buffer layer 106. Buffer layer 126 can be formed of the same material as buffer layer 106, or can include a different material than buffer layer 106.

[0050] A gap-fill dielectric 128 is then formed on the buffer layer 126. The gap-fill dielectric 128 and the buffer layer 126 are located around and between the second integrated circuit die 50B in the device region 70D. Initially, the gap-fill dielectric 128 and the buffer layer 126 may bury or cover the second integrated circuit die 50B such that the top surfaces of the gap-fill dielectric 128 and the buffer layer 126 are located above the top surface of the second integrated circuit die 50B.

[0051] Gapfill dielectric 128 may be formed of one of the candidate materials and by one of the candidate methods as described above in connection with gapfill dielectric 108. Gapfill dielectric 128 may be formed of the same material as gapfill dielectric 108, or may include a different material than gapfill dielectric 108.

[0052] exist Fig.11 In the process, a removal process is performed to make the top surface of the gap-fill dielectric 128 and the buffer layer 126 flush with the non-active surface of the second integrated circuit die 50B. In some embodiments, a planarization process is used, such as CMP, an etch-back process, a combination thereof, etc. After the planarization process, the gap-fill dielectric 128, the buffer layer 126, and the surface of the second integrated circuit die 50B (including the semiconductor substrate 52B) are substantially coplanar (within process variations). The conductive via 56B of the second integrated circuit die 50B can remain buried by the semiconductor substrate 52B after the removal process.

[0053] exist Fig.12In the embodiment of the present invention, an etching process is performed to form an opening 130 that exposes some of the bonding pads 124 (such as bonding pads 124 that do not have a second integrated circuit die 50B directly attached). The opening 130 can be formed using any suitable process, such as photolithography and etching. For example, the opening 110 can be formed by etching, milling, laser technology, a combination thereof, or the like. The etching process may include one or more isotropic etching and / or anisotropic etching processes. For example, a first etching process can be used to form the opening 130 to expose the buffer layer 126, and a second etching process can be used to extend the opening 130 to expose the bonding pad 124 below.

[0054] As discussed in more detail below, the openings 130 can have various shapes and sizes. For example, some of the openings 130A will be used for active through vias, while other openings 130B will be used for dummy through vias. Thus, the openings 130A and the openings 130B can have the same, similar, or different shapes and the same, similar, or different sizes.

[0055] exist Fig.13 , the opening 130 is filled with a conductive material to form a through via 156B / 158B. The through vias 156B / 158B include active through vias 156B and dummy through vias 158B. The active through via 156B will be electrically connected to other integrated circuits of the die structure (e.g., the integrated circuit die 50 / 70 and the active through via 156A). The dummy through via 158B will be electrically isolated from the integrated circuits of the die structure (e.g., the integrated circuit die 50 / 70 and the active through via 156A). In some embodiments, the dummy through via 158B can be connected to conductive elements on some of the integrated circuit dies 50 / 70 or to some of the integrated circuit dies 50 / 70, however, so that the dummy through via 158B remains electrically isolated from the integrated circuits within those integrated circuit dies 50 / 70. For simplicity, the active through via 156B and the dummy through via 158B can be electrically isolated from the integrated circuits within the die dies 50 / 70. Fig.13 The various layouts shown in the figure are formed with different cross sections. For example, FIG. 17A to FIG. 17K Various other arrangements that may be used for either or both of through vias 156A / 158A and through vias 156B / 158B are shown and described. It should be noted that by forming openings 130 and through vias 156B / 158B at this portion of the process, it is ensured that buffer layer 126 and gap fill dielectric 128 may be formed without cracks, without seams, and at a higher deposition rate and yield.

[0056] According to some embodiments, a thin barrier layer may be conformally deposited in the opening 130, such as by CVD, ALD, PVD, thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, a nitride, combinations thereof, and the like. A conductive material may be formed over the barrier layer and in the opening 130. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, and the like, or alloys or combinations thereof. Excess conductive material and the barrier layer are removed from the surface of the gap-fill dielectric 128 and the buffer layer 126 by, for example, CMP. The remaining portions of the barrier layer and the conductive material in the opening 130 form through vias 156B / 158B.

[0057] exist Fig.14 In the embodiment of the present invention, a redistribution structure 140 is formed over the backside surface of the second integrated circuit die 50B and over the buffer layer 126, the gap-fill dielectric 128, and the through vias 156B / 158B. The redistribution structure 140 includes a dielectric layer 142 and a metallization layer 144 (sometimes referred to as a redistribution layer or redistribution line) embedded in the dielectric layer 142. For example, the redistribution structure 140 may include a plurality of metallization layers 144 separated from each other by respective dielectric layers 142. The metallization layers 144 of the redistribution structure 140 may be electrically coupled to the conductive vias 56B of the second integrated circuit die 50B and electrically coupled to the through vias 156B / 158B (e.g., active through vias 156B). Although shown as not connected to the dummy through vias 158B, in some embodiments, the metallization layers 144 may be connected to the dummy through vias 158B to enhance the heat dissipation benefits.

[0058] In some embodiments, dielectric layer 142 is formed of a polymer, which may be a photosensitive material, such as PBO, polyimide, a BCB-based polymer, etc. In other embodiments, dielectric layer 142 is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. Dielectric layer 142 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After each dielectric layer 142 is formed, it is then patterned to form an opening that exposes the underlying conductive features (such as the underlying conductive via 56B, through vias 156B / 158B, and / or portions of the underlying metallization layer 144). Patterning may be performed by an acceptable process, such as by exposing the dielectric layer to light when the dielectric layer 142 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 142 is a photosensitive material, the dielectric layer 142 may be developed after exposure.

[0059] The metallization layer 144 includes conductive vias and wires. The conductive vias extend through the corresponding dielectric layer 142, and the wires extend along the corresponding dielectric layer 142. As an example of forming the metallization layer 144, a seed layer (not shown separately) is formed above the corresponding underlying conductive component. For example, the seed layer can be formed on the corresponding dielectric layer 142 and in an opening through the corresponding dielectric layer 142. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using a deposition process, such as PVD.

[0060] Then form and pattern a photoresist on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as chemical plating or electroplating from the seed layer. The conductive material can include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, etc. or a combination thereof. Then, remove the portion of the photoresist and the seed layer on which no conductive material is formed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, remove the exposed portion of the seed layer, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms a metallization layer 144 for the redistribution structure 140.

[0061] The illustrated redistribution structure 140 represents a simplified example. More or fewer dielectric layers 142 and metallization layers 144 than shown may be formed in the redistribution structure 140 by performing the previously described steps a desired number of times. In addition, the routing of the metallization layer 144 may electrically connect the conductive vias 56B of the second integrated circuit die 50B to the through vias 156B / 158B (e.g., active through vias 156B).

[0062] exist Fig.15 Optionally, additional features for attaching the die structure 100 to a package component may be formed. In some embodiments, an under bump metal (UBM) 146 is formed for external connection to the redistribution structure 140. In addition, a conductive connector 148 may be formed on the UBM 146. The conductive connector 148 may be used to connect the UBM 146 to a package component, such as an interposer, a package substrate, etc.

[0063] The UBM 146 may be formed to pass through the upper dielectric layer 142 of the redistribution structure 140. The UBM 146 has a bump portion located on and extending along a major surface of the upper dielectric layer 142, and has a via portion extending through the upper dielectric layer 142 to physically and electrically couple the upper metallization layer 144 of the redistribution structure 140. Thus, the UBM 146 is electrically coupled to the conductive via 56B of the second integrated circuit die 50B and to the through vias 156B / 158B. The UBM 146 may be formed of the same material as the metallization layer 144. In some embodiments, the UBM 146 has a different size than the metallization layer 144.

[0064] Conductive connector 148 can be formed on UBM 146. Conductive connector 148 can be ball grid array (BGA) connector, solder ball, metal column, controlled collapse chip connection (C4) bump, micro bump, bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. Conductive connector 148 can include conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or their combination. In some embodiments, conductive connector 148 is formed by initially forming a reflowable material layer (e.g., solder) by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, conductive connector 148 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, which may be formed by a plating process.

[0065] exist Fig.16 In the embodiment shown previously, the die structure 100 includes a first layer of a first integrated circuit die 50A and a second layer of a second integrated circuit die 50B, but any number of layers of integrated circuit dies 50 may be included in the die structure 100.

[0066] It should be noted that the previously described embodiment die structure 100 is a component that can be subsequently implemented in an integrated circuit package. The integrated circuit die 50 of the die structure 100 can be a heterogeneous die. Instead of or in addition to independently packaged integrated circuit dies, the packaged die structure 100 can allow heterogeneous dies to be integrated with a small footprint. In some embodiments, the integrated circuit package is formed by attaching one or more die structures 100 to additional components (such as an interposer, a packaging substrate, etc.). In some embodiments (not specifically shown), the integrated circuit package is formed by sealing the die structure 100 and forming redistribution lines on the encapsulant to fan out connections from the die structure 100.

[0067] refer to Fig.16 , the integrated circuit package 200 includes a die structure 100 (e.g., a first die structure 100A and a second die structure 100B) attached to a wiring structure 202. In the integrated circuit package 200, the die structure 100 includes a conductive connector 148. The first die structure 100A may be different from the second die structure 100B. For example, the first die structure 100A may be a memory device, and the second die structure 100B may be a logic device. The wiring structure 202 may be an interposer, a redistribution structure, etc. In the illustrated embodiment, the die structure 100 is attached to the wiring structure 202 with the conductive connector 148. The conductive connector 148 may be reflowed to attach the UBM of the die structure 100 to the die connector of the wiring structure 202. An underfill (not shown separately) may be formed around the conductive connector 148 and between the wiring structure 202 and the die structure 100. After the die structure 100 is attached to the wiring structure 202, an encapsulant 204 is formed over and around the various components. The encapsulant 204 seals the die structure 100. Subsequently, the wiring structure 202 can be singulated (if necessary) and attached to a package substrate 206.

[0068] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures (e.g., independent integrated circuit die 50 / 70 and / or die structure 100) and final structures (e.g., integrated circuit packages and / or subsequent packaging structures). In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of a known good die to increase yield and reduce costs.

[0069] FIG. 17A to FIG. 17IA plan view (e.g., top view) of an intermediate stage of a die structure 100 according to various embodiments is shown. In particular, various layout styles or schemes are provided for dummy through vias 158A associated with a first integrated circuit die 50A and an active through via 156A, and for dummy through vias 158B associated with a second integrated circuit die 50B and an active through via 156B. The illustrated embodiments may represent some or all layers of the integrated circuit die 50. For example, a first layer (e.g., including the first integrated circuit die 50A) and a second layer (e.g., including the second integrated circuit die 50B) may include the same, similar, or different layout styles.

[0070] 17A to 17C 158 of a particular layer is arranged in a dot pattern or a grid layout. For example, in a plan view, the pseudo through-via 158 may have a shape and size similar to the shape and size of the active through-via 156. In the illustrated embodiment, these shapes may be oval or elliptical (e.g., circular). In other embodiments (not specifically shown), any one or both of the types of through-vias 156 / 158 may have other shapes, such as rectangular (e.g., square), cross, bar, ring, or any suitable shape, including their rounded forms. In addition, the diameter of the pseudo through-via 158 may be smaller than, larger than, or substantially the same as the diameter of the active through-via 156. Pseudo through-vias 158 having a larger diameter will provide increased heat dissipation benefits, wherein pseudo through-vias 158 having a smaller diameter will allow a greater density of active components (such as active through-vias 156 and integrated circuit die 50).

[0071] refer to Fig.17A , the active through vias 156 can be close to the integrated circuit die 50 to facilitate connections between them and with components above or below (e.g., other integrated circuit dies 50 / 70). This layout is advantageous when components that carry or generate higher heat are located along the edge of the electrically connected component group (e.g., the integrated circuit die 50 and the active through vias 156). Therefore, those components are close to the dummy through vias 158, which can provide sufficient heat dissipation.

[0072] refer to Fig. 17B, the active through vias 156 and the pseudo through vias 158 can be interspersed with each other (e.g., an alternating grid layout). This layout is beneficial for ensuring that each electrically connected component is close to some of the pseudo through vias 158. Therefore, the pseudo through vias 158 are able to dissipate heat from all such components that may be located in the interior area of ​​a particular layer. In addition, these benefits are achieved without designing the layout so that components that carry or generate higher heat are located along the edges of the electrically connected component groups (e.g., the integrated circuit die 50 and the active through vias 156). Although the pseudo through vias 158 and the active through vias 156 are shown in an alternating scheme, it should be understood that they can be arranged in alternating clusters or in an irregular pattern.

[0073] refer to Fig. 17C , the dummy through vias 158 can be formed in a frame or perimeter (e.g., a discontinuous frame or ring) around the electrical connection elements (e.g., the integrated circuit die 50 and the active through vias 156). This layout achieves a combination of Fig.17A Similar benefits of the described embodiments. In addition, the frame layout ensures that heat from the electrical connection elements has less impact on or dissipates into any adjacent package components, and vice versa.

[0074] FIG. 17D to FIG. 17I Indicates that some or all of the pseudo through vias 158 of a specific layer have a rod shape or a strip shape (see Fig.17D and Fig.17E ), continuous frame shape (see Fig.17F and Figure 17G ) and / or bracket shapes (see Fig.17H and Fig.17I ) embodiment. For example, in plan view, each of these dummy through vias 158 may have a larger footprint than each of the active through vias 156. It should be noted that the dummy through vias 158 may include any combination of such designs, while also including some of the dummy through vias 158 in the dashed line layout described above.

[0075] refer to Fig.17D , some of the dummy through vias 158 may have a rod shape and be positioned on an outer region of a particular layer. It should be noted that the rod shape of the dummy through vias 158 may be formed in conjunction with any of the above or subsequently described layouts. In some embodiments, the active through vias 156 may be positioned in an inner region of a particular layer (e.g., close to the integrated circuit die 50) to facilitate connections between them and with components above or below (e.g., other integrated circuit dies 50 / 70). This layout achieves similar benefits as described above (e.g., Fig.17A and Fig. 17C), while also improving heat dissipation and occupying less space, thereby allowing more available space for electrically connected components (e.g., integrated circuit die 50 and active through vias 156).

[0076] refer to Fig.17E , some of the dummy through vias 158 may have a bar shape and may be interspersed (eg, alternating) or dispersed relative to the active through vias 156. This layout achieves similar benefits as described above (eg, Fig. 17B and Fig.17D ), such as providing thorough heat dissipation from electrically connected elements (eg, integrated circuit die 50 and active through vias 156) in its various designs and layouts.

[0077] refer to Fig.17F , the dummy through via 158 can be or include a continuous frame or perimeter (e.g., a continuous ring) around the electrical connection elements (e.g., the integrated circuit die 50 and the active through via 156). This layout achieves similar benefits as described above (e.g., Fig.17A , Fig. 17C and Fig.17D ).

[0078] exist Figure 17G In the embodiment of the present invention, the dummy through via 158 can be or include a continuous frame or perimeter (e.g., a continuous ring) around the integrated circuit die 50. For example, the continuous frame of the dummy through via 158 can be close to the integrated circuit die 50 and located within the active through via 156. This layout achieves similar benefits as described above (e.g., Fig. 17B and Fig.17E ), such as providing heat dissipation for components that carry or generate some of the greatest heat (e.g., integrated circuit die 50).

[0079] As discussed above, combinations of the above described arrangements may be utilized. Fig.17H and Fig.17I In FIG. 5 , the dummy through via 158 may include brackets around the integrated circuit die 50 , the active through via 156 , and other dummy through vias 158 . Fig.17H shows a long bracket layout, and Fig.17I A short bracket layout is shown. Fig.17H and Fig.17I The brackets can also be called open frame layout. In addition, Fig.17J and Figure 17K It is shown that by forming segments around the perimeter of a particular layer, for example, Fig. 17C and Fig.17F Examples of various aspects of the embodiments of the present invention. For example, Fig.17J The rod shape arranged in the frame is shown, and Figure 17KCorner segments arranged in a frame are shown. Thus, the components of the frame are discontinuous with each other. These layouts achieve the various benefits described above, and in particular, the discontinuity provides greater flexibility and robustness during high physical and / or thermal stress processes.

[0080] Various advantages are achieved. In particular, the disclosed embodiments provide a layout of pseudo through-vias 158 associated with the integrated circuit die 50 and the active through-vias 156 to improve heat dissipation in a variety of ways. The pseudo through-vias 158 can be formed simultaneously with the active through-vias 156, which ensures that no additional processing steps (or fewer additional process steps) are included to form the pseudo through-vias 158. The pseudo through-vias 158 can have a shape similar to the active through-vias. In addition, the pseudo through-vias 158 can include a rod shape for improving heat dissipation in proportion to the amount of spacing used by the pseudo through-vias 158. In addition, the pseudo through-vias 158 can include a frame shape (e.g., a continuous annular shape) for additional heat dissipation benefits. Combinations of these can be utilized within a single layer of the die structure 100 or between different layers. In addition, the pseudo through-vias 158 can be formed as conductive elements for uniform density, which reduces the effects of thermal expansion such as wafer warpage.

[0081] In an embodiment, a method includes: forming a first bonding pad along a wafer; bonding a first die to a first group of first bonding pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming an opening in the gap-fill dielectric to expose a second group of first bonding pads and a third group of first bonding pads; forming a first active through-via in physical contact with the second group of first bonding pads and a first dummy through-via in physical contact with the third group of first bonding pads, the first active through-via being electrically connected to the wafer, the first dummy through-via being electrically isolated from the wafer; forming a second bonding pad along a back side of the first die, an upper surface of the first active through-via, and an upper surface of the first dummy through-via; and bonding the second die to the first die and the first active through-via of the first active through-via. In another embodiment, the second die is bonded to the first dummy through-via of the first dummy through-via. In another embodiment, the integrated circuit of the second die is electrically isolated from the first dummy through-via of the first dummy through-via. In another embodiment, in plan view, the first active through via and the first pseudo through via have an alternating grid layout. In another embodiment, in plan view, the first pseudo through via is arranged in a frame around the first tube core and the first active through via. In another embodiment, the first pseudo through via includes a continuous ring around the first tube core and the first active through via. In another embodiment, the method also includes: depositing an additional gap filling dielectric above the gap filling dielectric and around the second tube core; forming an additional opening in the additional gap filling dielectric to expose some of the second bonding pads; and forming an additional through via in the additional opening. In another embodiment, the additional through via includes a second active through via electrically connected to the second active through via of the first active through via, and wherein the additional through via includes a second pseudo through via electrically connected to the second pseudo through via of the first pseudo through via.

[0082] In an embodiment, a semiconductor device includes: a first top die bonded to a bottom die, a first bonding pad electrically connecting the first top die to the bottom die; a first active through-via located above the bottom die, a second bonding pad electrically connecting the first active through-via to the bottom die; a first dummy through-via located above the bottom die, the first dummy through-via being in physical contact with a third bonding pad; and a dielectric layer sealing the first top die, the first active through-via, and the first dummy through-via. In another embodiment, the semiconductor device further includes: a second top die bonded to the first top die, a fourth bonding pad electrically connecting the second top die to the first top die, a fifth bonding pad electrically connecting the second top die to the first active through-via; a redistribution structure located above the second top die; a second active through-via and a second dummy through-via sealed in the dielectric layer; a third active through-via located above the second active through-via and electrically connected to the second active through-via; and a third dummy through-via located above the second dummy through-via and electrically connected to the second dummy through-via. In another embodiment, in plan view, the first pseudo through via is circular and the second pseudo through via is rod-shaped. In another embodiment, in plan view, the third pseudo through via is rod-shaped. In another embodiment, in plan view, the third pseudo through via is circular. In another embodiment, the sixth bonding pad electrically connects the second top die to the first pseudo through via, and wherein the first pseudo through via is electrically isolated from the integrated circuit of the second top die.

[0083] In an embodiment, a semiconductor device includes: a first die level, the first die level includes a first die; a second die level, the second die level includes: a second die; a first active through-via; and a first dummy through-via, in a first plan view, the first dummy through-via includes a discontinuous frame around the second die; and a first bonding structure, between the first die level and the second die level, the first bonding structure electrically connects the first die to the second die, the first bonding structure electrically connects the first die to the first active through-via. In another embodiment, the semiconductor device also includes: a third die level, the third die level includes: a third die; a second active through-via; and a second dummy through-via, in a second plan view, the second dummy through-via includes a continuous frame around the third die; and a second bonding layer, between the second die level and the third die level, the second bonding layer electrically connects the second die to the first die. In another embodiment, the second bonding layer electrically connects the third die to the first active through-via of the first active through-via, and wherein the second bonding layer electrically connects the third die to the first pseudo through-via of the first pseudo through-via. In another embodiment, the second bonding layer electrically connects the second active through-via of the first active through-via to the second active through-via. In another embodiment, the second bonding layer electrically connects the second pseudo through-via of the first pseudo through-via to the second pseudo through-via, and wherein the first pseudo through-via and the second pseudo through-via are electrically isolated from the integrated circuits of the first die, the second die, and the third die. In another embodiment, in the first plan view, the first pseudo through-via includes a circular shape and a rod shape.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a first bonding pad along the wafer; bonding a first die to a first set of the first bonding pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming openings in the gap-fill dielectric to expose a second group of the first bonding pads and a third group of the first bonding pads; forming a first active through via in physical contact with the second group of the first bonding pads and a first dummy through via in physical contact with the third group of the first bonding pads, the first active through via being electrically connected to the wafer, and the first dummy through via being electrically isolated from the wafer; forming a second bonding pad along a back side of the first die, an upper surface of the first active through via, and an upper surface of the first dummy through via; as well as A second die is bonded to the first die and to a first active via of the first active through via.

2. The method according to claim 1, wherein: The second die is bonded to a first dummy via of the first dummy through via.

3. The method according to claim 2, wherein: The integrated circuit of the second die is electrically isolated from the first dummy via of the first dummy through via.

4. The method according to claim 1, wherein: In a plan view, the first active through vias and the first dummy through vias have an alternating grid layout.

5. The method according to claim 1, wherein: In a plan view, the first dummy through via is arranged in a frame around the first die and the first active through via.

6. The method according to claim 5, wherein: The first dummy through via includes a continuous ring around the first die and the first active through via.

7. The method according to claim 1, further comprising: depositing additional gapfill dielectric over the gapfill dielectric and around the second die; forming additional openings in the additional gap-fill dielectric to expose some of the second bond pads; as well as An additional through via is formed in the additional opening.

8. The method according to claim 7, wherein: The additional through via includes a second active through via electrically connected to a second active through via of the first active through via, and wherein the additional through via includes a second dummy through via electrically connected to a second dummy through via of the first dummy through via.

9. A semiconductor device comprising: a first top die bonded to the bottom die, a first bonding pad electrically connecting the first top die to the bottom die; a first active through via located above the bottom die, a second bonding pad electrically connecting the first active through via to the bottom die; a first dummy through via located above the bottom die, the first dummy through via being in physical contact with a third bonding pad; as well as A dielectric layer seals the first top die, the first active through via, and the first dummy through via.

10. A semiconductor device comprising: a first die level, the first die level comprising a first die; A second die level, the second die level comprising: A second tube core; a first active through via; and a first dummy through via, the first dummy through via comprising a discontinuous frame around the second die in a first plan view; and A first bonding structure is disposed between the first die level and the second die level, the first bonding structure electrically connecting the first die to the second die, and the first bonding structure electrically connecting the first die to the first active through via.

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