Semiconductor device and method of forming semiconductor package

Abstract

In an embodiment, a method includes forming a device region along a first substrate; forming an interconnection structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, the forming the metal pillar including: forming a substrate layer over the interconnect structure; forming an intermediate layer over the substrate layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etching process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region. Embodiments of the present disclosure provide a semiconductor device and a method of forming a semiconductor package.

Description

Technical Field

[0001] Embodiments of the present disclosure provide semiconductor devices and methods of forming semiconductor packages. Background Art

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvements in integration density are due to repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the need for smaller and more creative packaging technologies for semiconductor dies has emerged. Summary of the invention

[0003] An embodiment of the present disclosure provides a method for forming a semiconductor package, comprising: forming a device region along a first substrate; forming an interconnect structure above the device region and the first substrate; forming a metal column above the interconnect structure, wherein forming the metal column comprises: forming a base layer above the interconnect structure; forming an intermediate layer above the base layer; and forming a covering layer above the intermediate layer; forming a solder region above the covering layer; and performing an etching process to make the side walls of the base layer and the covering layer recessed from the side walls of the intermediate layer and the solder region.

[0004] Another embodiment of the present disclosure provides a method for forming a semiconductor package, the method comprising: forming a first integrated circuit over a first substrate; forming a patterned plating mask over the first integrated circuit, the patterned plating mask comprising an opening; forming a first connector structure, the forming of the first connector structure comprising: forming a base layer in the corresponding opening; forming an intermediate layer over the corresponding base layer, the intermediate layer comprising nickel; forming a covering layer over the corresponding intermediate layer, the covering layer being nickel-free; and forming a first solder region over the corresponding covering layer, the first solder region being nickel-free; removing the patterned plating mask; performing an etching process using an etchant that is selective to the materials of the base layer and the covering layer; depositing a polymer material over and between the first connector structure; planarizing the polymer material so that the polymer material is flush with the upper surface of the first solder region; and depositing a non-conductive film over the polymer material.

[0005] Yet another embodiment of the present disclosure provides a semiconductor device, comprising: a first interconnect structure located above a first substrate; a first metal pillar located above the first interconnect structure, the first metal pillar comprising: a first base layer located above the first interconnect structure, the first base layer having a first lateral width; a first intermediate layer located above the first base layer, the first intermediate layer having a second lateral width, the second lateral width being greater than the first lateral width; and a first covering layer located above the first intermediate layer, the first covering layer having the first lateral width; a solder region located above the first covering layer and around a sidewall of the first covering layer; a second metal pillar located above the solder region, the second metal pillar comprising: a second covering layer, the solder region being around a sidewall of the second covering layer, the second covering layer having a third lateral width; a second intermediate layer located above the second covering layer, the second intermediate layer having a fourth lateral width, the fourth lateral width being greater than the third lateral width; and a second base layer located above the second intermediate layer, the second base layer having the third lateral width; and a second interconnect structure located above the second metal pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 10 Intermediate stages in the formation of a package assembly in accordance with some embodiments are shown.

[0008] Figures 11 to 18B An intermediate stage in the bonding of package components to form a semiconductor package is shown in accordance with some embodiments.

[0009] Figures 19 to 21 An intermediate stage in processing a semiconductor package is shown in accordance with some embodiments.

[0010] FIG. 22A to FIG. 22C A processed semiconductor package according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] In a system on integrated circuit (SoIC) device, integrated circuit devices (also referred to as dies or chips) are attached together to form a single system device package. Such a SoIC device can be formed by, for example, bonding the die to a wafer in a chip on wafer (CoW) bonding process, and then later dividing the wafer to form a SoIC device. One way to perform such bonding is to form a solder connector (e.g., a solder area) extending between two metal connectors (e.g., metal pillars, one on the die and one on the wafer). The solder area and the metal pillars can be collectively referred to as connector structures. As the size of the connector structures and the pitches between them become smaller to achieve greater connection density to match the device density, the risk of connector failure is greater. For example, a common failure is the formation of voids (e.g., Kirkendall voids) in and around the merged solder area. As the solder regions reflow to join two connector structures together, the merged solder regions can squeeze up and down along the metal pillars, which can create larger areas through which elements (e.g., copper, tin, etc.) can diffuse, resulting in voids, potentially leading to device failure, unreliability, or disconnection. In addition to the joining process, this phenomenon can be caused by functional use and / or storage of the semiconductor device. Additionally, certain types of stress testing of semiconductor devices can simulate these conditions at a faster rate to adequately reproduce the phenomenon.

[0014] Embodiments disclosed herein improve the bonding of package components in the manufacture of semiconductor devices (such as semiconductor packages). In particular, the metal pillars of the connector structure are designed to include an intermediate layer that reduces the diffusion of the merged solder area up and down along the metal pillar. After bonding the package components and performing subsequent processing, the semiconductor device can be subjected to the above-mentioned stress test to show that voids are prevented in and around the bonded connector structure.

[0015] Figure 1 1 is a cross-sectional view of a wafer 100 having a die area 105 defined therein. In subsequent processes, the die area 105 may be divided into a plurality of integrated circuit dies. The type of die formed in each die area 105 is not limited. For example, the die area 105 may be divided into logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system on chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), etc. or a combination thereof.

[0016] The formation of the integrated circuit die in each die region 105 can be completed according to an applicable manufacturing process to form an integrated circuit. For example, the die formed in the die region 105 includes a semiconductor substrate 110, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 110 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 110 has an active surface (e.g., Figure 1 The upward-facing surface (sometimes called the front side) and the passive surface (e.g. Figure 1 The median downward-facing surface) (sometimes called the posterior side).

[0017] Devices are disposed at an active surface of the semiconductor substrate 110 in a device region 115. The device region 115 may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. For example, the device region 115 may include a transistor including a gate structure and source / drain regions, wherein the gate structure is located on a channel region and the source / drain regions are adjacent to the channel region.

[0018] The interconnect structure 120 is disposed above the active surface of the semiconductor substrate 110. The interconnect structure 120 includes one or more dielectric layers (such as an interlayer dielectric (ILD) or an intermetallic dielectric (IMD)) and one or more metallization patterns disposed therein. Conductive vias can be used to connect the device region 115 to the metallization pattern and to connect the metallization patterns to each other. The dielectric layer can be formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The conductive vias can extend through the dielectric layer to electrically and physically couple the contacts of the device in the device region 115. In some embodiments, the dielectric layer can be a low-k dielectric layer. The metallization pattern and the via can be formed in the dielectric layer by a damascene process, such as a single damascene process, a dual damascene process, etc. The metallization patterns and conductive vias may be formed of suitable conductive materials, such as copper, tungsten, aluminum, silver, gold, combinations thereof, and the like.

[0019] The passivation layer 122 is disposed on the interconnect structure 120. The passivation layer 122 may include one or more layers and is formed of one or more suitable dielectric materials, such as silicon oxynitride, silicon nitride, low-k dielectrics (such as carbon-doped oxides), ultra-low-k dielectrics (such as porous carbon-doped silicon oxides), polymers (such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB)-based polymers, molding compounds, etc.), or combinations thereof. The passivation layer 122 may be formed by chemical vapor deposition (CVD), spin coating, lamination, etc., or combinations thereof. In some embodiments, the passivation layer 122 includes a silicon oxynitride layer or a silicon nitride layer.

[0020] Figures 2 to 9 yes Figure 1 FIG. 1 is an enlarged view of the dashed box F2 in FIG. 1 and illustrates a process of forming a connector on the die area 105 according to an embodiment.

[0021] exist Figure 2, forming an opening in the passivation layer 122. The passivation layer 122 may be patterned using acceptable photolithography and etching techniques to form an opening that exposes a conductive element electrically coupled to the interconnect structure 120. For example, a photomask may be formed over the passivation layer 122 by spin coating or other deposition, the photomask exposed to a light pattern, and the photomask developed to form a pattern therein. The passivation layer 122 may be patterned by transferring the photomask pattern to the passivation layer 122 by an etching technique to form an opening. The photomask may then be removed using any acceptable technique, such as an ashing technique.

[0022] exist FIG. 3A to FIG. 3D In the embodiment of the present invention, a metal pillar 124 (e.g., under bump metal (UBM)) is formed in the opening of the passivation layer 122. According to some embodiments of the present disclosure, the metal pillar 124 is formed to contact the metallization of the interconnect structure 120. According to some embodiments (not specifically shown), additional conductive lines and dielectric layers can be formed above the interconnect structure 120 below the metal pillar 124. For example, a metal pad can be formed above the interconnect structure 120, and the metal pillar 124 can be formed above the metal pad.

[0023] refer to Figure 3A , as an example of forming a metal pillar 124, a seed layer 124A may be deposited over the passivation layer 122. The seed layer 124A may include a multilayer structure (not shown separately), and may include a first layer of a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, etc., and a second upper layer of copper or a copper alloy. The seed layer 124A may be a single layer, for example, a copper layer. The seed layer 124A may be formed using physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc., but other applicable methods may also be used. The seed layer 124A is a conformal layer that extends into the opening of the passivation layer 122 and contacts the metal component exposed by the opening.

[0024] A plating mask 126 is then formed over the seed layer 124A, and the plating mask 126 is patterned to form openings corresponding to the metal pillars 124. The plating mask 126 may be formed of a photoresist by spin coating, and patterned using an acceptable photolithography technique. The openings in the plating mask 126 expose portions of the seed layer 124A in the openings of the passivation layer 122. The patterning of the plating mask 126 may include an exposure process and a development process.

[0025] According to various embodiments, multiple plating processes are performed to form a column portion of the metal column 124 above the seed layer 124A. The column portion includes multiple non-solder metal layers. For example, the column portion may include a base layer 124B, one or more intermediate layers 124C, and a covering layer 124D. The base layer 124B may be a copper-containing layer, such as copper or a copper alloy. The intermediate layer 124C may include a nickel-containing layer, an iron-cobalt layer, a palladium-containing layer, a gold layer, etc. and / or a combination thereof. The covering layer 124D may be a copper-containing layer, such as copper or a copper alloy. In some embodiments (not specifically shown), the covering layer 124D may also include a topmost protective layer, which may include nickel, palladium, gold, etc.

[0026] refer to Figure 3B , base layer 124B is a copper-containing (e.g., substantially copper) layer and is formed by electroplating, chemical plating, or any suitable method. Base layer 124B may be formed over the exposed surface of seed layer 124A in the opening in plating mask 126. For example, base layer 124B may be formed to a thickness T1 in a range from 1 μm to 2 μm.

[0027] refer to Figure 3C , then an intermediate layer 124C may be formed over the base layer 124B by electroplating, chemical plating, or any suitable method. The intermediate layer 124C may be a single layer or multiple layers (e.g., a double layer) including nickel, iron, cobalt, or a combination thereof. In some embodiments, the intermediate layer 124C may be a single nickel-containing layer. For example, the intermediate layer 124C may be formed to have a thickness T2 in a range from 1 μm to 2 μm. In other embodiments, the intermediate layer 124C may be a double layer including the above materials, such as a nickel-containing layer and an iron-cobalt-containing layer (see FIG. 14A to FIG. 14C In such an embodiment, the double-layered intermediate layer 124C may also be formed to have a total thickness T2 ranging from 1 μm to 2 μm (eg, 0.5 μm to 1 μm per layer).

[0028] refer to Figure 3D , a capping layer 124D may be formed over the intermediate layer 124C by electroplating, chemical plating, or any suitable method. In some embodiments, the capping layer 124D is another copper-containing (eg, substantially copper) layer. For example, the capping layer 124D may be formed to a thickness T3 in a range from 1 μm to 2 μm.

[0029] Note that the seed layer 124A, the base layer 124B, the intermediate layer, and the capping layer 124D may be collectively referred to as a "metal pillar" or "UBM" (e.g., components of the metal pillar 124). In addition, the base layer 124B, the intermediate layer, and the capping layer 124D may be collectively referred to as a "pillar" or "metal pillar" of the UBM. However, the seed layer 124A alone may be referred to as a "UBM", while the other layers (e.g., the base layer 124B, the intermediate layer 124C, and the capping layer 124D) are referred to as "pillars" or "metal pillars".

[0030] exist Figure 4 In the embodiment, the plating mask 126 is retained to form a solder region 128 on the top of the metal pillar 124, which can be formed by a plating process (e.g., electroplating, chemical plating, etc.). The solder region 128 can be formed of a eutectic material, such as Sn-Ag-In alloy, Cu-Sn alloy (e.g., Cu3Sn, Cu6Sn5, etc.), Sn-Ag alloy, Sn-Ag-Cu alloy, etc., and can be lead-free. Alternatively, the solder region 128 can be formed by a printing process of depositing solder paste on the metal pillar 124. In such an embodiment, the plating mask 126 can be used as a printing mask, and the solder paste can be wiped on the plating mask 126 in the opening. The solder paste can then be reflowed to form the solder region 128. For example, the solder region 128 can be formed to a thickness T4 in the range from 3μm to 5μm, such as 3.5μm to 4.5μm.

[0031] exist Figure 5 , after the solder regions 128 are plated, the plating mask 126 is removed, and one or more etching processes are performed to remove the exposed portions of the seed layer 124A and recess the sidewalls of the copper layer of the metal pillars 124. For example, the plating mask 126 may be removed by a stripping process, such as by an ashing process. Removing the plating mask 126 exposes and exposes portions of the seed layer 124A between the metal pillars 124.

[0032] In some embodiments, the exposed portion of the seed layer 124A and the sidewalls of the copper layer of the metal pillar 124 are etched simultaneously. The exposed portion of the seed layer 124A includes those portions previously covered by the plating mask 126. As discussed above, the copper layer of the metal pillar 124 may include a base layer 124B and a capping layer 124D. For example, an etchant selective to copper compared to other materials in the metal pillar 124 (e.g., nickel, iron cobalt, etc.) and the solder region 128 (e.g., Cu-Sn alloy) may be used to etch the seed layer 124A, the base layer 124B, and the capping layer 124D. The portion of the seed layer 124A covered by the metal pillar 124 remains substantially unremoved. However, the portion of the seed layer 124A exposed during the etching of the base layer 124B may also be removed. Throughout the description, the remaining portion of the seed layer 124A is considered to be an integral part of the metal pillar 124. Note that for simplicity, some subsequent figures may not specifically show these remaining portions of the seed layer 124A. The resulting connector structure 130 includes the metal pillar 124 and the solder region 128.

[0033] As shown, the material of the intermediate layer 124C (e.g., nickel, iron cobalt, etc.) and the solder region 128 (e.g., Cu-Sn alloy) can remain substantially unetched. As a result, after performing the etching process, the sidewalls of the base layer 124B and the cover layer 124D are recessed from the sidewalls of the intermediate layer 124C and the solder region 128. In some embodiments, the metal pillars 124 and the solder region 128 can be initially deposited with a width W1 in the range of from 6 μm to 7 μm. After the etching process, the base layer 124B and the cover layer 124D can be recessed by a distance in the range of from 0.5 μm to 1 μm, so that those layers have a width W2 in the range of from 5 μm to 6 μm.

[0034] Embodiments may utilize narrow pitch groups. For purposes of this disclosure, a narrow pitch group is considered to be a pitch P1 between adjacent metal pillars 124 that is less than or equal to 10 μm, such as between 5 μm and 10 μm. In some embodiments, a wider pitch group may also utilize this embodiment. A wider pitch group may include a pitch P1 greater than 10 μm, such as between about 15 μm and 200 μm. In the narrow pitch group, the width W1 / W2 of the connector structure 130 (e.g., the metal pillar 124 and the solder region 128) may be between about 0.5 μm and about 8 μm, and the spacing S1 between the connector structures 30 may be between about 3 μm and about 9 μm.

[0035] exist Figure 6In the embodiment of the present invention, a filling film 132 is deposited over and between the connector structures 130 (e.g., the metal pillars 124 and the solder regions 128). The filling film 132 may be any suitable insulating film, such as a polymer, such as a polyimide, a solder resist, a polybenzoxazole (PBO), a benzocyclobutene (BCB)-based polymer, or a molding compound. The filling film 132 may be deposited using any suitable process, such as by CVD, spin coating, lamination, etc., or a combination thereof.

[0036] exist Figure 7 In the process, a planarization process is performed to make the upper surface of the filling film 132 flush with the upper surface of the solder region 128 of the connector structure 130 to form a filling structure 134. The planarization process may include a mechanical grinding or polishing process, or may include a chemical mechanical polishing (CMP) process.

[0037] exist Figure 8 In the embodiment of the present invention, an optional reflow process may be performed on the solder region 128. The reflow process may be performed to melt the solder region 128 and form the solder region 128 into a dome or round shape. When the solder region 128 is reflowed, the upper surface of the solder region 128 may be pulled apart at the edge of the filling structure 134 and recessed below the upper surface of the filling structure 134, and the vertex of the dome shape of the solder region 128 may protrude above the upper surface of the filling film 132. Therefore, the side walls of the filling film 132 may be exposed from the solder region 128 at their uppermost portions. The optional reflow process may be a convection reflow process, a laser reflow process, or the like.

[0038] exist Fig. 9 In the embodiment of the present invention, a non-conductive film (NCF) 136 is deposited over the filling film 132 and the solder area 128. The NCF 136 will help couple the solder area 128 to the corresponding solder area of ​​the package component. For example, the NCF 136 may contain a flux to improve or promote solder reflow and deoxidation. The NCF 136 may be any suitable material component. In some embodiments, the NCF 136 may be a coating adhesive with a flux or an epoxy resin with a filler and a flux. The NCF 136 may be a compressible film and may be formed by any suitable process, such as by lamination, spin coating, spraying, jetting, dipping, etc., and may be formed to a thickness between about 5 μm and about 10 μm.

[0039] exist Fig.10 In the process of separating the wafer 100, the separation process may include a die sawing process, an etching process, a laser cutting process, etc., or a combination thereof. The separation process is performed along the scribe lines (not specifically shown) between the die regions 105. The separated components may be referred to as package components 150 (see Fig.11 ), the packaging component 150 can be a device die, a packaging substrate, an interposer, a packaging part, etc.

[0040] exist Fig.11 In the present invention, a package assembly 200 is provided, which can be an interposer, a package substrate, a package, a device die, a printed circuit board, etc. The package assembly 200 includes a substrate 210 and a connector structure 230 protruding from the substrate 210. The connector structure 230 is arranged to have the same pitch as the connector structure 130 of the package assembly 150. In some embodiments, the substrate 210 may include a passivation layer (not specifically shown) including an opening through which the connector structure 230 can extend, similar to the above description in conjunction with the connector structure 130 and the passivation layer 122.

[0041] The connector structures 230 can be formed similarly to those described above in connection with the connector structures 130, although there are certain differences discussed below. For example, each connector structure 230 can include a metal pillar 224 and a solder region 228. In addition, the metal pillars 224 can include a seed layer 224A (not specifically shown), a base layer 224B, one or more intermediate layers 224C, and a capping layer 224D. In addition, the metal pillars 224 (including individual components) can be formed in a manner similar to that described above in connection with the metal pillars 124, and the solder regions 228 can be formed in a manner similar to that described above in connection with the solder regions 128.

[0042] In accordance with some embodiments, base layer 224B may include any material described in conjunction with base layer 124B (e.g., copper), intermediate layer 224C may include any material described in conjunction with intermediate layer 124C (e.g., nickel or iron cobalt), and covering layer 224D may include any material described in conjunction with covering layer 124D (e.g., copper).

[0043] It should be understood that in some embodiments, various components of the connector structure 230 of the package assembly 200 can be formed to have different dimensions than similar components of the connector structure 130 of the package assembly 150. In particular, the base layer 224B can be formed to have a thickness T5 in the range of 2 μm to 3 μm, the intermediate layer 224C can be formed to have a thickness T6 in the range of 1 μm to 2 μm, and the cover layer 224D can be formed to have a thickness T7 in the range of 3 μm to 4 μm. In addition, the solder region 228 can be formed to have a thickness T8 in the range of 2 μm to 3 μm.

[0044] After forming the metal pillar 224 and the solder region 228, an etching process may be performed to remove the exposed portion of the seed layer 224A and to recess the sidewall portion of the metal pillar 224, similar to that described in conjunction with the metal pillar 124 (see Figure 5). For example, the seed layer 224A, the base layer 224B (e.g., copper), and the capping layer 224D (e.g., copper) may be etched using an etchant that is selective for copper compared to other materials in the metal pillars 224 (e.g., nickel, iron cobalt, etc.) and solder regions 228 (e.g., Cu-Sn alloy). The portion of the seed layer 224A covered by the base layer 224B remains substantially unremoved. However, portions of the seed layer 224A exposed during etching of the base layer 224B may also be removed.

[0045] As shown, the material of the intermediate layer 224C (e.g., nickel, iron cobalt, etc.) and the solder region 228 (e.g., Cu-Sn alloy) can remain substantially unetched. As a result, after performing the etching process, the sidewalls of the base layer 224B and the cover layer 224D are recessed from the sidewalls of the intermediate layer 224C and the solder region 228. In some embodiments, the metal pillar 224 and the solder region 228 can be initially deposited with a width W3 in the range of from 4 μm to 5 μm. After the etching process, the base layer 224B and the cover layer 224D can be recessed by a distance in the range of from 0.5 μm to 1 μm, so that those layers have a width W4 in the range of from 3 μm to 4 μm.

[0046] In some embodiments, connector structure 230 may protrude between about 4 μm and 12 μm from substrate 210. Width W3 of connector structure 230 may be between about 0.2 μm and 1 μm less than width W1 of connector structure 130. In other embodiments (not specifically shown), width W3 of connector structure 230 may be substantially the same as width W1 or greater than width W1. Connector structure 230 may be coupled to a conductive component (not specifically shown) embedded in substrate 210, but may include an interconnect structure similar to interconnect structure 120, a device region similar to device region 115, or other conductive components. In some embodiments, substrate 210 may be a wafer having a plurality of device regions 205 disposed therein, which may be segmented in a subsequent segmentation process. Substrate 210 may include any of the candidate materials discussed above for substrate 110.

[0047] Still refer to Fig.11 , the connector structure 130 of the package assembly 150 is aligned with the selected connector structure 230. The alignment can be achieved by a pick and place process. Although one package assembly 150 is shown, it should be understood that additional package assemblies including additional package assemblies 150 may be used. FIG. 12A to FIG. 12B The dotted box F12 is provided in an enlarged view.

[0048] exist Fig. 12A and Fig. 12B In the process, the packaging component 150 is brought onto the packaging component 200 and pressed into the packaging component 200 . Fig. 12AThe package assembly 150 is shown aligned with the package assembly 200, and Fig. 12B The package components 150 / 200 are shown bonded to each other. When the package component 150 is pressed onto the package component 200, the connector structure 230 of the package component 200 penetrates the NCF 136 to contact the solder area 128 of the package component 150. When the connector structure 230 of the package component 200 penetrates the NCF 136, the NCF 136 surrounds and contacts the sidewalls of the metal pillar 224. Fig.13A and Fig. 13B After bonding, connector structure 130 and connector structure 230 may be collectively referred to as a bonded connector structure 330 .

[0049] exist FIG. 13A to FIG. 13C In the embodiment, the connector structure 130 / 230 / 330 is provided before the connection (see Fig. 12A and Fig.13A ), during or after engagement (see Fig. 13B ) and after testing, storage and / or use (see Fig. 12B and Fig. 13C ). As shown, the metal pillars 224 are brought to the surface of the solder region 128 and are surrounded by the NCF 136. Because the NCF 136 can be a compressible film, the NCF 136 can fill the space between the metal pillars 224 and can contact the surface of the package component 200.

[0050] In some embodiments, during bonding, due to the difference in the respective widths W1 / W3, the solder region 128 may partially surround the solder region 228. In addition, the solder region 128 may merge with the solder region 228 such that the boundary between them becomes indistinguishable, thereby producing a merged solder region 328. In addition, the solder region 128 may also extend around the cover layer 224D and toward the intermediate layer 224C, which acts as a physical barrier to prevent the solder region 128 (e.g., the merged solder region 328) from reaching the base layer 224B or the substrate 210. Similarly, the solder region 128 may be pushed back around the cover layer 124D and toward the intermediate layer 124C, which also acts as a physical barrier to prevent the solder region 128 (e.g., the merged solder region 328) from reaching the base layer 124B or the passivation layer 122.

[0051] As shown, the merged solder region 328 can be in physical contact with either or both of the intermediate layers 124C / 224C while surrounding the sidewalls of the capping layer 124D / 224D. During the bonding process of the completed semiconductor device and subsequent stress testing (e.g., thermal cycle testing), storage, and functional use, the elements within the merged solder region 328 tend to diffuse into adjacent components, such as adjacent conductive components. For example, in an embodiment where the solder region 128 / 228 includes a Cu-Sn alloy, copper and tin can diffuse into the metal pillars 124 and 224. Similarly, in an embodiment where either or both of the intermediate layers include nickel, nickel can diffuse into the merged solder region 328. As discussed in more detail below, these different and opposite diffusions of, for example, copper, tin, and nickel cause changes in the structure of the bonding connector structure 330 over time.

[0052] Copper atoms (e.g., within the merged solder region 328 and the capping layer 124D / 224D) diffuse through the bonding connector structure 330 at a higher rate than tin atoms (e.g., within the merged solder region 328) and nickel atoms (e.g., within the intermediate layer 124C / 224C). The imbalance of these rates combined with the different diffusion directions can result in voids or other structural weaknesses in the bonding connector structure 330. However, the composition, location, and size of the intermediate layer 124C / 224C create physical and chemical barriers that reduce these diffusions or their effects. As discussed above, the width W1 / W2 of the intermediate layer 124C / 224C provides a physical barrier to keep the merged solder region 328 in a confined area between the intermediate layers 124C / C24C. In addition, the composition of the intermediate layer 124C / 224C (e.g., nickel and / or an iron-cobalt alloy) provides a chemical barrier to slow or prevent the diffusion of copper atoms therein.

[0053] Due to these features and phenomena, the embodiment design of the connector structure 130 / 230 / 330 (e.g., including the intermediate layer 124C / 224C) can reduce the above-mentioned metal diffusion. The reduced diffusion prevents the formation of voids (e.g., Kirkendall voids) in and around the cover layer 124D / 224D and the merged solder area 328. The resulting semiconductor device maintains a stronger bond and a more robust electrical connection between the package assembly 150 / 200 during manufacturing, testing, packaging, storage, and functional use.

[0054] As mentioned above, Fig. 12B and Fig. 13C may represent a joined connector structure 330 after testing, storage and / or use, while Fig. 13BThe bond connector structure 330 may be represented shortly after a bonding process. In particular, during those subsequent processes, diffusion of copper, tin, and nickel may ultimately cause the composition of the merged solder region 328 to change, while forming one or more additional intermetallic layers.

[0055] For example, disproportionate diffusion of copper out of the merged solder region 328 and diffusion of nickel into the merged solder region 328 may result in an overall reduction in the copper concentration (eg, atomic ratio) within the merged solder region 328. x Sn y In embodiments of the alloy, the value of x can be reduced while the value of y is increased (e.g., the ratio of y:x can be increased). In addition, the diffusion of nickel into the merged solder region 328 has an additional effect on the composition change of the merged solder region 328. For example, the solder region 128 / 228 can be deposited as a Cu3Sn alloy, and the composition of the merged solder region 328 can ultimately be changed to a (Cu,Ni)6Sn5 alloy. In some embodiments, the ratio of nickel to copper will be different in various portions of the merged solder region 328, such as being larger in regions close to the intermediate layer 124C / 224C and smaller in regions away from the intermediate layer 124C / C24C (e.g., the central region of the merged solder region 328). For example, in regions close to the intermediate layer 124C / 224C, the ratio of nickel to copper can be as high as about 0.5-3, while the central region can be substantially Cu6Sn5.

[0056] In addition, after bonding (and subsequent testing, storage, and / or use), an intermetallic compound (IMC) layer 125 may be formed along the boundary between the merged solder region 328 and the capping layer 124D, and an intermetallic compound (IMC) layer 225 may be formed along the boundary between the merged solder region 328 and the capping layer 224D. In some embodiments, the IMC layer 125 / 225 includes a (Cu, Ni)6Sn5 alloy, and may also include a Cu-Sn alloy (e.g., Cu3Sn).

[0057] It should also be understood that after the joining process, the merged solder region 328 may include a composition that is substantially the same as the composition of the solder region 128 / 228 as deposited. For example, the merged solder region 328 may be Cu-Sn (e.g., Cu3Sn, Cu6Sn5, or a combination thereof) without significant flow of copper, tin, and nickel (e.g., outflow of copper, outflow of tin, inflow of nickel, or a combination thereof). For example, the merged solder region 328 may include a substantially continuous composition in the center region compared to the regions near the capping layer 124D / 224D and the intermediate layer 124C / 224C. Therefore, the merged solder region 328 may not include the IMC layer 125 / 225 until subsequent testing, storage, and / or functional use.

[0058] exist FIG. 14A to FIG. 14C In the embodiment, one or both of the intermediate layers 124C / 224C may be a double layer according to various embodiments. For example, the intermediate layer 124C may include a first layer 124C-1 including nickel and a second layer 124C-2 including iron and cobalt. However, the second layer 124C-2 of the double layer may be a palladium-containing layer, a gold layer, etc. In addition, the first layer 124C-1 of the intermediate layer 124C may be closer to the base layer 124A, and the second layer 124C-2 may be closer to the cover layer 124D (as shown), or vice versa. Fig.14A The connector structure 130 / 230 is shown before joining. Fig. 14B The joined connector structure 330 is shown shortly after joining, and Fig. 14C The joined connector structure 330 is shown after testing, storage, and / or use.

[0059] The dual-layer intermediate layer 124C and the intermediate layer 224C achieve similar benefits as described above to reduce diffusion of copper and other elements and prevent voids in and around the cover layer 124D / 224D and the merged solder area 328 during bonding or subsequent processes associated with testing, storage, or use. In addition, the IMC layer 125 / 225 can be formed similarly to the above. It should be understood that in an embodiment where the first layer 124C-1 of the dual-layer intermediate layer 124C is nickel, the IMC layer 125 and the area of ​​the merged solder area 328 near the intermediate layer 124C can have a lower nickel concentration (e.g., no nickel) than the IMC layer 225 and the area of ​​the merged solder area 328 near the intermediate layer 224C.

[0060] According to various embodiments, the dual-layer intermediate layer 124C / 224C may have a total thickness T2 / T6 as described above, such that the first layer 124C-1 / 224C-1 and the second layer 124C-2 / 224C-2 may have substantially the same thickness. However, the first layer 124C-1 / 224C-1 may include between 10% and 50% of the total thickness T2 / T6.

[0061] Note that this embodiment can be utilized in a variety of ways (not shown separately). For example, the intermediate layer 124C can have any of the above layouts or be omitted, and the intermediate layer 224C can have any of the above layouts or be omitted (so as to include at least one of these intermediate layers 124C / 224C). Therefore, there are eight combinations that can utilize this particular embodiment.

[0062] exist FIG. 15A to FIG. 16C In the embodiment, one of the connector structures 130 / 230 includes the corresponding intermediate layer 124C / 224C, while the other of the connector structures 130 / 330 does not include the corresponding intermediate layer 124C / 224C. In particular, FIG. 15A to FIG. 15C Metal pillar 124 is shown including intermediate layer 124C, while metal pillar 224 lacks intermediate layer 224C. FIG. 16A to FIG. 16C The metal pillar 224 including the intermediate layer 224C is shown, while the metal pillar 124 lacks the intermediate layer 124C. For example, the metal pillar 124 may include the intermediate layer 124C, while the entire metal pillar 224 is the base layer 224B (or the capping layer 224D). Conversely, the metal pillar 224 may include the intermediate layer 224C, while the entire metal pillar 124 is the base layer 124B (or the capping layer 124D).

[0063] The presence of only one of the intermediate layer 124C or the intermediate layer 224C can achieve similar benefits as described with respect to the previous embodiments to reduce diffusion of copper and other elements and prevent voids in and around the capping layer 124D / 224D and the merged solder region 328 during bonding or subsequent processes associated with testing, storage, or use. In addition, the IMC layer 125 / 225 can be formed similarly to the above. It should be understood that the IMC layer 125 / 225 and the region of the merged solder region 328 proximate to the metal pillar 124 / 224 (lacking the intermediate layer 124C / 224C) can have a lower nickel concentration (e.g., no nickel) than a similar component proximate to the metal pillar 124 / 224 (including the intermediate layer 124C / 224C). According to various embodiments, the metal pillar 124 / 224 lacking an intermediate layer may have a thickness consistent with the sum of the corresponding base layer 124B / 224B (e.g., thickness T1 / T5), the intermediate layer 124C / 224C (e.g., thickness T2 / T6), and the capping layer 124D / 224D (e.g., thickness T3 / T7).

[0064] exist Fig.17A and Fig. 17BIn some embodiments, process variations and / or warping of the wafer holding the package assembly 200 can cause variations in the height of the connector structure 230 with respect to contact with the connector structure 130 during the bonding process. In some embodiments, process variations during the formation of the connector structure 230 can cause thickness variations of its components, such as variations in one or more of the thicknesses T5 / T6 / T7 / T8. Due to these phenomena, variations between the connector structures 230 can range from about 1 μm to about 3 μm. As a result, some connector structures 230 (compared to other connector structures 230) can penetrate further into the corresponding connector structure 130. The penetration variation can also range from about 1 μm to about 3 μm.

[0065] As shown, the merged solder regions 328 that penetrate the smaller bond connector structures 330 may not be in physical contact with the corresponding intermediate layers 224C. As a result, nickel from these intermediate layers 224C may not diffuse into the merged solder regions 328 (or diffuse to a lesser extent).

[0066] exist Fig.18A and Fig.18B In the present invention, the connector structures 230 of the package component 200 can be formed to compensate for design or process changes in the package component 150 (e.g., the connector structures 130 of the package component). Examples of design changes include increasing the solder areas 128 of some of the connector structures 130. More specifically, the connector structures 130 positioned along the periphery of the package component 150 can utilize larger solder areas 128 to improve the bonding of the package component 150 / 200. In addition, the dummy connector structures 130 (e.g., electrically isolated from the integrated circuit of the package component 150 / 200) can utilize larger solder areas 128 to improve the bonding without the risk of shorting when the resulting merged solder areas 328 spread toward adjacent dummy components.

[0067] In some embodiments, the connector structure 130 may have a variation ranging from about 1 μm to about 3 μm. To account for this variation, the thickness T5 of the base layer 224B and the thickness T7 of the cover layer 224D are selected to determine the relative position of the intermediate layer 224C. Note that the thickness T6 of the intermediate layer 224C may remain unchanged.

[0068] For example, some base layers 224B may be formed to have a low thickness T5, while the corresponding cover layers 224D may be formed to have a high thickness T7. In addition, other base layers 224B may be formed to have a high thickness T5, while the corresponding cover layers 224D may be formed to have a low thickness T7. As a result, the placement of the corresponding intermediate layers 224C may vary from about 1 μm to about 3 μm.

[0069] As shown, due to the above adjustments, the merged solder region 328 can be in physical contact with the intermediate layer 224C regardless of the changes in the connector structure 130 of the package assembly 150. Therefore, the intermediate layer 224C can achieve the above benefits, and the joint connector structure 330 can produce similar components and dimensions as in similar embodiments described above.

[0070] Fig.19 A plurality of package assemblies 150 are shown attached to package assembly 200 using a thermocompression bonding (TCB) process and a baking process to attach package assemblies 150 to package assembly 200. It should be understood that in some embodiments, the plurality of package assemblies 150 may have different configurations and functions, i.e., may be different package types, while in other embodiments, each of the plurality of package assemblies 150 may be of the same type.

[0071] After attaching package component 150 to package component 200, encapsulant 350 may be deposited over and between package components 150. Encapsulant 350 may be a molding compound, a dielectric material, a polyimide, a polymer, etc., or a combination thereof. Encapsulant 350 may be deposited by any suitable process, such as by spin coating, CVD, flowable CVD, lamination, pressurization, etc.

[0072] exist Fig. 20 In the process, encapsulant 350 may be planarized, such as by a chemical mechanical planarization (CMP) process, so that the upper surface of package component 150 and the upper surface of encapsulant 350 are flush with each other. In some embodiments, planarization may continue to thin package component 150.

[0073] In some embodiments, the combination of package components 150 and package components 200 can be separated using a singulation process 205s so that the package regions 205 are separated from each other. The singulation process 205s may include a die sawing process, an etching process, a laser cutting process, etc., or a combination thereof. The singulation process 205s is performed along the scribe lines between the package regions 205. Thus, the package regions 205 are separated from each other to form discrete package components 300 (see FIG. Fig.21 ).

[0074] Fig.21A singulated discrete package component 300 is shown. After singulation, the discrete package component 300 can be used in another package or another device structure. In some embodiments, such as those shown, before or after singulation, a conductive connector 310 can be formed on a side of the substrate 210 opposite the package component 150. Forming the conductive connector 310 may include forming a contact pad 305 at a surface of the substrate 210, the contact pad 305 being electrically coupled to the metal pillar 224, for example, through an interconnect 315 and a through-hole 320 of the package component 200. The conductive connector 310 may be formed on the contact pad 305. In some embodiments, the conductive connector 310 may include an optional under-bump metal (UBM) extending through a passivation layer disposed on the substrate 210. The UBM may be formed of the same material as the contact pad 305. The conductive connector 310 may include a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. The conductive connector 310 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. The conductive connector 310 may be formed by sputtering, printing, electroplating, chemical plating, CVD, etc. In some embodiments, the conductive connector 310 includes a metal column and a metal covering layer formed on the top of the metal column. The metal covering layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process.

[0075] FIG. 22A to FIG. 22C An exemplary semiconductor package that may utilize some of the above-described embodiments of the connector structure 130 / 230 / 330 is shown. Fig.22A Any of the above embodiments may be used in a chip-on-wafer (CoW) semiconductor package to attach an integrated circuit chip (eg, package assembly 150 ) to an interposer (eg, package assembly 200 ). Fig. 22B Any of the above embodiments may be used to attach a bridge die (eg, package assembly 150 ) to two or more integrated circuit dies (eg, collectively referred to as package assembly 200 ). Fig. 22C , any of the above embodiments can be used to attach an integrated circuit die (e.g., package assembly 150) to a first redistribution structure (e.g., package assembly 200), and a second redistribution structure can be formed over the back side of the integrated circuit die, the second redistribution structure can be electrically connected to the back side of the integrated circuit die. Additional integrated circuit dies can then be attached to the second redistribution structure. It should be understood that the semiconductor package can include one or more of these exemplary package types and one or more embodiments of the connector structures 130 / 230 / 330 described in the present disclosure.

[0076] During the formation of the semiconductor package, the embodiments advantageously provide improved bonding between the package components 150 / 200. In particular, the metal pillars 124 / 224 of the connector structures 130 / 230 along each package component 150 / 200 are designed to improve the reliability of the merged solder area 328. After being subjected to stress testing, storage and / or functional use, the connection remains solid and void-free.

[0077] In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, the forming of the metal pillar including: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a cover layer over the intermediate layer; forming a solder region over the cover layer; and performing an etching process to recess the sidewalls of the base layer and the cover layer from the sidewalls of the intermediate layer and the solder region. In another embodiment, the base layer is a first copper layer, and wherein the cover layer is a second copper layer. In another embodiment, the intermediate layer is a nickel layer. In another embodiment, after performing the etching process: the base layer includes a first width; the intermediate layer includes a second width; the cover layer includes a first width; and the solder region includes a second width. In another embodiment, the solder region includes a lead-free solder material. In another embodiment, the method also includes joining the solder region to a connector structure of a package component, wherein after joining the solder region to the connector structure, the merged solder region physically contacts the intermediate layer, wherein the merged solder region is generated by reflowing the solder region with an additional solder region of the connector structure. In another embodiment, the connector structure includes: an additional base layer; an additional intermediate layer located above the additional base layer, wherein after the solder region is joined to the connector structure, the merged solder region physically contacts the additional intermediate layer; an additional cover layer located above the additional intermediate layer; and an additional solder region located above the additional cover layer. In another embodiment, wherein before joining the solder region to the connector structure: the additional base layer includes a third width; the additional intermediate layer includes a fourth width; the additional cover layer includes the third width; and the additional solder region includes the fourth width.

[0078] In an embodiment, a method for forming a semiconductor package includes: forming a first integrated circuit over a first substrate; forming a patterned plating mask over the first integrated circuit, the patterned plating mask including an opening; forming a first connector structure, the forming the first connector structure including: forming a base layer in a corresponding opening; forming an intermediate layer over the corresponding base layer, the intermediate layer including nickel; forming a cover layer over the corresponding intermediate layer, the cover layer not containing nickel; and forming a first solder region over the corresponding cover layer, the first solder region not containing nickel; removing the patterned plating mask; performing an etching process using an etchant selective to the materials of the base layer and the cover layer; depositing a polymer material over and between the first connector structure; planarizing the polymer material so that the polymer material is flush with the upper surface of the first solder region; and depositing a non-conductive film over the polymer material. In another embodiment, the method also includes forming a second connector structure over the second substrate, the second connector structure including a metal column and a second solder region; bonding the first connector structure to the second connector structure, wherein the first solder region is bonded to the corresponding second solder region to form a merged solder region. In another embodiment, the merged solder region is in physical contact with the intermediate layer. In another embodiment, the method further comprises: performing a cycle test on the semiconductor package after bonding the first connector structure to the second connector structure, wherein after performing the cycle test, the merged solder region comprises nickel. In another embodiment, the intermediate layer further comprises iron cobalt. In another embodiment, the method further comprises forming a seed layer over the first integrated circuit before forming the patterned plating mask, wherein performing the etching process comprises removing exposed portions of the seed layer.

[0079] In an embodiment, a semiconductor device includes: a first interconnect structure located above a first substrate; a first metal pillar located above the first interconnect structure, the first metal pillar including: a first base layer located above the first interconnect structure, the first base layer having a first lateral width; a first intermediate layer located above the first base layer, the first intermediate layer having a second lateral width, the second lateral width being greater than the first lateral width; and a first capping layer located above the first intermediate layer, the first capping layer having a first lateral width; a solder region located above the first capping layer and around a sidewall of the first capping layer; a second metal pillar located above the solder region, the second metal pillar including: a second capping layer, the solder region being located around a sidewall of the second capping layer, the second capping layer having a third lateral width; a second intermediate layer located above the second capping layer, the second intermediate layer having a fourth lateral width, the fourth lateral width being greater than the third lateral width; and a second base layer located above the second intermediate layer, the second base layer having a third lateral width; and a second interconnect structure located above the second metal pillar. In another embodiment, the first intermediate layer includes a first nickel layer, wherein the second intermediate layer includes a second nickel layer. In another embodiment, the first nickel layer physically contacts the first base layer and the first cover layer, and wherein the second intermediate layer further comprises an iron-cobalt layer. In another embodiment, the solder region comprises a first intermetallic compound layer along the first cover layer and a second intermetallic compound layer along the second cover layer. In another embodiment, the second intermetallic compound layer comprises nickel. In another embodiment, the first intermetallic compound layer does not contain nickel.

[0080] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor package, comprising: forming a device region along the first substrate; forming an interconnect structure over the device region and the first substrate; Forming a metal column above the interconnect structure, wherein forming the metal column comprises: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a cover layer over the intermediate layer; forming a solder region over the cover layer; and An etching process is performed to recess sidewalls of the base layer and the cover layer from sidewalls of the intermediate layer and the solder region.

2. The method according to claim 1, wherein: The base layer is a first copper layer, and wherein the cover layer is a second copper layer.

3. The method according to claim 2, wherein: The intermediate layer is a nickel layer.

4. The method according to claim 1, wherein: After performing the etching process: The base layer comprises a first width; The intermediate layer comprises a second width; The cover layer comprises the first width; and The solder region includes the second width.

5. The method according to claim 1, wherein: The solder region includes a lead-free solder material.

6. The method of claim 1 , further comprising bonding the solder region to a connector structure of a package assembly, wherein After joining the solder region to the connector structure, a merged solder region physically contacts the intermediate layer, wherein the merged solder region results from reflow of the solder region and an additional solder region of the connector structure.

7. The method according to claim 6, wherein: The connecting piece structure comprises: Additional basal layer; an additional intermediate layer overlying the additional base layer, wherein the merged solder region physically contacts the additional intermediate layer after joining the solder region to the connector structure; an additional cover layer located above the additional intermediate layer; and An additional solder region is located above the additional cover layer.

8. The method according to claim 7, wherein: Prior to joining the solder region to the connector structure: The additional base layer comprises a third width; The additional intermediate layer comprises a fourth width; The additional cover layer comprises the third width; and The additional solder area comprises the fourth width.

9. A method of forming a semiconductor package, the method comprising: forming a first integrated circuit over a first substrate; forming a patterned plating mask over the first integrated circuit, the patterned plating mask comprising an opening; Forming a first connector structure, wherein forming the first connector structure comprises: forming a base layer in the corresponding opening; forming an intermediate layer over the corresponding base layer, the intermediate layer comprising nickel; forming a cover layer over the corresponding intermediate layer, the cover layer not containing nickel; and forming a first solder region over the corresponding cover layer, the first solder region being free of nickel; removing the patterned plating mask; performing an etching process using an etchant selective to materials of the base layer and the cover layer; depositing a polymer material over and between the first connector structures; planarizing the polymer material so that the polymer material is flush with an upper surface of the first solder region; and A non-conductive film is deposited over the polymer material.

10. A semiconductor device comprising: a first interconnect structure located above the first substrate; A first metal column is located above the first interconnect structure, and the first metal column comprises: a first substrate layer, located above the first interconnect structure, the first substrate layer having a first lateral width; a first intermediate layer located above the first base layer, the first intermediate layer having a second lateral width, the second lateral width being greater than the first lateral width; and a first covering layer, located above the first intermediate layer, the first covering layer having the first lateral width; a solder region located above the first covering layer and around a sidewall of the first covering layer; A second metal column is located above the solder region, the second metal column comprising: a second covering layer, the solder region being located around a sidewall of the second covering layer, the second covering layer having a third lateral width; a second intermediate layer located above the second cover layer, the second intermediate layer having a fourth lateral width, the fourth lateral width being greater than the third lateral width; and a second substrate layer located above the second intermediate layer, the second substrate layer having the third lateral width; and The second interconnect structure is located above the second metal column.

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