Semiconductor device and forming method thereof

Abstract

The method includes forming a first integrated circuit device and a second integrated circuit device on a semiconductor substrate of a wafer; forming a metal layer as a part of the wafer; and forming a transistor including a first source / drain region connected to the first integrated circuit device. The transistor is farther from the semiconductor substrate than the metal layer. An electrical connection is formed on the surface of the wafer that is electrically connected to the second source / drain region of the transistor. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The head unit (power switch) is used in an integrated circuit to gate control the power supplied to the circuit. The head unit may include a transistor, the source of which may be connected to a power supply node such as VDD. The drain may serve as another power supply node, the voltage of which is determined by whether the transistor is on or off. When the head unit is on, the drain receives power, and thus the circuit is powered. When the head unit is off, no power is supplied to the circuit. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first integrated circuit device and a second integrated circuit device on a semiconductor substrate of a wafer; forming a first metal layer as part of the wafer; forming a transistor including a first source / drain region connected to the first integrated circuit device, wherein the transistor is farther away from the semiconductor substrate than the first metal layer; and forming an electrical connector on a surface of the wafer, wherein the electrical connector is electrically connected to the second source / drain region of the transistor.

[0004] Other embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; an integrated circuit device located at the surface of the semiconductor substrate; an electrical connector; a plurality of metal layers located on the semiconductor substrate, wherein the plurality of metal layers include an electrical path extending from the topmost end to the bottommost end of the plurality of metal layers; and a transistor, including: a first source / drain region connected to the electrical connector; and a second source / drain region connected to the integrated circuit device through the first electrical path.

[0005] Still other embodiments of the present application provide a semiconductor structure comprising: a semiconductor substrate; an integrated circuit device located on a surface of the semiconductor substrate; a plurality of metal layers located above the integrated circuit device; and a transistor located above the plurality of metal layers, wherein a drain region of the transistor is connected to the integrated circuit device via a first electrical path in the plurality of metal layers, and wherein the transistor is configured to gate-control a power supply voltage located on a source region of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 6 A cross-sectional view is shown of an intermediate stage in the formation of a die including a power switch in accordance with some embodiments.

[0008] Figures 7 to 11 A diagram illustrating a power switch according to some embodiments is shown.

[0009] Fig.12 A package of a device die including a power switch is shown according to some embodiments.

[0010] Fig.13 The bonding of a device die including a power switch is shown in accordance with some embodiments.

[0011] Fig.14 A process flow for forming a device die including a power switch is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] A power switch formed in a back-end-of-line (BEOL) structure of a die or in a back-side interconnect structure of a die is provided. A method for forming the power switch is provided. According to some embodiments of the present disclosure, a thin film transistor used as a power switch to gate power to a circuit in the die is formed in the BEOL structure of a device die or in the back-side interconnect structure of a device die, which may be an InGaZnO (IGZO) transistor. Because the power switch occupies a larger chip area, moving the power switch from the surface of the semiconductor substrate to the interconnect structure frees up chip area for forming other circuits. In addition, the path for providing power is reduced, and the resistance is reduced, so the performance of the circuit can be improved.

[0015] The embodiments discussed herein are intended to provide examples of the subject matter of the disclosed embodiments that can be manufactured or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the contemplation of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0016] Figures 1 to 6 1 shows a cross-sectional view of an intermediate stage in the formation of a device die according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.14 In the process flow shown in .

[0017] Figure 1 A cross-sectional view of wafer 20 is shown. According to some embodiments, wafer 20 is or includes a device wafer including active devices and possibly passive devices, which are shown as integrated circuit devices 24. Wafer 20 may include a plurality of chips / dies 20' therein, of which one of chips 20' is shown.

[0018] According to some embodiments, wafer 20 includes a semiconductor substrate 22 and a component formed at a top surface of semiconductor substrate 22. Semiconductor substrate 22 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. A shallow trench isolation (STI) region (not shown) may be formed in semiconductor substrate 22 to isolate active regions in semiconductor substrate 22.

[0019] According to some embodiments, an integrated circuit device 24, collectively referred to as a front-end-of-line (FEOL) structure, is formed on the top surface of a semiconductor substrate 22. The corresponding process is shown as follows: Fig.14202 in the process flow 200 shown in . According to some embodiments, the integrated circuit device 24 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. According to some embodiments, the integrated circuit device 24 includes an integrated circuit device 24A powered by a gate-controlled power supply and an integrated circuit device 24B powered by a non-gate-controlled power supply, as discussed in detail in subsequent paragraphs.

[0020] like Figure 1 and Figure 2 As shown in FIG. 1 , an interconnect structure 32 electrically connected to the integrated circuit device 24 is formed over the integrated circuit device 24. The corresponding process is shown as follows. Fig.14 204 in the process flow 200 shown in . According to some embodiments, the interconnect structure 32 includes an interlayer dielectric (ILD) 28 formed over the semiconductor substrate 22 and filling the space between the gate stacks (not shown) of the transistors in the integrated circuit device 24. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 can be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments, the ILD 28 can also be formed using a deposition method, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0021] Contact plugs 30 for electrically connecting integrated circuit device 24 to the above metal lines and vias are formed in ILD 28. According to some embodiments, contact plugs 30 are formed of or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of contact plugs 30 may include: forming a contact opening in ILD 28; filling the contact opening with a conductive material; and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of contact plug 30 flush with the top surface of ILD 28.

[0022] According to some embodiments, through-holes 26 (optionally referred to as through-silicon vias (TSVs) or semiconductor through-holes (also referred to as TSVs)) are formed in wafer 20. Through-holes 26 may extend from the top surface of semiconductor substrate 22 to an intermediate layer between the top surface and the bottom surface. The top end of through-holes 26 may extend to the top surface of ILD 28. Optionally, the top end of through-holes 26 may be located at any available level, such as the top surface level of semiconductor substrate 22 or the top surface level of any one of dielectric layers 38. Each of through-holes 26 may be surrounded by a dielectric isolation layer (not shown) that electrically insulates the corresponding through-hole 26 from semiconductor substrate 22.

[0023] According to some embodiments, such as Figure 1 In the embodiment shown in FIG. 1 , the formation of via 26 includes a via first process or a via middle process, wherein via 26 is formed from the front side of semiconductor substrate 22. According to alternative embodiments, a via last process may be used to form via 26, and via 26 may be formed from the back side of wafer 20.

[0024] Vias 26 include power vias 26A for conducting ungated power and vias 26B for conducting signals. Additional vias, such as via 26C, may or may not be present, which are also used to conduct gated power that may be gated on the back side of semiconductor substrate 22.

[0025] refer to Figure 2 , more metal layers and dielectric layers are formed to extend the interconnect structure 32 upward. The interconnect structure 32 also includes a dielectric layer 38 (also called an intermetallic dielectric (IMD)), an etch stop layer (not shown), and metal lines 34 and vias 36 formed in the dielectric layer 38. The metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments, the interconnect structure 32 includes: a plurality of metal layers (M0 to Mtop), including metal lines 34 interconnected by vias 36. The metal layers in the interconnect structure 32 can be represented as M0, M1, M2, M3, etc.

[0026] Metal lines 34 and vias 36 may be formed of copper or copper alloys, and may also be formed of or include other metals such as aluminum, tungsten, nickel, etc. According to some embodiments, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.5 or lower than about 3.0. Dielectric layer 38 may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The etch stop layer may be formed of or include aluminum oxide, aluminum nitride, SiOC, SiON, etc., or multiple layers thereof.

[0027] The formation of metal lines 34 and vias 36 in dielectric layers 38 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 38, followed by filling the trench or via opening with a conductive material. A planarization process such as a CMP process is then performed to remove excess portions of the conductive material above the top surface of the dielectric layer, leaving metal lines or vias in the corresponding trench or via openings.

[0028] In the dual damascene process, trenches and via openings are formed in the dielectric layer, wherein the via openings are located below the trenches and connected to the trenches. Conductive materials are then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0029] The top metal layer is referred to as metal layer Mtop, the metal layer immediately below metal layer Mtop is referred to as metal layer M(top-1), and the metal layer immediately below metal layer M(top-1) is referred to as metal layer M(top-2), and so on. According to some embodiments, the total number of metal layers may be greater than about 9, and may be in a range between about 9 and 16. According to some embodiments, the top metal layer Mtop is formed in dielectric layer 38T, which is the top layer of dielectric layer 38. Dielectric layer 38T may be formed of or include a low-k dielectric material, as discussed above. Alternatively, dielectric layer 38T may be formed of or include a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon oxynitride, silicon nitride, etc., or a combination thereof.

[0030] According to some embodiments, a thin film transistor 40 is formed in one of the metal layers or between two adjacent metal layers. The corresponding process is shown as follows Fig.14 The process 206 in the process flow 200 shown in FIG. According to some exemplary embodiments, as Figure 2 As shown in FIG. 4 , thin film transistor 40 is formed in a top position of interconnect structure 32 , such as between metal layers Mtop and M(top- 1 ).

[0031] A dielectric layer 42 may be formed over the top metal layer Mtop and the top dielectric layer 38T. The corresponding process is shown as follows. Fig.14 208 in the process flow 200 shown in FIG. According to some embodiments, dielectric layer 42 may be formed of or include a silicon-based dielectric material, such as SiO, SiN, SiON, SiOCN, SiOC, etc., combinations thereof, or multilayers thereof. Dielectric layer 42 may sometimes be used to bond to a supporting substrate, and thus may be referred to as a bonding layer hereinafter.

[0032] Forming thin film transistor 40 in the top position of interconnect structure 32 has some advantageous features. Thin film transistor 40 is used as a power switch. Therefore, the size of thin film transistor 40 (and the chip area occupied) is larger. For example, the chip area occupied by thin film transistor 40 in the device die can be in the range of between about 4% and about 8% of the device die. The upper metal layer has a larger spacing and a larger metal line width suitable for forming thin film transistor 40. In addition, the upper metal layer has a larger thickness and a larger distance from their adjacent metal layers, and the process difficulty in the formation of thin film transistor 40 is reduced.

[0033] Figure 7 A perspective view of thin film transistor 40 and underlying metal layers is shown in accordance with some embodiments. Integrated circuit device 24 and M0 power rail are also schematically shown.

[0034] Figure 8 A cross-sectional view of a thin film transistor 40 according to some embodiments is shown. According to some embodiments, the thin film transistor 40 is formed on the front side of the semiconductor substrate 22 as a power switch. According to an optional embodiment, the front side thin film transistor 40 is not formed. Instead, a back side power switch is formed. The thin film transistor 40 may include a channel layer 142, which may be formed of or include a metal oxide. For example, the channel layer 142 may include InGaZnO (IGZO), which is a semiconductor. According to some embodiments, the source region 144 and the drain region 146 are in contact with the channel layer 142 and are spaced apart from each other by a dielectric layer 148. The gate dielectric 145 may be located below the channel layer 142 and may be formed of a high K (HK) dielectric material. The bottom gate 150 may be located below the gate dielectric 145 and in contact with the gate dielectric 145. A dielectric region / layer 152 is formed to surround the bottom gate 150.

[0035] In the example shown, the thin film transistor 40 is a bottom gate transistor. According to alternative embodiments, the thin film transistor 40 is a top gate transistor. According to still other alternative embodiments, the thin film transistor 40 may be a dual gate transistor including a top gate and a bottom gate.

[0036] According to some embodiments, Figure 2 As shown in FIG. 1 , the thin film transistor 40 may be formed between the metal layers Mtop and M(top-1). For example, the thin film transistor 40 may be formed between the through hole 36T ( Figure 2), which is located between metal layers Mtop and M(top-1). According to optional embodiments, depending on how many integrated circuits are powered by the gate-controlled power supply and depending on the corresponding wiring requirements, thin film transistor 40 can be formed in any of the following layers, such as between metal layers M(top-1) and M(top-2), between metal layers M(top-2) and M(top-3) ... between metal layers M3 and M2, or between metal layers M2 and M1.

[0037] In addition, there may be multiple thin film transistors 40 (as power switches) formed at different levels. For example, when the thin film transistor 40 is formed between the metal layers Mtop and M(top-1), there may be other thin film transistors 40 formed between the metal layers M(top-1) and M(top-2), between the metal layers M(top-2) and M(top-3), and / or at other levels. Forming multiple thin film transistors 40 at different levels can save more chip area so that multiple thin film transistors 40 do not compete for the same chip area. In addition, the upper thin film transistors 40 can support more circuits because more metal layers can be used to wire their power supplies, while the lower thin film transistors 40 can support fewer circuits.

[0038] An exemplary process for forming the thin film transistor 40 is briefly discussed herein. In the following discussion, it is assumed that the bottom gate 150 is formed above the metal layer M(top-1). According to some embodiments, the metal layer M(top-1) is formed. According to some embodiments, Figure 8 The bottom gate 150 shown in FIG. 1 may be part of the metal layer M(top-1), as shown in FIG. Fig. 9 Optionally, as shown in Figure 8 The bottom gate 150 shown in FIG. 1 is formed to be located above and contact the metal line in the metal layer M(top- 1 ).

[0039] According to some embodiments, Figure 8 As shown in , a dielectric layer 152 is deposited. The dielectric layer 152 may include silicon oxide, silicon nitride, silicon oxynitride, etc. Next, a bottom gate 150 is formed in the dielectric layer 152, for example, by a damascene process. The bottom gate 150 may be formed of or include copper, aluminum, tungsten, nickel, cobalt, etc., or a combination thereof. Optionally, the bottom gate 150 and the dielectric layer 152 are formed by: depositing a metal layer; patterning the metal layer to form the bottom gate 150; depositing a dielectric layer; and performing a planarization process.

[0040] Next, a gate dielectric 145 is deposited, which may include silicon oxide or a high-k dielectric material such as hafnium oxide, lanthanum oxide, zirconium oxide, etc. A channel layer 142 is then deposited, which may include InGaZnO. In a subsequent process, a source region (S) and a drain region (D) contacting the channel layer 142 are formed over the channel layer 142. An oxide layer 148 is formed between the source region 144 and the drain region 146 to separate the source region 144 from the drain region 146. The formation process may be similar to the formation of the bottom gate 150 and the dielectric layer 152.

[0041] In a subsequent process, dielectric layer 148, channel layer 142, gate dielectric 145, and dielectric layer 152 are patterned in an anisotropic etching process so that portions of these layers located outside thin film transistor 40 are patterned, leaving thin film transistor 40 standing above metal layer M (top-1). A top dielectric layer 38T ( Figure 2 ), followed by forming a through hole 155 ( Fig. 9 and Fig.10 ). A metal layer Mtop connected to the via 155 may then be formed.

[0042] Fig. 9 4 shows a thin film transistor 40 in a larger view according to some embodiments. According to some embodiments, there are multiple source regions 144 and multiple drain regions 146 formed alternately. Each of the source regions 144 is connected to the upper via 155. Each of the drain regions 146 is also connected to the upper via 155. Through the via 155 in the metal layer Mtop and the upper metal line 156 (also refer to Fig.10 ), all drain regions 146 are interconnected. Through vias 155 in metal layer Mtop (marked with dashed lines to indicate that they are not in the plane shown) and metal lines 158 ( Fig.10 ), all source regions 144 are interconnected. Therefore, the thin film transistor 40 includes a plurality of sub-transistors connected in parallel, and thus can have a larger current supporting the operation of a plurality of integrated circuit devices.

[0043] Fig.10 A thin film transistor 40 according to some embodiments is shown. The channel layer 142 can be formed as a long and wide sheet. In the top view, the source region 144 and the drain region 146 can be formed as a plurality of elongated strips. The elongated strips of the source region 144 are parallel to the elongated strips of the drain region 146 and are formed on the channel layer 142. The bottom gate 150 can also be formed as an elongated strip or multiple elongated strips located below the channel layer 142 and contacting the channel layer 142. A through hole 155 connected to the source region 144 and the drain region 146 is also shown.

[0044] Figures 3 to 6 A process for forming backside features on the backside of semiconductor substrate 22 is shown. Figure 3 , a carrier 48 (which may be a glass carrier) is attached to the front side of the wafer 20. The corresponding process is shown as Fig.14 Attachment may be performed by an adhesive such as a light-to-heat conversion (LTHC) material 50 that is configured to decompose under the heat of light, such as a laser beam.

[0045] According to alternative embodiments, carrier 48 may be a support substrate, which may be a blank silicon substrate according to some embodiments. The support substrate may be formed of a homogenous material such as silicon, and no other material may exist in the support substrate except the homogenous material. Layer 50 according to these embodiments may be a bonding layer formed of a silicon-containing dielectric material such as SiO, SiC, SiOC, SiON, SiOCN, etc.

[0046] refer to Figure 4 , a backside grinding process is performed to remove a portion of the semiconductor substrate 22 until the through hole 26 is exposed. The corresponding process is shown as follows Fig.14 200. Then, the semiconductor substrate 22 is slightly recessed (e.g., by etching) so that the end portion of the through hole 26 protrudes from the back side of the semiconductor substrate 22. Next, a dielectric layer 52 is deposited, followed by a CMP process or a mechanical grinding process to re-expose the through hole 26. Therefore, the through hole 26 also penetrates the dielectric layer 52. According to some embodiments, the dielectric layer 52 is formed of silicon oxide, silicon nitride, etc.

[0047] refer to Figure 5 , forming metal pad 54 and dielectric layer 56. According to some embodiments, the formation process may include: depositing dielectric layer 56 on the back side of semiconductor substrate 22; etching dielectric layer 56 to form an opening, forming through-hole 26 through the opening; and filling the opening with a conductive material. The corresponding process is shown as follows Fig.14 214 and 216 in the process flow 200 shown in FIG.

[0048] refer to Figure 6 In the subsequent process, a backside redistribution structure 62 is formed. The corresponding process is shown as follows Fig.14218 in the process flow 200 shown in . The backside redistribution structure 62 includes a dielectric layer 58, and an RDL 60 is formed in the dielectric layer 58. The RDL 60 may be formed of or include aluminum, copper, nickel, tungsten, titanium, etc. According to some embodiments, the formation of the layers of the RDL 60 may include: forming the dielectric layer 58; etching the respective dielectric layer 58 to form an opening; plating a metal seed layer extending into the opening; forming a patterned plating mask in which some portions of the metal seed layer are exposed; and plating to form the RDL 60. According to an alternative embodiment, the RDL 60 may be formed by a damascene process.

[0049] A thin film transistor 40' may be formed inside the backside redistribution structure 62. The corresponding process is shown as follows Fig.14 200 in the process flow 200 shown in FIG. According to some embodiments, similar to thin film transistor 40, thin film transistor 40' is formed in a metal layer that is further away from semiconductor substrate 22 than some other metal layers. For example, there may be four backside metal layers on the back side of semiconductor substrate 22, and these metal layers are referred to as BM0, BM1, BM2, and BM3. Thin film transistor 40' may be formed between metal layers BM2 and BM3, and it may also be formed between other adjacent backside metal layers (such as between metal layers BM3 and BM4, such as Fig.11 ).

[0050] The thin film transistor 40' may be formed using substantially the same process as the thin film transistor 40, and may have a structure similar to or the same as the thin film transistor 40. Figures 8 to 10 The thin film transistor 40' may include a source region 144', a gate 150' and a drain region 146', such as Figure 6 as shown in .

[0051] According to some embodiments, thin film transistor 40' is formed on the back side of semiconductor substrate 22 without forming thin film transistor 40. According to alternative embodiments, thin film transistor 40 is formed on the front side of semiconductor substrate 22 without forming thin film transistor 40'. According to still other alternative embodiments, thin film transistor 40 and thin film transistor 40' are formed.

[0052] Fig.11 A perspective view of a portion of the backside structure of wafer 20 according to some embodiments is shown. Frontside metal layer M0 (on the front side of substrate 22), integrated circuit device 24, and metal layers BM0 to BM4 (on the back side of substrate 22) are shown. Thin film transistor 40' is shown formed between metal layers BM3 and BM4 according to some embodiments.

[0053] Reference again Figure 6 , forming an electrical connection 64. The corresponding process is shown as follows Fig.14 222 in the process flow 200 shown in FIG. According to some embodiments, the electrical connector 64 includes a solder region, which can be formed by plating a solder ball on a metal pad of the RDL 60 and reflowing the solder ball. According to an alternative embodiment, the electrical connector 64 is formed of a non-reflowable (non-solder) metal material. For example, the electrical connector 64 can be formed as a copper pad or a copper pillar, and may or may not include a nickel capping layer.

[0054] When the carrier 48 is a glass carrier, the carrier 48 can be peeled off from the wafer 20 below. The wafer 20 can then be divided into a plurality of identical device dies 20'. The corresponding process is shown as follows Fig.14 224 in the process flow 200 shown in FIG. According to alternative embodiments, when carrier 48 is a silicon support substrate and is bonded to wafer 20 by fusion bonding, support substrate 48 may be removed, or may remain on wafer 20 during singulation. The resulting package including the support substrate (if included) is also referred to as device die 20'.

[0055] like Figure 6 As shown in FIG. 1 , according to some embodiments, when thin film 40 is formed, a true VDD (TVDD) voltage (also referred to as power supply TVDD or power supply voltage TVDD) can be introduced into device die 20' from electrical connector 64A. The TVDD voltage is conducted to thin film transistor 40 through electrical path 72 (which includes RDL 60, via 26A, metal line 34, and via 36). The TVDD voltage is provided to source region 144 (also referred to as Figure 8 ), the source region 144 is optionally referred to as a TVDD node. The voltage on the drain region 146 may be referred to as a virtual VDD (VVDD) voltage (also referred to as a power supply VVDD or a power supply voltage VVDD). Therefore, the drain region 146 is referred to as a VVDD node, which receives power when the thin film transistor 40 is turned on, and is disconnected from the power supply when the thin film transistor 40 is turned off. The power supply VVDD on the VVDD node 146 is provided to the integrated circuit device (power user circuit) 24A through the electrical path 74.

[0056] The TVDD voltage may also be conducted to metal line 34T', which is a portion of top metal line 34T. The portion of the connecting metal line that connects the top metal pad of electrical path 72 to metal line 34T' is not shown and may be located in a plane that is not shown. Metal line 34T' may also be referred to as an always-on node because whenever electrical connection 64A has power, metal line 34T' also has power. Voltage TVDD is provided to integrated circuit device 24B through electrical path 76, regardless of whether integrated circuit device 24A is disconnected from power or provided with power.

[0057] The device die 20 ′ also has a signal via 26B that is connected to the electrical connector 64B and is used to conduct signals to the integrated circuit device 24B.

[0058] According to some embodiments, when thin film transistor 40' is formed on the back side of semiconductor substrate 22, power supply TVDD can be transmitted from electrical connection 64A to thin film transistor 40' through electrical path 72'. Drain region 146' is a VVDD node, which receives power when thin film transistor 40' is turned on and is disconnected from the power when thin film transistor 40' is turned off. Power on VVDD node 146' is provided to power user circuit 24A through electrical path 78, which includes RDL 60, via 26C, metal line 34 and via 36. Electrical path 78 may include upper metal lines, such as top metal line 34T in the top metal layer. Electrical path 78 also includes metal line 34 and via 36 connected from top metal line 34T to integrated circuit device 24A.

[0059] Fig.12 A package 120 including a device die 20' is shown according to some embodiments. The device die 20' is bonded to a package component 80. The package component 80 may be a silicon interposer, an organic interposer, a package substrate, a printed circuit board, a package, etc. A power supply TVDD may be provided to an electrical connection 81 of the package component 80 and conducted to an electrical connection 64A of the device die. The power supply TVDD may be gated by the thin film transistor 40 and / or 40', and the gated power supply VVDD and the un-gated power supply TVDD may be provided to some integrated circuits.

[0060] According to some embodiments, heat spreader 84 is attached to package assembly 80 via adhesive 82. Heat spreader 84 may also be attached to device die 20' via thermal interface material 86.

[0061] Fig.13 Wafer 20 (and device die 20') formed according to alternative embodiments of the present disclosure are shown. In these embodiments, instead of providing power from the back side of device die 20', electrical connections 64' (including 64A' and 64B') are formed on the front side of device die 20'. Power supply TVDD is also provided from the front side of device die 20'.

[0062] This paper briefly discusses Fig.13 Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components represented by the same reference numerals in the aforementioned embodiments. The details of the materials, structures, and formation processes provided in each of the embodiments throughout the entire description can be applied to any other embodiment when applicable.

[0063] The initial steps of these embodiments are Figure 1 and Figure 2 , except that no through-holes are formed. After forming the thin film transistor 40 and the metal layer Mtop thereon, an etch stop layer 90 may be formed over the interconnect structure 32. A passivation layer 92 (sometimes referred to as passivation-1 or pass-1) is formed over the etch stop layer 90. According to some embodiments, the passivation layer 92 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. The passivation layer 92 may be formed of or include an inorganic dielectric material, which may include materials selected from, but not limited to, undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide (SiC), etc., combinations thereof and / or multilayers thereof.

[0064] According to some embodiments, a via 94 is formed in the passivation layer 92 and the etch stop layer 90 to electrically connect to the top metal feature 34T below. A metal pad 96 is further formed above the via 94. According to some embodiments, the metal pad 96 includes aluminum, aluminum copper, etc. A passivation layer 98 (sometimes referred to as passivation-2 or pass-2) is also formed that can extend on the sidewalls and top surface of the metal pad 96. The passivation layer 98 can be formed of or include silicon oxide, silicon nitride, etc., or multiple layers thereof.

[0065] According to some embodiments, dielectric layer 100 is formed, for example, by dispensing a polymer in a flowable form and then curing the polymer layer. Dielectric layer 100 is patterned to expose metal pads 96. Dielectric layer 100 (when formed of a polymer) may be formed of or include polyimide, polybenzoxazole (PBO), etc. Alternatively, dielectric layer 100 may be formed of or include an organic dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0066] Under bump metal (UBM) 102 and bonding pad 64' may be formed to electrically connect to underlying metal pad 96. The formation process of UBM 102 and bonding pad 64' may include: forming openings in passivation layer 98 and dielectric layer 100; depositing a blanket metal seed layer extending into the openings; forming a patterned plating mask on the metal seed layer; plating bonding pad 64'; removing the plating mask; and etching portions of the blanket metal seed layer previously covered by the plating mask. According to some embodiments, dielectric layer 106 is formed to have a top surface coplanar with a top surface of bonding pad 64' and may be used for hybrid bonding. Other electrical connections for other bonding schemes such as solder bonding may also be formed.

[0067] In the device die 20', the un-gated voltage TVDD can be conducted into the device die 20' through the bonding pad 64A' and conducted to the source region 144 of the thin film transistor 40. Then, the gate voltage VVDD at the drain region 146 of the thin film transistor 40 is conducted to the integrated circuit device 24A. Since the thin film transistor 40 is used as a power switch, the electrical path is shorter. The voltage conduction path 104 for conducting power to the integrated circuit device 24A passes through the metal layer once. Therefore, the voltage drop is lower and the performance of the circuit is improved. This advantageous feature is combined with saving chip area.

[0068] In comparison, if the power switch is formed on semiconductor substrate 22, the un-gated voltage TVDD will be conducted downward (e.g., through electrical path 110A) to the power switch located below metal layer M0 (indicated by dashed box 112), and the gated voltage VVDD will be conducted upward back to a high metal layer, such as metal layer Mtop, through electrical paths 110B1 and 110B2 so that it can be distributed downward from the high metal layer. Therefore, before the power supply VVDD can reach integrated circuit device 24A, the voltage may have to pass through the metal layer three times, and the voltage drop is high.

[0069] Embodiments of the present disclosure have several advantageous features. By forming the power switch in the interconnect structure of the device die, such as in the back-end process structure and / or the backside interconnect structure of the device die, rather than on the surface of the semiconductor substrate, chip area is saved, sometimes as much as between about 4% and about 8% of the chip area. The speed of the integrated circuit can be increased by about 1.5%. The IR drop can be reduced to about 80%.

[0070] According to some embodiments of the present disclosure, a method includes: forming a first integrated circuit device and a second integrated circuit device on a semiconductor substrate of a wafer; forming a first metal layer as part of the wafer; forming a transistor including a first source / drain region connected to the first integrated circuit device, wherein the transistor is further away from the semiconductor substrate than the first metal layer; and forming an electrical connector on a surface of the wafer, wherein the electrical connector is electrically connected to a second source / drain region of the transistor. In an embodiment, forming the transistor includes: forming a metal oxide layer as a channel layer; forming a gate dielectric contacting the metal oxide layer; forming a gate electrode contacting the gate dielectric; and forming a source region and a drain region contacting the metal oxide layer.

[0071] In an embodiment, the method further comprises: forming a second metal layer further away from the semiconductor substrate than the first metal layer, wherein the metal oxide layer is formed between the first metal layer and the second metal layer. In an embodiment, the transistor is formed on the front side of the wafer. In an embodiment, the electrical connector is located on the back side of the wafer, and wherein the method further comprises: forming a via penetrating the semiconductor substrate, wherein the via electrically connects the electrical connector to a second source / drain region of the transistor.

[0072] In an embodiment, the method also includes: forming a first electrical path connecting the via to the second source / drain region; and forming a second electrical path connecting the first source / drain region to the first integrated circuit device, wherein the first electrical path and the second electrical path include portions of multiple metal layers.

[0073] In an embodiment, the electrical connector is located on the front side of the wafer, and wherein the method further comprises: forming a first electrical path connecting the electrical connector to the second source / drain region; and forming a second electrical path connecting the first source / drain region to the first integrated circuit device, wherein a portion of the first electrical path is further away from the semiconductor substrate than the entirety of the second electrical path. In an embodiment, the transistor is formed on the back side of the wafer.

[0074] In an embodiment, the electrical connector and the transistor are both formed on the back side of the wafer, and wherein the method further comprises: forming a via through the semiconductor substrate, wherein the via connects the electrical connector to the second source / drain region. In an embodiment, the method further comprises: forming a second integrated circuit device, wherein the second integrated circuit device is configured to have power when the first integrated circuit device is disconnected from the power supply.

[0075] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate; an integrated circuit device located at a surface of the semiconductor substrate; an electrical connector; a plurality of metal layers located on the semiconductor substrate, wherein the plurality of metal layers include an electrical path extending from a topmost end to a bottommost end of the plurality of metal layers; and a transistor including: a first source / drain region connected to the electrical connector; and a second source / drain region connected to the integrated circuit device via the first electrical path. In an embodiment, the transistor includes a metal oxide layer as a channel layer.

[0076] In an embodiment, the channel layer comprises InGaZnO. In an embodiment, the structure further comprises: a first metal layer spaced apart from the semiconductor substrate by a plurality of metal layers; and a second metal layer spaced apart from the semiconductor substrate by the first metal layer, wherein the transistor comprises a portion between the first metal layer and the second metal layer. In an embodiment, the transistor is configured to gate a power source to the integrated circuit device. In an embodiment, both the transistor and the integrated circuit device are located on the front side of the semiconductor substrate. In an embodiment, the integrated circuit device is located on the front side of the semiconductor substrate, and the transistor is located on the back side of the semiconductor substrate.

[0077] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate; an integrated circuit device located on a surface of the semiconductor substrate; a plurality of metal layers located above the integrated circuit device; and a transistor located above the plurality of metal layers, wherein a drain region of the transistor is connected to the integrated circuit device via a first electrical path in the plurality of metal layers, and wherein the transistor is configured to gate a power supply voltage located on a source region of the transistor. In an embodiment, the semiconductor substrate and the transistor are included in a device die, and the device die further includes: an electrical connector electrically connected to a source region of the transistor; a second electrical path located in the plurality of metal layers; and a via penetrating the semiconductor substrate, wherein a top metal line in a top metal layer of the plurality of metal layers connects the via to a source region of the transistor. In an embodiment, the transistor is configured to provide power to the integrated circuit device when the transistor is turned on, and is configured to cut off power to the integrated circuit device when the transistor is turned off.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a first integrated circuit device and a second integrated circuit device on a semiconductor substrate of a wafer; forming a first metal layer as a portion of the wafer; forming a transistor including a first source / drain region connected to the first integrated circuit device, wherein the transistor is further away from the semiconductor substrate than the first metal layer; and An electrical connection is formed on the surface of the wafer, wherein the electrical connection is electrically connected to a second source / drain region of the transistor.

2. The method according to claim 1, wherein: Forming the transistor includes: forming a metal oxide layer as a channel layer; forming a gate dielectric contacting the metal oxide layer; forming a gate electrode contacting the gate dielectric; and A source region and a drain region are formed contacting the metal oxide layer.

3. The method according to claim 1, further comprising: A second metal layer is formed further away from the semiconductor substrate than the first metal layer, wherein the metal oxide layer is formed between the first metal layer and the second metal layer.

4. The method according to claim 1, wherein: The transistors are formed on the front side of the wafer.

5. The method according to claim 4, wherein: The electrical connector is located on the back side of the wafer, and wherein the method further comprises: A via is formed through the semiconductor substrate, wherein the via electrically connects the electrical connection to the second source / drain region of the transistor.

6. The method according to claim 5, further comprising: forming a first electrical path connecting the via to the second source / drain region; as well as A second electrical path is formed connecting the first source / drain region to the first integrated circuit device, wherein the first electrical path and the second electrical path include portions in a plurality of metal layers.

7. The method according to claim 4, wherein: The electrical connector is located on the front side of the wafer, and wherein the method further comprises: forming a first electrical path connecting the electrical connection to the second source / drain region; and A second electrical path is formed connecting the first source / drain region to the first integrated circuit device, wherein a portion of the first electrical path is further away from the semiconductor substrate than the entirety of the second electrical path.

8. The method according to claim 1, wherein: The transistors are formed on the back side of the wafer.

9. A semiconductor structure comprising: Semiconductor substrate; An integrated circuit device is located at the surface of the semiconductor substrate; Electrical connectors; a plurality of metal layers disposed on the semiconductor substrate, wherein the plurality of metal layers include electrical paths extending from a topmost end to a bottommost end of the plurality of metal layers; and Transistors, including: a first source / drain region connected to the electrical connection; and A second source / drain region is connected to the integrated circuit device through the first electrical path.

10. A semiconductor structure comprising: Semiconductor substrate; an integrated circuit device located on the surface of the semiconductor substrate; a plurality of metal layers located above the integrated circuit device; as well as A transistor is located above the plurality of metal layers, wherein a drain region of the transistor is connected to the integrated circuit device through a first electrical path in the plurality of metal layers, and wherein the transistor is configured to gate a power supply voltage located on a source region of the transistor.

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