Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a stack including a chip region and a protection region surrounding the chip region; a contact structure in the chip region; and a chip protection structure in the protection region and including a first protrusion protruding a first width and a second protrusion protruding a second width greater than the first width.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an electronic device and a method of manufacturing the electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device in which a memory cell is formed as a single layer on a substrate has reached a limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate has been proposed. In addition, in order to improve the operational reliability of the semiconductor device, various structures and manufacturing methods are being developed. Summary of the invention

[0003] According to an embodiment of the present disclosure, a semiconductor device may include: a stack including a chip area and a protection area surrounding the chip area; a contact structure located in the chip area; and a chip protection structure located in the protection area and including a first protrusion protruding a first width and a second protrusion protruding a second width greater than the first width.

[0004] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stack including a chip area and a protective area surrounding the chip area; forming a first opening extending through the chip area of ​​the stack; forming a second opening and a third opening extending through the protective area of ​​the stack and spaced apart from each other; forming a fourth opening by connecting the second opening and the third opening; forming a contact structure in the first opening; and forming a chip protection structure in the fourth opening.

[0005] These and other features and advantages of the present invention will become apparent from the detailed description of embodiments of the present invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2A , Figure 2B and Figure 2C is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B and Figure 7C 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0010] According to the present technology, a semiconductor device having a stable structure and improved characteristics can be provided.

[0011] Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0012] Figure 1 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Reference Figure 1 , the substrate 100 may have a shape of a plate extending in a plane defined by a first direction I and a second direction II intersecting the first direction I. The substrate 100 may include a plurality of chip regions CHR, a plurality of protection regions GR, and a scribe region SLR. The chip region CHR may be a region where a semiconductor chip is formed. The semiconductor chip may be repeatedly formed on the substrate 100, and the plurality of chip regions CHR may be arranged in the first direction I and the second direction II. The scribe region SLR may be located between the plurality of chip regions CHR. The scribe region SLR may be a portion cut out in a dicing process for separating semiconductor chips. The protection region GR may surround the chip region CHR of the semiconductor chip on the semiconductor chip. The protection region GR may include a chip protection structure, and prevent or reduce damage to the chip region CHR by cracks generated when dicing along the scribe region SLR to separate the semiconductor chip.

[0014] The chip region CHR may include a unit region CER and a peripheral circuit region PR. For example, the chip region CHR may include a plurality of unit regions CER and a plurality of peripheral circuit regions PR. A plurality of unit regions CER and a plurality of peripheral circuit regions PR may be combined and arranged. For example, the peripheral circuit region PR may be located between a plurality of unit regions CER, or the unit region CER may be located between a plurality of peripheral circuit regions PR. The embodiments of the present disclosure are not limited thereto, and the unit region CER and the peripheral circuit region PR may be stacked. For example, the unit region CER may be located on the peripheral circuit region PR, or may be located below the peripheral circuit region PR. For reference, although not shown in the present figure, a pair of substrates 100 may be bonded. For example, a substrate 100 including a peripheral circuit region PR and a substrate 100 including a unit region CER may be bonded.

[0015] The cell region CER may be a region where stacked memory cells are formed. For example, a cell array including a memory string may be located in the cell region CER. In the peripheral circuit region PR, a peripheral circuit may be provided for driving the cell array formed in the cell region CER. The cell region CER may also include a contact structure connected to the peripheral circuit of the peripheral circuit region PR.

[0016] According to the above structure, the substrate 100 may include a chip region CHR and a protection region GR surrounding the chip region CHR. The protection region GR may minimize damage to the chip region CHR by cracks generated in a process of separating semiconductor chips along the scribe lane region SLR.

[0017] FIG. 2A to FIG. 2C is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2A and Figure 2B It can be a floor plan, Figure 2C Can be Figure 2A The cross-sectional view AA′, Figure 2B The cross-sectional view BB' and the cross-sectional view CC' of FIG.

[0018] Reference FIG. 2A to FIG. 2C , the semiconductor device may include a semiconductor chip 200. The semiconductor chip 200 may include a chip region CHR and a protection region GR. The gate structure 210G may be located on the semiconductor chip 200. The gate structure 210G may be formed at a position corresponding to the chip region CHR or the protection region GR of the semiconductor chip 200. The gate structure 210G may include the chip region CHR and the protection region GR. A portion of the gate structure 210G may be a stack 210. Here, in the manufacturing process, the stack 210 may be retained without being replaced by the gate structure 210G.

[0019] The chip region CHR of the stack 210 may include a first unit region CER1 where a contact structure 220 connected to a peripheral circuit is located, a second unit region CER2 where a cell array is located, and a peripheral circuit region (not shown) including a peripheral circuit. For reference, for the convenience of describing the first unit region CER1 and the second unit region CER2, Figure 2A and Figure 2B An enlarged portion of a region may be shown. For example, Figure 2A It may be an enlarged view of the first unit region CER1 of the chip region CHR, Figure 2BIt may be an enlarged view of the second unit region CER2 of the chip region CHR. Here, the first unit region CER1 and the second unit region CER2 may be spaced apart from each other or connected to each other. Alternatively, the first unit region CER1 and the second unit region CER2 may be stacked. The peripheral circuit region may be spaced apart from the first unit region CER1 and the second unit region CER2, or may be stacked with the first unit region CER1 or the second unit region CER2. However, the present disclosure is not limited thereto, and the first unit region CER1, the second unit region CER2, and the peripheral circuit region may be combined and arranged in various methods.

[0020] At least one of the contact structure 220, the first support 240, the channel structure 250, the second support 260, the first contact via 270, the insulating spacer 270S, the slit structure 280, the isolation insulating structure 290, and the second contact via CV may be located in the chip region CHR of the stack 210. For example, at least one of the contact structure 220 and the first support 240 may be located in the first cell region CER1. At least one of the channel structure 250, the second support 260, the first contact via 270, the insulating spacer 270S, the slit structure 280, and the isolation insulating structure 290 may be located in the second cell region CER2. The protection region GR of the stack 210 may include a chip protection structure 230.

[0021] The stack 210 may include an insulating layer 210A and a sacrificial layer 210B alternately stacked. The gate structure 210G may include an insulating layer 210A and a conductive layer 210C alternately stacked. Here, the insulating layer 210A may include an insulating material such as an oxide, and the sacrificial layer 210B may include a sacrificial material such as a nitride. The conductive layer 210C may include a conductive material such as tungsten, polysilicon, or molybdenum.

[0022] Reference Figure 2A and Figure 2C , the contact structure 220 may be located in the chip region CHR. For example, the contact structure 220 may be located in the first cell region CER1. The contact structure 220 may extend through the stack 210. For example, the contact structure 220 may extend into the stack 210 through the mask pattern M. Here, the mask pattern M may be located on the stack 210 and may be retained without being removed during the manufacturing process. The mask pattern M may include polysilicon or the like.

[0023] The sidewall of the contact structure 220 may include a curved surface in a plane defined by a first direction I and a second direction II intersecting the first direction I. For example, the contact structure 220 may have a dumbbell shape. This is because an opening formed corresponding to a position where the contact structure 220 is to be formed in a process of forming the contact structure 220 may be expanded and adjacent openings may be connected. The contact structure 220 may include at least one of titanium nitride, tungsten, molybdenum, and polysilicon.

[0024] The first support 240 may be located in the chip region CHR. For example, the first support 240 may be located in the first cell region CER1. The first support 240 may be arranged around the contact structure 220 in the first direction I and the second direction II. The first support 240 may be used to prevent or reduce bending of the stack 210 during the manufacturing process. The first support 240 may have a structure similar to that of the channel structure 250. For example, the first support 240 may include a first dummy channel structure 240A, a first dummy memory layer 240B surrounding the first dummy channel structure 240A, and a first dummy insulating core 240C in the first dummy channel structure 240A.

[0025] The chip protection structure 230 may be located in the protection region GR. The chip protection structure 230 may extend through the stack 210. For example, the chip protection structure 230 may extend into the stack 210 through the mask pattern M. The chip protection structure 230 may be formed simultaneously with the contact structure 220. The upper surface of the chip protection structure 230 may be located at the same height as the upper surface of the contact structure 220. For example, the upper surface of the chip protection structure 230 may be located at substantially the same height as the upper surface of the contact structure 220. Here, the meaning of "substantially the same" may mean that they are the same, including an error range within the range that can be understood by a person of ordinary skill in the art of the present disclosure. Hereinafter, the present disclosure is described with reference to this point. In addition, the chip protection structure 230 and the contact structure 220 may include substantially the same material. For example, the chip protection structure 230 may include at least one of titanium nitride, tungsten, molybdenum, and polysilicon. However, the present disclosure is not limited thereto, and the chip protection structure 230 and the contact structure 220 may be formed at different times and may include different materials.

[0026] The chip protection structure 230 may have a ring shape in a plane, for example, Figure 2A and Figure 2B The chip protection structure 230 may be a rectangular ring shape shown in the described embodiment. The chip protection structure 230 may surround the chip region CHR and may prevent or reduce damage to the chip region CHR in the process of separating the semiconductor chip. The chip protection structure 230 may include a plurality of first protrusions P1 and a plurality of second protrusions P2. The first protrusion and the second protrusion may each have a concave shape. The chip protection structure 230 may have an annular cross-section (e.g., a rectangular ring shape), and its side includes a continuous concave first protrusion P1 and a second protrusion P2.

[0027] The second protrusions P2 may be individually disposed between a plurality of continuous first protrusions P1, such as Figure 2A and Figure 2B As shown in the described embodiment.

[0028] For example, the first protrusions P1 may be continuously arranged in a pattern of 2 or 3 or more protrusions P1 adjacent to each other. The second protrusions P2 may be individually arranged between the first protrusions P1. Figure 2B As shown, a single second protrusion may be provided every 3 first protrusions in some parts of the ring of the chip protection structure 230, or every 5 protrusions in other parts of the ring of the chip protection structure 230. However, it should be noted that the number of first protrusions and second protrusions may vary according to the design.

[0029] The first protrusion P1 may have a first width D1, and the second protrusion P2 may have a second width D2 greater than the first width D1. For reference, the first protrusion P1 may be formed to have a uniform first width D1 or different first widths D1 during the manufacturing process. For example, the first width D1 may be uniform throughout. The first width D1 may be different at the top, bottom, and side. Since the chip protection structure 230 includes the second protrusion P2 having a relatively large second width D2, even if cracks occur in the process of separating the semiconductor chip, the cracks can be prevented or reduced from occurring in the chip region CHR, and thus the chip region CHR is not damaged.

[0030] Reference Figure 2B and Figure 2C , the channel structure 250 may be located in the chip region CHR. For example, the channel structure 250 may be located in the second cell region CER2. The channel structure 250 may extend through the gate structure 210G. The channel structure 250 may be arranged in the first direction I and the second direction II. The channel structure 250 may be arranged in a staggered shape with misaligned centers. The channel structure 250 may be formed simultaneously with the first support 240. Therefore, the channel structure 250 and the first support 240 may have similar structures. The channel structure 250 may include a channel layer 250A, a memory layer 250B surrounding the channel layer 250A, and an insulating core 250C in the channel layer 250A. The upper surface of the channel structure 250 may be located at substantially the same height as the upper surface of the first support 240.

[0031] The second support 260 may be located in the chip region CHR. For example, the second support 260 may be located in the second cell region CER2. The second support 260 may extend through the gate structure 210G. The second support 260 may be arranged in the first direction I and the second direction II. The second support 260 may be arranged in a staggered shape with misaligned centers. The second support 260 may be formed simultaneously with the channel structure 250 or the first support 240. Therefore, the second support 260 may include a second dummy channel layer 260A, a second dummy memory layer 260B surrounding the second dummy channel layer 260A, and a second dummy insulating core 260C in the second dummy channel layer 260A.

[0032] The first contact via 270 may be located in the chip region CHR. For example, the first contact via 270 may be located in the second cell region CER2. The first contact via 270 may extend through the gate structure 210G. For example, the first contact via 270 may extend into the gate structure 210G through the mask pattern M. The first contact via 270 may be connected to at least one conductive layer 210C. The first contact via 270 may be located between the second supports 260. The first contact via 270 may include a conductive material such as tungsten or molybdenum.

[0033] The insulating spacer 270S may cover the sidewall of the first contact via 270. The insulating spacer 270S may prevent the first contact via 270 from being connected to the remaining conductive layer 210C except for the conductive layer 210C connected to the contact via. The insulating spacer 270S may include an insulating material such as oxide.

[0034] For reference, although not shown in this figure, the semiconductor device may include a plurality of first contact vias 270. The plurality of first contact vias 270 may be respectively connected to the conductive layer 210C of the gate structure 210G. Therefore, the heights of the plurality of first contact vias 270 may be different from each other.

[0035] The second contact via CV may be located in the chip region CHR. The second contact via CV may be connected to the channel structure CH, the first contact via 270, and the contact structure 220, respectively. For example, the second contact via CV may extend through the interlayer insulating layer IL and may be connected to the channel structure CH, the first contact via 270, and the contact structure 220, respectively. The second contact via CV may be electrically connected to the structures in the first cell region CER1 and the second cell region CER2, and may be used to transmit a voltage or current applied to the first cell region CER1 and the second cell region CER2 to the respective structures. Here, the interlayer insulating layer IL may be located on the mask pattern M and may include an insulating material such as an oxide. The second contact via CV may include a conductive material such as tungsten or molybdenum.

[0036] According to the structure as described above, the chip protection structure 230 may include the first protrusion P1 and the second protrusion P2. When the chip protection structure 230 includes the second protrusion P2 having a relatively larger second width D2, cracks may be prevented or reduced from occurring in the chip region CHR during a process of separating semiconductor chips.

[0037] In addition, the contact structure 220 and the chip protection structure 230 may be formed at the same time. Therefore, the upper surface of the contact structure 220 and the upper surface of the chip protection structure 230 may be located at substantially the same height and may include substantially the same material. In addition, the channel structure 250, the first support 240, and the second support 260 may be formed at the same time. Therefore, the channel structure 250, the first support 240, and the second support 260 may have structures similar to each other. The process of forming the semiconductor device can be simplified by unifying the process of forming the contact structure 220 and the chip protection structure 230 and unifying the process of forming the channel structure 250, the first support 240, and the second support 260.

[0038] FIG. 3A to FIG. 7C 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Fig. 6A , Fig. 7A and Figure 7B It is a floor plan. Figure 3C , Figure 4C , Figure 5B , Figure 6B and Figure 7C It is a cross-sectional view of each of Figure A or Figure B. Hereinafter, the contents overlapping with the above contents may be omitted.

[0039] Reference FIG. 3A to FIG. 3C , a first sub-stack 311 may be formed by alternately stacking first material layers 310A and second material layers 310B. A first sub-stack 311 may be formed. A first sacrificial contact through hole 370A1 may be formed in the first sub-stack 311. The first sacrificial contact through hole 370A1 may include a sacrificial material such as polysilicon or carbon. For reference, although one first sacrificial contact through hole 370A1 is shown in the figure, a plurality of first sacrificial contact through holes 370A1 may be formed in the first sub-stack 311. The respective first sacrificial contact through holes 370A1 may be formed at different heights to be connected to the second material layer 310B of the first sub-stack 311.

[0040] Subsequently, a second sub-stack 312 may be formed by alternately stacking a first material layer 310A and a second material layer 310B on the first sub-stack 311. Thus, a stack 310 including the first sub-stack 311 and the second sub-stack 312 may be defined. Thus, the stack 310 may include the first material layer 310A and the second material layer 310B alternately stacked. The stack 310 may include a chip region CHR and a protection region GR surrounding the chip region CHR. The chip region CHR may include a second cell region CER2 and a first cell region CER1. For reference, a first sacrificial contact through hole 370A1 may be formed in the second cell region CER2.

[0041] A first opening OP1 extending through the stack 310 may be formed. The first opening OP1 may extend through the chip region CHR of the stack 310. For example, the first opening OP1 may be formed in the first unit region CER1. The first openings OP1 may be spaced apart from each other. For example, the first openings OP1 may be spaced apart by gripping units. The first openings OP1 belonging to the same group may be spaced apart by a first distance R1, and the first openings OP1 of different groups may be spaced apart by a second distance R2 greater than the first distance R1. Subsequently, a sacrificial contact structure 320A may be formed in the first opening OP1. The sacrificial contact structure 320A may include a sacrificial material such as carbon or polysilicon.

[0042] A second opening OP2 and a third opening OP3 extending through the stack 310 may be formed. The second opening OP2 and the third opening OP3 may extend through the protection region GR and may be spaced apart from each other. When the first opening OP1 is formed, the second opening OP2 and the third opening OP3 may be formed. The second opening OP2 and the third opening OP3 may have similar or different shapes, arrangements or sizes. For example, the second opening OP2 and the third opening OP3 may have a hole shape arranged in the first direction I, and the width of the third opening OP3 may be greater than the width of the second opening OP2. As another example, the second opening OP2 may be arranged in the first direction I, and the third opening OP3 may be arranged in the second direction II intersecting the first direction I. Alternatively, the second opening OP2 may have a hole shape, and the third opening OP3 may have an elliptical shape extending in the second direction II. Subsequently, a sacrificial chip protection structure 330A may be formed in the second opening OP2 and the third opening OP3. When the sacrificial contact structure 320A is formed, the sacrificial chip protection structure 330A may be formed. The sacrificial chip protection structure 330A may include a sacrificial material such as polysilicon or carbon.

[0043] A fifth opening OP5 extending through the chip region CHR of the stack 310 may be formed. For example, the fifth opening OP5 may be formed in the second cell region CER2. The fifth opening OP5 may be formed when the first opening OP1, the second opening OP2, and the third opening OP3 are formed. Subsequently, a channel structure 350 may be formed in the fifth opening OP5. The channel structure 350 may include a channel layer 350A, a memory layer 350B surrounding the channel layer 350A, and an insulating core 350C in the channel layer 350A.

[0044] A sixth opening OP6 extending through the chip region CHR of the stack 310 may be formed. For example, the sixth opening OP6 may be formed in the second cell region CER2. The sixth opening OP6 may be formed when at least one of the first opening OP1, the second opening OP2, the third opening OP3, and the fifth opening OP5 is formed. Subsequently, a first support 340 may be formed in the sixth opening OP6. When forming the channel structure 350, the first support 340 may be formed. The first support 340 may have a structure similar to that of the channel structure 350. The first support 340 may include a first dummy channel layer 340A, a first dummy memory layer 340B surrounding the first dummy channel layer 340A, and a first dummy insulating core 340C in the first dummy channel layer 340A.

[0045] A second supporter 360 may be formed extending through the chip region CHR of the stack 310. The second supporter 360 may be formed simultaneously with at least one of the channel structure 350 and the first supporter 340, and may have a similar structure. The second supporter 360 may include a second dummy channel layer 360A, a second dummy memory layer 360B surrounding the second dummy channel layer 360A, and a second dummy insulating core 360C in the second dummy channel layer 360A.

[0046] Subsequently, a first mask pattern M1 may be formed on the stack 310. Here, the first mask pattern M1 may open a position corresponding to the first sacrificial contact through hole 370A1 and cover the remaining area. Subsequently, the stack 310 may be etched using the first mask pattern M1 as an etching barrier to expose the first sacrificial contact through hole 370A1, and a second sacrificial contact through hole 370A2 may be formed on the first sacrificial contact through hole 370A1. Thus, a sacrificial contact through hole 370A including the first sacrificial contact through hole 370A1 and the second sacrificial contact through hole 370A2 may be formed. Here, the second sacrificial contact through hole 370A2 may include a material substantially the same as the first sacrificial contact through hole 370A1, and may include a sacrificial material such as polysilicon or carbon.

[0047] Reference FIG. 4A to FIG. 4C, a slit SL extending through the chip region CHR of the stack 310 may be formed. The slit SL may extend in the first direction I. Subsequently, the second material layer 310B may be replaced with the third material layer 310C through the slit SL. Here, the second unit region CER2 may be replaced with the third material layer 310C, and the first unit region CER1 may not be replaced with the third material layer 310C and the second material layer 310B may remain. The third material layer 310C may include a conductive material such as tungsten, polysilicon, or molybdenum. Therefore, a gate structure 310G including the first material layer 310A and the third material layer 310C alternately stacked may be formed. However, when the second material layer 310B includes a conductive material, the process of replacing the second material layer 310B with the third material layer 310C may be omitted. In this case, the stack 310 may be used as the gate structure 310G. Subsequently, a slit structure 380 may be formed in the slit SL. Here, the slit structure 380 may include at least one of an insulating material such as oxide, a conductive material, and a semiconductor material.

[0048] An isolation insulating structure 390 may be formed through the chip region CHR of the stack 310. The isolation insulating structure 390 may extend in the first direction I and may be located between the channel structures 350. Here, the isolation insulating structure 390 may be formed as shown in FIG. Figure 4B The slit structure 380 partially penetrates at least one of the channel structures 350. The height of the isolation insulating structure 390 may be less than the height of the slit structure 380. The isolation insulating structure 390 may have a height penetrating the source selection line or the drain selection line. The isolation insulating structure 390 may include an insulating material such as an oxide.

[0049] Reference Figure 5A and Figure 5B , a second mask pattern M2 may be formed on the first mask pattern M1. Here, the second mask pattern M2 may cover at least one of the channel structure 350 and the first support 340, and expose the first opening OP1, the second opening OP2, and the third opening OP3. The second mask pattern M2 may expose the sacrificial contact structure 320A and the sacrificial chip protection structure 330A. Subsequently, the first mask pattern M1, the sacrificial contact structure 320A, and the sacrificial chip protection structure 330A may be etched using the second mask pattern M2 as an etching barrier to reopen the first opening OP1, the second opening OP2, and the third opening OP3.

[0050] Reference Fig. 6A and Figure 6B, the stack 310 may be selectively etched using the second mask pattern M2 as an etching barrier. First, portions of the first material layer 310A exposed by the first opening OP1, the second opening OP2, and the third opening OP3 may be removed. Subsequently, a portion of the second material layer 310B may be removed. The first opening OP1, the second opening OP2, and the third opening OP3 may be expanded by removing the first material layer 310A and the second material layer 310B. The second opening OP2 and the third opening OP3 may be connected to form a fourth opening OP4. When forming the fourth opening OP4, each first opening OP1 may be expanded. Here, the first openings OP1 formed at adjacent positions may be connected. Return to reference Figure 3A , the first openings OP1 spaced apart by a relatively small first distance R1 may be connected to each other. For example, the first openings OP1 belonging to the same group may be connected to each other, and the first openings OP1 of different groups may maintain a spaced-apart state.

[0051] The fourth opening OP4 may be formed in the protection region GR and may have a ring shape surrounding the chip region CHR. Here, the fourth opening OP4 may include protrusions having different widths. Return to reference Figure 3A , the second opening OP2 and the third opening OP3 may have different shapes, arrangements or sizes. For example, the width of the third opening OP3 may be greater than the width of the second opening OP2, and the third opening OP3 may be arranged in the second direction II. Therefore, the fourth opening OP4 may include a protrusion having a relatively large width.

[0052] Reference FIG. 7A to FIG. 7C , a sacrificial material (not shown) may be formed in the first opening OP1 and the fourth opening OP4. Here, the sacrificial material may include a sacrificial material such as polysilicon or tungsten. Subsequently, the second mask pattern M2 may be removed. Subsequently, the sacrificial material formed in the sacrificial contact through hole 370A, the first opening OP1, and the fourth opening OP4 may be removed.

[0053] Subsequently, a contact structure 320 may be formed in the first opening OP1. The contact structure 320 may be formed in the first cell region CER1 and may be connected to a peripheral circuit formed in the chip region CHR. Since the contact structure 320 is formed after the first opening OP1 is expanded and connected to each other, the resistance of the contact structure 320 connected to the peripheral circuit may be reduced. The contact structure 320 may include titanium nitride, tungsten, molybdenum, etc.

[0054] A chip protection structure 330 may be formed in the fourth opening OP4. The chip protection structure 330 may be formed in the protection region GR. When the chip protection structure 330 is formed, the contact structure 320 may be formed. Therefore, the upper surface of the chip protection structure 330 may be located at substantially the same height as the upper surface of the contact structure 320. The chip protection structure 330 may include substantially the same material as the contact structure 320, and may include titanium nitride, tungsten, molybdenum, etc. However, the present disclosure is not limited thereto, and the chip protection structure 330 and the contact structure 320 may be formed at different times. Here, the chip protection structure 330 may include an insulating material such as an oxide. The chip protection structure 330 may prevent or reduce cracks from occurring in the chip region CHR in a process of separating semiconductor chips in a subsequent process.

[0055] When the contact structure 320 and the chip protection structure 330 are formed, the first contact via 370 may be formed. After the sacrificial contact via 370A is removed, the first contact via 370 may be formed. For example, a conductive layer may be formed in the first opening OP1, the fourth opening OP4, and the opening (not shown) formed after the sacrificial contact via 370A is removed. Each of the contact structure 320, the chip protection structure 330, and the first contact via 370 may be formed by planarizing the conductive layer. Before forming the first contact via 370, an insulating spacer 370S may be formed in the opening formed after the sacrificial contact via 370A is removed. For reference, although not shown in the figure, since a plurality of sacrificial contact vias 370A of different heights connected to the corresponding third material layer 310C may be formed in the gate structure 310G, the first contact via 370 may have different heights and may be connected to the corresponding third material layer 310C.

[0056] Subsequently, an interlayer insulating layer IL may be formed on the first mask pattern M1. Subsequently, a second contact via CV may be formed. For example, a second contact via CV extending through the interlayer insulating layer IL and connected to the channel structure 350, the first contact via 370, and the contact structure 320 may be formed. Subsequently, although not shown in the present figure, a dicing process for separating semiconductor chips may be performed. Here, since the chip protection structure 330 of the protection region GR is formed to surround the chip region CHR, damage to the chip region CHR by cracks that may occur during dicing may be prevented or reduced.

[0057] According to the manufacturing method as described above, when the first opening OP1 is formed, the second opening OP2 and the third opening OP3 can be formed. In addition, when the fourth opening OP4 is formed by connecting the second opening OP2 and the third opening OP3, the first opening OP1 can be expanded. Therefore, by unifying the process of forming and expanding the openings OP1, OP2 and OP3, the manufacturing process can be simplified.

[0058] In addition, the second opening OP2 and the third opening OP3 may have different shapes, arrangements or sizes. Therefore, the fourth opening OP4 may include protrusions having different widths and may protect the chip region CHR from cracks occurring in subsequent processes.

[0059] When the fourth opening OP4 is formed, the first opening OP1 may be expanded, and the contact structure 320 may be formed in the expanded first opening OP1 , and thus the resistance of the contact structure 320 connected to the peripheral circuit may be reduced.

[0060] Although the embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings, this is only for describing the embodiments according to the concepts of the present disclosure, and the present disclosure is not limited to the above embodiments. Within the scope of the technical spirit of the present disclosure described in the claims, technicians in the field to which the present disclosure belongs may perform various forms of replacement, modification and change to these embodiments, which also belong to the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

[0061] CROSS-REFERENCE TO RELATED APPLICATIONS

[0062] This application claims priority to Korean Patent Application No. 10-2023-0111529, filed on August 24, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a stack comprising a chip region and a protection region surrounding the chip region; a contact structure, the contact structure being located in the chip region; as well as A chip protection structure is located in the protection region and includes a first protrusion protruding with a first width and a second protrusion protruding with a second width greater than the first width.

2. The semiconductor device according to claim 1, wherein In a plan view, the chip protection structure has a ring shape.

3. The semiconductor device according to claim 1, wherein An upper surface of the contact structure is located at the same height as an upper surface of the chip protection structure.

4. The semiconductor device according to claim 1, wherein The contact structure and the chip protection structure include the same material.

5. The semiconductor device according to claim 4, wherein: The contact structure and the chip protection structure include at least one of titanium nitride, tungsten and molybdenum.

6. The semiconductor device according to claim 4, wherein: The contact structure and the chip protection structure include insulating materials.

7. The semiconductor device according to claim 1, further comprising: A channel structure is located in the chip region.

8. The semiconductor device according to claim 7, further comprising: A support is provided in the chip region and is arranged around the contact structure in a first direction and a second direction intersecting the first direction.

9. The semiconductor device according to claim 8, wherein: An upper surface of the channel structure is located at the same height as an upper surface of the support.

10. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stack including a chip region and a protection region surrounding the chip region; forming a first opening extending through the chip region of the stack; forming a second opening and a third opening extending through the protected area of ​​the stack and spaced apart from each other; forming a fourth opening by connecting the second opening and the third opening; forming a contact structure in the first opening; as well as A chip protection structure is formed in the fourth opening.

11. The method according to claim 10, wherein: When forming the fourth openings, each of the first openings is expanded.

12. The method according to claim 10, wherein: When the contact structure is formed, the chip protection structure is formed.

13. The method according to claim 10, wherein: When the first opening is formed, the second opening and the third opening are formed.

14. The method according to claim 10, further comprising the steps of: forming a fifth opening extending through the chip region; as well as A channel structure is formed in the fifth opening.

15. The method according to claim 14, further comprising the steps of: forming a mask pattern covering the channel structure and exposing the first opening, the second opening, and the third opening, The first opening, the second opening, and the third opening are selectively expanded by using the mask pattern.

16. The method according to claim 14, wherein: When the fifth opening is formed, the first opening, the second opening, and the third opening are formed.

17. The method according to claim 10, further comprising the steps of: forming a sixth opening extending through the chip region; as well as A support is formed in the sixth opening.

18. The method according to claim 17, further comprising the steps of: forming a mask pattern covering the support and exposing the first opening, the second opening, and the third opening, The first opening, the second opening, and the third opening are selectively expanded by using the mask pattern.

19. The method according to claim 17, wherein: When the sixth opening is formed, the first opening, the second opening, and the third opening are formed.

20. The method according to claim 10, wherein: A width of the third opening is greater than a width of the second opening.

21. The method according to claim 10, wherein: The second opening has a circular shape, and the third opening has an elliptical shape.

22. The method according to claim 10, wherein: The second openings are arranged in a first direction, and the third openings are arranged in a second direction crossing the first direction.

23. A semiconductor device, comprising: a stack comprising a chip region and a protection region surrounding the chip region; a contact structure, the contact structure being located in the chip region; as well as A chip protection structure is located in the protection area, the chip protection structure has a rectangular ring-shaped cross section, and a side surface includes a continuous concave protrusion.

24. The semiconductor device according to claim 23, in, The continuous concave protrusions include a first protrusion of a first width and a second protrusion of a second width, and Wherein, the second width is greater than the first width.

25. The semiconductor device according to claim 24, wherein: The second protrusions are individually disposed between a plurality of continuous first protrusions.

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