Semiconductor device

Abstract

Provided is a semiconductor device capable of reducing timing deviation when a plurality of semiconductor elements are simultaneously switched. The semiconductor device includes: three or more semiconductor elements connected in parallel with each other; and a wiring substrate disposed on the semiconductor elements, each semiconductor element having a control electrode and being an element that is switched by a voltage applied to the control electrode, the wiring substrate having an insulating layer; and a first wiring pattern that is disposed on the opposite side of the semiconductor elements with the insulating layer interposed therebetween, and that connects the control electrodes of the respective semiconductor elements to each other. The first wiring pattern includes equal-length wirings of the same number as the semiconductor elements, and voltage input points that input voltages to the control electrodes of the respective semiconductor elements via the respective equal-length wirings, and the control electrodes of the respective semiconductor elements are connected to the voltage input points only through the equal-length wirings extending in different directions from the voltage input points.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Conventionally, as a semiconductor device, there is known a power system semiconductor device (power module) that performs power control or power supply. Such a semiconductor device includes, for example, a plurality of semiconductor elements having gate electrodes, and the gate electrodes are electrically connected to each other so that the plurality of semiconductor elements perform switching operations simultaneously (for example, see Patent Document 1).

[0003] <Prior Art Literature>

[0004] <Patent Documents>

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-125546 Summary of the invention

[0006] <Problems to be Solved by the Invention>

[0007] However, when a plurality of semiconductor elements are switched simultaneously, it is difficult to match the timing of the switching operations.

[0008] In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device capable of reducing timing deviation when a plurality of semiconductor elements are switched simultaneously.

[0009] <Methods used to solve the problem>

[0010] The semiconductor device comprises: more than three semiconductor elements connected in parallel with each other; and a wiring substrate arranged on the semiconductor elements, each of the semiconductor elements having a control electrode and being an element switched by a voltage applied to the control electrode, the wiring substrate having an insulating layer; and a first wiring pattern arranged on the side opposite to the semiconductor element across the insulating layer and connecting the control electrodes of each of the semiconductor elements to each other, the first wiring pattern comprising the same number of equal-length wirings as the semiconductor elements, and a voltage input point for inputting a voltage to the control electrode of each of the semiconductor elements via each of the equal-length wirings, the control electrode of each of the semiconductor elements being connected to the voltage input point only via the equal-length wirings extending in different directions from the voltage input point.

[0011] <Effects of the Invention>

[0012] According to the disclosed technology, it is possible to provide a semiconductor device capable of reducing timing variations when a plurality of semiconductor elements are switched simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A , Figure 1B FIG. 1 is a diagram schematically showing a semiconductor device according to a first embodiment.

[0014] Figure 2A , Figure 2B , Figure 2C FIG. 1 is a diagram exemplarily showing a manufacturing process of a semiconductor device according to the first embodiment (part 1).

[0015] Figure 3A , Figure 3B This is a diagram (part 2) schematically showing the manufacturing process of the semiconductor device according to the first embodiment.

[0016] Figure 4A , Figure 4B FIG. 1 is a diagram schematically showing a semiconductor device according to Modification 1 of the first embodiment.

[0017] Figure 5 FIG. 1 is a plan view exemplarily showing a semiconductor device according to a second modification of the first embodiment.

[0018] Figure 6 FIG. 1 is a plan view exemplarily showing a semiconductor device according to Modification 3 of the first embodiment.

[0019] Fig. 7A , Figure 7B FIG. 1 is a diagram schematically showing a semiconductor device according to a fourth modification of the first embodiment.

[0020] Figure 8 FIG. 1 is a plan view exemplarily showing a semiconductor device according to a fifth modification of the first embodiment.

[0021] Explanation of symbols

[0022] 1, 1A, 1B, 1C, 1D, 1E Semiconductor devices

[0023] 10 Wiring substrate

[0024] 11 Insulation layer

[0025] 12.13 Metal layer

[0026] 20 Semiconductor components

[0027] 21 Semiconductor substrate

[0028] 22, 23, 24 electrodes

[0029] 22x recess

[0030] 30 Wiring substrate

[0031] 30x, 332x through hole

[0032] 30y Degassing hole

[0033] 31 Insulation layer

[0034] 32 Adhesive layer

[0035] 33 Wiring Layer

[0036] 40 Joint

[0037] 50 Sealing resin

[0038] 60 Connecting parts

[0039] 331, 332 Wiring pattern DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that in each of the drawings, the same components may be given the same reference numerals and repeated descriptions may be omitted.

[0041] <First Embodiment>

[0042] [Semiconductor devices]

[0043] Figure 1A , Figure 1B is a diagram exemplarily showing a semiconductor device according to a first embodiment, Figure 1A It is a top view. Figure 1B is along Figure 1A Cross-sectional view along line AA.

[0044] like Figure 1A , Figure 1B As shown, the semiconductor device 1 includes a wiring substrate 10, a plurality of semiconductor elements 20, a wiring substrate 30, a bonding portion 40, and a sealing resin 50. It should be noted that, although the present invention may include three or more semiconductor elements, an example of a case where four semiconductor elements 20 are included is described in the first embodiment.

[0045] In this embodiment, for convenience, the wiring substrate 30 side of the semiconductor device 1 is regarded as the upper side, and the wiring substrate 10 side is regarded as the lower side. In addition, the surface of the wiring substrate 30 side of each part is regarded as the upper surface, and the surface of the wiring substrate 10 side is regarded as the lower surface. However, the semiconductor device 1 can also be used in an upside-down state, or can be arranged at any angle. In addition, the top view refers to the view obtained by observing the object from the normal direction of the upper surface of the wiring substrate 30, and the top view shape refers to the shape obtained by observing the object from the normal direction of the upper surface of the wiring substrate 30.

[0046] The wiring substrate 10 is formed in a flat plate shape. The wiring substrate 10 can have any planar shape and any size. Figure 1A , Figure 1B In the example shown in FIG. 1 , the planar shape of the wiring substrate 10 is a rectangular shape.

[0047] The wiring substrate 10 includes an insulating layer 11, a metal layer 12, and a metal layer 13. The thermal expansion coefficient of the wiring substrate 10 may be, for example, approximately 2 ppm / °C to 7 ppm / °C.

[0048] The insulating layer 11 may be formed of ceramics such as oxide ceramics or non-oxide ceramics. The oxide ceramics may include, for example, aluminum oxide (Al 2 O 3 )、ZrO 2 ) etc. As non-oxide ceramics, for example, aluminum nitride (AlN), silicon nitride (Si 3 N 4 ) etc. The thickness of the insulating layer 11 may be, for example, about 200 to 400 μm.

[0049] The metal layer 12 is formed on the upper surface of the insulating layer 11. The metal layer 12 may be in any pattern. The metal layer 12 may also be formed in a solid shape. The metal layer 13 may be used as a wiring layer for electrical connection. As the material of the metal layer 12, copper or a copper alloy may be used, for example. The thickness of the metal layer 12 may be, for example, about 100 μm to 800 μm. The thermal expansion coefficient of the metal layer 12 may be, for example, about 15 ppm / °C to 18 ppm / °C.

[0050] As required, a surface treatment layer can be formed on the surface (upper surface and side surface, or only upper surface) of the metal layer 12. As the surface treatment layer, metal layers such as Au layer, Ni layer / Au layer, Ni layer / Pd layer / Au layer, Ni layer / Ag layer can be included. As the Au layer, Ni layer, Pd layer, Ag layer, for example, a metal layer (electroless plated metal layer) formed by electroless plating can be used. It should be noted that the Au layer is a metal layer composed of Au or Au alloy, the Ni layer is a metal layer composed of Ni or Ni alloy, the Pd layer is a metal layer composed of Pd or Pd alloy, and the Ag layer is a metal layer composed of Ag or Ag alloy.

[0051] The metal layer 13 is formed on the lower surface of the insulating layer 11. The metal layer 13 may be in any pattern. The metal layer 13 may also be formed in a solid shape. For example, the metal layer 13 may be formed to extend over the entire surface of the lower surface of the insulating layer 11 except for the outer peripheral edge portion. The metal layer 13 may not be used for electrical connection. For example, the metal layer 13 may be used as a reinforcement layer for suppressing warping of the wiring substrate 10. The metal layer 13 may also be used as a heat dissipation component.

[0052] As the material of the metal layer 13, copper or a copper alloy can be used, for example. It should be noted that, as required, the above-mentioned surface treatment layer can be formed on the surface (lower surface and side surface, or only lower surface) of the metal layer 13. The thickness of the metal layer 13 can be, for example, about 100 μm to 800 μm. The thickness of the metal layer 13 can be, for example, the same as that of the metal layer 12, or thinner than the metal layer 12.

[0053] Each semiconductor element 20 is bonded to the upper surface of the metal layer 12 of the wiring substrate 10 via a conductive bonding portion 40. As a material for the bonding portion 40, for example, a sintered material of a metal can be used. As a sintered material, for example, a sintered material having silver (Ag) particles as a main component (silver sintered material) or a sintered material having copper particles as a main component (copper sintered material) can be used. In addition, as a material for the bonding portion 40, for example, a conductive paste such as solder or silver paste or a metal brazing material can be used. The thickness of the bonding portion 40 can be, for example, about 20 μm to 60 μm.

[0054] Each semiconductor element 20 is, for example, a power semiconductor element. Each semiconductor element 20 has a control electrode and is an element that switches by a voltage applied to the control electrode. The semiconductor element 20 includes, for example, an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a diode.

[0055] In the first embodiment, the semiconductor element 20 is a MOSFET. The planar shape of the semiconductor element 20 may be any shape and any size. The planar shape of the semiconductor element 20 is formed into a rectangular shape, for example. The thickness of the semiconductor element 20 may be, for example, about 50 μm to 600 μm. The thermal expansion coefficient of the semiconductor element 20 may be, for example, about 3 ppm / °C to 6 ppm / °C.

[0056] The semiconductor element 20 includes a semiconductor substrate 21, an electrode 22, an electrode 23, and an electrode 24. The electrode 23 is a control electrode of the semiconductor element 20. The semiconductor substrate 21 is formed of, for example, silicon (Si) or silicon carbide (SiC).

[0057] Electrodes 22 and 23 are formed on the upper surface of each semiconductor substrate 21. Electrode 22 and electrode 23 are arranged to be separated from each other. For example, in a top view, electrode 22 is roughly rectangular and has a recess 22x opened to one side. In a top view, electrode 23 can be arranged in recess 22x to be separated from electrode 22. Electrode 22 is, for example, a source electrode of a MOSFET. Electrode 23 is, for example, a gate electrode of a MOSFET. In addition, electrode 24 is formed on the lower surface of each semiconductor substrate 21. Electrode 24 is, for example, a drain electrode of a MOSFET.

[0058] As the material of the electrodes 22, 23 and 24, for example, metals such as aluminum (Al) or copper (Cu), or alloys containing at least one metal selected from these metals can be used. It should be noted that the above-mentioned surface treatment layer can be formed on the surfaces of the electrodes 22, 23 and 24 as needed.

[0059] Each semiconductor element 20 is arranged to be rotated by a certain angle relative to the adjacent semiconductor element 20. In the first embodiment, each semiconductor element 20 is arranged to be rotated by 90 degrees relative to the adjacent semiconductor element 20. Figure 1A , the upper right semiconductor element 20 is arranged to be rotated 90 degrees in the clockwise direction relative to the upper left semiconductor element 20. In addition, the lower right semiconductor element 20 is arranged to be rotated 90 degrees in the clockwise direction relative to the upper right semiconductor element 20. In addition, the lower left semiconductor element 20 is arranged to be rotated 90 degrees in the clockwise direction relative to the lower right semiconductor element 20. In addition, the upper left semiconductor element 20 is arranged to be rotated 90 degrees in the clockwise direction relative to the lower left semiconductor element 20. It should be noted that whether the semiconductor element 20 is rotated can be confirmed by the position of the electrode 23 in the top view.

[0060] The wiring substrate 30 is arranged on the semiconductor element 20. The wiring substrate 30 is formed in a flat plate shape. The wiring substrate 30 can be set to any plane shape and any size. Figure 1A , Figure 1B In the example of , the planar shape of the wiring substrate 30 is a rectangular shape. The thickness of the wiring substrate 30 may be, for example, about 200 to 400 μm. The thermal expansion coefficient of the wiring substrate 30 may be, for example, about 20 ppm / °C to 25 ppm / °C. The wiring substrate 30 may be, for example, arranged so that its entirety overlaps with the wiring substrate 10 in a plan view.

[0061] The wiring substrate 30 includes an insulating layer 31, an adhesive layer 32, and a wiring layer 33. The insulating layer 31 is bonded to the semiconductor element 20 via the adhesive layer 32. As a material for the insulating layer 31, an insulating resin such as a polyimide resin or a polyester resin can be used. The thickness of the insulating layer 31 can be, for example, about 30 μm to 100 μm.

[0062] The adhesive layer 32 is formed under the insulating layer 31. The thickness of the adhesive layer 32 can be, for example, about 20 μm to 45 μm. As the adhesive layer 32, for example, an epoxy-based, polyimide-based or silicone-based adhesive can be used. The adhesive layer 32 can be configured to embed a portion of the semiconductor element 20. In other words, a portion of the semiconductor element 20 can be buried in the adhesive layer 32. For example, the outer peripheral edge portions of the electrodes 22 and 23 of the semiconductor element 20 can be buried in the adhesive layer 32. In addition, the upper portion of the side surface of the semiconductor element 20 can be covered by the adhesive layer 32.

[0063] The wiring substrate 30 is provided with a through hole 30x that penetrates the insulating layer 31 and the adhesive layer 32 in the thickness direction. The through hole 30x is formed, for example, to expose a portion of the upper surface of the electrodes 22 and 23. The planar shape of the through hole 30x is, for example, circular. A plurality of through holes 30x may be provided at a position corresponding to one electrode.

[0064] The wiring layer 33 is formed on one side of the insulating layer 31. The wiring layer 33 may include wiring patterns 331 and 332 arranged on the same side of the insulating layer 31. The wiring patterns 331 and 332 are arranged on the side opposite to the semiconductor element 20 across the insulating layer 31. The wiring patterns 331 and 332 include a planar wiring formed on the upper surface of the insulating layer 31 and a via wiring formed in the through hole 30x. Figure 1A In the example of FIG. 3 , the wiring pattern 331 is surrounded by the wiring pattern 332 in the top view.

[0065] The wiring pattern 331 connects the electrodes 23, which are control electrodes of the semiconductor elements 20. The wiring pattern 332 connects the electrodes 22 of the semiconductor elements 20. It should be noted that the metal layer 12 of the wiring substrate 10 connects the electrodes 24 of the semiconductor elements 20. In this way, the semiconductor elements 20 are connected in parallel.

[0066] The wiring pattern 331 includes the same number of equal-length wirings as the semiconductor elements 20, and voltage input points I for inputting voltages to the electrodes 23, which are control electrodes of the semiconductor elements 20, via the respective equal-length wirings. Figure 1A In FIG. 1 , the equal-length wiring is the wiring that connects the voltage input point I to each electrode 23. In other words, the voltage input point I is defined at a position equidistant from each electrode 23. Figure 1A In the example of , in the top view, four L-shaped equal-length wirings are connected near the voltage input point I, and the wiring pattern 331 is swastika-shaped. The respective equal-length wirings preferably have the same width.

[0067] As a material of the wiring layer 33, copper or a copper alloy may be used, for example. It should be noted that, as required, the above-mentioned surface treatment layer may be formed on the surface (upper surface and side surface, or only upper surface) of the wiring layer 33. The thermal expansion coefficient of the wiring layer 33 may be, for example, about 15 ppm / °C to 18 ppm / °C. The thickness of the wiring layer 33 may be, for example, about 50 μm to 200 μm.

[0068] It should be noted that in the present invention, when there are n semiconductor elements (n is a natural number greater than 3), in the top view, the wiring pattern 331 and the electrode 23 as the control electrode of each semiconductor element 20 can be n-fold symmetric with respect to the voltage input point I. Figure 1A , Figure 1B In the example, there are four semiconductor elements 20, and in the plan view, the wiring pattern 331 and the electrodes 23 serving as control electrodes of the respective semiconductor elements 20 are four-fold symmetric with respect to the voltage input point I.

[0069] The sealing resin 50 seals the semiconductor element 20 arranged between the wiring substrate 10 and the wiring substrate 30. As the material of the sealing resin 50, for example, a non-photosensitive insulating resin with a thermosetting resin as the main component can be used. Specifically, as the material of the sealing resin 50, for example, insulating resins such as epoxy resins or polyimide resins, or resin materials in which fillers such as silicon dioxide or aluminum oxide are mixed into these resins can be used. As the sealing resin 50, for example, a molding resin can be used. The thermal expansion coefficient of the sealing resin 50 can be, for example, about 5ppm / °C to 18ppm / °C. It should be noted that the metal layer 12 is pulled out to the outside of the sealing resin 50 to enable electrical connection.

[0070] In this way, in the semiconductor device 1, the electrode 23 (for example, the gate electrode of MOSFET) serving as the control electrode of each semiconductor element 20 is connected to the voltage input point I only through equal-length wiring extending in different directions from the voltage input point I. That is, the wiring lengths connected from the voltage input point I to the electrode 23 serving as the control electrode of each semiconductor element 20 are the same. As a result, it is possible to reduce the timing deviation when the control voltage is input from the voltage input point I to each semiconductor element 20 so that each semiconductor element 20 performs a switching action at the same time. In addition, the current flowing to the electrode 24 (for example, the drain electrode of MOSFET) of each semiconductor element 20 can be equalized. It should be noted that the above-mentioned effect is further increased by making the widths of the equal-length wirings connected from the voltage input point I to the electrode 23 serving as the control electrode of each semiconductor element 20 the same.

[0071] In addition, it is preferable that each semiconductor element 20 is arranged to be rotated at a certain angle relative to the adjacent semiconductor element 20, so that each electrode 23 can be easily connected to the voltage input point I through equal-length wiring. In the case where each semiconductor element 20 is arranged to be rotated 90 degrees relative to the adjacent semiconductor element 20, since the crystal orientations of each semiconductor element 20 are different, the apparent strength of the semiconductor device 1 can be improved.

[0072] It should be noted that in the example described in FIG. 3 of Patent Document 1, the control electrodes of each semiconductor element are not connected to the voltage input point only by equal-length wiring extending in different directions from the voltage input point. In the example described in FIG. 3 of Patent Document 1, the gate circuit pattern is formed by connecting the L portion 24a, which is L-shaped in the top view, with the H portion 24b, which is H-shaped in the top view. In this structure, it is not preferred because it is easy to generate current concentration to the semiconductor element. For example, when the semiconductor element is turned off, the current is temporarily concentrated to the semiconductor element with a lower threshold voltage due to the deviation of the threshold voltage of the gate, but in the structure of Patent Document 1, the H portion 24b is divided into 2 on the left and 2 on the right, so if the threshold voltage of one side increases and a deviation occurs, the current is easily concentrated on the other side. In addition, oscillation is easy to occur.

[0073] In contrast, in the semiconductor device 1, the electrodes 23 serving as control electrodes of the semiconductor elements 20 are connected to the voltage input point I only through equal-length wirings extending in different directions from the voltage input point I, and there is no branch in the wiring pattern 331 as in Patent Document 1. Therefore, even if the threshold voltage of one semiconductor element 20 increases and a deviation occurs, the other three semiconductor elements 20 can receive current equally, so that current concentration to a specific semiconductor element 20 is unlikely to occur, and oscillation is unlikely to occur.

[0074] In addition, if there is a branch in the structure of Patent Document 1, the resin needs to be routed from both sides of the branch when forming the sealing resin, so it is easy to form a void in the sealing resin. In the semiconductor device 1, since the wiring pattern 331 does not have a branch in Patent Document 1, the resin easily flows and it is difficult to form a void in the sealing resin.

[0075] It should be noted that the semiconductor device 1 may not include the wiring substrate 10. In this case, the metal layer 12 for connecting the electrodes 24 to each other is provided on the lower surface side of the semiconductor element 20. In other words, the semiconductor device 1 may include only the metal layer 12 instead of the wiring substrate 10.

[0076] [Method for manufacturing semiconductor device]

[0077] Next, a method for manufacturing the semiconductor device 1 will be described. For convenience of description, components that will eventually become components of the semiconductor device 1 are denoted by reference numerals of the final components.

[0078] First, in Figure 2A In the process shown in the figure, a sheet-like insulating layer 31 is prepared, and an adhesive layer 32 is formed on the lower surface of the insulating layer 31. Then, through holes 30x are formed at required locations of the insulating layer 31 and the adhesive layer 32. The through holes 30x can be formed by, for example, using CO 2 It is formed by laser processing such as laser or UV-YAG laser.

[0079] Then, in Figure 2B In the illustrated process, the semiconductor element 20 is fixed to the lower surface side of the insulating layer 31 by the adhesive layer 32. The semiconductor element 20 is fixed so that a part of the upper surface of the electrodes 22 and 23 is exposed in the through hole 30x.

[0080] Then, in Figure 2C In the process shown in FIG. 1 , a wiring layer 33 is formed on the insulating layer 31. Thus, a wiring substrate 30 having the insulating layer 31, the adhesive layer 32, and the wiring layer 33 is completed. The wiring layer 33 is formed to include wiring patterns 331 and 332 arranged on the same side of the insulating layer 31. The wiring pattern 331 is electrically connected to the electrode 23, and the wiring pattern 332 is electrically connected to the electrode 22. The wiring patterns 331 and 332 are formed to Figure 1A The wiring patterns 331 and 332 include a planar wiring formed on the upper surface of the insulating layer 31 and a via wiring formed in the through hole 30x. The wiring patterns 331 and 332 can be formed using various wiring forming methods such as a semi-additive method.

[0081] Then, in Figure 3A In the process shown in FIG. 1 , a wiring substrate 10 is prepared in which a metal layer 12 is formed on the upper surface and a metal layer 13 is formed on the lower surface. Then, a bonding portion 40 is formed on the upper surface of the metal layer 12. Figure 1A , Figure 1B The four locations where the semiconductor element 20 is arranged as shown form a joint 40. The joint 40 can be formed, for example, by applying a paste-like sintering material (sintering paste) using a printing method or a dispenser method. As the sintering paste, for example, a silver sintering paste obtained by dispersing silver particles in an organic solvent can be used. As the printing method, for example, a screen printing method or a stencil printing method can be used.

[0082] Next, the semiconductor element 20 mounted on the wiring substrate 30 is placed on the upper surface of each joint 40. More specifically, the semiconductor element 20 is placed on the upper surface of the joint 40 so that the electrode 24 formed on the lower surface of the semiconductor element 20 is in contact with the upper surface of the joint 40.

[0083] Next, the bonding portion 40 is heated to be sintered. Thus, the metal layer 12 and the electrode 24 of the semiconductor element 20 are bonded via the bonding portion 40. That is, the semiconductor element 20 is bonded to the metal layer 12 via the bonding portion 40. The electrodes 24 of the semiconductor elements 20 are connected in parallel via the metal layer 12.

[0084] Then, in Figure 3B In the process shown, a sealing resin 50 is formed to seal the semiconductor element 20 provided between the wiring substrate 10 and the wiring substrate 30. The sealing resin 50 can be formed, for example, to expose the upper surface of the wiring layer 33 and the lower surface of the metal layer 13 and cover the other parts. The sealing resin 50 can be formed, for example, by a transfer molding method, a compression molding method, or an injection molding method. Through the above process, the semiconductor device 1 is completed.

[0085] <Modification of the First Embodiment>

[0086] The modification of the first embodiment shows an example of a semiconductor device different from the first embodiment in the number of semiconductor elements, wiring pattern shape, etc. In the modification of the first embodiment, description of components identical to those of the embodiment already described may be omitted.

[0087] Figure 4A , Figure 4B is a diagram exemplarily showing a semiconductor device according to a first modification of the first embodiment, Figure 4A It is a top view. Figure 4B is along Figure 4A The cross-sectional view of line BB. Figure 4A , Figure 4B As shown, the semiconductor device 1A is different from the semiconductor device 1 in that a degassing hole 30 y is formed penetrating the wiring substrate 30 .

[0088] The degassing hole 30y is a hole for exhaust. A through hole 332x is provided at a position of the wiring pattern 332 that overlaps with the degassing hole 30y in a top view. That is, the degassing hole 30y is provided at a position that does not overlap with the wiring patterns 331 and 332 in a top view. The degassing hole 30y is filled with the sealing resin 50. Figure 4A , Figure 4B In the example of FIG. 4 , four degassing holes 30y are provided, but the number thereof may be any number greater than one.

[0089] Thus, by providing the degassing holes 30y in the wiring substrate 30, the gas generated inside the semiconductor device 1A during heating can be released to the outside during the step of forming the sealing resin 50 of the semiconductor device 1A. This can reduce the risk of voids being generated in the sealing resin 50.

[0090] Figure 5 FIG. 1 is a top view exemplarily showing a semiconductor device according to a second variation of the first embodiment. Figure 5 As shown, in the semiconductor device 1B, the shape of the wiring pattern 331 is different from that of the semiconductor device 1 .

[0091] In the semiconductor device 1B, in a top view, four straight lines of equal length are connected near a voltage input point I, and a wiring pattern 331 is in a cross shape. The voltage input point I is located at the center of the cross. In a top view, all imaginary straight lines connecting the center of the electrode 23 of each semiconductor element 20 and the voltage input point I overlap with the wiring pattern 331.

[0092] Thus, by setting the wiring pattern 331 in a cross shape, the distance between the voltage input point I and each electrode 23 can be minimized. Thus, the timing deviation when the control voltage is input from the voltage input point I to each semiconductor element 20 so that each semiconductor element 20 performs a switching operation simultaneously can be further reduced.

[0093] Figure 6 FIG. 1 is a top view exemplarily showing a semiconductor device according to a third variation of the first embodiment. Figure 6 As shown, the semiconductor device 1C is different from the semiconductor device 1 having four semiconductor elements 20 in that it has three semiconductor elements 20 .

[0094] In this way, the semiconductor device can have three semiconductor elements 20. In the semiconductor device 1C, in a plan view, three straight wires of equal length are connected near the voltage input point I, and the wiring pattern 331 is T-shaped. The semiconductor device 1C has the same effect as the semiconductor device 1B.

[0095] Fig. 7A , Figure 7B FIG. 1 is a diagram exemplarily showing a semiconductor device according to a fourth modification of the first embodiment. Fig. 7A It is a top view. Figure 7B is along Fig. 7A The cross-sectional view of the CC line. Fig. 7A , Figure 7B As shown, the semiconductor device 1D is different from the semiconductor device 1 in that it has a connection member 60 .

[0096] The lower surface of the connection component 60 is electrically connected to the metal layer 12 of the wiring substrate 10 via the bonding portion 40. However, the connection component 60 is connected to another wiring pattern different from the wiring pattern connected to the electrode 24 of the semiconductor element 20 in the metal layer 12. The upper surface of the connection component 60 is electrically connected to the wiring pattern 331 of the wiring substrate 30. Thus, the wiring pattern 331 is electrically connected to the metal layer 12 via the connection component 60.

[0097] The connection member 60 is, for example, a column extending in the thickness direction of the semiconductor device 1D. The connection member 60 is, for example, a metal column. As a material of the connection member 60, copper or a copper alloy can be used, for example. The thickness of the connection member 60 can be, for example, substantially the same as the thickness of the semiconductor element 20. The thickness of the connection member 60 can be, for example, about 50 μm to 600 μm. The upper surface of the connection member 60 can be, for example, set to the same plane as the upper surfaces of the electrodes 22 and 23 of the semiconductor element 20.

[0098] In this way, the wiring pattern 331 of the wiring substrate 30 may include a wiring electrically connected to the metal layer 12 via the connection component 60. That is, the connection component 60 may be arranged in a region where the semiconductor element 20 is not arranged in a top view, and the wiring pattern 331 of the wiring substrate 30 may be connected to the metal layer 12 of the wiring substrate 10. The length of the wiring may be different from the length of the three equal-length wirings. A voltage is input to the voltage input point I via the metal layer 12 and the connection component 60.

[0099] Figure 8 FIG. 1 is a top view exemplarily showing a semiconductor device according to a fifth variation of the first embodiment. Figure 8 As shown, the semiconductor device 1E is different from the semiconductor device 1 having four semiconductor elements 20 in that it has six semiconductor elements 20 .

[0100] In this way, the semiconductor device can have six semiconductor elements 20. In the semiconductor device 1E, six straight equal-length wirings are connected near the voltage input point I in the top view. In the top view, the wiring pattern 331 and the electrode 23 as the control electrode of each semiconductor element 20 are 6-fold symmetric with respect to the voltage input point I, or 12-fold symmetric. The semiconductor device 1E has the same effect as the semiconductor device 1B.

[0101] Although preferred embodiments and the like have been described in detail above, the present invention is not limited to the above embodiments and the like, and various modifications and substitutions may be made to the above embodiments and the like without departing from the scope described in the claims.

Claims

1. A semiconductor device comprising: Three or more semiconductor elements are connected in parallel with each other; as well as a wiring substrate arranged on the semiconductor element, Each of the semiconductor elements has a control electrode and is an element that is switched by a voltage applied to the control electrode. The wiring substrate comprises: Insulation layer; as well as a first wiring pattern arranged on the side opposite to the semiconductor element via the insulating layer and connecting the control electrodes of the respective semiconductor elements to each other, The first wiring pattern includes the same number of equal-length wirings as the semiconductor elements, and voltage input points for inputting voltages to the control electrodes of the respective semiconductor elements via the respective equal-length wirings. The control electrodes of the respective semiconductor elements are connected to the voltage input point only through the wirings of equal length extending in different directions from the voltage input point.

2. The semiconductor device according to claim 1, wherein Each of the semiconductor elements is arranged to be rotated at a certain angle relative to an adjacent semiconductor element.

3. The semiconductor device according to claim 1, wherein In a plan view, all imaginary straight lines connecting the center of the control electrode of each of the semiconductor elements and the voltage input point overlap with the first wiring pattern.

4. The semiconductor device according to claim 1, wherein The number of the semiconductor elements is n, where n is a natural number greater than 3. In a plan view, the first wiring pattern and the control electrodes of the respective semiconductor elements are n-fold symmetric with respect to the voltage input point.

5. The semiconductor device according to claim 4, wherein: There are four semiconductor elements. In a top view, the first wiring pattern is in a swastika shape.

6. The semiconductor device according to any one of claims 1 to 5, wherein: Each semiconductor element has a semiconductor substrate. A first electrode and a control electrode are formed on the upper surface of each of the semiconductor substrates. A second electrode is formed on the lower surface of each of the semiconductor substrates. The wiring substrate has a second wiring pattern that is arranged on the same side of the insulating layer as the first wiring pattern and connects the first electrodes to each other. A metal layer for connecting the second electrodes to each other is provided on the lower surface side of the semiconductor element.

7. The semiconductor device according to claim 6, wherein: In a plan view, the first wiring pattern is surrounded by the second wiring pattern.

8. The semiconductor device according to claim 6, wherein: The first wiring pattern includes wiring electrically connected to the metal layer via a connection member.

9. The semiconductor device according to claim 6, wherein: The metal layer is formed on the insulating layer.

10. The semiconductor device according to any one of claims 1 to 5, wherein: A degassing hole is formed penetrating the wiring substrate.

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