Semiconductor device structure and semiconductor package

Abstract

Semiconductor device structures and methods of forming the same are described. The structure includes a through silicon via (TSV) disposed in the interconnect structure and the substrate, a protection structure in the interconnect structure surrounding the TSV, and an active region surrounding the protection structure. The spacing between the protection structure and the active region is free of dummy devices. The embodiment of the invention also relates to a semiconductor package.

Description

Technical Field

[0001] Some embodiments of the present application relate to semiconductor device structures and semiconductor packages. Background Art

[0002] Through silicon vias (TSVs) provide paths (e.g., for electrical connections) between wafers stacked in a vertical direction in an electronic device. TSVs can facilitate increased levels of integration in electronic device packaging, such as three-dimensional integrated circuits (3DICs). 3DICs can be formed by stacking two or more wafers, with one or more TSVs formed through at least one of the two or more wafers to provide a path to connect the two or more wafers to a substrate. TSVs can be formed in a wafer by forming a groove that extends partially through the substrate and filling the groove with a conductive material (such as copper). Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device structure, comprising: a through silicon via (TSV) disposed in an interconnect structure and a substrate; a protection structure located in the interconnect structure surrounding the through silicon via; and an active area surrounding the protection structure, wherein there is no dummy device in the interval between the protection structure and the active area.

[0004] Other embodiments of the present application provide a semiconductor device structure, comprising: a substrate; an interconnect structure disposed above the substrate; a protection structure disposed in the interconnect structure; a first through silicon via (TSV) disposed in the interconnect structure and the substrate, wherein the protection structure surrounds the first through silicon via; and a first boundary region surrounding the protection structure, wherein the first boundary region comprises: a first device adjacent to the protection structure, wherein there is no dummy device in the interval between the protection structure and the first device; and a plurality of conductive components disposed in the interconnect structure above the first device, wherein the plurality of conductive components surround the protection structure.

[0005] Still other embodiments of the present application provide a semiconductor package, comprising: a first die, comprising: a first substrate; a first interconnect structure, arranged below the first substrate; a through silicon via (TSV), arranged in the first substrate and the first interconnect structure; a protection structure surrounding the through silicon via, wherein the protection structure extends in the first interconnect structure; a first device, arranged above the substrate; a first plurality of conductive components, arranged in the first interconnect structure above the first device, wherein there are no pseudo conductive components in the intervals between the first plurality of conductive components and the protection structure; and a second device, arranged adjacent to the first device; and a second die, comprising: a second interconnect structure, arranged above the first die; and a second substrate, arranged above the second interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A and Figure 1B is a diagram of a semiconductor device structure including a through silicon via (TSV) according to some embodiments.

[0008] Figure 1A-1 is a top view of a semiconductor device structure including TSVs according to an alternative embodiment.

[0009] Figure 1A-2 is a top view of a semiconductor device structure including TSVs according to an alternative embodiment.

[0010] Figure 2 is a cross-sectional side view of one of the various stages in fabricating a semiconductor device structure in accordance with some embodiments.

[0011] Figure 3A According to some embodiments Figure 2 An enlarged portion of a semiconductor device structure.

[0012] Figure 3B According to some embodiments Figure 2 An enlarged portion of a semiconductor device structure.

[0013] Figure 4 is a cross-sectional side view of one of the various stages in fabricating a semiconductor device structure in accordance with some embodiments.

[0014] Figure 5 is a cross-sectional side view of one of the various stages in fabricating a semiconductor device structure in accordance with an alternative embodiment.

[0015] Fig. 6A According to some embodiments Figure 5 An enlarged portion of a semiconductor device structure.

[0016] Figure 6B According to some embodiments Figure 5 An enlarged portion of a semiconductor device structure.

[0017] Figure 7 is a cross-sectional side view of one of the various stages in fabricating a semiconductor device structure in accordance with an alternative embodiment.

[0018] Figure 8 is a top view of a semiconductor device structure according to some embodiments.

[0019] FIG. 9A to FIG. 9G According to some embodiments Figure 8 An enlarged portion of a semiconductor device structure.

[0020] Fig. 10A and Fig. 10B is a top view of a semiconductor device structure according to some embodiments.

[0021] Fig.11 and Fig.12 An IC design layout including a semiconductor device structure is shown in accordance with some embodiments.

[0022] FIG. 13A to FIG. 13E A semiconductor package in accordance with some embodiments is shown.

[0023] Fig.14 is a top view of a semiconductor device structure according to an alternative embodiment. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "above," "on," "top," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0026] In some instances, devices (such as semiconductor devices) near through silicon vias (TSVs) suffer severe performance degradation due to stress caused by through silicon vias (TSVs). In order to minimize such performance variations, a keep-out zone (KOZ) is set around the TSV, in which no other active devices can be placed in the KOZ. In some embodiments, in order to reduce the non-uniform load effect, a dummy device is set in the KOZ. For example, the dummy device can be placed between the protection structure and the active device. The dummy device in the KOZ improves the overall uniformity of the distribution of the device, resulting in a uniform load effect. However, since the area is occupied by the dummy device and the TSV is arranged outside the active device area. In some applications, such as face-to-back (F2B) die-to-die (D2D) communication, the TSV spacing determines the bandwidth of the signal. Since the dummy device occupies the area around the TSV, it becomes difficult to achieve TSV spacing reduction. Embodiments of the present disclosure provide a TSV KOZ without a dummy device located between the protection structure and the active device and / or without a dummy conductive component located between the protection structure and the active conductive component. Instead, the boundary cells or boundary tap cells of the standard device are integrated into the TSV KOZ. Benefits such as high signal bandwidth (especially for SoIC F2B stacking), high power efficiency, lower area overhead (e.g., for standard cells and SRAM periphery), better latching (e.g., more boundary tap cells), or better standard cell power, performance, area (PPA) may come from integrating TSVs into standard cells.

[0027] Figure 1A and Figure 1B is a diagram of a semiconductor device structure 100 including TSVs 102 according to some embodiments. Figure 1A is a top view of the semiconductor device structure 100, and Figure 1B is a cross-sectional side view of the semiconductor device structure 100. Figure 1A and Figure 1B As shown in , the semiconductor device structure 100 includes a substrate 101, such as a semiconductor wafer or a semiconductor die. The substrate 101 can be a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The substrate 101 can include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. Active and / or passive devices, such as transistors, diodes, capacitors, resistors, etc., can be formed in and / or on the substrate 101.

[0028] like Figure 1BAs shown in , multiple devices 105 are formed on a substrate 101. The multiple devices 105 may include any suitable devices, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. In some embodiments, the multiple devices 105 are transistors, such as planar field effect transistors (FETs), FinFETs, nanostructure transistors, fork-piece FETs, complementary FETs (CFETs), or other suitable transistors. In some embodiments, the multiple devices 105 include: standard cells (STDs), such as logic gates, such as AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, and XOR gates; and combinational logic circuits, such as multiplexers, flip-flops, adders, and counters. The STDs of the multiple devices 105 may be located in an active region 108, such as Figure 1A . The plurality of devices 105 may also include a boundary cell or a tap cell located in the boundary region 106. The boundary cell may be a cell placed at the boundary of the STD row to protect the STD from external signals. The tap cell may be a cell for preventing latch-up, which is a type of short circuit that sometimes occurs in an integrated circuit. The boundary or tap cell is described in detail below. Because the plurality of devices 105 are active devices, the boundary region 106 is part of the active region 108. In other words, the STD, the tap cell, and the boundary cell are all active devices.

[0029] like Figure 1B As shown in , the interconnect structure 103 is arranged above the substrate 101 and multiple devices 105. The interconnect structure 103 includes multiple dielectric layers 110, such as intermetallic dielectric (IMD) layers. Multiple conductive components 112 are formed in the dielectric layer 110 to provide signals and power to the multiple devices 105. Therefore, the conductive component 112 is an active conductive component. The conductive component 112 can be a wire or a conductive via. The conductive component 112 can be made of one or more conductive materials, such as metal, metal alloy, metal nitride or silicide. For example, the conductive component 112 is made of copper, aluminum, aluminum-copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicon nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials or combinations thereof.

[0030] The semiconductor device structure 100 further includes TSVs 102 disposed in the interconnect structure 103 and the substrate 101. The TSVs 102 include a conductive material such as a metal, for example copper. Figure 1AAs shown in , when viewed from the top, TSV 102 may have a circular shape. TSV 102 may have any suitable shape, such as a rectangle or a square. In some embodiments, TSV 102 has a dimension D ranging from about 0.1 micron to about 10 microns, such as from about 1 micron to about 5 microns. In some embodiments, a liner 118 is formed in an opening in the interconnect structure 103 and the substrate 101, and TSV 102 is formed on the liner 118 in the opening. The liner 118 includes a dielectric material, such as an oxide or a nitride, and may be formed by a conformal process, such as atomic layer deposition (ALD). In some embodiments, a barrier layer (not shown) may be formed on the liner 118, and TSV 102 is formed on the barrier layer. The barrier layer includes a metal or a metal nitride, such as Ti, TiN, Ta, TaN or other suitable materials.

[0031] In some embodiments, a buffer region 116 is formed on the substrate 101 between the plurality of devices 105 and the TSV 102. The buffer region 116 can protect the plurality of devices 105 during the formation of the TSV 102. In some embodiments, the buffer region is not present. For example, during the formation of the opening for the TSV 102, the buffer region is removed by the process of forming the opening.

[0032] As described above, based on the stress caused by the TSV and / or based on the process of forming the TSV, the semiconductor device near the TSV may suffer performance degradation. For example, water vapor and / or sulfur (e.g., generated during a cleaning operation in the process of forming the TSV) may damage the barrier layer of the semiconductor device near the TSV, which may allow the metal of the TSV to diffuse into one or more dielectric layers that electrically insulate the semiconductor device. The diffusion of metal into one or more dielectric layers (e.g., low-k films) may cause the semiconductor device to have an electrical short circuit and / or may damage the structural integrity of the semiconductor device.

[0033] In order to reduce the performance degradation of semiconductor devices near the TSV, a protection structure 111 is formed around the TSV 102 to prevent water vapor and residual ions (e.g., generated during the process of forming the TSV 102) from penetrating the dielectric layer and / or damaging the barrier layer of the semiconductor device, such as the plurality of devices 105 near the TSV 102. Figure 1A and Figure 1B As shown in FIG. 1 , in some embodiments, the protection structure 111 includes a protection ring 104 having a conductive component stack disposed in the interconnect structure 103. In some embodiments, each conductive component of the conductive component stack is a closed loop structure, which is different from the conductive component 112, which is a conductive wire or a conductive via. For example, the protection ring 104 is a continuous wall, such as Figure 1A The width of the closed loop structure can vary, as shown in Figure 1B The material of the guard ring 104 can be the same as the material of the conductive component 112. In some embodiments, the guard ring 104 is formed simultaneously with the conductive component 112. Figure 1B As shown in FIG. 1 , the protection structure 111 includes one protection ring 104. In some embodiments, the protection structure 111 includes a plurality of protection rings 104. For example, in some embodiments, the protection structure 111 includes a first protection ring surrounding the TSV and a second protection ring surrounding the first protection ring.

[0034] The guard ring 104 may further include a dummy device 114 formed on the substrate 101. The dummy device 114 may be a device that is not electrically connected to a signal source, a power source, or any active device, such as a transistor. In some embodiments, the dummy device is a transistor including a gate electrode, a source region, a drain region, and a channel region between the source region and the drain region. The dummy device 114 may be formed with the active device to improve the loading effect. In some embodiments, the dummy device 114 is not present, and the guard ring 104 includes a plurality of conductive components disposed in the interconnect structure 103.

[0035] like Figure 1A As shown in , in some embodiments, the KOZ can be defined by a dimension Dx along the X direction and a dimension Dy along the Y direction. The dimension Dx can extend from the TSV 102 to a position in the active area 108 along the X direction, and the dimension Dy can extend from the TSV 102 to a position in the active area 108 along the Y direction. The boundary area 106 is defined within Dx and Dy, and the boundary cell or tap cell of the active device is placed in the boundary area 106. In some embodiments, the ratio of Dx to Dy is between about zero and about one. The boundary area 106 is part of the active area 108, and the boundary area 106 is also part of the KOZ. In such an embodiment, the size of the KOZ can be the same as the size of the KOZ in which the dummy device is formed. In other words, in a circuit design, the design rules may include a KOZ having dimensions Dx and Dy. However, the design rules are modified so that the boundary cell or tap cell of the active device is placed within the KOZ instead of placing the dummy device within the KOZ. In some embodiments, Figure 1A The ratio of the dimension Dx or Dy shown in FIG. 1 to the dimension D of the TSV 102 is greater than 1, such as from 1 to about 10.

[0036] Figure 1A-1 1 is a top view of a semiconductor device structure 100 including TSV 102 according to an alternative embodiment. In some embodiments, the size of the KOZ is changed in the design rules used to design the circuit. Figure 1A-1 As shown in FIG. 1 , the KOZ is defined by dimensions Dx and Dy, and the dimensions Dx and Dy extend from the TSV 102 to the guard ring 104, as shown in FIG. Figure 1A-1 In some embodiments, the size of the KOZ is substantially smaller than a conventional KOZ, and no active devices are placed in the KOZ. In some embodiments, Figure 1A-1 The ratio of the dimension Dx or Dy shown in FIG. 1 to the dimension D of the TSV 102 is less than 1, such as from 0.1 to about 0.5.

[0037] In some embodiments, Figure 1A and Figure 1A-1 As shown in FIG. 1 , a conductive feature 120 is formed to surround a portion of the guard ring 104 . The conductive feature 120 may include the same material as a gate electrode layer of the active device in the active region 108 . The conductive feature 120 may be formed to protect the device in the active region 108 .

[0038] Figure 1A-2 1 is a top view of a semiconductor device structure 100 including TSV 102 according to an alternative embodiment. In some embodiments, a dummy region 107 is located around the guard ring 104, and the KOZ includes the dummy region 107. The dummy region 107 may be located around the interconnect structure 103 ( Figure 1B ) in the conductive member 112 ( Figure 1B ) and the guard ring 104 ( Figure 1B ) include dummy devices located on the substrate 101 and / or multiple dummy conductive components located above the substrate 101. The boundary region 106 surrounds the dummy region 107, such as Figure 1A-2 In some embodiments, two TSVs 102 may not be placed within the die because the spacing between the TSVs 102 for active devices is reduced due to the presence of the dummy region 107 .

[0039] Figure 2 is a cross-sectional side view of one of the various stages in fabricating a semiconductor device structure 100 in accordance with some embodiments. Figure 2 1 shows a manufacturing stage before forming an opening for TSV 102. Figure 2As shown in , a front-end-of-line (FEOL) process is performed to form a device in region 122, a middle-end-of-line (MOL) process is performed to form a contact in region 124, and a back-end-of-line (BEOL) process is performed to form an interconnect structure 103 in region 125. FEOL generally includes processes associated with manufacturing IC devices (such as transistors). For example, FEOL processes may include forming isolation components, gate structures, and source and drain regions (commonly referred to as S / D regions). MOL generally includes processes associated with manufacturing contacts to conductive components (or conductive regions) of IC devices (such as contacts to gate structures and / or S / D regions). BEOL generally includes processes associated with manufacturing a multi-layer interconnect structure 103, which interconnects IC components manufactured by FEOL and MOL to achieve operation of the IC device.

[0040] like Figure 2 As shown in FIG. 1 , a plurality of devices 105 are located in the active region 108 and the boundary region 106. The dummy devices 114, the conductive features 120, and the buffer region 116 of the guard ring 104 are also formed in the region 122 by the FEOL process. In some embodiments, gate spacers 126 may be formed on opposite sidewalls of the conductive features 120, such as Figure 2 As shown in . A conductive contact 127 is formed in region 124 by an MOL process. The conductive contact 127 may include a conductive material such as TiN, W, Ru, Mo, Co, Cu or other suitable conductive materials. The interconnect structure 103 is formed in region 125 by a BEOL process. A conductive component stack of conductive features 112 and guard ring 104 is formed in dielectric layer 110. For clarity, some conductive features 112 may be omitted. In some embodiments, the conductive features 112 electrically connect the plurality of devices 105 to an external signal and / or power source. In other words, the conductive features 112 may be formed in each dielectric layer 110 from the plurality of devices 105 to the top of the interconnect structure 103. In some embodiments, as Figure 2 As shown in FIG. 1 , the conductive feature 112 is not formed in the dielectric layer 110 over the buffer region 116. Therefore, the area where the opening for the TSV 102 will be formed is free of metal spacers, which makes the opening for the TSV 102 easier to form.

[0041] Figure 3A According to some embodiments Figure 2 The enlarged portion 128 of the semiconductor device structure 100 may be a portion of the buffer region 116. Figure 3AAs shown in , a portion 128 of the buffer region 116 includes a plurality of S / D regions 132 formed over a well region 133. In some embodiments, the S / D region 132 includes an epitaxial component that may be an n-type epitaxial component for an n-type FET (nFET) or a p-type epitaxial component for a p-type FET (pFET). The S / D region 132 including the n-type epitaxial component may include one or more layers of Si, SiP, SiC, and SiCP, and the S / D region 132 including the p-type epitaxial component may include one or more layers of Si, SiGe, and Ge. For a PFET, a p-type dopant, such as boron (B), may also be included in the S / D region 132. In some embodiments, the S / D region 132 includes a first type dopant, such as a p-type or an n-type, and the well region 133 includes a second type dopant opposite to the first type. In other words, a p-type S / D region 132 may be formed on an n-type well region 133, and an n-type S / D region 132 may be formed on a p-type well region 133. In the embodiments of the present disclosure, source region and drain region are used interchangeably, and their structures are substantially the same. In addition, source / drain region can refer to source or drain, individually or collectively depending on the context.

[0042] In some embodiments, the buffer region 116 does not include active devices, and the gate structure and the channel region are removed and replaced with a dielectric material 134. In some embodiments, the device formed on the substrate 101 is a nanostructure device, and the channel region includes a plurality of nanostructures. The dielectric material 134 may include any suitable dielectric material 134, such as SiN. In some embodiments, the structures in the buffer region 116 may be formed simultaneously with the active devices in the active region 108, and the gate structure and the channel region located in the buffer region 116 are replaced with the dielectric material 134 by a continuous polysilicon on diffusion edge (CPODE) process. In some embodiments, the CPODE process does not remove the gate spacer 126 and the inner spacer 136. Since the dielectric material 134 replaces the gate structure, the area where the opening for the TSV 102 will be formed is free of metal spacers.

[0043] like Figure 3A As shown in FIG. 1 , a contact etch stop layer (CESL) 138 is formed on the plurality of S / D regions 132, and a first interlayer dielectric (ILD) layer 140 is formed on the CESL 138. The CESL 138 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 138 is a single layer, such as Figure 3A. In some embodiments, CESL 138 includes two or more layers. Materials for ILD layer 140 may include compounds including Si, O, C and / or H, such as silicon oxide, SiCOH or SiOC. Organic materials such as polymers may also be used for ILD layer 140. ILD layer 140 may be deposited by a PECVD process or other suitable deposition techniques. Another etch stop layer 142 is formed on gate spacers 126, dielectric material 134, CESL 138 and ILD layer 140. Etch stop layer 142 may include the same material as CESL 138 and is formed by the same process as CESL 138. Another ILD layer 144 is formed on etch stop layer 142, another etch stop layer 146 is formed on ILD layer 144, and another ILD layer 148 is formed on etch stop layer 146. ILD layers 144, 148 and etch stop layers 142, 146 are used to form conductive contacts 127 ( Figure 3B ) and conductive vias 156 ( Figure 3B ). Since the structure in the buffer region 116 does not include active devices, the conductive contact 127 and the conductive via 156 are not formed in the ILD and the etch stop layer. The etch stop layer 142, the ILD layer 144 and the conductive contact 127 may be formed in the region 124 ( Figure 2 )middle.

[0044] Figure 3B According to some embodiments Figure 2100. The enlarged portion 130 of the semiconductor device structure 100. The portion 130 may be a portion of the boundary region 106, which is a portion of the active region 108. In some embodiments, the tap cell or boundary cell in the boundary region 106 includes a nanostructure transistor having a plurality of S / D regions 132 disposed above the well region 131. The tap cell may be implemented to prevent a short circuit from the drain to the ground through a parasitic bipolar transistor. In some instances, the tap cell may be used to couple a certain n-type well region (n-well) to Vdd (drain supply voltage or positive supply voltage) and a p-type well region (p-well) on the substrate to Vss (source supply voltage or negative supply voltage). In some embodiments, Vdd is the maximum positive voltage of the STD or IC device, and Vss is the maximum negative voltage of the STD or IC device. Vss may be a ground voltage or may be grounded. The tap cells may take the shape of transistors, but they do not have a functional gate structure. The tap cells implement their anti-latch function through their source / drain regions. Unlike transistors in STDs, the active region in the tap cell does not have a conductivity type that is different from the conductivity type of the underlying well. For example, when the tap cell is formed over an n-well, it has an active region doped with n-type dopants instead of p-type dopants. When the tap cell is formed over a p-well, it has an active region doped with p-type dopants instead of n-type dopants.

[0045] In some embodiments, the well region 131 is different from the well region 133 in that the dopant type of the well region 131 is the same as the dopant type of the S / D region 132. For example, the S / D region 132 may be an n-type region, and the well region 131 is an n-well. The S / D region 132 may be a p-type region, and the well region 131 is a p-well. In some embodiments, for a p-type device, the well region 131 includes SiGe doped with boron. For an n-type device, the well region 131 includes SiP doped with phosphorus. The well region 131 includes the same type of dopant as the dopant of the S / D region 132 formed thereon to implement the function of a tap cell or a boundary cell.

[0046] like Figure 3B As shown in , the nanostructure transistor also includes a gate structure. In some embodiments, each gate structure includes a gate dielectric layer 150, one or more work function layers 152, and a gate electrode layer 154. The channel region may include multiple semiconductor layers 158, and the gate structure surrounds a portion of each semiconductor layer 158. The gate structure is disposed between the internal spacers 136, such as Figure 3B. The semiconductor layer 158 may include any suitable semiconductor material, such as undoped silicon. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 150 and the semiconductor layer 158. In some embodiments, the gate dielectric layer 150 includes one or more dielectric material layers, such as silicon oxide, silicon nitride or high-K dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-K dielectric materials and / or combinations thereof. The gate dielectric layer 150 may be formed by CVD, ALD or any suitable deposition technique. The work function layer 152 may include polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys or other suitable materials. The gate electrode layer 154 may include one or more conductive material layers, such as platinum (Pt), palladium (Pd), tantalum (Ta), ytterbium (Yb), aluminum (Al), silver (Ag), titanium (Ti), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), copper (Cu) or similar materials and / or any combination thereof. The gate electrode layer 154 may be formed by CVD, ALD, electroplating or other suitable deposition techniques.

[0047] Because the tap cell or boundary cell is active, the conductive contact 127 and the conductive via 156 are formed in the boundary region 106. In some embodiments, the conductive via 156 includes the same material as the conductive feature 112. In some embodiments, the conductive via 156 is also the conductive feature 112 and is an interconnect structure 103 ( Figure 2 ). In some embodiments, the devices of the tap cell or the boundary cell are electrically connected to the STD in the active region 108 via the conductive contacts 127, the conductive vias 156, and the conductive features 112. For example, the conductive features 112 electrically connected to the S / D regions 132 in the boundary region 106 may be electrically connected to or in direct contact with the conductive features 112 of the active devices electrically connected to the STD in the active region 108. In some embodiments, the dummy devices (such as the dummy region 107 ( Figure 1A-2 ) is not electrically connected to any active device, signal source, or power source. For example, Figure 1A-2 The semiconductor device structure 100 shown in FIG. 1 may not include the conductive contact 127, the conductive via 156, and / or one or more conductive features 112 electrically connected to the dummy device. In some embodiments, the dummy region 107 ( Figure 1A-2 ) includes an interconnect structure 103 ( Figure 1B ) in the plurality of pseudo conductive components. The pseudo conductive components include conductive wires and conductive vias that are not electrically connected to any active device, signal source, or power source. The pseudo conductive components may be connected to the conductive component 112 ( Figure 1B ) are formed together. In some embodiments, the pseudo conductive component is located in the boundary region 106 ( Figure 1B ) in the conductive member 112 ( Figure 1B ) and the guard ring 104 ( Figure 1B )between.

[0048] In some embodiments, the active devices in the active region 108 are formed simultaneously with the devices formed in the boundary region 106. For example, the active devices in the active region 108 may include S / D regions 132 formed on the well region 133, semiconductor layers 158 located between the S / D regions 132, and a gate structure surrounding a portion of each semiconductor layer 158. The gate structure may include a gate dielectric layer 150, one or more work function layers 152, and a gate electrode layer 154.

[0049] Figure 4 is a cross-sectional side view of one of the various stages in fabricating a semiconductor device structure 100 according to some embodiments. Figure 4 As shown in , the pad 118 and TSV 102 are formed in the interconnect structure 103, the buffer region 116 and the substrate 101. In some embodiments, an opening is first formed in the interconnect structure 103, the buffer region 116 and the substrate 101, and then the pad 118 is formed in the opening, and then the TSV 102 is formed on the pad 118 in the opening. As described above, there is no material made of metal in the portion of the interconnect structure 103 and the buffer region 116 where the opening is formed. Therefore, in the absence of a metallic material, the formation of the opening may be easier. Additional conductive components 160 are formed above the interconnect structure 103, such as a redistribution layer (RDL), a bonding pad and / or a bonding structure. In some embodiments, the conductive via 156 is electrically connected to the active device of the STD in the active area 108 through the RDL.

[0050] Figure 5 is a cross-sectional side view of one of various stages in fabricating a semiconductor device structure 100 in accordance with an alternative embodiment. Figures 2 to 4 The embodiments shown in include active devices that are nanostructure transistors. In some embodiments, the active devices are FinFETs. Figure 5As shown in FIG. 1 , a plurality of devices 105 are FinFETs, and the dummy devices 114 and the buffer region 116 are based on a FinFET structure. In some embodiments, the devices of the tap cell or the boundary cell in the boundary region 106 are adjacent to the dummy devices 114 of the guard ring 104, and the spacing between the devices in the boundary region 106 and the dummy devices 114 is free of dummy devices and / or the spacing between the conductive features 112 in the boundary region 106 and the guard ring 104 is free of dummy conductive features. In some embodiments, only dielectric material (such as dielectric layer 110, CESL 138, ILD layer 140, or other suitable dielectric material) is disposed between the devices in the boundary region 106 and the dummy devices 114. In some embodiments, only dielectric layer 110 is disposed between the conductive features 112 and the guard ring 104.

[0051] Fig. 6A According to some embodiments Figure 5 The enlarged portion 202 of the semiconductor device structure 100 is shown. The portion 202 may be a portion of the buffer region 116. Fig. 6A As shown in FIG. 1 , the portion 202 of the buffer region 116 includes a plurality of S / D regions 132 formed above the well region 133 and a dielectric material 134 formed to replace the gate structure and the channel region. The portion 202 of the buffer region 116 also includes an isolation region 206, such as a shallow trench isolation (STI). The CESL 138, the ILD layers 140, 144, 148, and the etch stop layers 142, 146 may be formed in a manner similar to that of FIG. Figure 3A Formed in a similar manner as described in .

[0052] Figure 6B According to some embodiments Figure 5 The enlarged portion 204 of the semiconductor device structure 100 is shown in FIG. 204. The portion 204 may be a portion of the boundary region 106, which is a portion of the active region 108. In some embodiments, the tap cell or boundary cell in the boundary region 106 includes a FinFET having a plurality of S / D regions 132 disposed above the well region 131. The well region 131 has a dopant type that is the same as the dopant type of the S / D region 132. For example, the S / D region 132 may be an n-type region, and the well region 131 is an n-well. The S / D region 132 may be a p-type region, and the well region 131 is a p-well. In some embodiments, for a p-type device, the well region 131 includes SiGe doped with boron. For an n-type device, the well region 131 includes SiP doped with phosphorus. A gate structure 210 may be formed over the substrate, and a gate spacer 208 may be formed on a sidewall of the gate structure 210. In some embodiments, the gate structure 210 includes a gate dielectric layer, one or more work function layers, and a gate electrode layer. The gate dielectric layer may include a gate dielectric layer 150 ( Figure 3B) of the same material, one or more work function layers may include the same material as the work function layer 152 ( Figure 3B ) and the gate electrode layer may include the same material as the gate electrode layer 154 ( Figure 3B ) The conductive contact 212 is formed in the ILD layers 140, 144 and the etch stop layer 142. A conductive via 216 is formed in the ILD layer 148 and the etch stop layer 146. The conductive contact 212 may include the same conductive contact 127 ( Figure 3B ) and the conductive via 216 may include the same material as the conductive via 156 ( Figure 3B ). In some embodiments, the structure in the boundary region 106 also includes conductive features 214, 218 electrically connected to the gate structure 210. The conductive features 214, 218 may include the same material as the conductive feature 112. In some embodiments, the conductive feature 218 is electrically connected to the gate structure 210 and the S / D region 132.

[0053] Because the tap cell or boundary cell is active, the conductive contact 212 and the conductive via 216 are formed in the boundary region 106. In some embodiments, the conductive via 216 is also a conductive feature 112 and is an interconnect structure 103 ( Figure 2 ). In some embodiments, the devices of the tap cell or the boundary cell are electrically connected to the STD in the active region 108 via the conductive contacts 212, the conductive vias 216, and the conductive features 112. For example, the conductive features 112 electrically connected to the S / D regions 132 in the boundary region 106 may be electrically connected to or in direct contact with the conductive features 112 of the active devices electrically connected to the STD in the active region 108. The dummy devices located between the guard rings and the TSVs of the conventional structure are not electrically connected to any active devices, signal sources, or power sources. For example, the conventional structure may not include the conductive contacts 212, the conductive vias 216, and / or one or more conductive features 112 electrically connected to the dummy devices.

[0054] Figure 7 is a cross-sectional side view of one of the various stages in fabricating a semiconductor device structure 100 according to some embodiments. Figure 7 As shown in , the liner 118 and TSV 102 are formed in the interconnect structure 103, the buffer region 116, and the substrate 101. In some embodiments, an opening is first formed in the interconnect structure 103, the buffer region 116, and the substrate 101, and then the liner 118 is formed in the opening, and then the TSV 102 is formed on the liner 118 in the opening. As described above, there is no material made of metal in the portion of the interconnect structure 103 and the buffer region 116 where the opening is formed. Therefore, in the absence of a metal material, the formation of the opening may be easier. Conductive member 160 is formed above the interconnect structure 103.

[0055] Figure 8 FIG. 1 is a top view of a semiconductor device structure 100 according to some embodiments. Figure 8 As shown in , the buffer region 116 includes the S / D region 132 and the dielectric material 134, and the buffer region 116 is surrounded by the guard ring 104. In some embodiments, the conductive feature 120 surrounds the guard ring 104, and the boundary region 106 surrounds the conductive feature 120. The KOZ is defined by the dimensions Dx and Dy. In some embodiments, when designing a circuit including the semiconductor device structure 100, an electronic device automation (EDA) tool may first check the design rules and then define the KOZ based on the location of the TSV 102 and the dimensions Dx and Dy. Next, a tap cell or a boundary cell (such as Figure 3B and Figure 6B ) is placed in the KOZ. Therefore, the conventional process of placing dummy devices in the KOZ (especially between the guard ring 104 and the active device) can be omitted. Therefore, the size of the KOZ becomes smaller and the active device density can be increased.

[0056] According to some embodiments, 9A to 9D Shows Figure 8 an enlarged portion 302 of the semiconductor device structure 100, and FIG. 9E to FIG. 9G Shows Figure 8 The enlarged portion 304 of the semiconductor device structure 100 is shown. The portion 302 in the boundary region 106 includes a tap cell or a boundary cell, such as an STD boundary tap, a logic pick-up, or an SRAM tap. Fig. 9A As shown in , the tap cell or boundary cell includes a nanostructure transistor having an S / D region 132, a dielectric material 134, a gate electrode layer 154, a conductive contact 127, and a conductive via 156. As described above, the well region 131 includes the same dopant type as the S / D region 132. Thus, in some embodiments, the S / D region 132 includes an n-type epitaxial material, such as SiP, and the well region 131 is an n-well doped with phosphorus. In some embodiments, the S / D region 132 includes a p-type epitaxial material, such as SiGe, and the well region 131 is a p-well doped with boron.

[0057] like Fig. 9BAs shown in , the tap cell or boundary cell includes a FinFET having an S / D region 132, a dielectric material 134, a gate structure 210, a conductive contact 212, and a conductive via 216. As described above, the well region 131 includes the same dopant type as the S / D region 132. Therefore, in some embodiments, the S / D region 132 includes an n-type epitaxial material, such as SiP, and the well region 131 is an n-well doped with phosphorus. In some embodiments, the S / D region 132 includes a p-type epitaxial material, such as SiGe, and the well region 131 is a p-well doped with boron.

[0058] like Fig. 9C As shown in , the tap cell or boundary cell includes a FinFET or nanostructure transistor having an S / D region 132, a gate electrode layer 154, a conductive contact 127, and a conductive via 156. In some embodiments, the width of the fin of the FinFET or nanostructure transistor can be different. For example, Fig. 9C As shown in , the width of the S / D region 132 along the Y direction is different. Similarly, the width of the channel (the portion of the fin located below the gate electrode layer 154) is also different. As described above, the well region 131 includes the same dopant type as the S / D region 132. Therefore, in some embodiments, the S / D region 132 includes an n-type epitaxial material, such as SiP, and the well region 131 is an n-well doped with phosphorus. In some embodiments, the S / D region 132 includes a p-type epitaxial material, such as SiGe, and the well region 131 is a p-well doped with boron.

[0059] like Fig.9D As shown in , the tap cell or boundary cell includes a FinFET or nanostructure transistor having an S / D region 132, a gate electrode layer 154 and a conductive via 156. Fig. 9C The width of the fins of a FinFET or nanostructure transistor can be different. Fig.9D As shown in , the width of S / D region 132 is different, and the width of the channel is also different. As described above, well region 131 includes the same dopant type as S / D region 132. Therefore, in some embodiments, S / D region 132 includes n-type epitaxial material, such as SiP, and well region 131 is an n-well doped with phosphorus. In some embodiments, S / D region 132 includes p-type epitaxial material, such as SiGe, and well region 131 is a p-well doped with boron.

[0060] FIG. 9E to FIG. 9G According to some embodiments Figure 8An enlarged portion 304 of the semiconductor device structure 100 is shown. The portion 304 in the active region 108 includes an active cell, such as an STD cell, a logic cell, or an SRAM cell. In some embodiments, the portion 304 includes an STD cell having a plurality of active fin patterns 306. Each active fin pattern 306 may include a plurality of S / D regions (such as S / D region 132) formed by a well region 308 (such as well region 133). As described above, in the active region 108, the active cell includes an S / D region and a well portion having opposite types of impurities. For example, the well region 308 is a p-type region, and the S / D region of the fin pattern 306 formed thereon includes an n-type epitaxial material. The fin pattern 306 may also include a channel surrounded by a gate electrode layer (not shown) such as the gate electrode layer 154. In some embodiments, the fin pattern 306 has the same width along the Y direction, such as Fig.9E In some embodiments, the fin pattern 306 has different widths along the Y direction, such as Fig.9F as shown in .

[0061] In some embodiments, Figure 9G As shown in FIG. 3 , portion 304 includes an SRAM cell having a staggered fin pattern 306. For example, portion 304 includes discrete fin pattern 306a and discrete fin pattern 306b, as shown in FIG. Figure 9G Each fin pattern 306a, 306b includes a group of one or more transistors. For example, each group includes at least a source region, a drain region, and a channel region. The channel region is surrounded by a gate electrode layer (not shown). In some embodiments, the transistor groups of the fin patterns 306a, 306b are staggered along the Y direction, such as Figure 9G In some embodiments, the plurality of fin patterns 306a, 306b are separated by fin patterns 306c, and each fin pattern 306c is a continuous fin pattern.

[0062] Fig. 10A and Fig. 10B FIG. 1 is a top view of a semiconductor device structure 100 according to some embodiments. Fig. 10A and Fig. 10B As shown in FIG. 1 , the semiconductor device structure 100 includes a plurality of TSVs 102 arranged adjacent to each other. An example of such an arrangement may be a SoIC F2B stack (2-die). Eliminating dummy devices in the KOZ (between the guard ring 104 and the active devices in the active area 108) results in reduced dimensions Dx, Dy of the KOZ, as shown in FIG. Figure 1A-1 In an alternative embodiment, the TSV KOZ includes a boundary region 106, which includes the outermost boundary cells or tap cells of the STD, such as Figure 1A As shown in . Therefore, active STD in the circuit can exist in the space between adjacent TSVs 102. Due to short wiring, including Fig. 10A and Fig. 10B The circuit of adjacent TSVs 102 shown in has high signal transmission efficiency. In some embodiments, the active area 108 between horizontally adjacent TSVs 102 has a size Sx, and the active area 108 between vertically adjacent TSVs 102 has a size Sy. In some embodiments, the ratio of Sx to Sy is greater than or equal to about 1. In some embodiments, the TSVs 102 have a pitch less than or equal to 10 microns. Conventional TSVs with a pitch less than or equal to 10 microns include dummy devices in the KOZ, resulting in reduced spacing for active devices between adjacent TSVs.

[0063] Fig.11 and Fig.12 An IC design layout including a semiconductor device structure 100 according to some embodiments is shown. The IC design layout generally includes individual intellectual property (IP) blocks, wherein each IC pattern is classified based on the IP block to which the IC pattern belongs. An IP block generally refers to a reusable, custom-designed logic component, storage component, or other component. For example, Fig.11 As shown in , IC design layout 400 includes IP blocks 402, 404, 406, 408, 410, 412, 414. IP blocks 402, 404, 406, 408, 410, 412, 414 can be any suitable IP blocks. In some embodiments, IP block 402 includes a first STD, IP block 408 includes a second STD, IP block 410 includes a third STD, IP block 404 includes a first SRAM cell, IP block 406 includes a second SRAM cell, IP block 412 includes a third SRAM cell, and IP block 414 includes other IPs. At least one of IP blocks 402, 404, 406, 408, 410, 412, 414 includes one or more TSVs 102. As shown in FIG. Fig.11 As shown in FIG, TSVs 102 are formed inside IP blocks 402, 404, 406, 408, 410, 412, 414 due to increased spacing for active devices between adjacent TSVs 102. Due to such an arrangement of IP blocks, die-to-die signal transmission is increased due to short wiring, which may be beneficial for high-speed computing with lower power consumption for applications such as GPU or AI.

[0064] like Fig.12As shown in , an IC design layout 500 for a nearby memory computing (NMC) application in a 3DIC includes IP blocks 502, 504, 506, 508, 510. In some embodiments, IP block 502 includes a first STD (CPU / GPU), IP block 504 includes a logic cell, IP block 506 includes an SRAM cell, IP block 508 includes a second STD (SRAM periphery), and IP block 510 includes a third STD (SRAM periphery). As described above, active devices such as active STD cells in IP block 502 and active logic cells in IP block 504 can be formed between adjacent TSVs 102. Since TSVs 102 are located inside IP blocks 502 and 504, the data movement efficiency between IP block 502 and IP block 506 is enhanced.

[0065] FIG. 13A to FIG. 13E A semiconductor package 600 is shown in accordance with some embodiments. For clarity, FIG. 13A to FIG. 13E Components such as the border region 106 and the buffer region 116 may be omitted. Fig.13A As shown in , semiconductor package 600 may be a SoIC / InFO F2B package having a first die 602 and a second die 604 disposed on the first die 602. The second die 604 includes a substrate 608 and an interconnect structure 610. Active devices are formed on the front side of the substrate 608, and the interconnect structure 610 is formed on the front side of the substrate 608. The first die 602 includes a substrate 101, an interconnect structure 103, and a backside interconnect structure 606. The interconnect structure 610 of the second die 604 is bonded to the backside interconnect structure 606 of the first die 602. Fig.13A As shown in , active devices in the active area 108 of the first tube core 602 are formed on the front side of the substrate 101. In some embodiments, the active devices in the active area 108 are located between two TSVs 102, and the TSVs 102 have a pitch of less than about 10 microns. In some embodiments, a tap or boundary cell located in a boundary area (not shown) is set between the active devices in the active area 108 and the guard ring 104. By placing the active devices in the active area 108 located between adjacent TSVs 102, the distance D1 between the TSVs 102 and the active devices in the active area 108 is reduced. Therefore, the signal bandwidth in the CPU / GPU and SRAM periphery is widened, and the power consumption is reduced. As shown in FIG. Fig.13A As shown in FIG. 1 , the guard ring 104 and the spacing between the active devices in the active area 108 are free of dummy devices.

[0066] like Fig. 13BAs shown in , semiconductor package 600 can be used for near memory computing (NMC) applications and includes a first die 602 and a second die 612 disposed on the first die 602. The second die 612 includes a substrate 614 and an interconnect structure 616. Active devices are formed on the front side of the substrate 614, and the interconnect structure 616 is formed on the front side of the substrate 614. The interconnect structure 616 of the second die 612 is bonded to the backside interconnect structure 606 of the first die 602. For clarity, Fig. 13B The guard ring 104 is omitted. Fig. 13B As shown in , active devices in the active region 108 of the first die 602 are formed on the front side of the substrate 101. Fig. 13B As shown in FIG. 6 , TSV 102 provides an electrical path between active devices (such as CPU / GPU or SRAM macro) in second die 612 and active devices (such as CPU / GPU) in first die 602. In some embodiments, the distance between TSV 102 and the active devices is reduced due to the absence of KOZ of dummy devices. Therefore, the signal bandwidth in CPU / GPU and SRAM micro is widened and power efficiency is improved.

[0067] like Fig. 13C As shown in , the semiconductor package 600 may be a SoIC F2F package having a first die 620 and a second die 630 disposed on the first die 620. The second die 630 includes a substrate 632 and an interconnect structure 634. Active devices (not shown) are formed on the front side of the substrate 632, and the interconnect structure 634 is formed on the front side of the substrate 632. The first die 620 includes a substrate 621, a front side interconnect structure 622, and a back side interconnect structure 624. The interconnect structure 634 of the second die 630 is bonded to the front side interconnect structure 622 of the first die 620. The active devices (not shown) of the first die 620 are formed on the front side of the substrate 621. In some embodiments, the distance between the TSV 102 and the active device is reduced, because there is no KOZ of the dummy device. Therefore, the signal bandwidth is widened and the power consumption is reduced.

[0068] like Fig.13D As shown in FIG. , the semiconductor package 600 may be an INFO-3DF2B package including a first die 640, a second die 642, a third die 644, and a fourth die 638 disposed below the first die 640, the second die 642, and the third die 644. A plurality of TSVs 102 are formed in the fourth die 638 to be electrically connected to the first die 640, the second die 642, and the third die 644. Fig.13E yes Fig.13D FIG. 6 is an enlarged view of a portion 646 of a semiconductor package 600. Fig.13EAs shown in FIG. 1 , a fourth die 638 is disposed over a redistribution layer 650 (or interposer). A plurality of conductive features are disposed in the redistribution layer 650. Another redistribution layer 658 is disposed over the fourth die 638, and a second die 642 is disposed over the redistribution layer 658. Fig.13E As shown in FIG. 6 , the fourth die 638 includes a substrate 632, a front-side interconnect structure 654, and a back-side interconnect structure 656. TSVs 102 are formed through the substrate 632. Active devices of the active region 108 are formed on the front side of the substrate 632. In some embodiments, the distance between the TSVs 102 and the active devices is reduced due to the absence of the KOZ of the dummy devices. Therefore, the signal bandwidth is widened and the power consumption is reduced.

[0069] Fig.14 1 is a top view of a semiconductor device structure 100 according to an alternative embodiment. In some embodiments, the guard ring 104 is not surrounded by the border region 106. For example, the border region 106 may be adjacent to one side, two sides, or three sides of the guard ring 104. In some embodiments, the border region 106 is located below the TSV 102. Fig.14 As shown in , the dummy device region 702 is located on three adjacent sides (left side, right side and top) of the guard ring 104, and the dummy device region 702 includes a plurality of dummy devices. As described above, the dummy device can be a transistor including a gate electrode, a source region, a drain region, and a channel region between the source region and the drain region. However, the dummy device is not electrically connected to a signal source, a power source, or any active device. The boundary cell or tap cell of the boundary region 106 (indicated by a dotted line located at the outer edge of the active region 108) is located below the guard ring 104. The boundary cell or tap cell may include Figure 3B and Figure 6B The structure shown in .

[0070] Embodiments of the present disclosure provide a semiconductor device structure 100 including a TSV 102, a KOZ surrounding the TSV 102, and an active region 108 surrounding the KOZ. In some embodiments, a guard ring 104 is located in the KOZ, and the KOZ has no dummy devices and / or dummy conductive components between the guard ring 104 and the active region 108. Some embodiments can achieve advantages. For example, a KOZ without dummy devices reduces the size of the KOZ. Therefore, high signal bandwidth, high power efficiency, lower area overhead, better latching, and better STD PPA can be achieved.

[0071] The embodiment is a semiconductor device structure. The structure includes a through silicon via (TSV) disposed in an interconnect structure and a substrate, a protection structure located in the interconnect structure surrounding the TSV, and an active region surrounding the protection structure. The space between the protection structure and the active region is free of dummy devices.

[0072] Another embodiment is a semiconductor device structure. The structure includes a substrate, an interconnect structure disposed above the substrate, a protection structure disposed in the interconnect structure, and a first through silicon via (TSV) disposed in the interconnect structure and the substrate. The protection structure surrounds the first TSV. The structure also includes a first boundary region surrounding the protection structure, and the first boundary region includes a first device adjacent to the protection structure. There is no dummy device in the spacing between the protection structure and the first device. The boundary region also includes a plurality of conductive components disposed in the interconnect structure above the first device, and the plurality of conductive components surround the protection structure.

[0073] A further embodiment is a semiconductor package. The semiconductor package includes a first die, the first die having a first substrate, a first interconnect structure disposed below the first substrate, a through silicon via (TSV) disposed in the first substrate and the first interconnect structure, and a protection structure surrounding the TSV. The protection structure extends in the first interconnect structure. The first die also includes a first device disposed above the substrate and a first plurality of conductive components disposed in the first interconnect structure above the first device. There is no pseudo conductive component in the interval between the first plurality of conductive components and the protection structure. The first die also includes a second device disposed adjacent to the first device. The semiconductor package also includes a second die, the second die having a second interconnect structure disposed above the first die and a second substrate disposed above the second interconnect structure.

[0074] Some embodiments of the present application provide a semiconductor device structure, comprising: a through silicon via (TSV) disposed in an interconnect structure and a substrate; a protection structure located in the interconnect structure surrounding the through silicon via; and an active area surrounding the protection structure, wherein there is no dummy device in the interval between the protection structure and the active area.

[0075] In some embodiments, the semiconductor device structure further comprises a boundary region between the protection structure and the active region. In some embodiments, the boundary region comprises a first device comprising a first source / drain region having a first type of dopant formed on a first well region having a first type of dopant. In some embodiments, the first type is n-type. In some embodiments, the first type is p-type. In some embodiments, the active region comprises a second device comprising a second source / drain region having a first type of dopant formed on a second well region having a second type of dopant opposite to the first type. In some embodiments, the first device further comprises a plurality of semiconductor layers connected to the first source / drain region and a gate structure surrounding a portion of each of the semiconductor layers. In some embodiments, the first device is a FinFET, a CFET, a nanostructure transistor, or a fork-piece FET. In some embodiments, the protection structure comprises one or more guard rings.

[0076] Other embodiments of the present application provide a semiconductor device structure, comprising: a substrate; an interconnect structure disposed above the substrate; a protection structure disposed in the interconnect structure; a first through silicon via (TSV) disposed in the interconnect structure and the substrate, wherein the protection structure surrounds the first through silicon via; and a first boundary region surrounding the protection structure, wherein the first boundary region comprises: a first device adjacent to the protection structure, wherein there is no dummy device in the interval between the protection structure and the first device; and a plurality of conductive components disposed in the interconnect structure above the first device, wherein the plurality of conductive components surround the protection structure.

[0077] In some embodiments, the first device is part of a tap unit. In some embodiments, the semiconductor device structure further includes a second through silicon via disposed adjacent to the first through silicon via and a second boundary region surrounding the second through silicon via. In some embodiments, the semiconductor device structure further includes a second device disposed between the first boundary region and the second boundary region. In some embodiments, the first through silicon via and the second through silicon via are located inside the IP block. In some embodiments, the first device and the second device are FinFETs, CFETs, nanostructure transistors, or fork-piece FETs. In some embodiments, the semiconductor device structure further includes a liner and a barrier layer, wherein the first through silicon via is disposed on the barrier layer, and the barrier layer includes Ti or Ta. In some embodiments, the first device includes a first source / drain region having a first type of dopant formed on a first well region having a first type of dopant, and the second device includes a second source / drain region having a first type of dopant formed on a second well region having a second type of dopant opposite to the first type.

[0078] Still other embodiments of the present application provide a semiconductor package, comprising: a first die, comprising: a first substrate; a first interconnect structure, arranged below the first substrate; a through silicon via (TSV), arranged in the first substrate and the first interconnect structure; a protection structure surrounding the through silicon via, wherein the protection structure extends in the first interconnect structure; a first device, arranged above the substrate; a first plurality of conductive components, arranged in the first interconnect structure above the first device, wherein there are no pseudo conductive components in the intervals between the first plurality of conductive components and the protection structure; and a second device, arranged adjacent to the first device; and a second die, comprising: a second interconnect structure, arranged above the first die; and a second substrate, arranged above the second interconnect structure.

[0079] In some embodiments, the first device includes a first source / drain region having a first type of dopant formed on a first well region having a first type of dopant, and the second device includes a second source / drain region having a first type of dopant formed on a second well region having a second type of dopant opposite to the first type. In some embodiments, the semiconductor package further includes a border region surrounding the protection structure, wherein the first device is located in the border region, and the border region is free of dummy devices.

[0080] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device structure, comprising: Through Silicon Vias (TSVs), which are placed in the interconnect structure and the substrate; a protection structure located in the interconnect structure surrounding the through silicon via; as well as An active region surrounds the protection structure, wherein a space between the protection structure and the active region has no dummy devices. 2 . The semiconductor device structure according to claim 1 , further comprising a boundary region between the protection structure and the active region.

3. The semiconductor device structure according to claim 2, wherein: The boundary region includes a first device including a first source / drain region having a first type of dopant formed on a first well region having a first type of dopant.

4. The semiconductor device structure according to claim 3, wherein: The first type is n-type.

5. The semiconductor device structure according to claim 3, wherein: The first type is p-type.

6. The semiconductor device structure according to claim 3, wherein: The active region includes a second device including a second source / drain region having a first type of dopant formed on a second well region having a second type of dopant opposite to the first type.

7. The semiconductor device structure according to claim 3, wherein: The first device also includes a plurality of semiconductor layers connected to the first source / drain regions and a gate structure surrounding a portion of each of the semiconductor layers.

8. The semiconductor device structure according to claim 3, wherein: The first device is a FinFET, a CFET, a nanostructure transistor, or a fork-piece FET.

9. A semiconductor device structure, comprising: substrate; an interconnect structure disposed above the substrate; a protection structure disposed in the interconnection structure; a first through silicon via (TSV) disposed in the interconnect structure and the substrate, wherein the protection structure surrounds the first through silicon via; and A first boundary region surrounds the protection structure, wherein the first boundary region includes: a first device adjacent to the protection structure, wherein a space between the protection structure and the first device is free of dummy devices; and A plurality of conductive components are disposed in the interconnect structure above the first device, wherein the plurality of conductive components surround the protection structure.

10. A semiconductor package comprising The first die comprises: a first substrate; A first interconnect structure, disposed below the first substrate; a through silicon via (TSV) disposed in the first substrate and the first interconnect structure; a protection structure surrounding the through silicon via, wherein the protection structure extends in the first interconnect structure; A first device, disposed above the substrate; a first plurality of conductive features disposed in the first interconnect structure above the first device, wherein spaces between the first plurality of conductive features and the protection structure are free of dummy conductive features; and a second device disposed adjacent to the first device; and The second die comprises: a second interconnect structure disposed above the first die; and The second substrate is disposed above the second interconnect structure.

Images