Expandable embedded silicon bridge through hole stulds in

Abstract

The invention relates to a scalable embedded silicon bridge via pillar in photolithographically defined vias and a method of manufacturing the same. An embedded silicon bridge system is provided that includes a high interconnect via log that is part of a system in a packaged device. The high via pillars may span a Z height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that accommodates an embedded silicon bridge.

Description

[0001] Priority application This application is a divisional application of application number: 201780071671.9, invention name: Scalable embedded silicon bridge via pillars in lithographically defined through holes and methods for manufacturing the same. This application claims the benefit of priority of U.S. application serial number 15 / 389,100 filed on December 22, 2016, the entire text of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to embedded silicon bridge interconnects for system-in-package (SiP) devices including stacked chip configurations. Background Art

[0003] Computing devices such as mobile phones, smart phones and tablet computers are limited in available space because there are size restrictions determined by the intended use. Size reduction presents challenges to packaging both in terms of height and in terms of footprint. Interconnections between devices within a package are also challenged to reduce size without compromising performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various disclosed embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, and in which: Figure 1 is a cross-sectional elevation view of an embedded silicon bridge with high via posts according to an embodiment; Figure 1A Including the processing period according to the embodiment Figure 1 Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 1B According to an embodiment, after further processing Figure 1A Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 1C According to an embodiment, after further processing Figure 1B Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 1D According to an embodiment, after further processing Figure 1C Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 1E According to an embodiment, after further processing Figure 1D Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 1F According to an embodiment, after further processing Figure 1E Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 1G According to an embodiment, after further processing Figure 1F Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 1H According to an embodiment, after further processing Figure 1G Cross-sectional and perspective elevation views of the embedded bridge device depicted in; Figure 2 is a cross-sectional elevation view of an embedded silicon bridge with groups of via posts according to an embodiment; Figure 3 is a cross-sectional elevation view of an embedded silicon bridge with an on-bridge bond pad reinforced high-via pillar according to an embodiment; Figure 4 is a cross-sectional elevation view of an embedded silicon bridge having an on-bridge bond pad reinforced high via pillar that matches the metallization subsequent pad height according to an embodiment; Figure 5 is a cross-sectional elevation view of an embedded silicon bridge having a high via post that matches the height of a metallized subsequent pad according to an embodiment; Figure 6 is a process flow diagram illustrating a process according to an embodiment; Figure 7 is a computing system according to an embodiment; and Figure 8 is a perspective elevation view with cutaway and cross-sectional portions according to an embodiment illustrated. DETAILED DESCRIPTION

[0005] According to several disclosed embodiments, high density interconnects are implemented to bridge between different semiconductor devices in an organic package. The high density interconnects are useful, such as for high bandwidth memory interfaces according to embodiments. The high density interconnects are useful, such as for die-stitching interfaces according to embodiments. Other high density uses may be employed. Among other things, the disclosed embodiments eliminate the need for silicon interposer solutions.

[0006] Figure 1 1 is a cross-sectional elevation view of an expandable embedded silicon bridge 100 with via posts according to an embodiment. The embedded semiconductor bridge 10 (hereinafter referred to as "silicon bridge") is arranged within an organic substrate 20. In an embodiment, the bridge 10 is a planar inorganic substrate. In an embodiment, the bridge 10 is a glass material. The via posts 110 extend from the active surface of the silicon bridge 10. In an embodiment, during the manufacture of the organic substrate 20, the silicon bridge 10 has been placed together with the pre-existing via posts 110. Figure 1Illustrated in are six pre-existing via posts 110, which are grouped in threes at the edge of the silicon bridge 10, as shown in this cross-section along the X direction. In an embodiment, the pre-existing via post 110 has a YX aspect ratio greater than 1:1. In an embodiment, the pre-existing via post 110 has a YX aspect ratio less than 1:1. In an embodiment, the pre-existing via post 110 has a YX aspect ratio less than or equal to 10:1. In an embodiment, the pre-existing via post 110 has a YX aspect ratio in a range from 9:1 to 2:1. In an embodiment, the pre-existing via post 110 has a YX aspect ratio in a range from 8:1 to 3:1. In an embodiment, the pre-existing via post 110 has a YX aspect ratio in a range from 7:1 to 4:1. In an embodiment, the pre-existing via post 110 has a YX aspect ratio in a range from 6:1 to 5:1.

[0007] The organic substrate 20 may have a base layer 112 and a first trace layer 114. In an embodiment, the bridge organic layer 116 has been milled to form a groove 118 (see Figure 1C ), the silicon bridge 10 has been placed in the groove 118.

[0008] exist Figure 1 3 directs attention to the left from an arbitrary fracture 30 which is shown to aid in illustrating a selected process embodiment.

[0009] Focus on the left side Figure 1, including structures that contact the items indicated by reference numeral 124. In an embodiment, the substrate-base interconnect includes a seed layer 120, a first bonding pad 122, a first through hole 124, and a subsequent bonding pad 126. The first through hole 124 is above and on the subsequent bonding pad 122, and it extends orthogonally from the first bonding pad within normal processing parameters. The first bonding pad 122 has been electroplated on the seed layer 120, and the first through hole 124 has been formed on the first bonding pad 122 by semi-additive plating technology. In an embodiment, the first bonding pad 122 is first formed by patterning the first dielectric layer 129 using photolithography techniques, and then electroplating is performed, such as electroplating the first bonding pad 122 onto the seed layer 120. In an embodiment, a first dielectric layer 129 is first formed and patterned for the first bonding pad 122, but at a Z height that protects the pre-existing tall via pillar 110 during electroplating of the first bonding pad 122. Thereafter, the height of the first dielectric layer 129 is reduced, such as by wet etching, plasma etching, mechanical milling, or reactive ion etching (RIE), to obtain the first dielectric layer 129 as depicted, such that the etching is selective to leaving the first bonding pad 124 and the pre-existing via pillar 110. Next, semi-additive plating is completed by forming and patterning a second dielectric layer 131, which can also cover the pre-existing via pillar 110 during electroplating of the first via 124, followed by another etch that reduces the height of the second dielectric layer 131 to expose and stop at the Z height of both the first via 124 and the top of the pre-existing via pillar 110. Thereafter, a subsequent bonding pad 126 is formed by patterning a subsequent dielectric layer (not shown), then electroplating the subsequent bonding pad 126 and the via post bonding pad 128, stripping the subsequent dielectric layer, and further then forming a first metallization layer having an opening 132. It can now be understood that the via post bonding pad 126 and the via post bonding pad 128 can be formed simultaneously, wherein access to the via post 110 is achieved through the metallization layer having the opening 132. The metallization layer having the opening 132 can also be referred to as a solder resist layer having the opening 132. It can be seen that the solder resist layer having the opening 132 exposes the subsequent bonding pad 126. It can be understood that the "metallization layer having the opening 132" can be used colloquially in the industry, such as "solder resist opening" (SRO), wherein the opening is used as a contact channel that can facilitate the connection of the electrical bump and the bonding pad.

[0010] The first solder resist layer with openings 132 represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10. It will be understood throughout this disclosure that the subsequent bond pad 126 is above and in electrical communication with the first via 124, including being above and in direct electrical contact with the first via 124 as shown.

[0011] It can now be appreciated that the photolithographic processing embodiments depicted herein allow for small geometries that would otherwise be limited if laser drilling were used to open the locations of both the first bond pad 122 and the first via 124. For example, conventional laser drilling may not be able to form a bond pad opening where the bond pad opening is limited to approximately 25 micrometers (μm), and to obtain geometries less than 25 μm, an ultraviolet (UV) laser may be used, but at the expense of significantly reduced throughput.

[0012] Focus on the left Figure 1 , including structures that contact the items indicated by reference numeral 123. In an embodiment, the substrate-base interconnect includes an integral first bonding pad and via 123 that has been electroplated on the seed layer 120. In an embodiment, photolithography techniques are used by patterning a first dielectric layer 129 and then filling a sacrificial dummy (not depicted) that occupies an equal space of the first bonding pad 122 adjacent to and seen to the left of the integral first bonding pad and via 123. Thereafter, the height of the first dielectric layer 129 is reduced, such as by wet etching, plasma etching, and RIE, to obtain the first dielectric layer 129 as depicted, so that the etching is selective to leaving the pre-existing via post 110 and the sacrificial dummy. Next, a second dielectric layer 131 is formed, which may also cover the pre-existing via post 110, and the second dielectric layer 131 is patterned to open the via portion of the integral first bonding pad and via 123. After patterning, the dummy layer is dissolved by any known, useful technique, such as a wet etch that is selective to leaving behind the seed layer 120, the first dielectric layer 129, and the patterned second dielectric layer 131. The etch removes the dummy to form a negative space to be filled by electroplating the integral first bonding pad and via 123. Thereafter, the height of the second dielectric layer 131 is lowered to expose the Z height of both the top of the integral first bonding pad and via 123 and the top of the pre-existing via post 110. It can be observed that the integral first bonding pad and via 123 can have a lower resistance than the resistance of the first bonding pad 122 and the first via 124 because one reduces the metal-to-metal interface within the integral first bonding pad and via 123.

[0013] Thereafter, subsequent bond pads 126 are formed by patterning a subsequent dielectric layer (not shown), then electroplating subsequent bond pads 126 and via stud bond pads 128, stripping the subsequent dielectric layer, and further then forming a first solder resist layer having openings 132. The first solder resist layer having openings 132 represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10.

[0014] It can now be observed in embodiments that the first bond pad 122 and first via 124 depicted on the left side of any break 30 will usefully occupy all via structures useful at that level within the organic substrate 20. It can now be observed in embodiments that the overall bond pad and via 123 depicted on the left side of any break 30 will occupy all via structures useful at that level within the organic substrate 20.

[0015] exist Figure 1 3 directs attention to the right from an arbitrary fracture 30, which is shown to aid in illustrating a selected process embodiment.

[0016] Focus on the right side Figure 1, including structures that contact the items indicated by reference numeral 124. In an embodiment, the substrate-base interconnect includes a seed layer, a first bonding pad 122, a first via 124, and a subsequent bonding pad 126. The first bonding pad 122 has been plated on the seed layer 120, and the first via 124 has been formed on the first bonding pad 122 by a semi-additive plating technique. In an embodiment, the first bonding pad 122 is formed by first patterning a first dielectric layer 129 using photolithography techniques, and then electroplating is performed, such as electroplating the first bonding pad 122 onto the seed layer 120. In an embodiment, a first dielectric layer (not depicted) is first formed and patterned for the first bonding pad 122, but at a Z height that protects the pre-existing via post 110 during the electroplating of the first bonding pad 122. Thereafter, the first dielectric layer is stripped and removed, such as by wet etching, plasma etching, or reactive ion etching (RIE), such that the etching is selective to leaving behind the first bonding pad 124 and the pre-existing via post 110. Next, semi-additive plating is accomplished by forming and patterning a second dielectric layer 131, which may also cover the pre-existing via post 110 during plating of the first via 124, followed by another etch that reduces the height of the second dielectric layer 131 to a height that exposes and stops at the Z height of both the first via 124 and the top of the pre-existing via post 110. Thereafter, a subsequent bonding pad 126 is formed by patterning a subsequent dielectric layer (not shown), then plating the subsequent bonding pad 126 and via post bonding pad 128, stripping the subsequent dielectric layer, and further then forming a first solder resist layer having an opening 132. The first solder resist layer with openings 132 represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10 .

[0017] Focus on the right side Figure 1Items shown in , including structures that contact items indicated by reference numeral 123. In an embodiment, the substrate-base interconnect includes an integral first bonding pad and via 123 that has been electroplated on the seed layer 120. In an embodiment, photolithography is used by patterning a first dielectric layer (not depicted) and then filling a sacrificial dummy (not depicted) that occupies an equal space of the first bonding pad 122 adjacent to and seen to the left of the integral first bonding pad and via 123. Thereafter, the first dielectric layer is stripped and removed, such as by wet etching, plasma etching, and RIE, so that the etching is selective to leaving the pre-existing high-via column 110 and the sacrificial dummy. Next, a second dielectric layer 131 is formed, which may also cover the pre-existing via column 110, and the second dielectric layer 131 is patterned to open the through-hole portion of the integral first bonding pad and via 123. After patterning, the dummy layer is dissolved by any known, useful technique, such as a wet etch that is selective to leaving behind the seed layer 120 and the patterned second dielectric layer 131. The etch removes the dummy to form a negative space to be filled by electroplating the integral first bonding pad and via 123. Thereafter, the height of the second dielectric layer 131 is lowered to expose the Z height of both the top of the integral first bonding pad and via 123 and the top of the pre-existing high via column 110. It can be observed that the integral first bonding pad and via 123 can have a lower resistance than the resistance of the first bonding pad 122 and the first via 124 because one reduces the metal-to-metal interface within the integral first bonding pad and via 123.

[0018] Thereafter, subsequent bond pads 126 are formed by patterning a subsequent dielectric layer (not shown), then electroplating subsequent bond pads 126 and via stud bond pads 128, stripping the subsequent dielectric layer, and further then forming a first solder resist layer having openings 132. The first solder resist layer having openings 132 represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10.

[0019] It can now be observed in embodiments that the first bond pad 122 and first via 124 depicted to the right of any break 30 will effectively occupy all via structures useful at that level within the organic substrate 20. It can now be observed in embodiments that the overall bond pad and via 123 depicted to the right of any break 30 will occupy all via structures useful at that level within the organic substrate 20.

[0020] Figure 1A Including the processing period according to the embodiment Figure 1 Cross-section and perspective elevation views of the embedded bridge device depicted in FIG. The left figure is Figure 1 The left part of the illustration is an XZ cross-sectional elevation view of some of the Figure 1 1 . Some of the XYZ perspective elevation views of the left portion of the illustration in FIG. The cross-sectional elevation view is taken from the perspective elevation view along line 1 - 1 '. The processing conditions for the two-part pad and via process are illustrated and described, which produces the first bonding pad 122 and the first via 124, rather than for the integral first bonding pad and via 123 embodiment.

[0021] The base layer 112 and the bridge organic layer 116 may comprise several layers, here represented as an intermediate layer 113. A first bonding pad 122 has been formed on a seed layer (not depicted), such as Figure 1 The seed layer 120 is illustrated in FIG. The first trace 134 is also depicted as extending along the surface of the bridge-level organic layer 116 , and the first trace 134 may be an integral structure with the first bonding pad 122 due to simultaneous photolithography and electroplating processing conditions.

[0022] Figure 1B According to an embodiment, after further processing Figure 1A The first through hole 124 has been formed by a cross-sectional view and a perspective elevation view of the embedded bridge device depicted in FIG. Figure 1 The first through hole 124 depicted in the drawings is formed by any of the processes shown and described.

[0023] Figure 1C According to an embodiment, after further processing Figure 1B . The bridge level organic layer 116 has been milled to form a recess 118, and the silicon bridge 10 will be placed in the recess 118. In an embodiment, the placement surface 117 can be milled from the bridge level organic layer 116 so that the placement surface 117 is the remaining part of the bridge level organic layer 116, such as Figure 1 . In an embodiment, the mounting surface 117 is a structure below the bridge-level organic layer 116, so that the milling has resulted in the removal of all of the bridge-level organic layer 116. In an embodiment, the milling of the groove 118 includes laser drilling. In an embodiment, the milling of the groove 118 includes mechanical ablation or laser ablation. In an embodiment, the milling of the groove 118 includes photo-defined etching. In an embodiment, the milling of the groove 118 includes photo-defined etching such as reactive ion etching (RIE). In an embodiment, the milling of the groove 118 includes etching such as plasma etching.

[0024] According to an embodiment, the silicon bridge may be bonded into the groove 118 by placing a die attach film 119, such as an adhesive material. In an embodiment, the die attach film 119 has a smaller footprint than the silicon bridge 10. In an embodiment, the die attach film 119 has substantially the same footprint as the silicon bridge 10 under normal processing parameters. In an embodiment, the die attach film 119 has a larger footprint than the silicon bridge 10. In an embodiment, the die attach film 119 has a narrower footprint than the silicon bridge 10 when viewed in the X direction, but is one of substantially the same as or longer than the silicon bridge 10 when viewed in the Y direction.

[0025] In an embodiment, the adhesive material 119 is an anisotropic conductive film. In an embodiment, the adhesive material 119 is an anisotropic conductive film fashioned from a conductive paste. In an embodiment, the adhesive material 119 is a conductive film implemented with a sinterable conductive paste. In an embodiment, the adhesive material 119 is a metal ink printed into a pattern to receive and couple to a through silicon via (TSV) in the silicon bridge 10.

[0026] Focus on Figure 8 .

[0027] Figure 8 is a perspective elevation view with cutaway and cross-sectional portions according to an embodiment. Adhesive material 119 is depicted in recess 118 and is Figure 1C Compared to the silicon bridge 10 depicted in FIG. 1 , the silicon bridge 810 is cut away (compared to, for example, Figure 1 , 2 , 3 and 4, the silicon bridge 810 is also cut off).

[0028] The silicon bridge base 807 is depicted without metallization and active devices (if any), and the active surface 809 is depicted with at least metallization to connect to the pre-existing via post 110. A portion of the active surface is cut away to reveal several through silicon vias (TSVs), one of which is indicated by reference numeral 811. The TSV 811 extends from the active surface of the silicon bridge and in a direction opposite to the via post. Thus, the via post 110 extends vertically upward in the Z direction from the active surface 809, and the TSV 811 extends vertically downward in the Z direction from the active surface 809. Thus, the via post 110 and the TSV 811 extend in opposite directions away from the active surface 809.

[0029] It can be seen that the TSV 811 appears in the form of a "mouse-bite" because some of the silicon bridge base 807 is also cut away where it would have occupied the footprint of the bonding material 119 in the Y direction. In addition, in an embodiment, the "mouse-bite" TSV 811 shown is coupled to the fan-out trace 834. Also in an embodiment, the "mouse-bite" TSV 811 shown is coupled to the embedded via 824, which is also exposed in the cut-away perspective view.

[0030] It will be appreciated that in embodiments, active surface 809 is primarily metallized to couple pre-existing via posts 110 at the illustrated ends of silicon bridge 810 and in the X direction to portions not illustrated, but as will be described in detail in the accompanying drawings. Figure 1-5 Any one of them saw.

[0031] In an embodiment, TSV 811 is used to utilize the XY plane surface of silicon bridge 810 for both interconnection and power and ground, if necessary. In an embodiment, multiple pre-existing through-hole posts 110 are configured to connect to semiconductor devices in the die according to specific design rules specified by the semiconductor die, and multiple TSV 811 are configured to accommodate fan-in interconnect designs according to embodiments. For fan-out embodiments, the interconnects in organic substrate 20 are fanned in to mate with TSV 811 according to specific design rules. For example, a portion of the adhesive layer 119 is an organic adhesive and another portion is a metal ink that forms a fan-in interconnect pattern that is miniaturized from a larger pattern in the organic substrate 20 to a smaller pattern that mates with TSV 811.

[0032] Focus on Figure 1D .

[0033] Figure 1D According to an embodiment, after further processing Figure 1C The silicon bridge 10 has been placed in a groove 118 that has been formed in the bridge-level organic layer 116 (see Figure 1C ). It can be seen that the pre-existing via post 110 reaches a height Z above the upper surface of the bridge-level organic layer 116 that matches the height of the top of the first via 124. Therefore, the pre-existing via post 110 is high enough to be on the silicon bridge 10, and the design allows for a scalable embedded silicon bridge structure in a lithographically defined via package.

[0034] refer to Figure 4 and Figure 5 It can be seen that the pre-existing high-via pillar 110 can reach a Z height above the upper surface of the bridge-level organic layer 116, which will eventually be the same as Figure 4 and Figure 5 1. Hereinafter, a "high via pillar" extends to the same level as the subsequent bond pad 126. Thus, the pre-existing high via pillar 410 extends high enough from the silicon bridge 10 so that the design allows for a scalable embedded silicon bridge structure in a lithographically defined through-hole package.

[0035] Figure 1E According to an embodiment, after further processing Figure 1D A second dielectric precursor layer 130 is formed over the first via 124, the silicon bridge 10 and the pre-existing via pillar 110, so that after a height reduction such as an etch back, a Figure 1 The second dielectric layer 131 is depicted in FIG.

[0036] Figure 1F According to an embodiment, after further processing Figure 1E The etch-back process has been completed to reduce the height of the second dielectric layer precursor 130 (see Figure 1E ) to obtain a second dielectric layer 131 exposing the top of the first via 124 and the top of the pre-existing via post 110 extending from the silicon bridge 10.

[0037] Figure 1G According to an embodiment, after further processing Figure 1F 0048] A cross-sectional and perspective elevation view of an embedded bridge device depicted in. A subsequent bond pad 126 and a via post bond pad 128 have been formed on a subsequent dielectric layer 131, such as by patterning the subsequent dielectric layer 131 and then electroplating the bond pads 126 and 128.

[0038] Figure 1H According to an embodiment, after further processing Figure 1G A solder mask layer having an opening 132 has been formed so that a subsequent bonding pad 126 (see Figure 1G ) and pillar bonding pad 128 (see Figure 1G ) is exposed through layer 132.

[0039] Figure 2is a cross-sectional elevation view of an embedded silicon bridge 200 having a group of pre-existing via posts 210 according to an embodiment. The group of via posts 210 is seen to be wider in the X direction than the adjacent via posts 110. In an embodiment, the group of via posts 210 is wider in the X direction than the adjacent via posts 110 and has the same dimension as the adjacent via posts 110 in the Y direction (not shown). Hereinafter, it will be understood that the group of via posts 210 has at least one dimension, X or Y dimension, that is greater than the via posts 110. In an embodiment, the group of posts is eccentrically shaped having a widest dimension as seen in the X direction and a narrowest dimension as seen in the Y direction (not shown).

[0040] An embedded semiconductor bridge 10 (hereinafter referred to as a "silicon bridge") is arranged within an organic substrate 20. During the manufacture of the organic substrate 20, the silicon bridge 10 has been placed together with a pre-existing via post 110. Figure 2 Illustrated in are two pre-existing via posts 110 and two groups of pre-existing via posts 210, which are grouped at the edge of the silicon bridge 10, as shown in this cross-section along the X direction. In an embodiment, the pre-existing via posts 110 have a YX aspect ratio greater than 1:1, and the groups of pre-existing via posts 210 have similar heights as the pre-existing via posts under the processing parameter constraints. In an embodiment, the pre-existing via posts 110 have a YX aspect ratio less than 1:1, and the groups of pre-existing via posts 210 have similar heights. In an embodiment, the pre-existing via posts 110 have a YX aspect ratio less than or equal to 10:1, and the groups of pre-existing via posts 210 have similar heights. In an embodiment, the pre-existing via posts 110 have a YX aspect ratio in a range from 9:1 to 2:1, and the groups of pre-existing via posts 210 have similar heights. In an embodiment, the pre-existing via pillar 110 has a YX aspect ratio in a range from 8:1 to 3:1, and the group of pre-existing via pillars 210 has a similar height. In an embodiment, the pre-existing via pillar 110 has a YX aspect ratio in a range from 7:1 to 4:1, and the group of pre-existing high via pillars 210 has a similar height. In an embodiment, the pre-existing high via pillar 110 has a YX aspect ratio in a range from 6:1 to 5:1, and the group of pre-existing high via pillars 210 has a similar height.

[0041] The organic substrate 20 may have a base layer 112 and a first trace layer 114. In an embodiment, the bridge level organic layer 116 has been milled to form a groove in which the silicon bridge 10 has been placed.

[0042] exist Figure 23 directs attention to the left from an arbitrary fracture 30 which is shown to aid in illustrating a selected process embodiment.

[0043] Focus on the left side Figure 2 , including structures that contact the items indicated by reference numeral 124. In an embodiment, the substrate-base interconnect includes a seed layer 120, a first bonding pad 122, a first via 124, and a subsequent bonding pad 126. The first bonding pad 122 has been plated on the seed layer 120, and the first via 124 has been formed on the first bonding pad 122 by a semi-additive plating technique. In an embodiment, the first bonding pad 122 is formed by first patterning a first dielectric layer 129 using photolithography techniques, and then electroplating is performed, such as electroplating the first bonding pad 122 onto the seed layer 120. In an embodiment, the first dielectric layer 129 is first formed and patterned for the first bonding pad 122, but at a Z height that protects the pre-existing high via pillars 110 and 210 during the electroplating of the first bonding pad 122. Thereafter, the height of the first dielectric layer 129 is reduced, such as by wet etching, plasma etching, and reactive ion etching (RIE), to obtain the first dielectric layer 129 as depicted, such that the etching is selective to leaving the first bonding pad 124 and the pre-existing via posts 110 and 210. Next, the semi-additive plating is completed by forming and patterning the second dielectric layer 131, which can also cover the pre-existing via posts 110 and 210 during the plating of the first via 124, and then another etch is performed that reduces the height of the second dielectric layer 131 that exposes and stops at the Z height of both the first via 124 and the top of the pre-existing via post 110. Thereafter, the subsequent bonding pad 126 is formed by patterning a subsequent dielectric layer (not shown), then electroplating the subsequent bonding pad 126 and the pre-existing via post bonding pads 128 and 128', stripping the subsequent dielectric layer, and further then forming a first solder resist layer having openings 132. The first solder resist layer having openings 132 exposes the subsequent bonding pad 126 and the post bonding pads 128 and 128', and it represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10.

[0044] It can now be appreciated that the photolithographic processing embodiments depicted herein allow for small geometries that would otherwise be limited if laser drilling were used to open the locations of both the first bond pad 122 and the first via 124. For example, conventional laser drilling may not be able to form a bond pad opening where the bond pad opening is limited to approximately 25 micrometers (μm), and to obtain geometries less than 25 μm, an ultraviolet (UV) laser may be used, but at the expense of significantly reduced throughput.

[0045] Focus on the left Figure 2 , including structures that contact the items indicated by reference numeral 123. In an embodiment, the substrate-base interconnect includes an integral first bonding pad and via 123 that has been electroplated on the seed layer 120. In an embodiment, photolithography techniques are used by patterning a first dielectric layer 129 and then filling a sacrificial dummy (not depicted) that occupies an equal space of the first bonding pad 122 adjacent to and seen to the left of the integral first bonding pad and via 123. Thereafter, the height of the first dielectric layer 129 is reduced, such as by wet etching, plasma etching, and RIE, to obtain the first dielectric layer 129 as depicted, so that the etching is selective to leaving the pre-existing via posts 110 and 210 and the sacrificial dummy. Next, a second dielectric layer 131 is formed, which may also cover the pre-existing via posts 110 and 210, and the second dielectric layer 131 is patterned to open the via portion of the integral first bonding pad and via 123. After patterning, the dummy layer is dissolved by any known, useful technique, such as a wet etch that is selective to the seed layer 120, the first dielectric layer 129, and the patterned second dielectric layer 131. The etch removes the dummy to form the negative space to be filled by electroplating the integral first bonding pad and via 123. Thereafter, the height of the second dielectric layer 131 is lowered to expose the Z height of both the top of the integral first bonding pad and via 123 and the top of the pre-existing via posts 110 and 210. It can be observed that the integral first bonding pad and via 123 can have a lower resistance than the resistance of the first bonding pad 122 and the first via 124 because one reduces the metal-to-metal interface within the integral first bonding pad and via 123.

[0046] Thereafter, subsequent bond pads 126 are formed by patterning a subsequent dielectric layer (not shown), then electroplating subsequent bond pads 126 and via post bond pads 128 and 128', stripping the subsequent dielectric layer, and further then forming a first solder resist layer having openings 132. Via post bond pads 128' contact the grouped via posts 210, and via post bond pads 128 contact the non-grouped via posts 110. The first solder resist layer having openings 132 exposes subsequent bond pads 126 and via bond pads 128 and 128', and it represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10.

[0047] It can now be observed in embodiments that the first bond pad 122 and first via 124 depicted to the left of any break 30 will effectively occupy all via structures useful at that level within the organic substrate 20. It can now be observed in embodiments that the overall bond pad and via 123 depicted to the left of any break 30 will occupy all via structures useful at that level within the organic substrate 20.

[0048] exist Figure 2 3 directs attention to the right from an arbitrary fracture 30, which is shown to aid in illustrating a selected process embodiment.

[0049] Focus on the right side Figure 2, including structures that contact the items indicated by reference numeral 124. In an embodiment, the substrate-base interconnect includes a seed layer, a first bonding pad 122, a first via 124, and a subsequent bonding pad 126. The first bonding pad 122 has been plated on the seed layer 120, and the first via 124 has been formed on the first bonding pad 122 by a semi-additive plating technique. In an embodiment, the first bonding pad 122 is formed by first patterning a first dielectric layer (not depicted) using photolithography techniques, and then electroplating is performed, such as electroplating the first bonding pad 122 onto the seed layer 120. In an embodiment, the first dielectric layer is first formed and patterned for the first bonding pad 122, but at a Z height that protects the pre-existing via posts 110 and 210 during the electroplating of the first bonding pad 122. Thereafter, the first dielectric layer is stripped and removed, such as by wet etching, plasma etching, and reactive ion etching (RIE), to obtain the first dielectric layer 129 as depicted, such that the etching is selective to leaving the first bonding pad 124 and the pre-existing via posts 110 and 210. Next, the semi-additive plating is completed by forming and patterning the second dielectric layer 131, which can also cover the pre-existing via posts 110 and 210 during the plating of the first via 124, and then another etch is performed, which reduces the height of the second dielectric layer 131 to a height that exposes and stops at the Z height of both the first via 124 and the top of the pre-existing via posts 110 and 210. Thereafter, subsequent bond pads 126 are formed by patterning a subsequent dielectric layer (not shown), then electroplating subsequent bond pads 126 and via post bond pads 128 and 128', stripping the subsequent dielectric layer, and further then forming a first solder resist layer having openings 132. The first solder resist layer having openings 132 represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10.

[0050] Focus on the right side Figure 2Items shown in , including structures that contact items indicated by reference numeral 123. In an embodiment, the substrate-base interconnect includes an integral first bonding pad and via 123 that has been electroplated on the seed layer 120. In an embodiment, photolithography is used by patterning a first dielectric layer (not depicted) and then filling a sacrificial dummy (not depicted) that occupies an equal space of the first bonding pad 122 adjacent to and seen to the left of the integral first bonding pad and via 123. Thereafter, the first dielectric layer is stripped and removed, such as by wet etching, plasma etching, and RIE, so that the etching is selective to leaving the pre-existing via posts 110 and 210 and the sacrificial dummy. Next, a second dielectric layer 131 is formed, which may also cover the pre-existing via posts 110 and 210, and the second dielectric layer 131 is patterned to open the via portion of the integral first bonding pad and via 123. After patterning, the dummy layer is dissolved by any known, useful technique, such as a wet etch that is selective to the seed layer 120 and the patterned second dielectric layer 131. The etch removes the dummy to form a negative space to be filled by electroplating the integral first bonding pad and via 123. Thereafter, the height of the second dielectric layer 131 is lowered to expose the Z height of both the top of the integral first bonding pad and via 123 and the top of the via posts 110 and 210. It can be observed that the integral first bonding pad and via 123 can have a lower resistance than the resistance of the first bonding pad 122 and the first via 124 because one reduces the metal-to-metal interface within the integral first bonding pad and via 123.

[0051] Thereafter, subsequent bond pads 126 are formed by patterning a subsequent dielectric layer (not shown), then electroplating subsequent bond pads 126 and via post bond pads 128 and 128', stripping the subsequent dielectric layer, and further then forming a first solder resist layer having openings 132. The first solder resist layer having openings 132 represents the interface between the organic substrate 20 and any metallization that may be required for a given particular use of the embedded silicon bridge 10.

[0052] It can now be observed in embodiments that the first bond pad 122 and first via 124 depicted to the right of any break 30 will effectively occupy all via structures useful at that level within the organic substrate 20. It can now be observed in embodiments that the overall bond pad and via 123 depicted to the right of any break 30 will occupy all via structures useful at that level within the organic substrate 20.

[0053] Figure 3 FIG. 3 is a cross-sectional elevation view of an embedded silicon bridge 300 with a bonding pad reinforcement via post on the bridge according to an embodiment. Figure 1 A similar structure is seen on the right side of the arbitrary fracture 30 in relation to the processing of the first via 124, and where the second dielectric layer 131 has been formed after stripping away any previous dielectric layer that may have affected the silicon bridge 10. However, it will be appreciated that during fabrication of the embedded silicon bridge 300, the integral first bond pad and via structure may be accompanied by a reinforced, pre-existing via post 311.

[0054] The reinforcing via post pad 311 accompanies the pre-existing via post 310. During processing, when the silicon bridge 10 is placed, for example, Figure 1C and 1D As seen in the recess 118 , the stiffener via post pad 311 and the pre-existing via post 310 have been previously assembled to the silicon bridge 10 prior to placement.

[0055] It can be seen that the pre-existing via post 110 reaches a height Z above the upper surface of the bridge-level organic layer 116, which will eventually match the height at the bottom of the subsequent bond pad 126. Therefore, the pre-existing via post 110 is high enough to be on the silicon bridge 10, and the design allows for a scalable embedded silicon bridge structure in a lithographically defined via package.

[0056] Figure 4 is a cross-sectional elevation view of an embedded silicon bridge 400 having a high via post reinforced with a bond pad on the bridge that matches the metallization subsequent pad height 401, according to an embodiment. Again, the "high via post" extends to the same level as the subsequent bond pad 126. Thus, the pre-existing high via post 410 extends high enough from the silicon bridge 10 that the design allows for a scalable embedded silicon bridge structure in a lithographically defined through-hole package.

[0057] For simplicity, in Figure 3 A similar structure is seen in relation to the processing of the first via 124, and wherein the second dielectric layer 131 has been formed after stripping away any previous dielectric layers that may have affected the silicon bridge 10. However, it will be appreciated that during fabrication of the embedded silicon bridge 400, the integral first bond pad and via structure may be accompanied by a reinforced, pre-existing high via pillar 410.

[0058] The reinforcing high via post pad 411 accompanies the pre-existing high via post 410. During processing, when the silicon bridge 10 is placed, for example, Figure 1C and 1D As seen in the recess 118 , the reinforcing high via post pad 411 and the pre-existing high via post 410 have been previously assembled to the silicon bridge 10 prior to placement.

[0059] It can be seen that the pre-existing high via post 410 reaches a Z height that is substantially the top surface of the metallization subsequent pad height 401. Therefore, the pre-existing high via post 410 is tall enough to be on the silicon bridge 10, and the design allows for a scalable embedded silicon bridge structure in a lithographically defined through-hole package.

[0060] It can now be appreciated that the pre-existing high via pillar 410 on the bridge bond pad can be high enough so that the first via 124 can be followed by the second bond pad and the subsequent via, followed by the subsequent bond pad 126, when reaching the same height as the subsequent pad height 401. This means that the pre-existing high via pillar 410 on the bridge bond pad can reach a height that involves a plurality of vias equivalent to being stacked in sequence above the first bond pad 122.

[0061] Figure 5 is a cross-sectional elevation view of an embedded silicon bridge 500 having a high via post 510 matching the metallization subsequent pad height 501 according to an embodiment.

[0062] For simplicity, in Figure 4 A similar structure is seen in relation to the processing of the first via 124, and wherein the second dielectric layer 131 has been formed after stripping away any previous dielectric layer that may have affected the silicon bridge 10. However, it will be appreciated that during fabrication of the embedded silicon bridge 400, the integral first bond pad and via structure may be accompanied by a reinforced, pre-existing high via pillar 510.

[0063] During processing, when the silicon bridge 10 is placed, for example, Figure 1C and 1D As seen in the recess 118 , the pre-existing high via post 510 has been previously assembled to the silicon bridge 10 prior to placement.

[0064] It can be seen that the pre-existing high via post 510 reaches a Z height that is substantially the top surface of the metallization subsequent pad height 501. Therefore, the pre-existing high via post 510 is tall enough to be on the silicon bridge 10, and the design allows for a scalable embedded silicon bridge structure in a lithographically defined through-hole package.

[0065] It can now be appreciated that the pre-existing high via pillar 510 can be tall enough so that the first via 124 can be followed by the second bond pad and the subsequent via, followed by the subsequent bond pad 126, when reaching the same height as the subsequent pad height 501. This means that the pre-existing high via pillar 510 can reach a height that involves a plurality of vias equivalent to being stacked in sequence above the first bond pad 122.

[0066] Figure 5Also illustrated is a semiconductor device in die 50 attached to an electrical bump 502 present in a solder mask having an opening 132 located at a metallized subsequent pad height 501. It will now be appreciated that silicon bridge 10 is configured to provide communication between a first semiconductor device in die 50 (illustrated on the right) and a subsequent semiconductor device in die 52 (illustrated by downward arrow movement during mating) mounted on the die 52. Figure 5 , where the top of the pre-existing high via post 528 is exposed through the solder resist layer having the opening 132 .

[0067] It is now understood that including but not limited to Figure 1-5 , 1A-1H, and 6-8 may include at least one semiconductor device in die 50. Also in an embodiment, all illustrated embodiments may also include a semiconductor device in die 50 as a first semiconductor device in die 50, and a semiconductor device in die 52, such as a second semiconductor device in die 52.

[0068] Figure 6 is a process flow diagram 600 illustrating a process according to an embodiment.

[0069] At 610, the process includes forming a first bonding pad on the organic substrate by photolithography. In a non-limiting example embodiment, the first bonding pad 122 and the trace 134 are formed on the bridge organic layer 116, such as Figure 1A As depicted in .

[0070] At 620, the process includes forming a first via on the first bonding pad by photolithography. In a non-limiting example, the first via 124 is formed on the first bonding pad 122, such as Figure 1B As depicted in .

[0071] At 630, the process instead begins by forming an integral first bonding pad and via on an organic substrate by photolithography. In a non-limiting example embodiment, the first bonding pad and via are formed as described. Figure 1 The integral bonding pad and via 123 are depicted in FIG.

[0072] At 640, the process includes opening a groove in the organic substrate to accommodate the silicon bridge including the pre-existing via post. Milling techniques may be used to form the groove, as disclosed. In a non-limiting example embodiment, an adhesive film such as Figure 1C In a non-limiting example embodiment, at the level of the adhesive film, if any, the metal ink is patterned to be aligned with the TSV (such as Figure 8 The TSV 811) depicted in FIG.

[0073] At 650, the process includes placing a silicon bridge in the groove. In a non-limiting example embodiment, the silicon bridge 10 has been placed in the groove, such as Figure 1D As depicted in .

[0074] At 660, the process includes forming a subsequent bonding pad coupled to the first via. In a non-limiting example embodiment, the subsequent bonding pad 126 is formed on top of the first via 124, such as Figure 1 As shown in the figure.

[0075] At 662 , the process includes forming a bond pad over and on the pre-existing via post. In a non-limiting example embodiment, the pre-existing via post bond pad 128 is formed at the same level as the subsequent bond pad 126 .

[0076] At 670 , the process includes forming a dielectric layer having an opening that exposes a subsequent bond pad and at least one of a pre-existing via post or a bond pad over and on the pre-existing via post.

[0077] At 680, the process includes assembling at least one die to the silicon bridge to form a system-in-package (SiP) device. Figure 5 As shown in simplified form in FIG. 1 , the semiconductor device in die 50 has been assembled to silicon bridge 10 by bumps that have filled some of the openings in the solder resist layer having openings 132. It can now be understood that another semiconductor device in the die can be attached opposite the illustrated semiconductor device in die 50.

[0078] At 690 , the process includes assembling the SiP into a computing system.

[0079] Figure 7 is a computing system 700 according to an embodiment.

[0080] Further discussion of embodiments of computing system 700 is set forth herein.

[0081] Figure 7 is a computing system 700 according to an embodiment. Figure 7 A system level diagram according to an embodiment of the present invention is illustrated. For example, Figure 7 An example of a microelectronic device including an embedded silicon bridge with a pre-existing via post embodiment as described in the present disclosure is depicted.

[0082] include Figure 7700 is a computer system 700 that is used to store and process data of a plurality of computer components. The computer system 700 includes ...

[0083] In an embodiment, the processor 710 has one or more processing cores 712 and 712N, where 712N represents the Nth processor core inside the processor 710, where N is a positive integer. In an embodiment, the electronic device system 700 using the wire-bonded SiP embodiment includes a plurality of processors, the processors including 710 and 705, wherein the processor 705 has logic similar to or identical to the logic of the processor 710. In an embodiment, the processing core 712 includes, but is not limited to, pre-fetch logic for fetching instructions, decoding logic for decoding instructions, execution logic for executing instructions, and the like. In an embodiment, the processor 710 has a cache memory 716 for caching at least one of instructions and data for an embedded silicon bridge using a pre-existing through-hole pillar embodiment computing system 700. The cache memory 716 can be organized into a hierarchical structure including one or more levels of cache memory.

[0084] In an embodiment, the processor 710 includes a memory controller 714 that is operable to perform functions that enable the processor 710 to access and communicate with a memory 730, which includes at least one of a volatile memory 732 and a non-volatile memory 734. In an embodiment, the processor 710 is coupled to the memory 730 and the chipset 720. The processor 710 may also be coupled to an antenna 778 to wirelessly communicate with any device configured to transmit and receive at least one of wireless signals. In an embodiment, the antenna interface 778 operates according to, but is not limited to, the IEEE 802.11 standard and its related series, Home Plug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0085] In an embodiment, the volatile memory 732 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 734 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0086] Memory 730 stores information and instructions to be executed by processor 710. In an embodiment, memory 730 may also store temporary variables or other intermediate information while processor 710 is executing instructions. In the illustrated embodiment, chipset 720 is connected to processor 710 via point-to-point (PtP or PP) interfaces 717 and 722. Any of these PtP embodiments may be implemented using an embedded silicon bridge with a pre-existing through-hole post embodiment, as described in the present disclosure. Chipset 720 enables processor 710 to connect to other elements in a wire-bonded SiP embodiment system 700. In an embodiment, interfaces 717 and 722 are configured in accordance with a method such as The PtP communication protocol operates over a QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0087] In an embodiment, the chipset 720 is operable to communicate with the processor 710, 705N, the display device 740, and other devices 772, 776, 774, 760, 762, 764, 766, 777, etc. The chipset 720 may also be coupled to an antenna for wireless communications 778 to communicate with any device configured to perform at least one of transmitting and receiving wireless signals.

[0088] Chipset 720 is connected to display device 740 via interface 726. Display 740 can be, for example, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other form of visual display device. In an embodiment, processor 710 and chipset 720 are combined into a single SOC, such as the selected ladder stack memory module SiP embodiment described herein. In addition, chipset 720 is connected to one or more buses 750 and 755 that interconnect various elements 774, 760, 762, 764, and 766. Buses 750 and 755 can be interconnected via bus bridge 772. In an embodiment, chipset 720 is coupled to non-volatile memory 760, (one or more) mass storage device 662, keyboard / mouse 664, and network interface 766 through at least one of interfaces 724 and 704, smart TV 776, and consumer electronic device 777, etc.

[0089] In an embodiment, the mass storage device 762 includes, but is not limited to, a solid-state drive, a hard disk drive, a universal serial bus flash drive, or any other form of computer data storage medium. In an embodiment, the network interface 766 is implemented by any type of well-known network interface standard, including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) Express interface, a wireless interface, and / or any other suitable type of interface. In an embodiment, the wireless interface operates according to, but is not limited to, the IEEE 802.11 standard and its related series, Home Plug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0090] Although it will Figure 7 The modules shown in are depicted as separate blocks within an embedded silicon bridge with a pre-existing via post computing system 700, but the functions performed by some of these blocks may be integrated within a single semiconductor circuit, or may be implemented using two or more separate integrated circuits. For example, although cache memory 716 is depicted as a separate block within processor 710, cache memory 716 (or selected aspects of 716) may be incorporated into processor core 712.

[0091] In an embodiment, computing system 700 is contained in a housing that houses any embedded silicon bridge with pre-existing via post embodiments. In an embodiment, base layer 112 is substantially constructed as an insulating housing for a computing device. In an embodiment, the housing is part of a board.

[0092] To illustrate a system-in-package device with a package bottom interposer embodiment and the methods disclosed herein, a list of non-limiting examples is provided herein: Example 1 is a semiconductor device in a package, comprising: an organic substrate, wherein the organic substrate comprises: a first bonding pad; a first through hole above and on the first bonding pad, wherein the first through hole extends vertically from the first bonding pad; and a subsequent bonding pad above and electrically connected to the first through hole; a solder resist layer having openings, wherein one of the openings exposes the subsequent bonding pad; and a semiconductor bridge embedded in the organic substrate, wherein the semiconductor bridge comprises a through hole post, wherein the through hole post extends vertically from the silicon bridge in the same vertical direction as the first through hole, and wherein the through hole post extends vertically to at least the first through hole.

[0093] In Example 2, the subject matter of Example 1 optionally includes a via post bond pad disposed on the via post.

[0094] In Example 3, the subject matter of any one or more of Examples 1-2 optionally includes a via post bond pad disposed on the via post, wherein the metallized dielectric having the opening also exposes the via post bond pad.

[0095] In Example 4, the subject matter of any one or more of Examples 1-3 optionally includes a via post bonding pad arranged on a via post, wherein the via post bonding pad and a subsequent bonding pad are each arranged on a second dielectric layer, and wherein the second dielectric layer is in contact with a solder resist layer having an opening.

[0096] In Example 5, the subject matter of any one or more of Examples 1-4 optionally includes, wherein the via post is a group of via posts contacting at least two via post bonding pads, further comprising a second via post extending vertically from the silicon bridge and contacting a single via post bonding pad.

[0097] In Example 6, the subject matter of any one or more of Examples 1-5 optionally includes that the via post is a group of via posts contacting at least two via post bonding pads, further including a second via post extending vertically from the silicon bridge and contacting a single via post bonding pad.

[0098] In Example 7, the subject matter of any one or more of Examples 1-6 can optionally include, wherein the via post is disposed on a stiffener via post pad, the stiffener via post pad being attached to the silicon bridge.

[0099] In Example 8, the subject matter of Example 7 optionally includes a via post bond pad disposed on the via post.

[0100] In Example 9, the subject matter of any one or more of Examples 7-8 optionally includes a via post bonding pad arranged on a via post, wherein the via post bonding pad and a subsequent bonding pad are each arranged on a second dielectric layer, and wherein the second dielectric layer is in contact with a solder resist layer having an opening.

[0101] In Example 10, the subject matter of any one or more of Examples 7-9 optionally includes, wherein the via post is a group of via posts contacting at least two via post bonding pads, further comprising a second via post extending vertically from the silicon bridge and contacting a single via post bonding pad.

[0102] In Example 11, the subject matter of any one or more of Examples 7-10 optionally includes the via post extending to a height equal to that of a subsequent bond pad, and wherein each of the subsequent bond pad and the via post is exposed through a corresponding opening in the solder resist layer having the opening.

[0103] In Example 12, the subject matter of any one or more of Examples 1-11 optionally includes a semiconductor device in a die, wherein the semiconductor device in the die is attached to an organic substrate, and wherein the semiconductor device in the die is electrically connected to at least a through-hole post through a solder resist layer having an opening.

[0104] In Example 13, the subject matter of any one or more of Examples 1-12 optionally includes a first semiconductor device in a die, wherein the first semiconductor device in the die is attached to an organic substrate, and wherein the first semiconductor device in the die is electrically connected to at least a through-hole post through a solder resist layer having an opening; and a subsequent semiconductor device in the die, wherein the subsequent semiconductor device in the die is attached to an organic substrate opposite to the first semiconductor device in the die, and wherein the subsequent semiconductor device in the die is electrically connected to at least the through-hole post through a solder resist layer having an opening 132.

[0105] In Example 14, the subject matter of any one or more of Examples 1-13 optionally includes, wherein the silicon bridge includes an active surface, the through-hole pillars extending from the active surface, and further includes through-silicon vias (TSVs) in the silicon bridge, wherein the TSVs extend from the active surface and in a direction opposite to the through-hole pillars.

[0106] Embodiment 15 is a method for embedding a silicon bridge, comprising: forming a first bonding pad on an organic substrate by patterning a mask and electroplating the first bonding pad onto a seed layer; forming a first through hole on the first bonding pad by patterning a mask and electroplating a first through hole on the first bonding pad; opening a groove in the organic substrate to accommodate the silicon bridge, wherein the silicon bridge includes a pre-existing through hole column arranged thereon; placing the silicon bridge in the groove; forming a subsequent bonding pad above the first through hole; and forming a dielectric layer with an opening under certain conditions to expose the subsequent bonding pad and expose a passage to the pre-existing through hole column.

[0107] In Example 16, the subject matter of Example 15 can optionally include, wherein forming the first bonding pad and the first via comprises forming the integral first bonding pad and via by electroplating onto the seed layer.

[0108] In Example 17, the subject matter of any one or more of Examples 15-16 optionally includes forming the via post bond pad simultaneously with forming the subsequent bond pad.

[0109] In Example 18, the subject matter of any one or more of Examples 15-17 optionally includes wherein the pre-existing via post is one of a plurality of via posts including at least one grouped via post, further comprising forming a plurality of bonding pads on the grouped via posts simultaneously with forming subsequent bonding pads.

[0110] In Example 19, the subject matter of any one or more of Examples 15-18 may optionally include assembling at least one semiconductor device in the die to an organic substrate in communication with the silicon bridge.

[0111] Example 20 is a computing system comprising: an organic substrate, wherein the organic substrate comprises: a first bonding pad; a first through hole above and on the first bonding pad, wherein the first through hole extends vertically from the first bonding pad; and a subsequent bonding pad above and in electrical communication with the first through hole; a solder resist layer having an opening, wherein one of the openings exposes the subsequent bonding pad; a semiconductor bridge embedded in the organic substrate, wherein the semiconductor bridge comprises a through hole post extending vertically from a silicon bridge in the same vertical direction as the first through hole, and wherein the through hole post extends vertically to at least the first through hole; a housing containing the silicon bridge; a first semiconductor device in a die, wherein the first semiconductor device in the die is attached to the organic substrate, and wherein the first semiconductor device in the die is electrically connected to at least the through hole post through the solder resist layer having an opening 132; and a subsequent semiconductor device in the die, wherein the subsequent semiconductor device in the die is attached to the organic substrate opposite to the first semiconductor device in the die, and wherein the subsequent semiconductor device in the die is electrically connected to at least the through hole post through the solder resist layer having an opening 132.

[0112] In Example 21, the subject matter of Example 20 optionally includes a via post bonding pad disposed on the via post, wherein the solder resist layer having the opening further exposes the via post bonding pad.

[0113] In Example 22, the subject matter of any one or more of Examples 20-21 optionally includes a via post bonding pad arranged on a via post, wherein the via post bonding pad and a subsequent bonding pad are each arranged on a second dielectric layer, and wherein the second dielectric layer is in contact with a solder resist layer having an opening.

[0114] In Example 23, the subject matter of any one or more of Examples 20-22 optionally includes, wherein the via post is a group of via posts contacting at least two via post bonding pads, further comprising a second via post extending vertically from the silicon bridge and contacting a single via post bonding pad.

[0115] In Example 24, the subject matter of any one or more of Examples 20-23 optionally includes, wherein the via post is one of a plurality of via posts including at least one group of via posts, further comprising forming a plurality of bonding pads on the group of via posts simultaneously with forming subsequent bonding pads.

[0116] The above detailed description includes reference to the accompanying drawings that form a part of the detailed description. The accompanying drawings illustrate specific embodiments in which the present invention can be implemented by way of illustration. These embodiments are also referred to as "examples" in this article. Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the inventors also contemplate examples of any combination or arrangement of those elements shown or described (or one or more aspects thereof) or about other examples shown or described in this article (or one or more aspects thereof).

[0117] In the event of inconsistent usages between this document and any document so incorporated by reference, the usage in this document controls.

[0118] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise indicated. In this document, the terms "including" and "wherein" are used as the plain English equivalents of the respective terms "comprising" and "wherein". In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, composition, formula, or process that includes elements other than those listed after such terms in the claim is still deemed to fall within the scope of the claim. Moreover, in the appended claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0119] The method examples described herein may be at least partially machine or computer-implemented. Some examples may include computer-readable media or machine-readable media that are operable to configure an electronic device to perform an instruction encoding of a method as described in the above example. The implementation of such a method may include code, such as microcode, assembly language code, higher-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, in an example, the code may be tangibly stored on one or more volatile, non-temporary or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0120] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as by a person of ordinary skill in the art, when reviewing the above description. An abstract is provided to comply with 37C.FR§1.72(b) to allow readers to quickly ascertain the essence of the technical disclosure. The following understanding is proposed: it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above specific embodiments, various features can be grouped together to simplify the disclosure (streamline). This should not be interpreted as intended to be necessary for any claim to disclose features that are not required for protection. Instead, the subject matter of the invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the specific embodiments as examples or embodiments, wherein each claim is independent as a separate embodiment, and it is considered that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the attached claims together with the full scope of equivalents enjoyed by such claims.

Claims

1. A semiconductor device in a package, comprising: An organic substrate, wherein the organic substrate comprises: a first bonding pad; a first through-hole over and on the first bonding pad, wherein the first through-hole extends vertically from the first bonding pad; and a subsequent bonding pad over and electrically connected to the first through-hole; a solder mask layer having openings, wherein one opening exposes a subsequent bond pad; and A semiconductor bridge embedded in an organic substrate, wherein the semiconductor bridge comprises a via post extending vertically from the silicon bridge in the same vertical direction as the first via, and wherein the via post extends vertically to at least the first via. 2 . The semiconductor device of claim 1 , further comprising a via post bonding pad disposed on the via post. 3 . The semiconductor device of claim 1 , further comprising a via post bonding pad disposed on the via post, wherein the metallization dielectric having the opening also exposes the via post bonding pad.

4. The semiconductor device according to claim 1 further comprises a via post bonding pad arranged on the via post, wherein the via post bonding pad and the subsequent bonding pad are each arranged on a second dielectric layer, and wherein the second dielectric layer contacts the solder resist layer having the opening. 5 . The semiconductor device of claim 1 , wherein the via post is a group of via posts contacting at least two via post bonding pads, further comprising a second via post extending vertically from the silicon bridge and contacting a single via post bonding pad.

6. A method of embedding a silicon bridge, comprising: forming a first bonding pad on the organic substrate by patterning a mask and electroplating the first bonding pad onto the seed layer; forming a first via on the first bonding pad by patterning a mask and electroplating the first via on the first bonding pad; opening a recess in the organic substrate to accommodate a silicon bridge, wherein the silicon bridge includes a pre-existing via post disposed thereon; placing the silicon bridge in the groove; forming a subsequent bond pad over the first through hole; as well as A dielectric layer is formed with openings under conditions to expose subsequent bond pads and to expose access to pre-existing via posts. 7 . The method of claim 6 , wherein forming the first bonding pad and the first via comprises forming the integral first bonding pad and via by electroplating onto the seed layer. 8 . The method of claim 6 , further comprising forming the via stud bond pad simultaneously with forming a subsequent bond pad.

9. A computing system comprising: An organic substrate, wherein the organic substrate comprises: a first bonding pad; a first via over and on the first bonding pad, wherein the first via extends vertically from the first bonding pad; and a subsequent bonding pad over and in electrical communication with the first via; a solder mask layer having openings, wherein one opening exposes a subsequent bonding pad; a semiconductor bridge embedded in an organic substrate, wherein the semiconductor bridge includes a via post extending vertically from the silicon bridge in the same vertical direction as the first via, and wherein the via post extends vertically to at least the first via; a housing to house the silicon bridge; a first semiconductor device in a die, wherein the first semiconductor device in the die is attached to an organic substrate, and wherein the first semiconductor device in the die is electrically connected to at least a via post through a solder resist layer having an opening; and A subsequent semiconductor device in a die, wherein the subsequent semiconductor device in the die is attached to an organic substrate opposite to the first semiconductor device in the die, and wherein the subsequent semiconductor device in the die is electrically connected to at least a via post through a solder resist layer having an opening. 10 . The computing system of claim 9 , further comprising a via post bonding pad disposed on the via post, wherein the solder resist layer having the opening further exposes the via post bonding pad.

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