Semiconductor element with resistance-modified doped region

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source and drain (S / D) region, and a resistance modified doped region. The well region is located in the substrate and has a first conductive type. The fuse medium is disposed on the substrate. The gate electrode is disposed on the fuse medium. The fuse doped region is located below the gate electrode and has a second conductivity type different from the first conductivity type. The S / D region is adjacent to the fuse doped region having the second conductivity type. The resistance modification doped region has the second conductivity type and partially overlaps the fuse doped region.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 238,022 (i.e., the priority date is "August 25, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a resistance-modified doping region. Background Art

[0003] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advances in materials and design of integrated circuits have created generations of integrated circuits, and each generation of integrated circuits is smaller and more complex than the previous generation.

[0004] A dynamic random access memory (DRAM) device is a type of random access memory that stores each data bit in a separate capacitor in an integrated circuit. Typically, DRAM is arranged in a square array, with one capacitor and one transistor per cell. The vertical transistor is a 4F 2 Developed for DRAM cells, F represents the minimum feature width or critical dimension (CD) of photolithography. However, DRAM manufacturers have recently faced huge challenges with the evolution of technology nodes.

[0005] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] One aspect of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate, a well region, a fuse dielectric, a gate electrode, a fuse doping region, a source and drain (S / D) region, and a resistance modified doping region. The well region is located in the substrate and has a first conductivity type. The fuse dielectric is disposed on the substrate. The gate electrode is disposed on the fuse dielectric. The fuse doping region is located under the gate electrode and has a second conductivity type different from the first conductivity type. The S / D region is adjacent to the fuse doping region having the second conductivity type. The resistance modified doping region has the second conductivity type and partially overlaps with the fuse doping region.

[0007] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a well region, a fuse dielectric, a gate electrode, a fuse doping region, a source and drain (S / D) region, and a nitrogen derivative impurity. The well region is located in the substrate and has a first conductivity type. The fuse dielectric is disposed on the substrate. The gate electrode is disposed on the fuse dielectric. The fuse doping region is located under the gate electrode and has a second conductivity type different from the first conductivity type. The S / D region is adjacent to the fuse doping region having the second conductivity type. The nitrogen derivative impurity is in the substrate and under the gate electrode.

[0008] Another aspect of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate, wherein a well region in the substrate has a first conductivity type; forming a resistance modification doping region in the substrate, wherein the resistance modification doping region has a second conductivity type different from the first conductivity type; forming a fuse doping region in the substrate, wherein the fuse doping region has the second conductivity type; and forming a gate electrode on the fuse doping region.

[0009] Embodiments of the present disclosure provide a semiconductor element. The semiconductor element may include a resistance-modified doped region. When the fuse medium is blown at an operating current of less than 4 mA (e.g., a current of less than 1.2 mA), the resistance-modified doped region may make the fuse an ohmic type fuse. The resistance of the ohmic type fuse is positively proportional to the temperature, and the resistance deviation is small. Therefore, the misjudgment of the read operation and / or the write operation can be reduced.

[0010] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purposes as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the disclosure of this application may be obtained when referring to the detailed description and claims taken in conjunction with the drawings, and:

[0012] Figure 1 is a circuit diagram illustrating the circuits of some embodiments of the present disclosure.

[0013] Figure 2is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0014] Figure 3 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0015] Figure 4 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0016] Figure 5 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0017] Figure 6 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0018] Fig. 7A is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 7B is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 7C is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0021] Fig.7D is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0022] Fig. 7E is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0023] Figure 7F is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 8 FIG. 4 is a graph illustrating the relationship between the temperature and the resistance of a hopping type fuse.

[0025] Fig. 9 is a graph illustrating the relationship between the temperature and the resistance of an ohmic type fuse.

[0026] Fig.10 is a graph illustrating the relationship between the temperature and the resistance of an ohmic fuse.

[0027] Fig.11 is a flow chart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0028] The reference numerals are described as follows:

[0029] 100: Circuit

[0030] 110: Fuse

[0031] 112: Terminal

[0032] 114: Terminal

[0033] 120: Transistor

[0034] 122: Terminal

[0035] 124: Terminal

[0036] 126: Terminal

[0037] 200a: Semiconductor components

[0038] 200b: Semiconductor components

[0039] 200c: Semiconductor components

[0040] 200d: Semiconductor components

[0041] 200e: Semiconductor components

[0042] 210: Base

[0043] 210s1: Surface

[0044] 212: Quarantine

[0045] 221: Well region

[0046] 222: Fuse doping area

[0047] 222': Doping area

[0048] 222a: Partial

[0049] 222b: Partial

[0050] 222s1: Lower boundary

[0051] 222s2: Horizontal Boundary

[0052] 223: Source and drain (S / D) region

[0053] 224: Resistance modified doping area

[0054] 224': Doping area

[0055] 224a: Partial

[0056] 224s1: Lower boundary

[0057] 224s2: Horizontal Boundary

[0058] 231: Fuse medium

[0059] 232: Gate electrode

[0060] 232s1: lateral surface

[0061] 241: Interstitial

[0062] 242: Interstitial

[0063] 251: Conductive contacts

[0064] 252: Conductive contacts

[0065] 261: Metal layer

[0066] 262: Metal layer

[0067] 271: Impurities

[0068] 272: Impurities

[0069] 300: Preparation method

[0070] 310: Operation

[0071] 320: Operation

[0072] 330: Operation

[0073] 340: Operation

[0074] 350: Operation

[0075] 360: Operation

[0076] V1: power supply voltage

[0077] V2: power supply voltage

[0078] V3: power supply voltage DETAILED DESCRIPTION

[0079] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally be done by one of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numerals.

[0080] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0081] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers or parts, these elements, components, regions, layers or parts are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part without departing from the teaching of the concept of the present invention.

[0082] The terms used herein are only used to describe specific embodiments and are not intended to be limited to the concepts of the present invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly indicates. It should be further understood that the terms "comprise" and "include", when used in this specification, indicate the presence of the features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

[0083] It should be noted that the term "approximately" modifies the quantity of an ingredient, component, or reactant employed to refer to variations in numerical quantities that may occur, for example, through typical measurements and liquid handling routines used to make concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to make the composition or perform the method, etc. In one aspect, the term "approximately" means within 10% of the reported value. In another aspect, the term "approximately" means within 5% of the reported value. However, in another aspect, the term "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0084] Figure 1 1 is a circuit diagram illustrating a circuit 100 of some embodiments of the present disclosure. In some embodiments, the circuit 100 may include a fuse 110 and a transistor 120. The circuit 100 may be included in a memory element, such as a dynamic random access memory (DRAM) element, a one-time programmable (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element.

[0085] The fuse 110 may include a terminal 112 and a terminal 114. The terminal 112 may be electrically connected to a power supply voltage V1. The terminal 114 may be electrically connected to the transistor 120.

[0086] Transistor 120 may be electrically connected to fuse 110. Transistor 120 may include terminal 122, terminal 124, and terminal 126. Terminal 122 may be electrically connected to power supply voltage V2. Terminal 124 may be electrically connected to terminal 114. Terminal 126 may be electrically connected to power supply voltage V3.

[0087] In some embodiments, during a read operation, the word line (e.g., terminal 122) may be asserted to turn on transistor 120. The enabled transistor 120 allows a sense amplifier to read the voltage on fuse 110 through a bit line (not shown). During a write operation, when the word line is asserted, data to be written may be provided on the bit line.

[0088] Figure 2 1 is a cross-sectional view illustrating a semiconductor device 200a in some embodiments of the present disclosure. In some embodiments, the semiconductor device 200a may be suitable for use in the circuit 100. More specifically, the semiconductor device 200a may include a structure that functions as a fuse, such as Figure 1 The fuse 110 is shown in FIG.

[0089] In some embodiments, the semiconductor element 200a may include a substrate 210. The substrate 210 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc. The substrate 210 may include an elementary semiconductor, including silicon or germanium in single crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a silicon germanium (SiGe) alloy having a gradient germanium (Ge) feature, wherein the composition of silicon and Ge changes from one ratio at one position of the gradient SiGe feature to another ratio at another position. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the silicon germanium alloy. In some embodiments, the substrate 210 may have a multilayer structure, or the substrate 210 may include a multilayer compound semiconductor structure. The substrate 210 may have a surface 210s1.

[0090] The semiconductor device 200a may include an isolation region 212. The isolation region 212 may be recessed from the surface 210s1. In some embodiments, the isolation region 212 may be a shallow trench isolation (STI). In other embodiments, the isolation region 212 may include a local oxidation of silicon (LOCOS) structure or any other suitable isolation structure. The isolation region 212 may include a dielectric material such as an oxide, a nitride, or other suitable material.

[0091] In some embodiments, the semiconductor device 200a may include a well region 221. The well region 221 may be disposed in the substrate 210. The well region 221 may have a first conductivity type. In some embodiments, the first conductivity type is a p-type. In some embodiments, the p-type dopant includes boron (B), other group III elements, or any combination thereof.

[0092] In some embodiments, the semiconductor element 200a may include a fuse doping region 222. The fuse doping region 222 may be disposed in the substrate 210. The fuse doping region 222 may have a second conductivity type different from the first conductivity type. In some embodiments, the second conductivity type is n-type. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), antimony (Sb), other Group V elements, or any combination thereof.

[0093] In some embodiments, the semiconductor device 200a may include a source and drain (S / D) region 223. The S / D region 223 may be disposed in the substrate 210. The S / D region 223 may be adjacent to the fuse doping region 222. The S / D region 223 may contact the fuse doping region 222. The S / D region 223 may partially overlap the fuse doping region 222. The S / D region 223 may have a second conductivity type. In some embodiments, the S / D region 223 may have a dopant including arsenic, phosphorus, other Group V elements, or any combination thereof.

[0094] In some embodiments, the semiconductor device 200a may include a resistance modification doping region 224. The resistance modification doping region 224 may be disposed in the substrate 210. The resistance modification doping region 224 may overlap with the fuse doping region 222. The resistance modification doping region 224 may have a second conductivity type. In some embodiments, the resistance modification doping region 224 may have a dopant including nitrogen (N) and / or a nitrogen derivative. In some embodiments, the dopant concentration of the resistance modification doping region 224 may range from about 10 15 cm -3 Up to about 10 16 cm -3 .

[0095] In some embodiments, the resistance-modified doped region 224 may be configured to make the semiconductor device 200a an ohmic type fuse after the semiconductor device 200a is blown, which will be described in detail later. In some embodiments, the resistance-modified doped region 224 may be configured to modify the relationship between the resistance and temperature of the fuse (e.g., the semiconductor device 200a) under a specific operating current. For example, the resistance-modified doped region 224 may make the resistance of the fuse (e.g., the semiconductor device 200a) positively proportional to the temperature under an operating current of about 0.4 mA to about 1.2 mA, such as 0.4 mA, 0.5 mA, 0.6 mA, 0.7 mA, 0.8 mA, 0.9 mA, 1 mA, 1.1 mA, or 1.2 mA. The operating current may be configured to blow the fuse medium (e.g., the fuse medium 231), so that the resistance of the fuse medium may be changed.

[0096] In some embodiments, the semiconductor element 200a may include a fuse medium 231. The fuse medium 231 may be disposed on the surface 210s1 of the substrate 210. In some embodiments, the fuse medium 231 may vertically overlap the fuse doping region 222. In some embodiments, the fuse medium 231 may vertically overlap the resistance-modified doping region 224. The fuse medium 231 may have a single-layer or multi-layer structure. In some embodiments, the fuse medium 231 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. In some embodiments, the fuse medium 231 is a multi-layer structure, including an interface layer and a high-k (dielectric constant greater than 4) dielectric layer. The interface layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or a combination thereof. The high-k dielectric layer may include a high-k dielectric material, such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-k dielectric materials or combinations thereof. In some embodiments, the high-k dielectric material may be further selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates and combinations thereof.

[0097] In some embodiments, the semiconductor element 200a may include a gate electrode 232. The gate electrode 232 may be disposed on the fuse dielectric. The gate electrode 232 may include polysilicon, silicon germanium and / or at least one metal material, including elements and compounds such as Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, or other suitable conductive materials known in the art. In some embodiments, the gate electrode 232 includes a work function metal layer that provides a metal gate having an n-type metal work function or a p-type metal work function. The p-type metal work function material includes ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or other suitable materials. The n-type metal work function material includes zirconium hafnium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or other suitable materials.

[0098] In some embodiments, the semiconductor element 200a may include a spacer 241 and a spacer 242. The spacer 241 may be disposed on the lateral surface 232s1 of the gate electrode 232. The spacer 242 may be disposed on the lateral surface 232s1 of the gate electrode 232. The spacer 241 and the spacer 242 may include a single layer structure or a multilayer structure. The spacer 241 and the spacer 242 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials or a combination thereof. In some embodiments, the spacer 241 (or the spacer 242) may vertically overlap the fuse doping region 222. In some embodiments, the spacer 241 (or the spacer 242) may not vertically overlap the resistance modified doping region 224.

[0099] In some embodiments, the semiconductor device 200a may include a conductive contact 251 and a conductive contact 252. The conductive contact 251 may be disposed on the gate electrode 232. The conductive contact 251 may be electrically connected to the gate electrode 232. The conductive contact 252 may be disposed on the S / D region 223. The conductive contact 252 may be electrically connected to the S / D region 223. The conductive contact 251 and the conductive contact 252 may include a conductive material. The conductive material may include tungsten, copper, aluminum, tantalum, or other suitable materials.

[0100] In some embodiments, the semiconductor device 200a may include a metal layer 261 and a metal layer 262. The metal layer 261 may be disposed on the conductive contact 251. The metal layer 261 may be electrically connected to the conductive contact 251. The metal layer 262 may be disposed on the conductive contact 252. The metal layer 262 may be electrically connected to the conductive contact 252. The metal layer 261 and the metal layer 262 may include a conductive material. The conductive material may include tungsten, copper, aluminum, tantalum, or other suitable materials.

[0101] In this embodiment, the size (e.g., area or volume) of the fuse doping region 222 may be larger than the size of the resistance modification doping region 224. In some embodiments, a portion 222a of the fuse doping region 222 may be disposed below or below a lower boundary 224s1 of the resistance modification doping region 224. In some embodiments, the fuse doping region 222 may exceed a lateral boundary 224s2 of the resistance modification doping region 224.

[0102] In the comparative semiconductor element, when the fuse medium is blown at an operating current of less than 4 mA, the resistance of the blown fuse is negatively proportional to the temperature, and this fuse (or blown fuse) can be called a hopping type fuse. The resistance deviation of the hopping type fuse is large, which may cause errors in the judgment of the read operation and / or the write operation. In the present embodiment, when the fuse medium 231 is blown at an operating current of less than 4 mA (for example, a current of less than 1.2 mA), the resistance-modified doping region 224 can make the fuse medium 231 an ohmic type fuse. The resistance of the ohmic type fuse is positively correlated with the temperature, and the deviation is small. Therefore, the erroneous judgment of the read operation and / or the write operation can be reduced.

[0103] Figure 3 FIG. 2 is a cross-sectional view illustrating a semiconductor device 200 b according to some embodiments of the present disclosure. The semiconductor device 200 b is similar to Figure 2 The semiconductor device 200a shown in FIG. 1 is different from the semiconductor device 200a in the following aspects.

[0104] In some embodiments, the size (e.g., area or volume) of the fuse doping region 222 may be smaller than the size of the resistance modified doping region 224. In some embodiments, the resistance modified doping region 224 may have a portion 224a disposed below or below the lower boundary 222s1 of the fuse doping region 222. In some embodiments, the resistance modified doping region 224 may exceed the lateral boundary 222s2 of the fuse doping region 222. In some embodiments, the resistance modified doping region may have a portion 224b disposed between the fuse doping region 222 and the substrate 210. In some embodiments, the spacer 241 may vertically overlap the resistance modified doping region 224. In some embodiments, the spacer 242 may vertically overlap the resistance modified doping region 224. In some embodiments, the resistance modified doping region 224 may contact the S / D region 223. In some embodiments, the resistance modified doping region 224 may partially overlap the S / D region 223.

[0105] Figure 4 FIG. 2 is a cross-sectional view illustrating a semiconductor device 200c according to some embodiments of the present disclosure. The semiconductor device 200c is similar to Figure 2 The semiconductor device 200a shown in FIG. 1 is different from the semiconductor device 200a in the following aspects.

[0106] In some embodiments, the fuse doping region 222 may have a portion 222b that exceeds a lateral boundary 224s2 of the resistance modification doping region 224. In some embodiments, the spacer 241 may not vertically overlap the resistance modification doping region 224, while the spacer 242 may vertically overlap the resistance modification doping region 224.

[0107] Figure 5 FIG. 2 is a cross-sectional view illustrating a semiconductor device 200d according to some embodiments of the present disclosure. The semiconductor device 200d is similar to Figure 2 The semiconductor device 200a shown in FIG. 1 is different from the semiconductor device 200a in the following aspects.

[0108] In some embodiments, the semiconductor element 200d may include an impurity 271 and an impurity 272. In some embodiments, the impurity 271 may be doped into the substrate 210. In some embodiments, the impurity 271 may be doped under the gate electrode 232. In some embodiments, the impurity 271 may be doped into the fuse doping region 222. The impurity 271 may include a nitrogen derivative impurity. In some embodiments, the impurity 271 may include a nitride. In some embodiments, the impurity 271 may include a nitrogen oxide. In some embodiments, a portion of the impurity 271 may extend beyond the fuse doping region 222 or be located outside the fuse doping region 222. In some embodiments, the impurity 271 may be located below the spacer 241. In some embodiments, the impurity 271 may be located below the spacer 242. In some embodiments, the concentration of the impurity 271 may be gradient or non-uniform. For example, the concentration of the impurity 271 is higher near the surface 210s1, and lower below the fuse doping region 222.

[0109] In some embodiments, the impurities 272 may be doped into the substrate 210. In some embodiments, the impurities 272 may be doped under the gate electrode 232. In some embodiments, the impurities 272 may be doped into the fuse doping region 222. The impurities 272 may include nitrogen.

[0110] When the fuse medium 231 is blown at an operating current below 4 mA (eg, a current below 1.2 mA), the impurities 271 and / or 272 may change the resistance of the fuse, making the fuse medium 231 an ohmic fuse. Therefore, misjudgment of read operations and / or write operations may be reduced.

[0111] Figure 6 FIG. 2 is a cross-sectional view illustrating a semiconductor device 200 e according to some embodiments of the present disclosure. The semiconductor device 200 e is similar to Figure 5 The semiconductor device 200d shown in FIG. 2 is different from the semiconductor device 200d in the following manner.

[0112] In some embodiments, impurities 271 may be located within S / D region 223. In some embodiments, impurities 272 may be located within S / D region 223.

[0113] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E and Figure 7F is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0114] Reference Fig. 7A , a substrate 210 may be provided. An isolation region 212 may be formed in the substrate 210 to define a fuse region.

[0115] Reference Figure 7B , a doping region 224' may be doped into the substrate 210. The doping technique of the doping region 224' may include an implantation technique. In some embodiments, the doping region 224' may include nitrogen. In some embodiments, the ion implantation energy of the doping region 224' may range from about 10 keV to about 30 keV, such as 10 keV, 15 keV, 20 keV, 25 keV, or 30 keV.

[0116] Reference Figure 7C , a doping region 222' may be doped into the substrate 210. The doping technique of the doping region 222' may include an implantation technique. In some embodiments, the doping region 222' may include phosphorus, arsenic, antimony, or a combination thereof. In some embodiments, the implantation energy of the doping region 222' may be greater than the implantation energy of the doping region 224'. In some embodiments, the implantation energy of the doping region 222' may be from about 20keV to about 40keV, for example, 20keV, 25keV, 30keV, 35keV, or 40keV. Although Figure 7C The exemplary doped region 224 ′ may be formed before the doped region 222 ′, but in other embodiments, the doped region 222 ′ may be formed before the doped region 224 ′.

[0117] Reference Fig.7D , a fuse medium 231 may be formed on the surface 210s1 of the substrate 210. In some embodiments, the doped region 222' may be activated to form the fuse doped region 222. In some embodiments, the doped region 224' may be activated to form the resistance modified doped region 224. In some embodiments, the manufacturing technology of the fuse medium 231 may include thermal oxidation, so that the doped region 222' and the doped region 224' may be activated.

[0118] Reference Fig. 7E, the fuse dielectric 231 may be patterned. A gate electrode 232 may be formed on the fuse dielectric 231. Spacers 241 and 242 may be located on opposite sides of the gate electrode 232. An S / D region 223 may be formed between the fuse doping region 222 and the isolation region 212. The manufacturing technology of the gate electrode 232, the spacer 241 and / or the spacer 242 may include a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process or a combination thereof. The manufacturing technology of the S / D region 223 may include an implantation technology.

[0119] See also Figure 7F , a conductive contact 251 may be formed on the gate electrode 232. A conductive contact 252 may be formed on the S / D region 223. A metal layer 261 may be formed on the conductive contact 251. A metal layer 262 may be formed on the conductive contact 252. The manufacturing techniques of the conductive contact 251, the conductive contact 252, the metal layer 261 and the metal layer 262 may include a deposition process, such as a CVD process, an ALD process, a PVD process, a sputtering process, an electroplating process or a combination thereof. It should be noted that some processes or stages are omitted for the sake of brevity. For example, before forming the conductive contacts 251 and the conductive contacts 252, an interlayer dielectric (ILD) may be formed on the substrate 210.

[0120] Figure 8 is a graph illustrating the relationship between temperature and resistance of a hopping type fuse. The horizontal axis represents resistance. The vertical axis represents the cumulative percentage of the test results of the comparative semiconductor element. The solid line is the resistance distribution of the semiconductor element at a higher temperature. The dotted line represents the resistance distribution of the semiconductor element at a lower temperature. The resistance is measured after the fuse medium is blown within the range of an operating current of about 0.4 mA to about 1.2 mA. The operating voltage may be between about 4 V and about 6 V. The comparative semiconductor element does not include a resistance-modifying doping region, such as Figure 2 The resistance modified doping region 224 is shown. Figure 8 As shown in FIG. 1 , the comparative semiconductor element has a lower resistance at a higher temperature and a higher resistance at a lower temperature. Figure 8 As shown, 90% of the measurements had a resistance between about 3 kohm and about 15 kohm.

[0121] Fig. 9is a graph illustrating the relationship between temperature and resistance of an ohmic type fuse. The horizontal axis represents resistance. The vertical axis represents the cumulative percentage of the test results of the comparative semiconductor element. The solid line is the resistance distribution of the semiconductor element at a higher temperature. The dotted line represents the resistance distribution of the semiconductor element at a lower temperature. The resistance is measured after the fuse medium is blown within the range of an operating current of about 0.4 mA to about 1.2 mA. The operating voltage may be between about 4 V and about 6 V. The comparative semiconductor element includes a resistance-modifying doped region, such as Figure 2 The resistance modified doping region 224 is shown. The doping concentration of the resistance modified doping region 224 is about 3E15. Fig. 9 As shown in Figure 1, semiconductor components have lower resistance at lower temperatures and higher resistance at higher temperatures. Fig. 9 As shown, 90% of the measurements have a resistance between about 1kohm and about 4kohm. Figure 8 compared to, Fig. 9 The resistance deviation is small.

[0122] Fig.10 is a graph illustrating the relationship between temperature and resistance of an ohmic fuse. The horizontal axis represents resistance. The vertical axis represents the cumulative percentage of the test results of the comparative semiconductor element. The solid line is the resistance distribution of the semiconductor element at a higher temperature. The dotted line represents the resistance distribution of the semiconductor element at a lower temperature. The resistance is measured after the fuse medium is blown in the range of an operating current of about 0.4 mA to about 1.2 mA. The operating voltage may be between about 4 V and about 6 V. The comparative semiconductor element includes a resistance-modifying doped region, such as Figure 2 The resistance modified doping region 224 is shown. The doping concentration of the resistance modified doping region 224 is about 5E15. Fig.10 As shown in Figure 1, semiconductor components have lower resistance at lower temperatures and higher resistance at higher temperatures. Fig.10 As shown, 90% of the measurements have a resistance between about 1kohm and about 4kohm. Figure 8 compared to, Fig.10 The resistance deviation is small.

[0123] Fig.11 is a flow chart illustrating a method 300 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0124] The manufacturing method 300 may start from operation 310, where a substrate is provided. The substrate may include a well region, and the well region has a first conductivity type.

[0125] The fabrication method 300 may continue with operation 320, in which a fuse doping region is formed in the substrate. The fuse doping region may have a second conductivity type that is different from the first conductivity type.

[0126] The preparation method 300 may continue with operation 330, in which a resistance modification doping region is formed in the substrate. The resistance modification doping region may have the second conductivity type different from the first conductivity type. The resistance modification doping region may partially overlap with the fuse doping region.

[0127] The fabrication method 300 may continue with operation 340, in which the resistance modification doped region and the fuse doped region are activated. A fuse dielectric may be formed on the fuse doped region and the resistance modification doped region.

[0128] The fabrication method 300 may continue with operation 350 , where a gate electrode is formed on the fuse dielectric to cover the fuse doping region and the resistance modification doping region, and an S / D region is formed near the fuse doping region in the substrate.

[0129] The manufacturing method 300 may continue with operation 360, where a conductive contact and a metal layer may be formed. Thus, a semiconductor device may be obtained.

[0130] The preparation method 300 is merely an example and is not intended to limit the content of the present disclosure beyond the scope explicitly recited in the claims. Additional operations may be provided before, during, or after each operation of the preparation method 300, and some of the operations described may be replaced, eliminated, or reordered for other embodiments of the method. In some embodiments, the preparation method 300 may also include Fig.11 In some embodiments, the preparation method 300 may include Fig.11 One or more operations described in .

[0131] One aspect of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate, a well region, a fuse dielectric, a gate electrode, a fuse doping region, a source and drain (S / D) region, and a resistance modified doping region. The well region is located in the substrate and has a first conductivity type. The fuse dielectric is disposed on the substrate. The gate electrode is disposed on the fuse dielectric. The fuse doping region is located under the gate electrode and has a second conductivity type different from the first conductivity type. The S / D region is adjacent to the fuse doping region having the second conductivity type. The resistance modified doping region has the second conductivity type and partially overlaps with the fuse doping region.

[0132] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a well region, a fuse dielectric, a gate electrode, a fuse doping region, a source and drain (S / D) region, and a nitrogen derivative impurity. The well region is located in the substrate and has a first conductivity type. The fuse dielectric is disposed on the substrate. The gate electrode is disposed on the fuse dielectric. The fuse doping region is located under the gate electrode and has a second conductivity type different from the first conductivity type. The S / D region is adjacent to the fuse doping region having the second conductivity type. The nitrogen derivative impurity is in the substrate and under the gate electrode.

[0133] Another aspect of the present disclosure provides a method for preparing a semiconductor element. The method includes: providing a substrate, wherein a well region in the substrate has a first conductivity type; forming a resistance modification doping region in the substrate, wherein the resistance modification doping region has a second conductivity type different from the first conductivity type; forming a fuse doping region in the substrate, wherein the fuse doping region has the second conductivity type; and forming a gate electrode on the fuse doping region.

[0134] Embodiments of the present disclosure provide a semiconductor element. The semiconductor element may include a resistance-modified doped region. When the fuse medium is blown at an operating current of less than 4 mA (e.g., a current of less than 1.2 mA), the resistance-modified doped region may make the fuse an ohmic fuse. The resistance of the ohmic fuse is positively correlated with the temperature, and the resistance deviation is small. Therefore, the misjudgment of the read operation and / or the write operation can be reduced.

[0135] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes may be implemented in different ways, and other processes, or combinations thereof may be used to replace many of the above processes.

[0136] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a base; a well region in the substrate having a first conductivity type; a fuse medium disposed on the substrate; a gate electrode disposed on the fuse dielectric; a fuse doped region, under the gate electrode, having a second conductivity type different from the first conductivity type; a source and drain (S / D) region adjacent to the fuse doped region of the second conductivity type; A resistance-modifying doping region partially overlaps with the fuse doping region of the second conductivity type. 2 . The semiconductor device as claimed in claim 1 , wherein the fuse doping region is in contact with the source and drain regions. 3 . The semiconductor device as claimed in claim 1 , wherein the resistance-modifying doped region is in contact with the source and drain regions. 4 . The semiconductor device as claimed in claim 1 , wherein a portion of the fuse doping region is located under the resistance modification doping region. 5 . The semiconductor device as claimed in claim 1 , wherein a portion of the resistance modification doping region is located under the fuse doping region. 6 . The semiconductor device as claimed in claim 1 , wherein the resistance modifying doping region is separated from the source and drain regions.

7. The semiconductor device as claimed in claim 1, wherein a doping concentration of the resistance modification doping region is in a range of about 10 15 cm -3 Up to about 10 16 cm -3 . 8 . The semiconductor device as claimed in claim 1 , wherein the fuse doping region comprises phosphorus, arsenic, antimony or a combination thereof.

9. The semiconductor device as claimed in claim 1, wherein the resistance modifying doping region comprises nitrogen.

10. The semiconductor device as claimed in claim 1, further comprising: An impurity is in the substrate and under the gate electrode. The semiconductor device as claimed in claim 10 , wherein the impurity comprises nitride and oxynitride. 12 . The semiconductor device as claimed in claim 1 , wherein the resistance-modifying doping region is disposed under the gate electrode.

13. The semiconductor device of claim 1, wherein the fuse medium is configured to be blown at a current of about 0.4 mA to about 1.2 mA.

14. The semiconductor device as claimed in claim 13, wherein the resistance of the fuse medium is positively correlated with temperature.

15. A method for preparing a semiconductor element, comprising: Providing a substrate, wherein a well region in the substrate has a first conductivity type; forming a resistance-modified doped region in the substrate, wherein the resistance-modified doped region has a second conductivity type different from the first conductivity type; forming a fuse doping region in the substrate, wherein the fuse doping region has the second conductivity type; and A gate electrode is formed on the fuse doping region.

16. The method for preparing a semiconductor device as claimed in claim 15, further comprising: A fuse dielectric is formed after forming the resistance modified heterogeneous region. 17 . The method for fabricating a semiconductor device as claimed in claim 15 , wherein the resistance-modifying doping region comprises nitrogen. 18 . The method for manufacturing a semiconductor device as claimed in claim 15 , wherein the manufacturing technology of the resistance modified doping region comprises an implantation technology, and the implantation energy thereof is in the range of about 10 keV to about 30 keV.

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