Radio frequency switch structure and method of manufacturing the same

Abstract

The application provides a radio frequency switch structure and a preparation method thereof. The radio frequency switch structure comprises: an SOI substrate; a transistor chain arranged on the front surface of the SOI substrate, which comprises first to Nth transistors cascaded between a head end and a tail end, the head end is connected to a radio frequency input, the tail end is grounded, and N is an integer greater than or equal to 4; a dielectric layer covering the SOI substrate and the transistor chain; first to Nth conductive ground layers arranged on the dielectric layer or the back surface of the SOI substrate, the first to Nth conductive ground layers correspond to the front surface or the back surface of the first to Nth transistors respectively, and the areas of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistors increase successively. The application can balance the voltage distribution of each transistor on the radio frequency switch structure to improve the power handling capability of the radio frequency switch structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a radio frequency switch structure and its fabrication method. Background Technology

[0002] Radio frequency (RF) switches are control devices used to control the transmission path and signal strength of RF signals. They are widely used in many fields such as wireless communication, electronic countermeasures, radar systems, and electronic measuring instruments.

[0003] In related technologies, such as Figure 1a As shown, the RF switch circuit may include a series branch connecting to the antenna and a parallel branch connecting to ground. The parallel branch may, for example, consist of 12 transistors connected in series, from top to bottom: transistor 1 (first transistor 1), transistor 2 (second transistor 2), transistor 3 (third transistor 3), ..., transistor 11 (eleventh transistor 11) and transistor 12 (twelfth transistor 12). The drain of transistor 1 serves as the input terminal of the RF switch circuit, connected to the RF input. Its source is connected to the drain of transistor 2. The source of transistor 2 is connected to the drain of transistor 3. ... The source of transistor 11 is connected to the drain of transistor 12. The source of transistor 12 serves as the output terminal of the RF switch circuit, connected to ground. The gate of each transistor is connected to a bias voltage Vgn via a high-resistance resistor. Each transistor's substrate is connected to a high-resistance resistor and grounded (or uniformly connected to the bias voltage). A high-resistance resistor is connected between the drain and source of each transistor. All of these high-resistance resistors have the same resistance value and are at least 50 kΩ.

[0004] Figure 1b The actual voltage distribution between the source and drain of each of the 12 transistors in the above parallel branch is as follows: Figure 1b As shown, the voltage distribution of the above-mentioned RF switch circuit is unbalanced, which seriously affects the power handling capability and may even cause high voltage breakdown of the transistor. Summary of the Invention

[0005] The purpose of this invention is to provide a radio frequency switch structure and its fabrication method, which improves the power handling capability of the radio frequency switch structure by balancing the voltage distribution of each transistor on the radio frequency switch structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a radio frequency switch structure, comprising:

[0007] SOI substrate;

[0008] A transistor chain, disposed on the front side of the SOI substrate, includes a first to an Nth transistor cascaded between a start end and a tail end, the start end being connected to an RF input and the tail end being grounded, where N is an integer greater than or equal to 4.

[0009] a medium layer covering the SOI substrate and the transistor chain;

[0010] a first to an Nth conductive ground layer disposed on the medium layer or the back surface of the SOI substrate, the first to the Nth conductive ground layer respectively corresponding to the front surface or the back surface of the first to the Nth transistor, and the first to the Nth conductive ground layer exposed to the area of the corresponding transistor front surface or back surface increases in turn.

[0011] Optionally, the first to the Nth conductive ground layer are connected to the ground terminal of the radio frequency switch structure or the semiconductor device comprising the radio frequency switch structure.

[0012] Optionally, the first to the Nth conductive ground layer are disposed in the same layer as the ground terminal of the radio frequency switch structure and are electrically connected.

[0013] Optionally, the first to the Nth conductive ground layer are disposed on the medium layer, and the first to the Nth conductive ground layer are top metal interconnection layers.

[0014] Optionally, the first to the Nth conductive ground layer are disposed on the back surface of the SOI substrate, and the first to the Nth conductive ground layer are redistribution line layers.

[0015] Optionally, the first to the Nth transistor have the same size of interdigital layout structure, the gate structure and the source-drain structure of the first to the Nth transistor extend along a first direction, and the first to the Nth conductive ground layer cross the gate structure and the source-drain structure of the first to the Nth transistor along a second direction, and the second direction is orthogonal to the first direction.

[0016] Optionally, the first to the Nth conductive ground layer are rectangular, and the width of the first to the Nth conductive ground layer along the first direction increases in turn.

[0017] Based on another aspect of the present application, a preparation method of a radio frequency switch structure is also provided, comprising:

[0018] providing an SOI substrate;

[0019] forming a transistor chain on the front surface of the SOI substrate, the transistor chain comprising a first to an Nth transistor cascaded between a head end and a tail end, the head end connected to a radio frequency input, the tail end grounded, and N being an integer greater than or equal to 4;

[0020] forming a medium layer on the SOI substrate and the transistor chain;

[0021] Forming first to Nth conductive ground layers on the surface of the dielectric layer or the back surface of the SOI substrate, the first to Nth conductive ground layers respectively correspond to the front surface or the back surface of the first to Nth transistors, and the areas of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistors increase in turn.

[0022] Optionally, the first to Nth conductive ground layers are located on the dielectric layer, and the first to Nth conductive ground layers are formed synchronously when forming the top metal interconnection layer of the radio frequency switch structure.

[0023] Optionally, the first to Nth conductive ground layers are located on the back surface of the SOI substrate, and the first to Nth conductive ground layers are formed synchronously when forming the redistribution layer of the radio frequency switch structure.

[0024] In summary, the radio frequency switch structure provided by the application comprises an SOI substrate, a transistor chain arranged on the front surface of the SOI substrate, the transistor chain comprising first to Nth transistors cascaded between a head end and a tail end, the head end being connected to a radio frequency input, the tail end being grounded, and N being an integer greater than or equal to 4, a dielectric layer covering the SOI substrate and the transistor chain, and first to Nth conductive ground layers arranged on the dielectric layer or the back surface of the SOI substrate, the first to Nth conductive ground layers respectively corresponding to the front surface or the back surface of the first to Nth transistors, and the areas of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistors increasing in turn. Since the areas of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistors increase in turn, the parasitic capacitances of the first to Nth conductive ground layers relative to the first to Nth transistors increase in turn, that is, the impedances of the first to Nth transistors increase in turn, and the closer to the tail end, the greater the impedance increases, so that the voltage distribution of each transistor is balanced and the processing power of each transistor is balanced, thereby improving the power processing capability of the radio frequency switch structure, and the maximum voltage difference between the source and the drain of each transistor is reduced, so as to reduce the risk of high-voltage breakdown of each transistor. BRIEF DESCRIPTION OF DRAWINGS

[0025] Those skilled in the art should understand that the provided drawings are used to better understand the application, and do not constitute any limitation on the scope of the application.

[0026] Figure 1a A circuit schematic diagram of a radio frequency switch circuit in the related art;

[0027] Figure 1b A voltage distribution schematic diagram of a radio frequency switch circuit in the related art;

[0028] Figure 2a A cross-sectional schematic diagram of a single transistor in the radio frequency switch structure provided in Embodiment One;

[0029] Figure 2b A top view of a transistor chain in the RF switch structure provided in Embodiment One;

[0030] Figure 2c A schematic diagram of optimizing the voltage distribution between the front and back source-drain of each transistor;

[0031] Figure 3a A cross-sectional view of a single transistor in the RF switch structure provided in Embodiment Two;

[0032] Figure 3b A top view of a transistor chain in the RF switch structure provided in Embodiment Two;

[0033] Figure 4a A flow chart of the preparation method of the RF switch structure provided in Embodiment Three;

[0034] Figure 4b A flow chart of the preparation method of the RF switch structure provided in Embodiment Four;

[0035] Figures 5a to 5d A structure schematic diagram corresponding to the respective steps of the preparation method of the RF switch structure provided in Embodiment Three.

[0036] In the drawings:

[0037] 10 - SOI substrate; 11 - silicon base layer; 12 - buried oxide layer; 13 - top silicon layer; 14 - head end; 15 - tail end; 20 - transistor; 21 - gate structure; 22 - source-drain structure; 23 - source-drain lead-out structure; 23a - source lead-out structure; 23b - drain lead-out structure; 24 - dielectric layer; 31 - conductive ground layer; X - first direction; Y - second direction; S1 - first curve; S2 - second curve. DETAILED DESCRIPTION

[0038] To make the objectives, advantages and features of the present application clearer, the following further describes the present application in detail with reference to the drawings and specific embodiments. It should be noted that the drawings are all very simplified and not drawn to scale, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the emphasis shown in each drawing is different, and sometimes different scales are used.

[0039] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0040] Example 1

[0041] Example 1 provides a radio frequency switch structure.

[0042] Figure 2a This is a cross-sectional schematic diagram of a single transistor in the radio frequency switch structure provided in Embodiment 1. Figure 2b This is a top view of the transistor chain in the RF switch structure provided in Embodiment 1.

[0043] like Figure 2a and Figure 2b As shown, the RF switch structure provided in this embodiment includes an SOI substrate 10, a transistor chain, a dielectric layer 24, and first to Nth conductive ground layers 31. The transistor chain is disposed on the front side of the SOI substrate 10, and includes first to Nth transistors 20 cascaded between a start end 14 and a tail end 15. The start end 14 is connected to the RF input, and the tail end 15 is grounded. N is an integer greater than or equal to 4. The dielectric layer 24 covers the SOI substrate 10 and the transistor chain. The first to Nth conductive ground layers 31 are disposed on the dielectric layer 24, and the first to Nth conductive ground layers 31 are respectively disposed on the front side of the first to Nth transistors 20, and the area of ​​the first to Nth conductive ground layers 31 exposed on the front side of the corresponding transistors 20 (facing area) increases sequentially.

[0044] Please refer to Figure 2a The SOI substrate 10 may include a silicon substrate 11, a buried oxide layer 12, and a top silicon layer 13 sequentially disposed. The side containing the top silicon layer 13 may be the front side of the SOI substrate 10, and the side containing the silicon substrate 11 may be the back side of the SOI substrate 10. A transistor chain is disposed on the front side of the SOI substrate 10, i.e., formed on the top silicon layer 13, and may include a source / drain structure 22, a gate structure 21, and a source / drain exit structure 23. The transistor chain uses the top silicon layer 13 as the active region, the gate structure 21 is disposed on the top silicon layer 13, the source / drain structure 22 is located in the active regions on both sides of the gate structure 21, the top silicon layer 13 between the source / drain structures 22 forms the channel region, and the source / drain exit structure 23 is disposed above the gate structure 21 for electrically exiting the source / drain structure 22.Figure 2b As shown, the gate structure 21 of the transistor 20 can be a first interdigital structure including a plurality of interdigitations extending along a first direction X, the source-drain structure 22 includes source terminals and drain terminals alternately arranged on both sides of the interdigitations along a second direction Y, and the source-drain lead-out structure 23 can include a plug on the gate structure 21 and a first metal interconnection layer, which can include source terminal lead-out structures 23a and drain terminal lead-out structures 23b arranged in the same layer and staggered, respectively electrically leading out the source terminals and the drain terminals. The source terminal lead-out structures 23a and the drain terminal lead-out structures 23b can each be a second interdigital structure, and the interdigitations of the second interdigital structure extend along the first direction X, and the first direction X and the second direction Y are orthogonal.

[0045] Specifically, in the embodiment, the transistor chain can include N transistors 20 (first to Nth transistors 20) connected in series between the head end 14 and the tail end 15, the head end 14 is connected to the radio frequency input, and the tail end 15 is connected to the ground, that is, the first transistor 20 is connected to the radio frequency input, and the Nth transistor 20 is connected to the ground. Each transistor 20 can be an nmos transistor arranged in the same manner as described above (same configuration), that is, the first to Nth transistors 20 have the same or substantially the same layout structure.

[0046] Please continue to refer to Figure 2a The dielectric layer 24 can be an intermetal dielectric layer covering the source-drain lead-out structure 23, and the first to Nth conductive ground layers 31 can be other metal interconnection layers on the first metal interconnection layer (source-drain lead-out structure 23). In a preferred example, the first to Nth conductive ground layers 31 can be arranged in the same layer (located in the same layer) and electrically connected with the ground end of the radio frequency switch structure. In the embodiment, the first to Nth conductive ground layers 31 and the ground end of the radio frequency switch structure (or the chip including the radio frequency switch structure) are all arranged in the top metal interconnection layer. Please continue to refer to Figure 2b The first to Nth conductive ground layers 31 are each arranged above the dielectric layer 24 of the first to Nth transistors 20, and form corresponding parasitic capacitances with the gate structure 21, the source terminal lead-out structure 23a and the drain terminal lead-out structure 23b of the corresponding transistor 20. Among them, the above-mentioned parasitic capacitances can be the parasitic capacitances of each transistor 20 to the ground, which can be respectively denoted as the first to Nth ground parasitic capacitances corresponding to the first to Nth transistors 20 respectively, and since the area of the first to Nth conductive ground layers 31 exposed to the front of the corresponding transistor 20 increases in turn, the first to Nth ground parasitic capacitances increase in turn, which can increase the impedance of the first to Nth transistors 20 in turn, and the impedance of the transistor closer to the tail end 15 increases more, so as to make the unbalanced voltage distribution similar to that shown in Figure 1b As shown, the unbalanced voltage distribution is as balanced as possible, so as to balance the processing power of each transistor 20, thereby improving the power processing capability of the radio frequency switch structure, and also can reduce the maximum voltage difference distributed between the source and drain of each transistor 20, so as to reduce the risk of breakdown of each transistor 20 by high voltage.

[0047] In detail, please continue to refer to Figure 2b , the first to the Nth conductive ground layers 31 can all be rectangular, and all extend along the second direction Y, which is orthogonal to the first direction X, that is, the first to the Nth conductive ground layers 31 are perpendicular to the interdigital structures of the first and second interdigital structures, and cross all the interdigital structures to uniformly act on all the source-drain lead structures 23 and gate structures 21 of the corresponding transistors 20. In addition to the first to the Nth transistors 20, connection lines are also provided to connect the first to the Nth conductive ground layers 31, which can extend along the first direction X, for example, and are connected to the ground end of the same layer. In particular, under the condition that the first to the Nth transistors 20 have the same size of layout structure as described above, the first to the Nth conductive ground layers 31 have widths (along the first direction X) that increase in sequence so that the exposed areas of the first to the Nth conductive ground layers 31 in front of the first to the Nth transistors 20 increase in sequence, thereby causing the first to the Nth parasitic capacitances to ground to increase (increment) in sequence. The present embodiment does not limit the width increment (i.e., the parasitic capacitance increment) between the first to the Nth conductive ground layers 31, and the width of the first to the Nth conductive ground layers 31 can be reasonably set according to actual debugging experience and simulation of the effect of the first to the Nth conductive ground layers 31 on the first to the Nth transistors 20, that is, the parasitic capacitance of the first to the Nth transistors 20 to ground is optimized. In a preferred example, Figure 2c A schematic diagram of optimizing the voltage distribution between the front and back source-drain of each transistor 20 is shown in Figure 2c , the first curve S1 is the voltage distribution between the source and drain of each transistor 20 in the related art (before optimization), and the second curve S2 is the voltage distribution between the source and drain of each transistor 20 after optimization in the present embodiment. The voltage distribution between the source and drain of each transistor 20 after optimization is basically consistent. Of course, the width of the largest conductive ground layer 31 (i.e., the Nth conductive ground layer 31) is usually less than or equal to the width of the active region.

[0048] It can be understood that the N transistors can be parallel branches (i.e., one end is grounded) of the radio frequency switch structure provided by the present embodiment. The radio frequency switch structure provided by the present embodiment can also include a series branch connected to an antenna. The series branch can include a plurality of transistors cascaded between a first end and the antenna. The plurality of transistors of the series branch have no corresponding relationship with the N transistors of the parallel branch, and the plurality of transistors of the series branch can also not need to be set as described above.

[0049] Embodiment Two

[0050] Embodiment Two provides a radio frequency switch structure.

[0051] Figure 3a A cross-sectional view of a single transistor in the radio frequency switch structure provided by Embodiment Two is shown in Figure 3bA top view of a transistor chain of the radio frequency switch structure provided in Embodiment Two.

[0052] As shown in Figure 3a and Figure 3b , the radio frequency switch structure provided in the embodiment includes an SOI substrate 10, a transistor chain, a dielectric layer 24, and first to N-th conductive ground layers 31. The transistor chain is disposed on the front surface of the SOI substrate 10 and includes first to N-th transistors 20 cascaded between a head end 14 and a tail end 15, the head end 14 being connected to a radio frequency input, the tail end 15 being grounded, and N being an integer greater than or equal to 4. The dielectric layer 24 covers the SOI substrate 10 and the transistor chain. The first to N-th conductive ground layers 31 are disposed on the back surface of the SOI substrate 10 and correspondingly disposed on the back surfaces of the first to N-th transistors 20, respectively, and the areas of the first to N-th conductive ground layers 31 exposed to the back surfaces of the corresponding transistors 20 increase successively.

[0053] The basic principle of the radio frequency switch structure in Embodiment Two is similar to that in Embodiment One, and the difference is only that the first to N-th conductive ground layers 31 are disposed on the back surface of the SOI substrate 10, facing away from the first to N-th transistors 20 and forming corresponding first to N-th parasitic capacitances to ground, and the areas (back surface areas) of the first to N-th conductive ground layers 31 are set to increase successively to increase the first to N-th parasitic capacitances to ground successively, thereby successively increasing the impedances of the first to N-th transistors 20 to make the voltage distributions of the transistors 20 (between the source and the drain) as balanced as possible, thereby balancing the processing powers of the transistors 20 and improving the power processing capability of the radio frequency switch structure, and also reducing the maximum voltage difference between the source and the drain of each transistor 20 to reduce the risk of high-voltage breakdown of each transistor 20. Of course, in the embodiment, the ground end of the radio frequency switch structure or a chip (semiconductor device) including the radio frequency switch structure can also be disposed on the back surface of the SOI substrate 10 (i.e., disposed in the same layer), and in an example, the first to N-th conductive ground layers 31 and the above-mentioned ground end can be redistribution lines disposed on the back surface of the SOI substrate 10.

[0054] Embodiment Three

[0055] Embodiment Three provides a preparation method of a radio frequency switch structure.

[0056] Figure 4a A flowchart of the preparation method of the radio frequency switch structure provided in Embodiment Three.

[0057] As shown in Figure 4a , the preparation method of the radio frequency switch structure shown in Embodiment One can include the following steps:

[0058] S01: providing an SOI substrate;

[0059] S02: forming a transistor chain on the front surface of the SOI substrate, the transistor chain comprising first to Nth transistors cascaded between a head end and a tail end, the head end being connected to a radio frequency input, the tail end being grounded, N being an integer greater than or equal to 4;

[0060] S03: forming a dielectric layer on the SOI substrate and the transistor chain;

[0061] S04: forming first to Nth conductive ground layers on the dielectric layer, the first to Nth conductive ground layers respectively corresponding to the front surface of the first to Nth transistors, and the area of the first to Nth conductive ground layers exposed to the front surface of the corresponding transistor increasing in turn.

[0062] Figures 5a to 5d is the corresponding structure diagram of the corresponding step of the preparation method of the radio frequency switch structure provided in Embodiment Three. Next, the preparation method of the radio frequency switch structure will be described in detail in combination with Figures 5a to 5d The preparation method of the radio frequency switch structure will be described in detail in combination with

[0063] First, referring to Figure 5a , step S01 is performed to provide an SOI substrate 10.

[0064] The SOI substrate 10 can comprise a silicon substrate layer 11, a buried oxygen layer 12 and a top silicon layer 13 arranged in turn. In this embodiment, the top silicon layer 13 of the SOI substrate 10 can be of P type to form a plurality of nmos transistors, thereby constituting a radio frequency switch structure.

[0065] Next, referring to Figure 5b , step S02 is performed to form a transistor chain on the front surface of the SOI substrate 10, the transistor chain comprising first to Nth transistors 20 cascaded between a head end 14 and a tail end 15, the head end 14 being connected to a radio frequency input, the tail end 15 being grounded, N being an integer greater than or equal to 4.

[0066] The first to Nth transistors 20 can all be nmos transistors of the same configuration (same size), which can comprise a source-drain structure 22, a gate structure 21 and a source-drain lead-out structure 23. The transistor chain takes the top silicon layer 13 as an active area, the gate structure 21 is arranged on the top silicon layer 13, the source-drain structure 22 is located in the active area on both sides of the gate structure 21, and the top silicon layer 13 between the source-drain structures 22 is a channel region, and the source-drain lead-out structure 23 is arranged above the gate structure 21 for electrically leading out the source-drain structure 22. Among them, the gate structure 21, the source-drain structure 22 and the source-drain lead-out structure 23 can all be in the form of an interdigital structure.

[0067] Next, referring to Figure 5c , step S03 is performed to form a dielectric layer 24 on the SOI substrate 10 and the transistor chain.

[0068] The source-drain lead-out structure 23 can include a plug on the gate structure 21 and a first metal interconnection layer, and the dielectric layer 24 covering the first to N-th transistors 20 can be an intermetal dielectric layer in the interconnection structure layer.

[0069] Next, referring to Figure 5d , a step S04 is performed to form first to N-th conductive ground layers 31 on the dielectric layer 24, the first to N-th conductive ground layers 31 respectively corresponding to the front surfaces of the first to N-th transistors 20, and the areas of the first to N-th conductive ground layers 31 exposed to the front surfaces of the corresponding transistors 20 increase in turn.

[0070] The first to N-th conductive ground layers 31 can be other metal interconnection layers on the first metal interconnection layer (source-drain lead-out structure 23). In a preferred example, the first to N-th conductive ground layers 31 can be disposed in the same layer as the ground end of the radio frequency switch structure (on the same layer) and electrically connected, that is, the first to N-th conductive ground layers 31 are formed at the same time as the ground end of the radio frequency switch structure is formed, thereby avoiding additional mask plates and photolithography times. In this embodiment, the first to N-th conductive ground layers 31 and the ground end of the radio frequency switch structure (or the chip including the radio frequency switch structure) are both disposed in the top layer metal interconnection layer, that is, the first to N-th conductive ground layers 31 and the ground end of the radio frequency switch structure are formed at the same time as the top layer metal interconnection layer is formed.

[0071] Embodiment Four

[0072] Embodiment Four provides a preparation method of a radio frequency switch structure.

[0073] Figure 4b A flowchart of the preparation method of the radio frequency switch structure provided in Embodiment Four is shown.

[0074] As shown in Figure 4b , the preparation method of the radio frequency switch structure provided in this embodiment can include the following steps:

[0075] S01: providing an SOI substrate;

[0076] S02: forming a transistor chain on the front surface of the SOI substrate, the transistor chain including first to N-th transistors cascaded between a head end and a tail end, the head end connected to a radio frequency input, the tail end grounded, and N being an integer greater than or equal to 4;

[0077] S03: forming a dielectric layer on the SOI substrate and the transistor chain;

[0078] S04: forming first to N-th conductive ground layers on the back surface of the SOI substrate, the first to N-th conductive ground layers respectively corresponding to the back surfaces of the first to N-th transistors, and the areas of the first to N-th conductive ground layers exposed to the back surfaces of the corresponding transistors increasing in turn.

[0079] The preparation method provided in Embodiment Four is used for preparing the radio frequency switch structure of Embodiment Two, and the basic principle is similar to that of Embodiment Three, and the difference is only that the first to Nth conductive ground layers are formed on the back surface of the SOI substrate. In a preferred example, the ground end of the radio frequency switch structure or the chip comprising the radio frequency switch structure is also provided on the back surface of the SOI substrate, and the first to Nth conductive ground layers and the above-mentioned ground end can all be redistribution lines provided on the back surface of the SOI substrate.

[0080] In summary, the radio frequency switch structure provided by the present application comprises an SOI substrate; a transistor chain provided on the front surface of the SOI substrate, which comprises first to Nth transistors cascaded between a head end and a tail end, the head end is connected to a radio frequency input, the tail end is grounded, and N is an integer greater than or equal to 4; a dielectric layer covering the SOI substrate and the transistor chain; first to Nth conductive ground layers provided on the dielectric layer or the back surface of the SOI substrate, the first to Nth conductive ground layers correspond to the front surface or the back surface of the first to Nth transistors respectively, and the area of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistor increases in turn. Among them, since the area of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistor increases in turn, the above-mentioned first to Nth conductive ground layers increase the parasitic capacitance to the ground of the first to Nth transistors in turn, that is, increase the impedance of the first to Nth transistors in turn, and the closer to the tail end, the greater the increase in impedance, so as to balance the voltage distribution of each transistor and balance the processing power of each transistor, thereby improving the power processing capability of the radio frequency switch structure, and also reducing the maximum voltage difference between the source and the drain of each transistor, so as to reduce the risk of breakdown of each transistor by high voltage.

[0081] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application, any modification or modification of the above-mentioned disclosure by a person skilled in the art within the scope of the present application is within the protection scope of the claims.

Claims

1. A radio frequency switch structure, characterized by The method comprises: providing an SOI substrate; forming a transistor chain on a front surface of the SOI substrate, the transistor chain comprising first to Nth transistors cascaded between a head end and a tail end, the head end connected to a radio frequency input, the tail end grounded, N being an integer greater than or equal to 4, the first to Nth transistors having the same size of interdigital layout structure, the gate structure and the source-drain structure of the first to Nth transistors extending along a first direction; forming a dielectric layer on the SOI substrate and the transistor chain; forming first to Nth conductive ground layers on the dielectric layer or a back surface of the SOI substrate, the first to Nth conductive ground layers respectively corresponding to the front surface or the back surface of the first to Nth transistors, and the area of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistors increasing in turn, the first to Nth conductive ground layers all spanning the gate structure and the source-drain structure of the first to Nth transistors along a second direction, the second direction being orthogonal to the first direction, the first to Nth conductive ground layers all being rectangular, and the widths of the first to Nth conductive ground layers along the first direction increasing in turn.

2. The radio frequency switch structure of claim 1, wherein, The first to Nth conductive ground layers are connected to the ground end of the radio frequency switch structure or a semiconductor device comprising the radio frequency switch structure.

3. The radio frequency switch structure of claim 2, wherein, The first to Nth conductive ground layers are provided in the same layer as the ground end of the radio frequency switch structure and are electrically connected.

4. The radio frequency switch structure of claim 3, wherein, The first to Nth conductive ground layers are located on the dielectric layer, and the first to Nth conductive ground layers are top metal interconnection layers.

5. The radio frequency switch structure of claim 3, wherein, The first to Nth conductive ground layers are located on the back surface of the SOI substrate, and the first to Nth conductive ground layers are redistribution line layers.

6. A method of fabricating a radio frequency switch structure, characterized by The method comprises: providing an SOI substrate; forming a transistor chain on a front surface of the SOI substrate, the transistor chain comprising first to Nth transistors cascaded between a head end and a tail end, the head end connected to a radio frequency input, the tail end grounded, N being an integer greater than or equal to 4, wherein the first to Nth transistors have the same size of interdigital layout structure, and the gate structure and the source-drain structure of the first to Nth transistors extend along a first direction; forming a dielectric layer on the SOI substrate and the transistor chain; forming first to Nth conductive ground layers on a surface of the dielectric layer or a back surface of the SOI substrate, the first to Nth conductive ground layers respectively corresponding to the front surface or the back surface of the first to Nth transistors, and the area of the first to Nth conductive ground layers exposed to the front surface or the back surface of the corresponding transistors increasing in turn, wherein the first to Nth conductive ground layers all span the gate structure and the source-drain structure of the first to Nth transistors along a second direction, the second direction being orthogonal to the first direction, the first to Nth conductive ground layers all being rectangular, and the widths of the first to Nth conductive ground layers along the first direction increasing in turn.

7. The method of claim 6, wherein the radio frequency switch structure is prepared by, The first to Nth conductive ground layers are located on the dielectric layer, and the first to Nth conductive ground layers are top metal interconnection layers.

8. The method of claim 6, wherein the radio frequency switch structure is prepared by, The first to Nth conductive ground layers are formed on the back surface of the SOI substrate, and are formed synchronously when forming the redistribution layer of the radio frequency switch structure.

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