Integrated circuit structure and manufacturing method of semiconductor device

Abstract

The embodiment of the invention relates to an integrated circuit (IC) structure and a manufacturing method of a semiconductor device. The IC structure includes a transistor device formed on a substrate, wherein the transistor device has a source / drain (S / D) region and a gate structure. A multilayer interconnect (MLI) structure including metal lines and metal vias embedded in an inter-metal dielectric (IMD) layer is formed on a substrate. And forming a heat dissipation layer having a surface having a plurality of peaks and valleys disposed over at least a portion of the MLI structure. The bonding layer is disposed over the heat dissipation layer and covers the plurality of peaks and valleys.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to methods for manufacturing integrated circuit structures and semiconductor devices. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry continues to trend toward manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been achieved in large part by reducing IC size (e.g., minimum IC feature size), thereby increasing production efficiency and reducing associated costs. However, this scale has also increased the complexity of the IC manufacturing process. Therefore, achieving continued advancements in IC devices and their performance requires similar advances in IC manufacturing processes and technologies.

[0003] As technology advances, concerns about the thermal dissipation of heat generated by semiconductor devices (such as transistors) have increased, as higher temperatures can degrade device performance. Semiconductor devices that include multiple chips, such as stacked die configurations, further restrict the heat dissipation paths, further complicating this problem. Thus, while existing semiconductor device structures have generally met their intended purposes, they are not completely satisfactory in every respect. Summary of the invention

[0004] One embodiment of the present invention provides an integrated circuit structure, comprising: a transistor device formed above a substrate, the transistor device having a source / drain (S / D) region and a gate structure; a multi-layer interconnect (MLI) structure located above the transistor device, wherein the multi-layer interconnect structure includes metal lines and metal vias embedded in an inter-metal dielectric (IMD) layer; a heat dissipation layer having a surface with multiple peaks and valleys disposed on at least a portion of the multi-layer interconnect structure; and a bonding layer located above the heat dissipation layer and covering the multiple peaks and valleys.

[0005] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a transistor on a semiconductor substrate; forming a first metal layer and an overlying second metal layer above the transistor, wherein a through hole extends between the first metal layer and the overlying second metal layer; depositing a heat dissipation layer above the overlying second metal layer, wherein the heat dissipation layer includes a rough surface presenting peaks and valleys; depositing a bonding layer above the rough surface, wherein the bonding layer covers at least one peak and valley of the rough surface; and forming another substrate above the bonding layer.

[0006] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a transistor device above a substrate; forming a multi-layer interconnect (MLI) on the transistor device; depositing a diamond-like carbon layer on the multi-layer interconnect, wherein the surface root mean square of the diamond-like carbon layer is at least one hundred nanometers; depositing a bonding layer on the diamond-like carbon layer; and flattening the bonding layer to form a flat surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the drawings illustrate only typical embodiments of the present invention, but should not be considered as limiting the scope, as the present invention is equally applicable to other embodiments. In addition, the drawings may implicitly describe features that are not explicitly described in the specific description.

[0008] Figure 1A A cross-sectional view of an embodiment of a portion of a semiconductor device structure having a heat dissipation layer according to an embodiment of the present disclosure is shown.

[0009] Figure 1B The embodiment according to the present disclosure is shown Figure 1A 0026 is a cross-sectional view of a portion of a semiconductor device structure showing hot spots and heat dissipation paths.

[0010] Figure 1C A cross-sectional view of a semiconductor device structure portion according to an embodiment of the present disclosure is shown.

[0011] Figure 2 A flow chart of an embodiment of a method of manufacturing a semiconductor device having a heat dissipation layer according to aspects of the present disclosure is shown.

[0012] Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Figure 7 and Figure 8 According to some aspects of the present disclosure Figure 2 A cross-sectional view of an embodiment of a semiconductor structure at an intermediate manufacturing step corresponding to a method.

[0013] Fig. 9 A cross-sectional view of an embodiment of a semiconductor structure having a heat dissipation layer according to aspects of the present disclosure is shown.

[0014] Fig.10 A cross-sectional view of an embodiment of a semiconductor structure having multiple heat dissipation layers included in a multi-layer interconnect according to aspects of the present disclosure is shown.

[0015] Fig.11 A cross-sectional view of an embodiment of a semiconductor structure having a first die and a second die stacked on the first die and including one or more heat spreading layers according to aspects of the present disclosure is shown.

[0016] Fig.12 Cross-sectional views of embodiments of semiconductor structures having a first die, a second die stacked on the first die, and additional components on the second die, the stack including one or more heat spreading layers, according to various aspects of the present disclosure are shown.

[0017] Fig.13 A cross-sectional view of an embodiment of a semiconductor structure having a first die and a second die stacked on the first die with multiple heat spreading layers included in multi-layer interconnects of the first and / or second die according to various aspects of the present disclosure is shown.

[0018] Fig.14 A cross-sectional view of another embodiment of a semiconductor structure having a heat sink layer and an overlying dielectric layer according to aspects of the present disclosure is shown.

[0019] Fig.15 A cross-sectional view of another embodiment of a semiconductor structure having a heat sink layer and an overlying dielectric layer according to aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0020] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] In addition, when a number or a series of numbers is described using "approximately," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances for manufacturing components with a thickness associated with the number, the number or range includes a reasonable range including the described number, such as within + / -10% of the described number. For example, a material layer with a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / -15%. In addition, the disclosed dimensions of different components may implicitly disclose the size ratios between the different components. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0023] The present disclosure relates to semiconductor structures, such as integrated circuit (IC) structures that include one or more tube cores to form semiconductor structures. These structures can be referred to as 3D ICs because they integrate ICs in a vertical direction in part by stacking tube cores. The components of the stacked structure can be connected physically and / or by electrical connections. 3D ICs provide form factor advantages as well as power and performance advantages including due to the length of interconnects between stacked devices. One application of 3D IC structures is vertically stacked processors and one or more memory chips. However, semiconductor structures including 3D ICs may encounter challenges in heat dissipation within the structure.

[0024] Therefore, some embodiments proposed herein provide that the semiconductor structure includes a heat dissipation layer, also referred to as a heat transfer layer, to provide a heat dissipation path. In some embodiments, diamond-like carbon can be used as a high thermal conductor in a 3D IC. The present disclosure provides benefits for structures and methods that allow high thermal conductivity between layers of a semiconductor structure (e.g., between tube cores) for thermal management. In some embodiments, this is achieved by providing a thermally conductive material layer with improved flatness, thereby increasing the applicability of bonding with additional components (e.g., tube cores, heat sinks, etc.). In some embodiments, this is provided by combining a diamond-like carbon layer with a bonding layer (e.g., a high conductivity and / or dielectric layer, such as AlN). Therefore, aspects of the present disclosure can improve the bonding between tube cores in a 3D IC structure. In particular, since the diamond-like carbon layer can provide a significantly rough surface, the bonding layer implemented according to one or more aspects of the present disclosure can solve the problem of compensating for the roughness of the underlying diamond-like layer.

[0025] In the following description, the front-end of the line (FEOL) generally refers to the portion of the circuit where functional devices such as logic and memory devices are formed. FEOL components include transistors and their components, such as source / drain components, channel regions, and gate structures. Device-level contacts or metal components extend to the terminals of the transistors. The back-end of the line (BEOL) in the present disclosure generally refers to components formed after the FEOL components, including multi-layer interconnects (MLI). The MLI includes a plurality of metal lines (also called interconnects) and inserted vias that provide electrical connections including to the FEOL components. The metal lines provide horizontal wiring and the vias provide vertical wiring to connect metal lines of different metal layers. Any number of metal layers may be used, including, for example, an exemplary MLI may include five (5) or more vertically stacked metal lines, generally referred to as M1, M2, M3, etc. The MLI includes a dielectric or insulating material surrounding the metal lines and vias that provide appropriate direction for the signals carried in the lines, and the dielectric may be referred to as an inter-metal dielectric (IMD), as described below.

[0026] Figure 1A A cross-sectional view of a portion of a semiconductor structure 100 according to an embodiment of the present disclosure is shown. The semiconductor structure 100 may be part of an integrated circuit (IC) device and may include a plurality of device components (not shown).

[0027] As will be further described below with reference to various embodiments, the semiconductor structure 100 is formed on a semiconductor structure that has undergone a FEOL process. Such a FEOL process can form various transistors on a substrate to serve different functions. For example, these different transistors can form a central processing unit (CPU), a graphics processing unit (GPU), an access transistor for a memory device, an image signal processing (ISP) circuit, and / or other suitable circuits. The transistor can be a planar transistor or a multi-gate transistor. A planar device refers to a device having a gate structure bonded to a planar surface of a semiconductor active region. A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. FinFETs have an elevated channel wrapped by a gate on multiple sides (e.g., the gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). A GAA transistor has a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the GAA transistor can also be called a surround gate transistor (SGT) or a multi-bridge-channel (MBC) transistor. The channel region of the GAA transistor can be formed by nanowires, nanosheets, or other nanostructures, and therefore, the GAA transistor can also be called a nanowire transistor or a nanosheet transistor. Transistors are broadly mentioned here, but each configuration discussed is applicable to the embodiments here.

[0028] The semiconductor structure 100 includes a multi-layer interconnect (MLI) structure that includes multiple metal layers and is part of the BEOL as described above. One metal layer 102 of the MLI is shown, and in some embodiments is the top or uppermost metal layer of the MLI. In some embodiments, the structure 100 is formed on a semiconductor substrate including silicon (Si). Alternatively or additionally, the substrate includes another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, the substrate includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some embodiments, the substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be fabricated by separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0029] The MLI of the semiconductor structure 100 includes a plurality of metal lines or layers in the MLI, for example, the MLI may generally include about five (5) to about twenty (20) metal layers (or metallization layers). Each metal layer of the MLI includes a plurality of vias and metal lines embedded in a dielectric or insulating layer, which dielectric layer or insulating layer may also be referred to herein as an inter-metal dielectric (IMD) layer. The vias and metal lines may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, they are formed of copper (Cu). The IMD layer may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass, boro-doped silicate glass (BSG) and / or other suitable dielectric materials. In one embodiment, the IMD layer includes silicon oxide.

[0030] Figure 1A Shown is a metallization layer 102. In one embodiment, the metallization layer 102 is the top metal layer of the MLI of the semiconductor structure 100. In one embodiment, the metallization layer 102 is the top metal layer of a die (e.g., a bottom die) of the semiconductor structure 100. The metallization layer 102 may include copper (Cu). Other components include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), or combinations thereof as described above.

[0031] In structure 100, on metallization layer 102 is heat sink layer 104. In one embodiment, heat sink layer 104 is a diamond-like carbon layer. In some embodiments, heat sink layer 104 is polycrystalline carbon providing a diamond-like film or DLC. Diamond-like carbon may be a class of amorphous carbon materials that exhibit certain properties of diamond. The heat sink layer may exhibit a low dielectric constant, such as a low-k material (e.g., a dielectric constant lower than that of SiO2, e.g., less than 3.9).

[0032] Heat dissipation layer 104 includes surface 104B. In some embodiments, surface 104B has a high surface roughness. For example, in some embodiments, surface 104B has a significant roughness because it includes peaks and valleys that vertically deviate from hundreds of nanometers to micrometers. In other words, the roughness root mean square (RMS value) of surface 104B is hundreds of nanometers to micrometers. RMS is the root mean square of the vertical variation between the peaks and valleys of the surface measured under a microscope. In one embodiment, a metrology tool (e.g., CD-SEM) provides a measurement of the vertical distance between the peaks and valleys. In one embodiment, surface 104B has a roughness (peak-to-valley RMS) of at least 100 nanometers.

[0033] The thickness of the heat dissipation layer 104 can be between about 0.5 micrometers (μm) and 10 μm. The heat dissipation layer 104 can be deposited at a temperature less than or equal to about 400 degrees Celsius. Exemplary deposition methods include chemical vapor deposition (CVD), such as microwave plasma (MPCVD). The heat dissipation layer 104 can include a diamond-like carbon material having a thermal conductivity greater than 400 W / m / K. In some embodiments, the diamond-like carbon material has the advantage of high in-plane thermal conductivity (K). In one embodiment, a seed layer can be used for the heat dissipation layer 104. For example, a seed layer of diamond nanoparticles can be used.

[0034] On the heat dissipation layer 104 is a bonding layer 106. The bonding layer 106 can be a dielectric material. Exemplary compositions of the bonding layer 106 include AlN, cubic BN, BP, Al2O3, SiN, BeO, SiO2, or a combination thereof. In one embodiment, SiO2, Al2O3, and SiN provide enhanced adhesion. Therefore, in some embodiments, it can be used in combination with other materials that provide the desired thermal properties. In some embodiments, the composition of the bonding layer 106 has a high thermal conductivity, for example, for a thickness greater than 200nm, the thermal conductivity (k) is greater than or equal to 50W / m / k. In one embodiment, the bonding layer 106 is AlN. In another embodiment, for a thickness>200nm, the thermal conductivity (k) of AlN>50W / m / k. In one embodiment, the bonding layer 106 is c-BN. In another embodiment, the thermal conductivity (k) of c-BN is several hundred W / m / k.

[0035] In some embodiments such as discussed below, a planarization process is performed on the surface of the heat dissipation layer 104 (i.e., surface 104B) before depositing the bonding layer 106. In one embodiment, after the planarization process or the ion milling process, the surface 104B has a roughness of 5nm to 100nm. The planarization process can be performed by chemical mechanical polishing (CMP), ion milling, and / or other suitable processes. In other embodiments, the deposited heat dissipation layer 104 is not planarized.

[0036] In one embodiment, the bonding layer 106 is conformally deposited so that it covers the entire heat dissipation layer 104. In one embodiment, the bonding layer 106 is deposited at a temperature below about 400 degrees Celsius. An exemplary deposition method includes chemical vapor deposition (CVD). In one embodiment, the thickness of the bonding layer 106 is less than the thickness of the heat dissipation layer 104. In some embodiments, the thickness of the bonding layer 106 is between about 100 nm and 1 μm.

[0037] In one embodiment, after the bonding layer 106 is deposited, a planarization process is performed on the bonding layer 106. A planarized surface 106A can be formed. In some embodiments, the roughness of the surface 106A is less than about 1 nm RMS. The planarized surface 106A provides a suitable surface for bonding additional components, such as additional dies, metallization layers, heat sinks, etc. In one embodiment, the RMS of the surface of the bonding layer 106 (e.g., surface 106A) is less than the RMS of the surface of the heat sink layer 104 (e.g., surface 104B). Figure 1A In one embodiment, another metallization layer 108 is formed on the bonding layer 106. In one embodiment, the metallization layer 108 may be a metallization layer of another die. In one embodiment, the metallization layer 108 may be a metallization layer of the same die as layer 102 (e.g., Mn and M(n+1)). Therefore, the bonding layer 106 may form an interface with different materials (e.g., dielectrics, metals, silicon, etc.). In one embodiment, the bonding layer 106 is in contact with the dielectric layer of the MLI. In one embodiment, the bonding layer 106 is in contact with the conductive layer of the MLI. In some embodiments, the bonding layer 106 forms a hybrid bond with the conductive layer of the MLI. In one embodiment, the bonding layer 106 forms a bond with each of the conductive layer and the dielectric layer of the MLI (e.g., metallization layers such as M2). As shown below, the bonding layer 106 may be bonded to a silicon layer (e.g., an overlying substrate).

[0038] It should be noted that the composition of the bonding layer 106 can be selected based on several factors. First, the composition can be selected to provide sufficiently high thermal conductivity to avoid a significant reduction in the overall thermal resistance of the structure. Second, the interface (between the bonding layer 106 and the heat dissipation layer 104) and its thermal resistance can be considered. The interface can also be controlled by adjusting the roughness of the heat dissipation layer 104. For example, in one embodiment, the bonding layer 106 is c-BN and the heat dissipation layer 104 is diamond-like carbon. The two compositions have a lattice mismatch, so that the interface has a very high thermal conductivity. Third, for semiconductor structure applications with small hot spots (e.g., hot spots less than the thickness of the heat dissipation layer 104), the influence of the interface between the heat dissipation layer 104 and the bonding layer 106 may become less significant or even insignificant. In such an embodiment, other dielectric materials with lower thermal conductivity can be used for the bonding layer 106 (e.g., SiO2, SiN). In one embodiment, the bonding layer 106 is AlN. In one embodiment, the bonding layer 106 is c-BN. The bonding layer 106 can be a multilayer structure.

[0039] In some embodiments, the heat dissipation layer provides a high in-plane thermal conductivity (e.g., k greater than 400 W / m / K), and the bonding layer (e.g., AlN) provides a cross-plane thermal conductivity k greater than 50 W / m / K. The bonding layer does not add in-plane thermal resistance to the stack of the heat dissipation layer and the bonding layer, thereby making the thermal path for heat dissipation effective.

[0040] Figure 1B The semiconductor structure 100 is shown with a hot spot 112 shown. The hot spot 112 has a thermal path extending into the heat spreader layer 104 and away from the hot spot 112. In some embodiments, the thermal path extends to and through the bonding layer 106.

[0041] Figure 1C An embodiment of a semiconductor structure 100' is shown having a dielectric or insulating layer 110 adjacent to the metallization layer 108 and the metallization layer 102. In some embodiments, the insulating layer 110 above and below the heat dissipation layer 104 has the same composition. In some embodiments, the insulating layer 110 above and below the heat dissipation layer 104 has different compositions. The insulating layer 110 can be an insulating layer of an MLI structure, referred to as an intermetallic dielectric (IMD) layer in some embodiments. The insulating layer 110 can include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), and / or other suitable dielectric materials. Figure 1C The structure of 100' and Figure 1A The semiconductor structures 100 of FIG. 1B and / or FIG. 1B may be different cross-sectional views of semiconductor structures formed on the same substrate and are merely illustrative. In some embodiments, only a dielectric layer such as the insulating layer 110 may be formed over the bonding layer 106 .

[0042] Reference now Figure 2 , a method 200 for forming a semiconductor structure or a portion thereof is shown. In an embodiment, the method 200 may be used to manufacture the semiconductor structure 100, as described above with reference to Figure 1A , Figure 1B and Figure 1C The steps of method 200 are merely exemplary, and additional steps may be performed and / or steps may be omitted. Figures 3 to 8 is a schematic diagram of a portion of an exemplary semiconductor structure corresponding to an intermediate fabrication step of method 200 .

[0043] In an embodiment of method 200, in block 202, a semiconductor device such as a transistor is formed on a substrate. The device may be part of an IC. Figure 3In an example of, a substrate 302 is provided, which has one or more transistors 304, including source / drain regions 306 and gate structures 308 disposed thereon. As described above, transistor 304 can be a planar transistor or a multi-gate transistor. The substrate can be substantially similar to the above. For example, in an embodiment, semiconductor substrate 302 includes silicon (Si). Alternatively or additionally, substrate 302 includes other elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In some embodiments, substrate 302 includes one or more III-V materials, one or more II-IV materials, or combinations thereof. In some embodiments, substrate 302 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate.

[0044] The source / drain region 306 may be a doped region and / or an epitaxial growth region that defines a source / source component associated with a gate structure 308 of a semiconductor device. The source / drain region 306 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain region 306 is n-type, it may include silicon (Si) doped with an n-type dopant such as phosphorus (P) or arsenic (As). When the source / drain region 306 is p-type, it may include silicon germanium (SiGe) doped with a p-type dopant such as boron (B) or boron difluoride (BF2). In some embodiments, the source / drain region 306 may include multiple layers, such as layers with different dopant concentrations.

[0045] The gate structure 308 includes an interface layer, a gate dielectric layer, and a gate electrode. The interface layer of the gate structure 308 may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may be formed on the interface layer. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer of the gate structure 308 may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate electrode layer of the gate structure 308 may include a single layer or a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to improve device performance, a liner layer, a wetting layer, a bonding layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (Ta AlC), tantalum carbonitride (Ta CN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof.

[0046] A dielectric layer 310, also referred to as an interlayer dielectric (ILD) layer, may be formed on the substrate 302 and adjacent to the gate structure 308. The ILD layer 310 may be deposited using PECVD, FCVD, spin coating, or a suitable deposition technique. In some embodiments, after forming the ILD layer 310, the structure may be annealed to improve the integrity of the ILD layer 310. Although not explicitly shown in the figures, it is understood that a contact etch stop layer (CESL) may be deposited prior to depositing the ILD layer 310, such that the CESL is disposed between the ILD layer 310 and the source / drain features. The CESL may include silicon nitride or silicon oxynitride and may be deposited using CVD, ALD, or a suitable method.

[0047] The contact structure 312 extends through the ILD layer 310 to the source / drain region 306 and the gate structure 308. The contact structure 312 may be referred to as a middle process (MEOL) structure. As an example, the contact structure 312 may include ruthenium (Ru), cobalt (Co), nickel (Ni), tungsten (W), copper (Cu) or other metals. In some embodiments, the contact plug 312 may include a barrier layer to interface with the ILD layer 310. Such a barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride or nickel nitride. In addition, in order to reduce the contact resistance, a silicide component may be part of the contact structure 312 and interface with a transistor component (such as the gate 308). The silicide component may include titanium silicide. The contact structure 312 may be deposited using CVD, PVD or a suitable method.

[0048] The method 200 then proceeds to block 204 where a multi-layer interconnect (MLI) is formed on the device. Figure 3As an example, an MLI 314 is provided, which includes a via 314B and a metal layer 314A formed on a substrate 302. Although an arbitrary number of three (3) metal layers are shown for ease of reference, any number of metal layers 314A and inserted vias 314B can be provided. A dielectric 314C is between the metal layer 314A and the via 314B. The metal layer 314A and the via 314B may include copper (Cu). Other components include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), or a combination thereof as described above. The dielectric layer 314C can be deposited using PECVD, FCVD, spin coating, or a suitable deposition technique. The dielectric layer 314C may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or other suitable dielectric materials. In one embodiment, the dielectric layer 314C includes silicon oxide. Each MLI 314 component may include a multilayer structure. As described in the embodiments below, one or more layers of the dielectric layer 314C may include a diamond-like carbon composition. In some embodiments, at least the first dielectric layer 314C is an oxide-based layer (e.g., adjacent to the ILD 310), and at least one dielectric layer 314 above the first dielectric layer 314C is a diamond-like carbon composition.

[0049] Then, the method 200 continues to block 206, where a heat sink layer is formed on and / or within the multi-layer interconnect. The heat sink layer may be similar to the heat sink layer described above with reference to FIG. Figure 1A , Figure 1B , Figure 1C The heat sink layer 104 discussed is substantially similar. In one embodiment, the heat sink layer is a diamond-like carbon layer. In some embodiments, the heat sink layer is polycrystalline carbon that provides a diamond-like film or DLC. The thickness of the heat sink layer is about 0.5 micrometers (μm) to 10 μm. The heat sink layer can be deposited at a temperature of less than or equal to about 400 degrees Celsius. Exemplary deposition methods include chemical vapor deposition (CVD), such as microwave plasma (MPCVD).

[0050] First reference FIG. 4A to FIG. 4B In the example of FIG. 1 , the heat dissipation layer 104 is formed above the MLI 314. In an embodiment, as shown in FIG. Figure 4B As shown, the heat dissipation layer 104 is formed by connecting with the uppermost dielectric layer 314C above the uppermost metal line 314A of the MLI 314. Figure 4A As shown, the heat sink layer 104 ′ is formed above and coplanar with the uppermost metal layer 314A of the MLI 314 .

[0051] In other examples, materials suitable for heat sink layer 104 (e.g., diamond-like carbon) may also be used as one or more IMD layers 314C within MLI 314. For example, see Fig.10 In some embodiments, the dielectric layers corresponding to metal layers 4 (M4) and above include a heat sink layer 104 as an intermetallic dielectric. Fig.10 As shown, metal layer 214A and via 214B are formed in heat dissipation layer 104. Fig.10 As shown in the structure 1000 of FIG. 1 , in some embodiments, another heat sink layer 104 is formed above the MLI 314. The upper heat sink layer 104 can be thicker than those provided within the MLI 314.

[0052] The thickness (t1) of the heat dissipation layer 104 may be between about 0.5 micrometers (μm) and 10 μm. The heat dissipation layer 104 may be deposited at a temperature less than or equal to about 400 degrees Celsius. Exemplary deposition methods include chemical vapor deposition (CVD), such as microwave plasma (MPCVD). When deposited, the heat dissipation layer 104 may have a rough top surface, for example, a roughness with an RMS value of hundreds of nanometers to micrometers, or a peak-to-valley vertical distance.

[0053] In one embodiment, method 200 continues to block 208, wherein the heat sink layer is planarized. In some embodiments, planarization may include a CMP process or ion milling. In an embodiment, the deposited heat sink layer includes a surface having a roughness of hundreds of nanometers to micrometers RMS value, and after planarization, the process can reduce the surface roughness by about 10% or 50%. In an embodiment, after planarization, the heat sink layer may have a surface with an RMS roughness between about 5nm and about 100nm. In one embodiment, after planarization, the heat sink layer may have a surface with an RMS roughness between 50 and 150nm. In other embodiments, block 208 is omitted, and a planarization process is not performed on the material (e.g., a bonding layer discussed below) before it is deposited on the heat sink layer 104.

[0054] In an embodiment, in addition to planarization or ion milling, block 208 also includes oxygen plasma treatment of the surface to provide a desired surface roughness. CMP, ion beam and / or oxygen plasma may be used to achieve a desired interface with an overlying bonding layer (e.g., AlN, c-BN) to maximize the performance of the thermal coating.

[0055] Then, method 200 continues to block 210, where a bonding layer is formed on the heat dissipation layer. Exemplary compositions of the bonding layer include AlN, cubic BN (c-BN), BP, Al2O3, SiN, BeO, SiO2, or combinations thereof. In some embodiments, the composition of the bonding layer has high thermal conductivity, such as a thermal conductivity (k) greater than or equal to 50 W / m / k for a thickness greater than 200 nm. In one embodiment, the bonding layer is AlN. In another embodiment, the thermal conductivity (k) of AlN is >50 W / m / k for a thickness >200 nm. In an embodiment, the bonding layer is c-BN. In another embodiment, the thermal conductivity (k) of c-BN is several hundred W / m / k. The bonding layer may be as described above with reference to Figure 1A , Figure 1B , Figure 1C The bonding layer 106 discussed is substantially similar.

[0056] refer to Figure 5 In the example of FIG. 1 , a bonding layer 106 is formed above the heat dissipation layer 104. (It should be noted that although Figure 4B configuration of the heat sink 104, but it will be appreciated that the inclusion Figure 4A or Fig.10 Other configurations of the heat dissipation layer are also within the scope of this embodiment. ) In one embodiment, the thickness of the bonding layer 106 formed is sufficient to fill / overfill each valley / peak area on the surface of the heat dissipation layer 104. In one embodiment, the bonding layer 106 is conformally deposited so that it covers the entire heat dissipation layer 104. In one embodiment, the bonding layer 106 is deposited at a temperature below about 400 degrees Celsius. Exemplary deposition methods include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the thickness (t2) of the bonding layer 106 is between about 100 nm and 1 μm.

[0057] In some embodiments, method 200 continues to block 212 and performs a planarization process on the bonding layer deposited in block 210. Block 212 may include CMP, ion milling, other suitable planarization processes, and / or combinations thereof. In one embodiment, the surface of the bonding layer has a roughness RMS of 5 nm to 100 nm before the planarization process or the ion milling process, and has an RMS of less than about 1 nm after planarization. Figure 6 In the example of FIG. 1 , the bonding layer 106 has been planarized to form a surface 106A. In some embodiments, after planarization, the thickness (t3) of the bonding layer 106 is between about 10 nm and 1 μm.

[0058] When performing a planarization process of the bonding layer 106, the process can be stopped at a point just above the highest peak of the surface of the heat spreader layer 104. In some embodiments, the etch rate of the planarization process is used to identify a stopping point for the process (e.g., when the etch rate slows down, the process can be stopped (as this is a clue to the composition of the underlying heat spreader layer). In other embodiments, a calibrated etch rate of the bonding layer 106 (e.g., AlN) during the CMP process can be used to control the thickness of the bonding layer.

[0059] In one embodiment of method 200, the method continues to block 214 where additional interconnect layers are formed in and / or over the bonding layer. Figure 7 , forming a through hole 316 extending through the bonding layer 106 and the heat dissipation layer 104. The through hole 316 is connected to the uppermost metallization layer (e.g., metal layer 314A) of the MLI 314 to provide an electrical connection. The through hole 316 can be formed by appropriate photolithography and etching processes to form an opening in the heat dissipation layer 104 and the bonding layer 106, and then one or more conductive materials are deposited to form the opening of the through hole 316. Exemplary compositions include copper (Cu), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), tantalum (Ta), or a combination thereof.

[0060] In one embodiment, method 200 continues to block 216 to activate or treat the surface of the bonding layer formed in block 210. Activation or treatment may include preparing the surface for bonding with additional layers or components. In some embodiments, the bonding layer is subjected to a surface treatment or activation treatment, such as a cleaning treatment and / or a plasma treatment. In some embodiments, functionalization of the surface may be accomplished by surface oxidation, by forming and activating surface hydroxyls, or by depositing a few nm of an oxide (such as SiO2). In some embodiments, functionalization of the surface may include plasma activation of the bonding layer 106, such as plasma treatment of the AlN surface with O2, Ar, SF6, or a combination thereof, which results in a change in the chemical and morphological state of the surface. In some embodiments, functionalization of the surface increases hydrophilicity. In some embodiments, a cleaning process, such as a wet cleaning process, is performed on the surface of the bonding layer. In certain embodiments, the cleaning process changes the state of the surface to increase hydrophilicity. Reference Figure 8 , an activated surface 802 is shown. In some embodiments, the activated surface may include AlN, cubic BN, BP, Al2O3, SiN, BeO, SiO2, or a combination thereof, modified to enhance bondability with an overlying component (e.g., a silicon substrate). In some implementations, block 216 is omitted. Figure 8As shown, the stack of the heat dissipation layer 104 and the bonding layer 106 together form a thermal coating layer having a thickness (t4) between about 500 nm and 10 μm.

[0061] In some embodiments, method 200 continues to block 218 where additional layers or components are formed on the structure. The additional layers or components may include other semiconductor structures, such as other dies, heat sinks, packaging components, such as input / output terminals (e.g., balls, bumps, pillars), substrates, such as semiconductor substrates or interposer substrates, carrier substrates, and / or various other components, including those implementing 3D IC structures.

[0062] Reference now Figures 9 to 12 , which shows that you can use Figure 2 A semiconductor structure formed by one or more aspects of the method 200. Any aspect of any of the exemplary devices may be used in combination with other embodiments.

[0063] refer to Fig. 9 , a semiconductor structure 900 is shown, which includes a semiconductor substrate 302, a semiconductor device 304, an MLI 314, a heat dissipation layer 104, and a bonding layer 106, which can be substantially similar to the above. The semiconductor structure 900 can be used as discussed above. Figure 2 316. As shown in structure 900, conductive features 902 are disposed on bonding layer 106 and connected to through-holes 316. Conductive features 902 may be interconnects, such as C4 bump interconnects, pillars (e.g., copper pillars), C3 balls, solder balls, and / or other conductive features. In some embodiments, the conductive features are connected to another semiconductor structure, such as another die, an interposer substrate, operable to connect to a printed circuit board and / or other packaging structure. A passivation or underfill material (not shown) may be formed on bonding layer 106 and adjacent to conductive features 902. Bonding layer 106 may provide improved adhesion to surrounding materials adjacent to the conductive features (e.g., surrounding bump interconnects, such as dielectric layers, underfills, passivation layers, etc. (not shown)). In some embodiments, the chip stack may include multiple occurrences of bonding layer 106 (e.g., between stacked structures), and to reduce process complexity, bonding layer 106 may be present on the upper semiconductor structure, providing a smooth surface, so that there may be no additional bonding between the uppermost bonding layer 106 and the overlying material.

[0064] refer to Fig.10 , a semiconductor structure 1000 is shown, which includes a semiconductor substrate 302, a semiconductor device 304 formed on the substrate 302, and an MLI 314 disposed above and connected to the semiconductor device 304, which is basically similar to the above. The semiconductor structure 1000 can be used as described above. Figure 2The semiconductor structure 1000 is manufactured according to aspects of the method 200. The semiconductor structure 1000 shows certain dielectric layers of the MLI 314, which include heat dissipation materials similar to the heat dissipation layer 104 described above. These heat dissipation material IMD layers are annotated as terminal heat dissipation IMD layers 104". As shown, the upper dielectric layer of the MLI 314 includes the heat dissipation IMD layer 104", and the lower dielectric layer in the MLI 314 includes the IMD layer 314C. That is, the lower dielectric layer IMD layer 314C of the MLI 314 may include a different dielectric material from the upper dielectric layer 104" of the MLI 314. In one embodiment, the heat dissipation IMD layer 104" of the MLI 314 is diamond-like carbon. And the dielectric 314C of the MLI 314 is one or more of silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), and / or other suitable dielectric materials. In other embodiments, each IMD layer of the MLI 314 includes a heat sink material (e.g., diamond-like carbon). Note that the heat sink layer 104 is formed above the MLI 314. The bonding layer 106 is formed on the heat sink layer 104. Additional structures (e.g., dies, layers, heat sinks, interconnects) may be formed on the bonding layer 106.

[0065] Reference examples Fig.11 , a semiconductor structure 1100 is shown having a second die 1102 disposed above the bonding layer 106 of the semiconductor structure 300. The semiconductor structure 300 may be similar to the method 200 and Figures 3 to 8 In one embodiment, the second die 1102 can be substantially similar to the first semiconductor structure 300. In some embodiments, the first semiconductor structure 300 and the second die 1102 can include different ICs.

[0066] Reference examples Fig.12 , a semiconductor structure 1200 is shown having a second die 1102 disposed on the bonding layer 106 of the semiconductor structure 300. As described above, the bonding layer 106 of the structure 300 provides a bonding surface suitable for receiving the surface of the die 1102. In one embodiment, a bond can be provided between the bonding layer 106 and the material of the substrate 302 of the die 1102. In other embodiments, an additional adhesive or dielectric layer can be provided on the lower surface of the substrate 302 and connected to the bonding layer 106. The semiconductor structure 300 can be similar to the method 200 and the method described above with reference to the present invention. Figures 3 to 8as discussed. In one embodiment, the second die 1102 may be substantially similar to the first semiconductor structure 300. In some embodiments, the first semiconductor structure 300 and the second die 1102 may include different ICs. On the second die 1102 including its heat dissipation layer 104 and bonding layer 106 is an additional component 1202. In one embodiment, the additional component 1202 is another die, such as another die substantially similar to the semiconductor structure 300 and / or the die 1102. In one embodiment, the additional component 1202 is another IC device including a die having a different function and / or package area than the structure 300 and / or the die 1102. In one embodiment, the additional component 1202 is a carrier substrate, such as a glass substrate. In one embodiment, the additional component 1202 is another substrate. In some embodiments, the component 1202 includes a silicon (Si) substrate. Alternatively or additionally, component 1202 includes another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, component 1202 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some embodiments, component 1202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate can be manufactured by isolation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. In one embodiment, component 1202 is a heat sink. The heat sink can include a thermally conductive plate (e.g., copper or aluminum), a coolant in a pipe, and / or other configurations.

[0067] Reference examples Fig.13 , a semiconductor structure 1300 is shown having a second die 1302 disposed over the bonding layer 106 of the semiconductor structure 1000. In an embodiment, the second die 1302 may be substantially similar to the first semiconductor structure 1000. The semiconductor structure 1000 may be similar to the reference structure discussed above. Fig.10The structures with similar markings are substantially similar. The semiconductor structure 1302 may also be substantially similar to the above. As described above, the heat dissipation material IMD layer is disposed in the upper dielectric layer of the MLI, and the lower dielectric layer of the MLI includes an IMD layer having a different composition (e.g., not including a thermal material similar to layer 104). In an embodiment, the heat dissipation IMD layer of the MLI is diamond-like carbon, and the dielectric layer of the lower layer of the MLI is one or more of silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicate glass (such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), and / or other suitable dielectric materials). In some embodiments, the first semiconductor structure 1000 and the second die 1302 may include different ICs. It should be noted that a combination of stacked semiconductor structure 300 and second die 1302 is also possible.

[0068] It should be noted that in Figures 11 to 13 Electrical connections are provided between the lower die and the upper die of the semiconductor structure stack shown, but not shown in the figure. One exemplary way to provide these electrical connections is through substrate through vias (TSVs). Other ways are also possible.

[0069] Fig.14 FIG. 1 is an illustration of an embodiment of a portion of a semiconductor structure 1400 according to aspects of the present disclosure. The structure 1400 has similar components as the structure 100 of FIG. 1 described above. The structure 1400 includes a first metal layer 102, which may be similar to the structure 100 described above with reference to FIG. Figure 1A , Figure 1B and Figure 1C 1. The heat dissipation layer 104 is formed above the metallization layer 102. The heat dissipation layer 104 can be substantially similar to the above. For example, in some embodiments, the heat dissipation layer is a diamond-like carbon material (amorphous carbon). The heat dissipation layer 104 includes an upper surface having a roughness exhibiting peaks and valleys. As described above, the upper surface can include an RMS of hundreds of nanometers or more. A bonding layer 106 is formed on the upper surface of the heat dissipation layer 104, including peaks and valleys covering the surface. The bonding layer 106 can be similar to the above referenced Figure 1A , Figure 1B and Figure 1C In the illustrated embodiment, the heat sink layer 104 is completely embedded within the bonding layer 106. In other words, no portion of the heat sink layer 104 extends above the top surface of the bonding layer 106. An additional bonding layer 1402 is formed above the bonding layer 106. The additional bonding layer 1402 can be deposited after the bonding layer 106 is planarized, such as described above with reference to Figure 2In one embodiment, the bonding layer 1402 is one or more of AlN, cubic BN (c-BN), BP, Al2O3, SiN, BeO, SiO2, or a combination thereof. In one embodiment, the bonding layer 1402 is a different material than the bonding layer 106. The metallization layer 108 is formed over the bonding layer 1402. The metallization layer 108 may be similar to the metallization layer 108 described above with reference to Figure 1A , Figure 1B , Figure 1C are substantially similar to those discussed above. In some embodiments, the metallization layer 108 is a layer having a different structure (e.g., a different die) than the metallization layer 102. In other embodiments, the metallization layer 108 is another component, such as a substrate, a dielectric layer, a heat sink, etc. As shown in the embodiment, at least one point of the bonding layer 106 has a top surface that is approximately coplanar with the peak of the heat sink layer 104. See "A." As shown in the embodiment, at least one point of the bonding layer 106 has a top surface that is precisely coplanar with the peak of the heat sink layer 104.

[0070] Fig.15 FIG. 1 is an illustration of an embodiment of a portion of a semiconductor structure 1500 according to aspects of the present disclosure. The structure 1500 has similar components as the structure 100 of FIG. 1 described above. The structure 1500 includes a first metal layer 102, which may be similar to the structure 100 described above with reference to FIG. Figure 1A , Figure 1B and Figure 1C 1. The heat dissipation layer 104 is formed above the metallization layer 102. The heat dissipation layer 104 can be substantially similar to the above. For example, in some embodiments, the heat dissipation layer is a diamond-like carbon material (amorphous carbon). The heat dissipation layer 104 includes an upper surface having a roughness exhibiting peaks and valleys. As described above, the upper surface can include an RMS of hundreds of nanometers or more. A bonding layer 106 is formed on the upper surface of the heat dissipation layer 104, including peaks and valleys covering the surface. The bonding layer 106 can be similar to the above referenced Figure 1A , Figure 1B and Figure 1C In the illustrated embodiment, the heat sink layer 104 extends through and over the bonding layer 106. In other words, a portion of the heat sink layer 104 extends over the top surface of the bonding layer 106. See "B". An additional bonding layer 1402 is formed over the bonding layer 106. The additional bonding layer 1402 may be deposited after the bonding layer 106 is planarized, such as described above with reference to FIG. Figure 2The planarization discussed in block 212 of method 200. In some embodiments, due to the etching difference between the bonding layer 106 and the heat sink layer 10, the peak of the heat sink layer 104 remains extended above the flat surface of the bonding layer 106. In other embodiments, the bonding layer 106 is not planarized before depositing another layer (e.g., the bonding layer 1402). In an embodiment, the bonding layer 1402 is one or more of AlN, cubic BN (c-BN), BP, Al2O3, SiN, BeO, SiO2, or a combination thereof. In an embodiment, the bonding layer 1402 is a different material than the bonding layer 106. The metallization layer 108 is formed above the bonding layer 1402. The metallization layer 108 can be the same as described above with reference to Figure 1A , Figure 1B , Figure 1C In some embodiments, the metallization layer 108 is a layer having a different structure (eg, a different die) than the metallization layer 102. In other embodiments, the metallization layer 108 is another component, such as a substrate, a dielectric layer, a heat sink, etc.

[0071] Thus, structures and methods are provided that allow stacked components, such as in a 3D IC configuration, with a heat sink layer within the stack. Although not limiting, the present disclosure provides advantages for IC semiconductor structures having a heat sink layer with a bonding layer integrated with the top surface of the heat sink layer to provide an improved bonding surface. One example advantage is providing a flat bonding surface with reduced roughness compared to a diamond-based layer.

[0072] In a broader embodiment, an integrated circuit (IC) structure is described, which includes a transistor device formed on a substrate, wherein the transistor device has a source / drain (S / D) region and a gate structure. A multi-layer interconnect (MLI) structure is formed above the transistor device, wherein the MLI includes metal lines and metal vias embedded in an inter-metal dielectric (IMD) layer. A heat sink layer having a surface having a plurality of peaks and valleys disposed on at least a portion of the MLI structure is formed. And a bonding layer is located above the heat sink layer and covers the plurality of peaks and valleys.

[0073] In another embodiment, the bonding layer has a first surface having a root mean square (RMS) value less than the RMS value of the surface of the heat dissipation layer. In one embodiment, the RMS value of the first surface is less than 1 nanometer. In one embodiment, the heat dissipation layer is a diamond-like carbon material. In some embodiments, the surface having multiple peaks and valleys has an RMS value of hundreds of nanometers to microns in peak-to-valley height. In one embodiment, the bonding layer is AlN. In one embodiment, the heat dissipation layer includes at least one additional peak extending above the top surface of the bonding layer. In some embodiments of the structure, the multiple peaks and valleys of the heat dissipation layer are completely covered by the bonding layer. In one embodiment, the bonding layer includes at least one of AlN, cubic BN (c-BN), BP, Al2O3, SiN, BeO, and SiO2.

[0074] In another more general embodiment, a method for manufacturing a semiconductor device is provided. The method includes forming a transistor above a semiconductor substrate, and forming a first metal layer and an overlying second metal layer above the transistor. A through hole may extend between the first metal layer and the overlying second metal layer. The method may also include depositing a heat dissipation layer on the overlying second metal layer, and the heat dissipation layer includes a rough surface presenting peaks and valleys. A bonding layer is deposited on the rough surface so that the bonding layer covers at least one peak and valley of the rough surface. And another substrate may be formed above the bonding layer.

[0075] In another embodiment, the method includes planarizing the surface of the bonding layer after deposition. In one embodiment, the deposited bonding layer includes at least one of AlN, cubic BN (c-BN), BP, Al2O3, SiN, BeO and SiO2. Depositing the heat dissipation layer may include depositing diamond-like carbon. In some embodiments of the method, before depositing the heat dissipation layer, a third metal layer is formed on the overlying second metal layer, and a fourth metal layer is formed on the third metal layer. Another through hole may extend between the third metal layer and the fourth metal layer. In one embodiment, a diamond-like carbon material is deposited around the third metal layer, the fourth metal layer and another through hole.

[0076] In another broader embodiment, a method is discussed. The method includes forming a transistor device over a substrate, forming a multi-layer interconnect (MLI) over the transistor device, depositing a diamond-like carbon layer over the MLI, depositing a bonding layer over the diamond-like carbon film, and planarizing the bonding layer to form a planar surface. The surface RMS of the diamond-like carbon layer is at least 100 nanometers.

[0077] In another embodiment, the method includes providing a die on a flat surface. In one embodiment, the bonding layer may be AlN or c-BN. In one embodiment, the method includes forming an interconnect extending through the diamond-like carbon layer and the bonding layer. In some further implementations, the interconnect is connected to a metal layer of the MLI. In one embodiment, the method also includes depositing another bonding layer above the bonding layer, wherein at least one peak of the surface of the diamond-like carbon layer extends into the other bonding layer.

[0078] Details of the methods and devices of the present disclosure are described in the accompanying drawings. The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the aspects of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit IC structure, comprising: a transistor device formed over the substrate, the transistor device having a source / drain (S / D) region and a gate structure; a multi-layer interconnect (MLI) structure located above the transistor device, wherein the multi-layer interconnect structure includes metal lines and metal vias embedded in an inter-metal dielectric (IMD) layer; a heat dissipation layer having a surface having a plurality of peaks and valleys disposed on at least a portion of the multi-layer interconnect structure; as well as The bonding layer is located above the heat dissipation layer and covers the plurality of peaks and valleys.

2. The IC structure according to claim 1, wherein: The bonding layer has a first surface having a root mean square (RMS) value smaller than a root mean square value of a surface of the heat dissipation layer.

3. The IC structure according to claim 2, wherein: The first surface of the bonding layer has a root mean square value of less than 1 nanometer.

4. A method for manufacturing a semiconductor device, comprising: forming a transistor on a semiconductor substrate; forming a first metal layer and an overlying second metal layer over the transistor, wherein a via extends between the first metal layer and the overlying second metal layer; depositing a heat dissipation layer over the overlying second metal layer, wherein the heat dissipation layer comprises a rough surface exhibiting peaks and valleys; depositing a bonding layer over the rough surface, wherein the bonding layer covers at least one peak and valley of the rough surface; and Another substrate is formed over the bonding layer.

5. The method according to claim 4, further comprising: The surface of the bonding layer is planarized after deposition.

6. The method according to claim 4, wherein: The bonding layer is deposited to include at least one of AlN, cubic BN (c-BN), BP, Al2O3, SiN, BeO, and SiO2.

7. A method for manufacturing a semiconductor device, comprising: forming a transistor device over the substrate; forming a multi-layer interconnect (MLI) on the transistor device; depositing a diamond-like carbon layer over the multi-layer interconnect, wherein the surface root mean square of the diamond-like carbon layer is at least several hundred nanometers; depositing a bonding layer on the diamond-like carbon layer; as well as The bonding layer is planarized to form a flat surface.

8. The method according to claim 7, further comprising: A die is provided on the planar surface.

9. The method according to claim 7, wherein: The bonding layer is AlN or c-BN.

10. The method according to claim 7, further comprising: An interconnect is formed extending through the diamond-like carbon layer and the bonding layer.

Images