Semiconductor device

Abstract

The embodiment provides a semiconductor device capable of inhibiting conduction between bonding pads from being hindered by oxide layers on the surfaces of the bonding pads. A semiconductor device according to an embodiment includes: a first chip including a first insulating layer; the semiconductor device includes a first chip including a first insulating layer, and a second chip including a second insulating layer and bonded to the first chip, the semiconductor device including a pad provided on a bonding surface of the first chip and the second chip. A second metal layer disposed between the first metal layer and the first insulating layer, and a third metal layer disposed between the first metal layer and the second insulating layer, and either or both of the second metal layer and the third metal layer contain a second metal having a lower oxidation energy than the first metal; the first metal layer further includes a second metal.

Description

[0001] Related Application

[0002] The present application claims priority based on Japanese Patent Application No. 2023-136376 (filing date: August 24, 2023), and the present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] Among semiconductor devices, there are semiconductor devices that are manufactured by forming different components on different substrates and then bonding these substrates together. Pads electrically connected to each component are formed on the bonding surfaces of these substrates. By bonding the substrates together, these pads are also bonded to each other, and different components are also electrically connected to each other. However, when bonding the pads together, an oxide layer formed on the surface of these pads due to natural oxidation or the like sometimes hinders electrical conduction between the pads. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing the obstruction of conduction between pads caused by an oxide layer on the surface of the pad.

[0006] A semiconductor device in an embodiment comprises: a first chip including a first insulating layer; and a second chip including a second insulating layer and bonded to the first chip, wherein the semiconductor device has a bonding surface arranged between the first chip and the second chip, the pad having a first metal layer including a first metal, a second metal layer arranged between the first metal layer and the first insulating layer, and a third metal layer arranged between the first metal layer and the second insulating layer, either or both of the second metal layer and the third metal layer contain a second metal having lower oxidation energy than the first metal, and the first metal layer also contains the second metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor storage device according to an embodiment.

[0008] Figure 2 It is an equivalent circuit diagram showing an example of the configuration of a memory cell array included in the semiconductor memory device according to the embodiment.

[0009] Figure 3 It is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to an embodiment.

[0010] Figure 4 A diagram showing an example of the configuration of a semiconductor memory device according to an embodiment.

[0011] Figure 5 The diagram sequentially illustrates a part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment.

[0012] Figure 6 The diagram sequentially illustrates a part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment.

[0013] Figure 7 The diagram sequentially illustrates a part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment.

[0014] Figure 8 The diagram sequentially illustrates a part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Fig. 9 The diagram sequentially illustrates a part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment.

[0016] Fig.10 The diagram sequentially illustrates a part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment.

[0017] Fig.11 This is a diagram illustrating a part of the steps of a method for manufacturing a semiconductor memory device according to Modification 1 of the embodiment.

[0018] Fig.12 It is a cross-sectional view of a bonding portion of an insulating layer of a semiconductor memory device according to Modification 2 of the embodiment.

[0019] Explanation of symbols

[0020] 1…semiconductor memory device, 21c, 21cp, 21cv, 21m, 21mp, 21mv…conductive layer, 22c, 22cp, 22m, 22mp, 22mv, 23c, 23cv, 23m, 23mv, 24c, 24m…conductive layer, CN…channel layer, LM, LMa, LMb, LMsa, LMsb…stacked body, MC…memory cell, MR…storage region, NL, OL…insulating layer, PDc, PDcb, PDcc, PDcd, PDm, PDma, PDmd…pad, PL…column, SR…step region, SGD, SGS…selection gate line, STD, STS…selection gate, VAc, VAcb, VAcc, VAcd, VAm, VAmc, VAmd…via, WL…word line. DETAILED DESCRIPTION

[0021] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the present invention is not limited to the embodiments described below. In addition, the constituent elements in the embodiments described below include constituent elements that can be easily thought of by those skilled in the art or substantially the same constituent elements.

[0022] (Configuration Example of Semiconductor Memory Device)

[0023] Figure 1 FIG. 1 is a block diagram of a semiconductor memory device 1 according to an embodiment. Figure 1 As shown, the semiconductor memory device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, an instruction register 350, a sequencer 360, a ready / busy circuit 370, a voltage generating circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540 and a column decoder 550.

[0024] The input / output circuit 310 controls input and output of a signal DQ with an external device such as a memory controller (not shown) for controlling the semiconductor memory device 1. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0025] The input circuit sends data DAT such as write data WD received from an external device to the data register 540 , sends an address ADD to the address register 340 , and sends a command CMD to the command register 350 .

[0026] The output circuit transmits the status information STS received from the status register 330 , the data DAT such as the read data RD received from the data register 540 , and the address ADD received from the address register 340 to an external device.

[0027] The logic control circuit 320 receives, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from an external device, and controls the input / output circuit 310 and the sequencer 360 according to the received signals.

[0028] The status register 330 temporarily stores status information STS during, for example, a data write operation, a read operation, and an erase operation, and notifies an external device whether the operation has been completed normally.

[0029] The address register 340 temporarily stores the address ADD received from the external device via the input / output circuit 310 . The address register 340 also transfers the row address RA to the row decoder 520 and transfers the column address CA to the column decoder 550 .

[0030] The command register 350 temporarily stores the command CMD received from the external device via the input / output circuit 310 and forwards it to the sequencer 360.

[0031] The sequencer 360 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generating circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550 according to the command CMD stored in the command register 350, and performs write operations, read operations, and delete operations.

[0032] The ready / busy circuit 370 sends a ready / busy signal R / Bn to an external device according to the operation status of the sequencer 360 .

[0033] The voltage generating circuit 380 generates voltages required for the write operation, the read operation, and the erase operation according to the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltages supplied from the voltage generating circuit 380 to the memory cells in the memory cell array 510.

[0034] The memory cell array 510 includes a plurality of blocks BLK (BLK0 to BLKn). n is an integer greater than or equal to 2. The block BLK is a collection of a plurality of memory cells associated with a bit line and a word line, and serves as a unit for deleting data, for example. The memory cell is constituted as a transistor, for example, and stores nonvolatile data.

[0035] By including such a memory cell, the semiconductor memory device 1 according to this embodiment is configured as, for example, a NAND type nonvolatile memory.

[0036] The row decoder 520 decodes the row address RA. In addition, the row decoder 520 selects a certain block BLK based on the decoding result. In addition, the row decoder 520 applies a required voltage to the block BLK.

[0037] The sense amplifier module 530 senses data read from the memory cell array 510 during a read operation. In addition, the sense amplifier module 530 sends read data RD to the data register 540. The sense amplifier module 530 sends write data WD to the memory cell array 510 during a write operation.

[0038] The data register 540 includes a plurality of latch circuits. The latch circuits store write data WD and read data RRD. For example, in a write operation, the data register 540 temporarily stores the write data WD received from the input / output circuit 310 and sends it to the sense amplifier module 530. In addition, for example, in a read operation, the data register 540 temporarily stores the read data RD received from the sense amplifier module 530 and sends it to the input / output circuit 310.

[0039] The column decoder 550 decodes the column address CA, for example, during a write operation, a read operation, and an erase operation, and selects a latch circuit in the data register 540 according to the decoding result.

[0040] In addition, the circuit group configured around the memory cell array 510 is also referred to as a peripheral circuit. The peripheral circuit includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The peripheral circuit may also include a status register 330, an address register 340, an instruction register 350, and a sequencer 360, and may further include an input / output circuit 310, a logic control circuit 320, a ready / busy circuit 370, and a voltage generating circuit 380.

[0041] As described above, the semiconductor memory device 1 according to the embodiment includes the memory cell array 510 including a plurality of memory cells and the peripheral circuit for operating the plurality of memory cells.

[0042] Figure 2 2 is an equivalent circuit diagram showing an example of the configuration of a memory cell array 510 included in the semiconductor memory device 1 according to the embodiment.

[0043] As described above, the memory cell array 510 includes a plurality of blocks BLK. Each of the plurality of blocks BLK includes a plurality of string units SU. Each of the plurality of string units SU includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to a peripheral circuit such as a sense amplifier module 530 via a bit line BL. The other ends of each of the plurality of memory strings MS are connected to a peripheral circuit via a common source line SL.

[0044] The memory string MS includes a drain select transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC, and a source select transistor STS. Hereinafter, the drain select transistor STD and the source select transistor STS may be simply referred to as select transistors (STD, STS).

[0045] The memory cell MC is, for example, a field effect transistor (FET: Field Effect Transistor) including a charge accumulation layer in the gate insulating layer. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge accumulation layer. It is also possible to set one or more threshold voltages so that the memory cell MC can store one or more bits of data. The gate electrodes of the plurality of memory cells MC corresponding to a memory string MS are respectively connected to word lines WL. These word lines WL are respectively connected in common to all the memory strings MS in a block BLK.

[0046] The selection transistors (STD, STS) are, for example, field effect transistors. The gate electrodes of the selection transistors (STD, STS) are connected to the selection gate lines (SGD, SGS), respectively. The drain selection line SGD connected to the drain selection transistor STD is set corresponding to the string unit SU, and is commonly connected to all the storage strings MS in one string unit SU. The source selection line SGS connected to the source selection transistor STS is commonly connected to all the storage strings MS in one block BLK.

[0047] One ends of the word lines WL and the select gate lines (SGD, SGS) are respectively connected to peripheral circuits such as the row decoder 520 .

[0048] Figure 3 FIG. 1 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. Figure 3 In the figure, hatching is omitted for the sake of easy viewing of the drawings.

[0049] like Figure 3 As shown, the semiconductor memory device 1 has a structure formed by joining two chips 2 and 3 using insulating layers 40 and 50 portions respectively provided on these chips 2 and 3. The chip 3 as the first chip has an electrode film EL, a source line SL, a plurality of word lines WL, and selection gate lines SGD and SGS in order from the bottom of the paper. The chip 2 as the second chip is arranged above the selection gate line SGD and has a peripheral circuit CBA provided on the semiconductor substrate SB.

[0050] The source line SL is arranged on the electrode film EL via the insulating layer 60. A plurality of plugs PG are arranged in the insulating layer 60, and the source line SL and the electrode film EL are electrically connected via the plugs PG. Figure 1 ) A source potential is applied to the source line SL via the electrode film EL and the plug PG.

[0051] One or more select gate lines SGS, a plurality of word lines WL, and one or more select gate lines SGD are sequentially stacked on the source line SL. A storage region MR is arranged in the center of the direction in which the word lines WL extend, and a step region SR is arranged at the end of the direction in which the word lines WL extend.

[0052] In the memory region MR, a plurality of pillars PL are arranged so as to penetrate the word lines WL and the like in the stacking direction. A plurality of memory cells MC are formed at intersections of the pillars PL and the word lines WL (see Figure 2 ). Thus, the semiconductor memory device 1 is configured as a three-dimensional nonvolatile memory in which memory cells MC are three-dimensionally arranged in the memory region MR, for example.

[0053] Thus, the memory region MR is connected to the memory cell array 510 (see Figure 2 ) is an example of a physical structure corresponding to . In addition, the column PL is the above-mentioned memory string MS (refer to Figure 2 ) is an example of a corresponding physical structure.

[0054] In the physical structure of the semiconductor memory device 1 , the pillars PL are electrically connected to the peripheral circuits CBA via the bit lines BL arranged above the pillars PL.

[0055] In the step region SR, a step portion SP is formed by processing a plurality of word lines WL and select gate lines SGD and SGS into a step shape to form a terminal. Contacts CC connected to the word lines WL of each layer are arranged at the mesa portion of each step of the step portion SP formed by each word line WL.

[0056] The word lines WL and the select gate lines SGD and SGS stacked in multiple layers are led out through these contacts CC. Write voltage and read voltage are applied to the memory cells MC included in the storage region MR in the center of the word lines WL from these contacts CC via the word lines WL at the same height as the memory cells MC.

[0057] The word lines WL, the select gate lines SGD and SGS, the pillars PL, and the contacts CC are covered by the insulating layer 50 as a first insulating layer. The insulating layer 50 also extends to the peripheral region PR around the word lines WL, etc. The contact C3 is arranged in the peripheral region PR, penetrating the insulating layer 50 and connected to the source line SL.

[0058] In addition, a plurality of pads PDm as first pads are arranged on the surface of the insulating layer 50 , and the above-mentioned pillars PL, contacts CC, C3 , etc. are electrically connected to the above-mentioned pads PDm through vias, wirings, and the like.

[0059] The semiconductor substrate SB on the insulating layer 50 is, for example, a silicon substrate. The row decoder 520 and the sense amplifier module 530 (see FIG. 5 ) including transistors TR and wiring are arranged on the surface of the semiconductor substrate SB. Figure 1 ) and other peripheral circuits CBA.

[0060] Various voltages applied from the contactors CC to the memory cells MC are controlled by the peripheral circuits CBA electrically connected to the contactors CC. In addition, data read from the memory cells MC arranged in the height direction of the pillars PL are read by the sense amplifier modules 530 of the peripheral circuits CBA. Thus, the peripheral circuits CBA control the electrical operation of the memory cells MC.

[0061] The peripheral circuit CBA is covered by an insulating layer 40 as a second insulating layer. A plurality of pads PDc as second pads are arranged on the surface of the insulating layer 40, and the transistor TR and the like described above are electrically connected to the pads PDc via vias, wirings, and the like.

[0062] The semiconductor memory device 1 of the embodiment is configured by bonding an insulating layer 40 covering the peripheral circuit CBA and an insulating layer 50 covering the word lines WL and the like to include a plurality of word lines WL, pillars PL, source lines SL, contacts CC and the like, and the peripheral circuit CBA.

[0063] The above-mentioned structures are electrically connected to each other by bonding the pads PDc and PDm together with the bonding of the insulating layers 40 and 50. That is, the pillar PL is connected to the peripheral circuit CBA via the bit line BL and the pads PDm and PDc, etc. The word line WL and the like are connected to the peripheral circuit CBA via the contactor CC and the pads PDm and PDc, etc. The source line SL is connected to the peripheral circuit CBA via the contactor C3 and the pads PDm and PDc, etc.

[0064] The semiconductor memory device 1 configured as described above is an example of a semiconductor device including chips 2 and 3 having a bonding surface between an insulating layer 50 and an insulating layer 40. These chips 2 and 3 are obtained by bonding substrates each having a plurality of word lines WL, pillars PL, source lines SL, contacts CC, etc., and a peripheral circuit CBA formed thereon, and then singulating the substrates.

[0065] In addition, in this specification, the side of the pad PDm configured with the pad PDm connected to multiple word lines WL, pillars PL, source lines SL and contacts CC, and the pad PDc connected to the peripheral circuit CBA is defined as the lower side of the semiconductor storage device 1, and the side of the pad PDc is defined as the upper side of the semiconductor storage device 1.

[0066] Next, use Figure 4 A detailed configuration example of the semiconductor memory device 1 will be described. Figure 4It is a diagram showing an example of the configuration of a semiconductor memory device 1 according to an embodiment.

[0067] In more detail, Figure 4 (a) is a cross-sectional view along the Y direction including the storage region MR of the semiconductor storage device 1. Figure 4 In (a), the structures below the insulating layer 60 and above the insulating layer 54 are omitted.

[0068] Figure 4 (b) is an XY cross-sectional view of the pillar PL at an arbitrary height position of the word line WL. Figure 4 (c) is an XY cross-sectional view of the pillar PL at an arbitrary height position of the selection gate lines SGD and SGS.

[0069] Figure 4 (d) is a cross-sectional view of a bonding portion between the insulating layers 40 and 50 . Figure 4 (e) is an XY cross-sectional view of the pad PDm provided on the insulating layer 50 .

[0070] In addition, in this specification, both the X direction and the Y direction are directions along the orientation of the surface of the word line WL, and the X direction and the Y direction are orthogonal to each other.

[0071] like Figure 4 As shown in (a), the source line SL has a multilayer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are sequentially stacked on the insulating layer 60. The intermediate source line BSL is not disposed below the step region SR of the laminate LM.

[0072] The lower source line DSLa, the middle source line BSL, and the upper source line DSLb are, for example, a polysilicon layer, etc. Among them, at least the middle source line BSL may be a conductive polysilicon layer, etc., in which impurities are diffused.

[0073] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb formed by alternately laminating a plurality of word lines WL and a plurality of insulating layers OL.

[0074] The stack LMa is arranged above the source line SL. A plurality of selection gate lines SGS0 and SGS1 are arranged in sequence from the upper layer side of the stack LMa through the insulating layer OL below the word line WL of the lowermost layer of the stack LMa. The stack LMb is arranged on the stack LMa. A plurality of selection gate lines SGD0 and SGD1 are arranged in sequence from the upper layer side of the stack LMb through the insulating layer OL above the word line WL of the uppermost layer of the stack LMb.

[0075] The number of stacked word lines WL and select gate lines SGD, SGS as conductive layers in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0076] The top insulating layer OL of each stacked body LMa, LMb is, for example, thicker than the other insulating layers OL in the stacked bodies LMa, LMb. However, the insulating layers OL of the stacked bodies LMa, LMb may be substantially equal in thickness. The top insulating layer OL of the stacked body LMa is connected to the word line WL of the bottom layer of the stacked body LMb, and insulating layers 52, 53, 54, ... are sequentially arranged on the top insulating layer OL of the stacked body LMb.

[0077] The insulating layers 52, 53, 54, ... constitute a part of the insulating layer 50 mentioned above. Figure 4 The uppermost surface not shown in (a) is in contact with the lower surface of the insulating layer 40 on the peripheral circuit CBA side as described above.

[0078] In addition, the laminated body LM is divided in the Y direction by the plurality of plate-shaped portions PT.

[0079] That is, the plate-like portions PT are arranged in the Y direction and extend in the direction along the stacking direction and the X direction of the stacked body LM. In this way, the plate-like portion PT extends continuously in the stacked body LM from one end to the other end in the X direction of the stacked body LM. In addition, the plate-like portion PT penetrates the stacked body LM and the upper source line DSLb and reaches the middle source line BSL in the memory region MR. The plate-like portion PT is formed as a single body of the insulating layer 55 such as a silicon oxide layer.

[0080] The plate-like portion PT has a tapered shape whose width in the Y direction decreases from the upper end toward the lower end, or a bowing shape whose width in the Y direction is the largest at a predetermined position between the upper end and the lower end.

[0081] In the memory region MR, a plurality of separation layers SHE are arranged between the plate-like portions PT adjacent in the Y direction, penetrating the upper layer of the laminate LM and extending in the direction along the X direction. These separation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the selection gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the selection gate line SGD1.

[0082] In other words, the separation layers SHE penetrating the upper portion of the laminate LM extend along the X direction in the memory region MR between adjacent plate-shaped portions PT, thereby dividing the upper portion of the laminate LM into the above-mentioned selection gate lines SGD0 and SGD1.

[0083] In addition, the area between the plate-like portions PT adjacent to each other in the Y direction is the same as the block BLK (see Figure 2 ) is an example of a physical structure equivalent to . In addition, the region divided into the pattern of the selection gate lines SGD0 and SGD1 by the separation layer SHE between the adjacent plate-like portions PT is the same as the above-mentioned string unit SU (refer to Figure 2 ) is an example of a corresponding physical structure.

[0084] In the memory region MR, a plurality of pillars PL are dispersedly arranged which penetrate the laminated body LM, the upper source line DSLb, and the intermediate source line BSL and reach the lower source line DSLa.

[0085] The plurality of columns PL are arranged, for example, in a staggered configuration when viewed from the stacking direction of the stack LM. Each column PL has a cross-sectional shape along the layer direction of the stack LM, that is, along the XY plane, such as a circle, an ellipse, or a "koban" shape ("koban" is an ancient Japanese oval gold coin).

[0086] In addition, the column PL has a conical shape in which the diameter and the cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the stack LMa and the portion penetrating the stack LMb. Alternatively, the column PL has a convex shape in which the diameter and the cross-sectional area are the largest at a predetermined position between the upper layer side and the lower layer side, for example, at the portion penetrating the stack LMa and the portion penetrating the stack LMb.

[0087] Each of the plurality of pillars PL includes a memory layer ME extending in the stacking direction in the stacked body LM, a channel layer CN penetrating the stacked body LM and connected to the intermediate source line BSL, a cap layer CP at an upper end of the pillar PL, and a core layer CR serving as a core material of the pillar PL.

[0088] like Figure 4 As shown in (b) and (c) of FIG. 1 , the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are sequentially stacked from the outer peripheral side of the pillar PL. More specifically, the memory layer ME is arranged on the side of the pillar PL except for the depth position of the middle source line BSL. In addition, the memory layer ME is also arranged on the bottom surface of the pillar PL reaching the depth of the lower source line DSLa.

[0089] The channel layer CN penetrates the stacked body LM, the upper source line DSLb and the middle source line BSL on the inner side of the storage layer ME and reaches the depth of the lower source line DSLa. In more detail, the channel layer CN is arranged on the side and bottom of the pillar PL through the storage layer ME. Among them, a part of the channel layer CN contacts the middle source line BSL on the side, thereby being electrically connected to the source line SL including the middle source line BSL. The core layer CR is filled further inside the channel layer CN.

[0090] In addition, each of the plurality of pillars PL has a cap layer CP connected to the channel layer CN at an upper end. The cap layer CP is connected to a bit line BL arranged in the insulating layer 53 via a plug CH arranged in the insulating layer 52. The bit line BL extends above the stacked body LM in a manner intersecting with the extraction direction of the word line WL, for example, in a direction along the Y direction.

[0091] In addition, Figure 4 In (a), in each region separated by the separation layer SHE, only one column PL is connected to the plug CH. Figure 4 The cross section shown in (a) is shown at different positions through Figure 4 (a) is connected to the plug CH not shown in the figure Figure 4 The bit line BL shown in (a) is parallel to other bit lines BL extending in the direction along the Y direction.

[0092] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, silicon nitride layers, etc. The channel layer CN and the cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0093] like Figure 4 As shown in (b), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL that face the word lines WL. By applying a predetermined voltage from the word lines WL, data is written into and read from the memory cells MC.

[0094] like Figure 4 As shown in (c), through the above-mentioned structure, a selection gate STD is formed on the side of the column PL and the portion opposite to the selection gate lines SGD0 and SGD1 arranged on the upper layer of the word line WL. In addition, a selection gate STS is formed on the side of the column PL and the portion opposite to the selection gate lines SGS0 and SGS1 arranged on the lower layer of the word line WL.

[0095] By applying a predetermined voltage from the selection gate lines SGD and SGS, respectively, the selection gates STD and STS are turned on or off, and the memory cells MC of the pillars PL to which the selection gates STD and STS belong can be set to a selected state or a non-selected state.

[0096] In addition, since the plurality of pillars PL are dispersedly arranged, when the laminated body LM is formed by a laminated body in which a sacrificial layer and an insulating layer are stacked, as described later, the laminated body is supported in the storage region MR. On the other hand, in the step region SR, a plurality of columnar portions (not shown) are dispersedly arranged instead of the pillars PL. Thus, when the laminated body LM is formed by a laminated body in which a sacrificial layer and an insulating layer are stacked, the laminated body is supported in the step region SR.

[0097] like Figure 4 As shown in (d) and (e) of FIG. 1 , the pad PDm is arranged on the insulating layer 50 in a manner having, for example, a rectangular upper surface on the bonding surface of the insulating layer 50 covering the laminate LM and bonded to the insulating layer 40. However, the shape of the pad PDm observed from above may be a shape other than a rectangular shape, such as a circle or an ellipse.

[0098] As described above, the insulating layer 50 is the insulating layers 52, 53, 54, etc. stacked on the upper surface of the stacked body LM. The insulating layer 50 generally has a structure of stacked silicon oxide layers, for example. However, in the stacked structure of the insulating layer 50, other insulating layers such as a silicon nitride layer and a silicon oxynitride layer may be sandwiched, and these other insulating layers may be arranged on the bonding surface of the insulating layer 50.

[0099] The pad PDm has a tapered shape in which the cross-sectional area along the XY plane decreases from the bonding surface of the insulating layer 50 toward the depth direction of the insulating layer 50 .

[0100] A via hole VAm having a circular cross-section in the direction of the XY plane is connected to the lower end of the pad PDm located at a predetermined depth in the insulating layer 50. The via hole VAm as the first via hole has a tapered shape in which the cross-sectional area and the diameter in the direction of the XY plane decrease as the upper end connected to the pad PDm moves toward the depth direction of the insulating layer 50.

[0101] Any number of vias and wirings are connected below the via VAm to electrically connect the pillars PL, word lines WL, select gate lines SGD and SGS, and source lines SL to different pads PDm, respectively.

[0102] The pad PDm and the via VAm have a conductive layer 21m containing a predetermined metal as a core material. The conductive layer 21m is, for example, a Cu layer, and in this case, Cu contained in the pad PDm and the via VAm is an example of the first metal.

[0103] The pad PDm and the via VAm also have a conductive layer 22m containing a predetermined metal as a liner. That is, the conductive layer 22m is arranged between the side surface of the conductive layer 21m of the pad PDm, the lower surface of the conductive layer 21m of the pad PDm except for the connection portion with the via VAm, and the side surface of the conductive layer 21m of the via VAm and the insulating layer 50. The conductive layer 22m is, for example, a Ti layer, and in this case, the Ti contained in the conductive layer 22m is an example of the second metal.

[0104] At this time, the metal contained in the conductive layer 22m is a metal that easily diffuses into the conductive layer 21m, and is a metal whose oxidation energy is lower than that of the metal contained in the conductive layer 21m. In addition, the conductive layer 22m such as a Ti layer functions as a barrier metal layer that suppresses the diffusion of the conductive layer 21m such as a Cu layer into the insulating layer 50.

[0105] The pad PDc is arranged on the insulating layer 40 so as to have a rectangular lower surface on the bonding surface of the insulating layer 40 that covers the peripheral circuit CBA and is bonded to the insulating layer 50. However, the shape of the pad PDc viewed from above may be a shape other than a rectangle, such as a circle or an ellipse.

[0106] Here, the insulating layer 40 has a structure of, for example, a stacked silicon oxide layer, similarly to the above-mentioned insulating layer 50. However, in the stacked structure of the insulating layer 40, other insulating layers such as a silicon nitride layer and a silicon oxynitride layer may be sandwiched, and these other insulating layers may be arranged on the bonding surface of the insulating layer 40.

[0107] The pad PDc has a tapered shape in which the cross-sectional area along the direction of the XY plane becomes smaller as it goes from the bonding surface of the insulating layer 40 toward the depth direction of the insulating layer 40 .

[0108] A via hole VAc having a circular cross-section in the direction of the XY plane is connected to the upper end of the pad PDc located at a predetermined depth in the insulating layer 40. The via hole VAc as the second via hole has a tapered shape in which the cross-sectional area and diameter in the direction of the XY plane decrease as it moves from the lower end connected to the pad PDc toward the depth direction of the insulating layer 40.

[0109] Any number of vias and wirings are connected above the via VAc to electrically connect the above-mentioned peripheral circuit CBA to different pads PDc respectively.

[0110] The pad PDc and the via VAc have a conductive layer 21c containing a predetermined metal as a core material. The conductive layer 21c is, for example, a Cu layer, similarly to the conductive layer 21m of the pad PDm described above. That is, the pad PDc and the via VAc also contain, for example, Cu as the first metal, similarly to the pad PDm and the via VAm.

[0111] The pad PDm and the via VAm also have a conductive layer 22m containing a predetermined metal as a lining layer. That is, the conductive layer 22c is arranged between the side surface of the conductive layer 21c of the pad PDc, the upper surface of the conductive layer 21c of the pad PDc except for the connection portion with the via VAc, and the side surface of the conductive layer 21c of the via VAc and the insulating layer 40. The conductive layer 22c is, for example, a Ti layer, etc., similar to the conductive layer 22m of the pad PDm and the via VAm described above.

[0112] At this time, the metal contained in the conductive layer 22c is also a metal that easily diffuses into the conductive layer 21c, and is also a metal whose oxidation energy is lower than that of the metal contained in the conductive layer 21c. In addition, the conductive layer 22c, which is a Ti layer or the like, also functions as a barrier metal layer that inhibits the conductive layer 21c, which is a Cu layer or the like, from diffusing into the insulating layer 40.

[0113] At least a portion of the metal such as Ti contained in the conductive layers 22m and 22c diffuses into the conductive layers 21m and 21c. More specifically, the metal from the conductive layers 22m and 22c is mainly localized at the grain boundaries 21g of the metal such as Cu contained in the conductive layers 21m and 21c.

[0114] Here, when elemental analysis of the conductive layers 21m and 21c is performed, metal from the conductive layers 22m and 22c and oxygen are detected at the grain boundaries 21g of the metal contained in the conductive layers 21m and 21c. Therefore, it is considered that the metal from the conductive layers 22m and 22c coexists with oxygen at the grain boundaries 21g of the metal contained in the conductive layers 21m and 21c.

[0115] In addition, in the above Figure 4 (d) shows the interface between the conductive layers 21m and 22m of the pad PDm and the conductive layers 21c and 22c of the pad PDc. However, the pad PDm and the pad PDc may be bonded by Cu-Cu bonds, for example, and the interface therebetween may not be observed.

[0116] In this case, it can be determined that a bonding surface exists between the pads PDm and PDc based on any of the following points.

[0117] That is, when the pads PDm and PDc are bonded, although the insulating layers 50 and 40 are also bonded to each other, the interface between the insulating layers 50 and 40 is mostly observed.

[0118] In addition, in the pad PDm and the pad PDc, the directions of the tapered shapes are often different. This is because, as described later, the pad PDm is processed from the outermost surface side of the insulating layer 50, that is, the bonding surface side with the insulating layer 40, and the pad PDc is processed from the outermost surface side of the insulating layer 40, that is, the bonding surface side with the insulating layer 50. As a result, the pad PDm has a tapered shape whose cross-sectional area decreases toward the via hole VAm side below the paper, and the pad PDc has a tapered shape whose cross-sectional area decreases toward the via hole VAc side above the paper.

[0119] (Method for manufacturing semiconductor memory device)

[0120] Next, use Figures 5 to 10 A method for manufacturing the semiconductor memory device 1 according to the embodiment will be described. Figures 5 to 10 The diagram sequentially illustrates a part of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0121] First, in Figure 5 2 shows a stacked body LMsa as a lower layer portion of the stacked body LM before the word line WL is formed, and a state where various structures are formed in the stacked body LMsa. Figure 5 It is a cross-sectional view along the X direction of a region which will later become the memory region MR and the step region SR.

[0122] like Figure 5 As shown in (a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are sequentially formed on a supporting substrate SS.

[0123] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The above-mentioned insulating layer 60 (see Figure 3 ).

[0124] The intermediate sacrificial layer SCN is formed in a region on the support substrate SS that will later become the storage region MR, and the intermediate insulating layer SCO is formed in a region on the support substrate SS that will later become the step region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which is later replaced by a polysilicon layer and becomes the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0125] In addition, a stacked body LMsa formed by alternately stacking a plurality of insulating layers NL and a plurality of insulating layers OL is formed on the upper source line DSLb. The insulating layer NL is, for example, a silicon nitride layer, and functions as a sacrificial layer that is later replaced by a conductive material to become a word line WL or a select gate line SGS.

[0126] like Figure 5 As shown in (b), in a part of the laminate LMsa, the insulating layer NL and the insulating layer OL are processed into a step shape to form a step portion SPsa. The step portion SPsa is formed by repeatedly thinning the mask pattern of the photoresist layer and etching the insulating layer NL and the insulating layer OL of the laminate LMsa.

[0127] That is, a mask pattern is formed on the upper surface of the laminated body LMsa, and the exposed portions of the insulating layer NL and the insulating layer OL are etched away layer by layer. In addition, by treatment based on oxygen plasma or the like, the ends of the mask pattern are retreated to expose the upper surface of the laminated body LMsa again, and the insulating layer NL and the insulating layer OL are further etched away layer by layer. Such treatment is repeated multiple times to form the step portion SPsa.

[0128] like Figure 5 As shown in (c), the insulating layer 51 is formed to cover the step portion SPsa and reach the height of the upper surface of the laminated body LMsa. The insulating layer 51 is also formed in the outer region of the step portion SPsa.

[0129] like Figure 5 As shown in (d) of FIG. 1 , for example, a plurality of memory holes MHa and a plurality of holes HLa extending in the stacking direction are formed together in the stacked body LMsa.

[0130] A plurality of memory holes MHa penetrate the stacked body LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa are formed in a region to be the memory region MR, which is a portion of the lower structure of the pillar PL.

[0131] A plurality of holes HLa penetrate the insulating layer 51, the laminated body LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa. These holes HLa are formed in a region that will later become the step region SR, and are a part of the lower structure of the columnar portion. As described above, the lower structure of the columnar portion supports these structures in the step region SR when the laminated body LMa is formed from the laminated body LMsa.

[0132] like Figure 5 As shown in (e) of FIG. 1 , the memory hole MHa and the hole HLa are filled with a sacrificial layer 26 such as an amorphous silicon layer.

[0133] Thus, pillars PLc formed by filling the plurality of memory holes MHa with the sacrificial layer 26 are formed in a region later to be the memory region MR. Also, columnar portions HRc formed by filling the plurality of holes HLa with the sacrificial layer 26 are formed in a region later to be the step region SR.

[0134] Then, in Figure 6 and Figure 7 4 shows a stacked body LMsb as an upper layer portion of the stacked body LM before the word line WL is formed, and a state where various structures are formed in the stacked body LMsb. Figure 6 and Figure 7 With the above Figure 5 Similarly, this is a cross-sectional view taken along the X direction of a region which will later become the memory region MR and the step region SR.

[0135] like Figure 6 As shown in (a), a stacked body LMsb is formed by alternately stacking a plurality of insulating layers NL and a plurality of insulating layers OL on the stacked body LMsa and the insulating layer 51 of the step portion SPsa. The sacrificial layer NL of the stacked body LMsb will be replaced by a conductive layer and become a word line WL or a selection gate line SGD.

[0136] like Figure 6 As shown in (b), in a part of the laminate LMsb, the insulating layer NL and the insulating layer OL are processed into a step shape to form a step portion SPsb. The step portion SPsb is formed by Figure 5 The process shown in (b) is similarly formed by repeatedly performing thinning of the mask pattern of the photoresist layer or the like and etching of the insulating layer NL and the insulating layer OL of the stacked body LMsb a plurality of times.

[0137] At this time, the step portion SPsb is formed by bringing the uppermost section of the step portion SPsa and the lowermost section of the step portion SPsb close to each other. Thus, the step portions SPsa and SPsb are arranged in a manner that they are continuously connected from the lower layer side to the upper layer side of the stacked bodies LMsa and LMsb. In addition, by removing the stacked body LMsb on the insulating layer 51 covering the step portion SPsb, the upper end portion of the columnar portion HRc formed on the step portion SPsa is exposed on the upper surface of the insulating layer 51.

[0138] like Figure 6 As shown in (c), the insulating layer 51 is formed to cover the step portion SPsb and to cover the insulating layer 51 formed on the step portion SPsa. Thus, the insulating layer 51 reaches the height of the upper surface of the laminated body LMsb.

[0139] like Figure 7 As shown in (a), for example, a plurality of memory holes MHb and a plurality of holes HLb extending in the stacking direction are formed together at a height position of the stacked body LMsb.

[0140] The plurality of memory holes MHb penetrates the stacked body LMsb and reaches the upper end of the pillars PLc formed in the stacked body LMsa. These memory holes MHb are arranged in a region to be the memory region MR and are the upper structure of the pillars PL.

[0141] The plurality of holes HLb penetrate the insulating layer 51 and the laminated body LMsb and reach the upper end of the columnar portion HRc formed in the laminated body LMsa. The holes HLb are arranged at positions overlapping with the step portions SPsa and SPsb in the stacking direction and are portions of the upper structure of the columnar portion. As described above, the upper structure of the columnar portion supports these structures in the step region SR when the laminated body LMb is formed from the laminated body LMsb.

[0142] like Figure 7 As shown in (b), the sacrificial layer 26 is removed from the pillar PLc and the columnar portion HRc respectively connected to their lower ends through the memory hole MHb and the hole HLb.

[0143] Thus, memory holes MHa are respectively opened at the bottoms of the plurality of memory holes MHb, thereby forming a plurality of memory holes MH that penetrate the insulating layer 51, the stacked bodies LMsb, LMsa, the upper source line DSLb and the intermediate sacrificial layer SCN and reach the lower source line DSLa.

[0144] In addition, holes HLa are respectively opened at the bottoms of the plurality of holes HLb to form a plurality of holes HL that penetrate the insulating layer 51, the laminated bodies LMsb and LMsa, the upper source line DSLb and the intermediate insulating layer SCO and reach the lower source line DSLa.

[0145] like Figure 7 As shown in (c), an insulating layer 58 such as a silicon oxide layer is filled in each of the plurality of holes HL to form a plurality of columnar portions HR that penetrate the insulating layer 51, the stacked bodies LMsb, LMsa, the upper source line DSLb and the intermediate insulating layer SCO and reach the lower source line DSLa.

[0146] When the insulating layer 58 is filled into the plurality of holes HL, the plurality of memory holes MH formed in a region to be the memory region MR later are protected in advance by a photoresist layer or the like.

[0147] Then, in Figure 8 2 shows a case where a multilayer structure or the like is formed in the memory hole MH to form the pillar PL. Figure 8 3 is an enlarged cross-sectional view of the memory hole MH at a height position of the middle sacrificial layer SCN.

[0148] like Figure 8 As shown in (a), a block insulating layer BK such as a silicon oxide layer is formed on the side walls of the memory hole MH and the hole HL.

[0149] like Figure 8 As shown in (b), the charge storage layer CT is formed on the side wall of the memory hole MH via the block insulating layer BK.

[0150] like Figure 8As shown in (c), a tunnel insulating layer TN is formed on the side wall of the memory hole MH via the block insulating layer BK and the charge storage layer CT.

[0151] Accordingly, the memory layer ME including the block insulating layer BK, the charge storage layer CT, and the tunnel insulating layer TN is formed in order from the outer peripheral side of the memory hole MH.

[0152] like Figure 8 As shown in (d), a channel layer CN is formed on the sidewall of the memory hole MH via the memory layer ME.

[0153] like Figure 8 As shown in (e), the core layer CR is filled into the gap remaining in the memory hole MH.

[0154] Then, the core layer CR at the upper end of the memory hole MH is removed and the semiconductor layer is filled to form a cap layer CP (see Figure 4 (a)).

[0155] In addition, a slit (not shown) is formed in the stacked bodies LMsa and LMsb, extending in the direction along the X direction and penetrating the stacked bodies LMsa and LMsb and the upper source line DSLb to reach the intermediate sacrificial layer SCN or the intermediate insulating layer SCO. The slit is later filled with the insulating layer 55 to form a plate-shaped portion PT.

[0156] like Figure 8 As shown in (f), a solution such as hot phosphoric acid is injected through the slit to remove the intermediate sacrificial layer SCN, and a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. As a result, a portion of the block insulating layer BK formed on the side wall of the memory hole MH is exposed in the gap layer GPs.

[0157] At this time, a protective layer such as a silicon oxide layer is formed in advance on the side wall of the slit to prevent the insulating layer NL in the stacked bodies LMsa and LMsb from being removed. The intermediate sacrificial layer SCN is removed exclusively by a chemical solution injected through the lower end of the slit. In addition, in the area that will later become the step region SR, the intermediate insulating layer SCO formed instead of the intermediate sacrificial layer SCN is not removed by the above-mentioned chemical solution. Therefore, the gap layer GPs is not formed in the area that will later become the step region SR.

[0158] like Figure 8 As shown in (g), different chemical solutions are injected through the slits to sequentially remove the block insulating layer BK, the charge storage layer CT and the tunnel insulating layer TN exposed in the gap layer GPs. Thus, a part of the side surface of the channel layer CN is exposed in the gap layer GPs.

[0159] like Figure 8As shown in (h), a raw material gas such as polysilicon is injected through the slit to fill the gap layer GPs with a polysilicon layer. Thus, an intermediate source line BSL is formed between the lower source line DSLa and the upper source line DSLb.

[0160] Accordingly, a pillar PL connected to the source line SL is formed on a portion of the side surface of the channel layer CN.

[0161] After that, the protective layer on the side wall of the slit is removed, and a chemical solution such as hot phosphoric acid is injected through the slit to remove the insulating layer NL in the stacked bodies LMsa and LMsb. In addition, a raw material gas such as tungsten is injected through the slit to fill the gaps in the stacked bodies LMsa and LMsb formed by the removal of the insulating layer NL with a tungsten layer or the like.

[0162] Thus, a stacked body LM is formed in which a plurality of word lines WL and a plurality of insulating layers OL are alternately stacked and further includes select gate lines SGD and SGS.

[0163] In addition, the insulating layer NL is removed, and the stacked bodies LMsa and LMsb having gaps in the multilayer become fragile structures. In the area that will later become the storage area M, the plurality of pillars PL support such fragile stacked bodies LMsa and LMsb. On the other hand, in the step portions SPsb and SPsa, the plurality of columnar portions HR support these stacked bodies LMsa and LMsb.

[0164] This can suppress the insulating layer OL remaining in the laminated bodies LMsa and LMsb from being warped or the laminated bodies LMsa and LMsb having gaps from being distorted or collapsed.

[0165] As described above, the process of forming the middle source line BSL from the middle sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also referred to as a replacement process.

[0166] Then, the slit is filled with an insulating layer 54 to form a plate-like portion PT. In addition, a groove is formed through one or more layers including the uppermost layer of the stacked body LMb, and an insulating layer 56 is filled in the groove to form a separation layer SHE that divides one or more upper layers of the stacked body LMb into a pattern of a selection gate line SGD.

[0167] In addition, a plurality of contacts CC are formed so as to penetrate the insulating layer 51 and reach the word lines WL and the select gate lines SGD and SGS at each step constituting the step portion SP.

[0168] Next, an insulating layer 52 is formed on the upper surface of the laminated body LM and the upper surface of the insulating layer 51 covering the step region SR, and a plug CH is formed that penetrates the insulating layer 52 and is connected to the pillar PL. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and a bit line BL and the like connected to the plug CH are formed. Thereafter, insulating layers 54, etc. are sequentially formed, and plugs and wirings and the like are formed in an arbitrary number of stacked layers.

[0169] Then, in Fig. 9 2 shows a state where a via hole VAm and a pad PDm are formed in the insulating layer 50 and then connected to the pad PDc on the insulating layer 40 side covering the peripheral circuit CBA. Fig. 9 It is a cross-sectional view of a portion where the insulating layer 50 is joined to the insulating layer 40 .

[0170] like Fig. 9 As shown in (a), etching is performed from the outermost surface of the insulating layer 50 to form a via hole VH and a groove GR connected to the upper end of the via hole VH. The via hole VH reaches other wirings (not shown) formed in the insulating layer 50.

[0171] The via hole VH and the groove GR are obtained, for example, by forming a via hole VH from the outermost surface of the insulating layer 50 to a predetermined depth and then expanding the upper end of the via hole VH into the shape of the groove GR. Alternatively, for example, after forming the groove GR from the outermost surface of the insulating layer 50 to a predetermined depth, a via hole VH extending from the bottom surface of the groove GR to a deeper position of the insulating layer 50 may be formed.

[0172] In any processing method, etching is performed from the outermost surface of the insulating layer 50 to form the groove GR and the via hole VH into a tapered shape whose cross-sectional area along the XY plane decreases from the upper end side toward the lower end side.

[0173] like Fig. 9 As shown in (b) of FIG. 5 , a conductive layer 22 m such as a Ti layer is formed to cover the side and bottom surfaces of the trench GR and the side surfaces of the via hole VH. At this time, the conductive layer 22 m is also formed on the upper surface of the insulating layer 50 .

[0174] like Fig. 9 As shown in (c), the gaps remaining in the groove GR and the via hole VH are filled with Cu material or the like to form a conductive layer 21m. At this time, the Cu material is filled into the groove GR and the via hole VH by plating or the like, and the conductive layer 21m is formed with a grain boundary 21g of a metal such as Cu. In addition, at this time, the conductive layer 21m is also formed on the upper surface of the insulating layer 50 via the conductive layer 22m. However, the conductive layers 21m and 22m on the upper surface of the insulating layer 50 are removed in sequence by CMP (Chemical Mechanical Polishing) or the like.

[0175] Thus, a pad PDm having an upper surface exposed on the outermost surface of the insulating layer 50 and a via VAm connected to a lower end of the pad PDm at an upper end are formed. Such a method of forming the pad PDm and the via VAm at the same time is also called a dual damascene method.

[0176] In addition, there is a case where the metal such as Cu in the pad PDm is chemically oxidized by performing CMP treatment on the surface of the conductive layer 21m filled in the groove GR and the via hole VH. In addition, there is also a case where the metal such as Cu in the pad PDm exposed on the surface of the insulating layer 50 is naturally oxidized by leaving it in the atmosphere for a predetermined time after the above structure is formed.

[0177] Fig. 9 The oxide layer 57m on the upper surface of the pad PDm shown in (d) is an oxide layer formed by chemical oxidation or natural oxidation.

[0178] On the other hand, a peripheral circuit CBA is formed on a semiconductor substrate SB that is different from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contactors, vias, wiring, etc. are formed in the insulating layer 40 to lead the peripheral circuit CBA to the surface of the insulating layer 40, and are connected to the pads PDc and vias VAc formed on the outermost surface of the insulating layer 40.

[0179] At this time, the pad PDc and the via VAc in the insulating layer 40 are also connected to Fig. 9 (a)~ Fig. 9 These pads PDc and via holes VAc are formed by etching from the outermost surface of the insulating layer 40, and thus have a tapered shape in which the cross-sectional area along the XY plane decreases as the depth increases from the outermost surface of the insulating layer 40.

[0180] like Fig. 9 As shown in (e), the insulating layer 50 on the support substrate SS side is bonded to the insulating layer 40 on the semiconductor substrate SB side. These insulating layers 50 and 40 can be bonded by, for example, activating them in advance by plasma treatment. In addition, at this time, the support substrate SS and the semiconductor substrate SB are aligned in such a way that the pads PDm formed on the insulating layer 50 and the pads PDc formed on the insulating layer 40 overlap in the vertical direction.

[0181] Furthermore, at the time when the insulating layers 50 and 40 are bonded to each other, an oxide layer 57 c is also formed on the surface of the pad PDc.

[0182] like Fig. 9As shown in (f), after the insulating layers 50 and 40 are bonded, annealing is performed to bond the pads PDm and PDc to each other. By the annealing, part of the metal such as Ti in the conductive layers 22m and 22c is diffused into the conductive layers 21m and 21c.

[0183] In addition, the oxide layers 57m and 57c on the upper surfaces of the pads PDm and PDc disappear by the annealing process. It is presumed that this is because the metal from the conductive layers 22m and 22c diffused into the conductive layers 21m and 21c reduces the oxide layers 57m and 57c on the upper surfaces of the pads PDm and PDc. According to the results of the above-mentioned elemental analysis, it is shown that the metal from the conductive layers 22m and 22c is offset together with oxygen at the grain boundaries 21g of the metal in the conductive layers 21m and 21c.

[0184] In addition, part of the metal in the conductive layers 22m and 22c reduces the oxide layers 57m and 57c and diffuses into the conductive layers 21m and 21c. Thus, the thickness of the conductive layers 22m and 22c may be slightly reduced partially or entirely.

[0185] By continuing the annealing process after the oxide layers 57 m and 57 c on the surface disappear, the pad PDm and the pad PDc are bonded to each other by, for example, a Cu—Cu bond.

[0186] Thereby, the supporting substrate SS and the semiconductor substrate SB are bonded together.

[0187] After that, the support substrate SS is removed by grinding to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 formed with the plug PG. In addition, the semiconductor substrate SB is singulated by dicing to obtain the above-mentioned chips 2 and 3 (see Figure 3 ) are connected together to form a semiconductor storage device 1.

[0188] In this way, the semiconductor memory device 1 according to the embodiment is manufactured.

[0189] In addition, there is a case where the interface between the pads PDm and PDc disappears as described above due to the bonding of the pads PDm and PDc. Even in this case, in addition to the case where the bonding interface between the insulating layers 50 and 40 can be observed, there is a case where the bonding surface between the pads PDm and PDc can be determined by observing the direction of the tapered shape of the pads PDm and PDc.

[0190] Below, use Fig.10 A method of identifying the bonding surfaces of the pads PDm and PDc other than the above will be described. Fig.10 With the above Fig. 9 It is also a cross-sectional view of a bonding portion between the insulating layer 50 and the insulating layer 40 .

[0191] like Fig.10 As shown in (a), there may be a misalignment in the vertical overlap between the pads PDm and PDc.

[0192] As described above, when the pads PDm and PDc are bonded to each other, the support substrate SS and the semiconductor substrate SB are aligned so that they overlap in the vertical direction. However, there is a case where the pads PDm and PDc are bonded with slight misalignment due to alignment errors or the like.

[0193] In this way, by observing the pads PDm and PDc that are misaligned, for example, it is possible to determine that a bonding surface exists between the pads PDm and PDc.

[0194] like Fig.10 As shown in (b), sometimes the size of the pad PDm is different from the size of the pad PDc. As the reason for the difference in size of these pads PDm and PDc, the size of these pads PDm and PDc is different in design. Or there is also the following situation, because these pads PDm and PDc are formed independently, the pads PDm and PDc are formed to have different sizes due to processing errors during formation.

[0195] In this way, by observing that the sizes of the pads PDm and PDc are different, it can be determined that a bonding surface exists between the pads PDm and PDc.

[0196] (Summary)

[0197] Among semiconductor devices, there are semiconductor devices that are constructed by forming different elements on different substrates and bonding these substrates. In order to electrically connect these elements, pads electrically connected to each element are formed on the bonding surface. When bonding the substrates, different elements can be electrically connected to each other by bonding these pads.

[0198] However, after the pads are formed, oxide layers may be formed on the surfaces of the pads before the pads are bonded to each other. When the pads are bonded to each other, the oxide layers on the surfaces may hinder electrical conduction between the pads.

[0199] On the other hand, in addition to pads for electrically connecting different elements to each other, semiconductor devices also have multiple contacts, vias, wirings, etc. In order to suppress the diffusion of the metal materials constituting them into the insulating layer, a barrier metal layer is sometimes used. When the metal material is Cu, a Ta layer is usually used as the barrier metal layer.

[0200] The present inventors paid attention to the barrier metal layer and studied the use of a metal with high diffusivity and high reducibility in Cu as a constituent material of the barrier metal layer. As a result, they found that the oxide layer on the pad surface disappears during the annealing process during pad bonding.

[0201] According to the semiconductor memory device 1 of the embodiment, the pads PDm and PDc respectively have conductive layers 22m and 22c disposed between the insulating layers 50 and 40, and the conductive layers 22m and 22c contain metals having lower oxidation energy than the metals of the conductive layers 21m and 21c of the pads PDm and PDc. Thus, it is possible to suppress the conduction between the pads PDm and PDc from being hindered by the oxide layers on the pad surfaces PDm and PDc.

[0202] According to the semiconductor memory device 1 of the embodiment, the metal contained in the conductive layers 22m and 22c is titanium, and the conductive layers 22m and 22c are barrier metal layers. By using Ti as the metal of the conductive layers 22m and 22c, the conductive layers 22m and 22c can function as barrier metal layers.

[0203] According to the semiconductor memory device 1 of the embodiment, a pillar PL having a channel layer CN penetrating the stacked body LM arranged in the insulating layer 50 along the stacking direction of the stacked body LM is provided, and the pillar PL is electrically connected to the pad PDm. A peripheral circuit CBA including a plurality of transistors TR arranged in the insulating layer 40 is provided, and the peripheral circuit CBA is electrically connected to the pad PDc.

[0204] In this way, by forming different elements on different substrates such as the supporting substrate SS and the semiconductor substrate SB and bonding them together, a semiconductor device having advanced and complex functions can be constructed in a space-saving manner.

[0205] In the above-mentioned embodiment, the pillar PL is connected to the source line SL at the side of the channel layer CN, but it is not limited to this. For example, the pillar may be formed by removing the storage layer at the bottom of the pillar and connecting to the source line at the lower end of the channel layer. In this case, the source line may be formed after the support substrate SS and the semiconductor substrate SB are bonded together.

[0206] More specifically, after the support substrate SS is bonded to the semiconductor substrate SB, when the support substrate SS is polished and removed, the polishing is continued until the lower end of the pillar PL is exposed, and the source line is formed in a manner covering the exposed lower end of the pillar PL. At this time, the source line of the metal layer may be formed instead of the polysilicon layer.

[0207] In the above-mentioned embodiment, the laminate LM has a 2-Tier structure including two laminates LMa and LMb. However, the number of tiers of the laminate may be 1 Tier, or may be 3 Tiers or more.

[0208] In the above embodiment, the step region SR is arranged at the end of the laminate LM in the X direction. However, the step region may be arranged at the center of the laminate as viewed in the stacking direction by digging out the center of the laminate in a step-like manner.

[0209] (Variant 1)

[0210] Next, use Fig.11 A semiconductor storage device according to a first variation of the embodiment will be described. In the semiconductor storage device according to the first variation, the formation steps of the pads PDma and the vias VAma are different from those of the above-described embodiment.

[0211] In the following drawings, the same reference numerals are given to the same structures as those in the above-described embodiment, and the description thereof may be omitted.

[0212] Fig.11 FIG. 1 is a diagram illustrating a part of the steps of a method for manufacturing a semiconductor memory device according to a first variation of the embodiment. More specifically, Fig.11 1 is a cross-sectional view of a portion where an insulating layer 50 is bonded to an insulating layer 40 in a semiconductor memory device in the process of being manufactured according to Modification 1. FIG.

[0213] Fig.11 The insulating layer 50n shown in (a) is formed by sequentially stacking the above-mentioned insulating layers 52, 53, 54, etc. to cover the laminated body LM and the pillar PL. In the insulating layer 50n, an unillustrated wiring is formed right below the via VAma connected to the pad PDma to be formed later, and has a thickness corresponding to the height of the via VAma to be formed later.

[0214] like Fig.11 As shown in (a) of FIG. 5 , etching or the like is performed from the outermost surface side of the insulating layer 50 n to form the via hole VH.

[0215] like Fig.11 As shown in (b), a conductive layer 22mv is formed to cover the side of the via hole VH. The conductive layer 22mv as the fifth metal layer is, for example, a Ti layer containing Ti, similar to the conductive layer 22m of the above-mentioned embodiment. In addition, the conductive layer 22mv is also formed on the upper surface of the insulating layer 50n.

[0216] like Fig.11 As shown in (c), the gap remaining in the via hole VH is filled with Cu material or the like to form a conductive layer 21mv as a fourth metal layer. The conductive layer 21mv is also formed on the upper surface of the insulating layer 50n via the conductive layer 22mv. These conductive layers 21mv and 22mv are removed in sequence by CMP or the like. Thus, a via hole VAma as a first via hole is formed.

[0217] like Fig.11 As shown in (d), an insulating layer such as a silicon oxide layer having a thickness corresponding to the height of a pad PDma to be formed later is stacked in a manner covering the via hole VAma to obtain an insulating layer 50. In addition, etching is performed from the outermost side of the insulating layer 50 to form a groove GR in the stacked portion of the insulating layer 50.

[0218] like Fig.11 As shown in (e), a conductive layer 22mp covering the side and bottom of the groove GR is formed. At this time, in addition to forming the conductive layer 22mp to cover the upper end of the via VAma, the conductive layer 22mp is also formed on the upper surface of the insulating layer 50. The conductive layer 22mp as the second metal layer is, for example, a Ti layer containing Ti, similar to the conductive layer 22m of the above-mentioned embodiment.

[0219] like Fig.11 As shown in (f), the gap remaining in the groove GR is filled with Cu material or the like to form a conductive layer 21mp as a first metal layer. The conductive layer 21mp is also formed on the upper surface of the insulating layer 50 via the conductive layer 22mp. These conductive layers 21mp and 22mp are removed in sequence by CMP or the like. Thus, a pad PDma as a first pad connected to a via VAma at the lower end is formed.

[0220] In addition, the method of forming the pad PDma and the via hole VAma in different steps is also called a single damascene method, etc. According to such a formation method, the conductive layer 22mp of the pad PDma is sandwiched between the pad PDma and the via hole VAma.

[0221] Thereafter, pad PDm is bonded to pad formed on insulating layer 40 as in the above embodiment. Also, pad on insulating layer 40 side may be formed by dual damascene as in the above embodiment, or may be formed by single damascene as in pad PDma of Modification 1.

[0222] According to the semiconductor memory device of Modification 1, the same effects as those of the semiconductor memory device 1 of the above-described embodiment are achieved.

[0223] (Variant 2)

[0224] Next, use Fig.12 A semiconductor storage device according to a second variation of the embodiment will be described. In the semiconductor storage device according to the second variation, the pads PDcb, PDmd, PDcd and the vias VAcb, VAmc, VAcc, VAmd, VAcd etc. have layers different from those of the pads PDm, PDc and the vias VAm, VAc in the above-described embodiment.

[0225] In the following drawings, the same reference numerals are given to the same structures as those in the above-described embodiment, and the description thereof may be omitted.

[0226] Fig.12 1 is a cross-sectional view of a bonding portion between insulating layers 40 and 50 of a semiconductor memory device according to Modification 2 of the embodiment.

[0227] exist Fig.12 In the example shown in (a), the pads PDm and vias VAm provided in the insulating layer 50 have the same structure as the above-mentioned embodiment. That is, these pads PDm and vias VAm are formed by dual damascene method, and have a conductive layer 22m containing metal such as Ti.

[0228] On the other hand, the pad PDcb and the via VAcb provided on the insulating layer 40 have a conductive layer 23c different from the conductive layer 22c of the above-mentioned embodiment as a barrier metal layer. More specifically, these pads PDcb and vias VAcb are formed by dual damascene method and have a conductive layer 23c containing a metal such as Ta as a third metal.

[0229] As described above, the conductive layer containing Ta or the like is often combined with a Cu material to be used as a barrier metal layer. On the other hand, Ta or the like is not highly diffusible into the Cu material and does not have the property of reducing the oxide layer formed on the surface of the pads PDm and PDcb, for example.

[0230] However, since at least one of the pads PDm and PDcb has the conductive layer 22m containing Ti or the like, the oxide layer formed on the surface of the pads PDm and PDcb can be eliminated.

[0231] exist Fig.12 In the example shown in (b), the pad PDma and the via VAmc provided on the insulating layer 50, and the pad PDcc and the via VAcc provided on the insulating layer 40 are respectively formed by a single damascene method. In addition, the pads PDma and PDcc both have conductive layers 21mp and 21cp including metals such as Cu and conductive layers 22mp and 22cp including metals such as Ti, similarly to the conductive layers 21m, 22m, 21c, and 22c of the above-mentioned embodiment.

[0232] On the other hand, vias VAmc and VAcc respectively provided in insulating layers 50 and 40 include conductive layers 21mv and 21cv including metal such as Cu, and conductive layers 23mv and 23cv including metal such as Ta instead of conductive layers 22m and 22c in the above-mentioned embodiment.

[0233] As described above, when the pad PDma and the via VAmc, or the pad PDcc and the via VAcc are formed by the single damascene method, a lining of a conductive layer including different metal materials can be formed on the pad PDmc, the pad PDcc and the vias VAmc and VAcc, respectively. In addition, at this time, as described above, as long as at least one of the pads PDma and PDcc has a conductive layer 22mp and 22cp including a metal such as Ti, the oxide layer on the surface of the pads PDma and PDcc can be eliminated.

[0234] Therefore, if Fig.12 As shown in the example of (b), for example, conductive layers 22mp and 22cc containing metal such as Ti can be formed as linings in pads PDma and PDcc, and conductive layers 23mv and 23cv containing no Ti such as Ta can be formed in vias VAma and VAcc.

[0235] In addition, at this time, the lining layer of the vias VAma and VAcc can be replaced with the conductive layer 23mv and 23cv that does not contain Ti, or based on this operation, at least one of the conductive layers 21mv and 21cv that will become the core material of the vias VAma and VAcc can be composed of other metals such as tungsten instead of Cu. In this way, the combination of the materials of the lining layer and the core material in the pad PDma and the via VAmc, or the pad PDcc and the via VAcc in the case of using the single damascene method can be changed in various ways.

[0236] The conductive layer 21cp is an example of a first metal layer, and the conductive layer 22cp is an example of a third metal layer. The conductive layer 21cv is an example of a sixth metal layer, and the conductive layer 23cv is an example of a seventh metal layer.

[0237] exist Fig.12 In the example shown in (c), the pad PDmd and the via VAmd provided in the insulating layer 50, and the pad PDcd and the via VAcd provided in the insulating layer 40 are respectively formed by the dual damascene method.

[0238] In addition, the pads PDmd and PDcd have conductive layers 24m and 24c containing metals different from Ti that are easily diffused into the conductive layers 21m and 21c of the Cu material of the pads PDmd and PDcd and have lower oxidation energy than the Cu material of the conductive layers 21m and 21c, inside the conductive layers 23m and 23c containing metals such as Ta. That is, the conductive layers 24m and 24c are sandwiched between the conductive layers 23m and 21m and between the conductive layers 23c and 21c in each of the pads PDmd and PDcd.

[0239] As metals that easily diffuse into the Cu material of the conductive layers 21m and 21c and have lower oxidation energy than the Cu material of the conductive layers 21m and 21c, in addition to Ti, Mn, Al, Mg, etc. can also be cited. Therefore, the conductive layers 24m and 24c as the second metal layer and the third metal layer can contain at least any one of the above-mentioned Mn, Al and Mg.

[0240] However, the above-mentioned Mn, Al and Mg do not function as barrier metal layers at least in their single substance form. Therefore, pads PDmd and PDcd respectively have conductive layers 23m and 23c containing Ti and the like that function as barrier metal layers in addition to conductive layers 24m and 24c.

[0241] As described above, as the lining of the pads and vias in the insulating layer 50, and the pads and vias in the insulating layer 40, in addition to the above Fig.12 In addition to the above-mentioned structures, conductive layers containing various metal materials may be used in various combinations.

[0242] According to the semiconductor memory device of the second modification, the same effects as those of the semiconductor memory device 1 of the above-described embodiment are achieved.

[0243] In the above-mentioned embodiment and modification examples 1 and 2, the semiconductor device is a semiconductor memory device 1 obtained by bonding elements including a memory cell MC and the like with elements such as a peripheral circuit CBA that controls the electrical operation of the memory cell MC. However, the semiconductor device to which the pads of the embodiment and modification examples 1 and 2 can be applied is not limited thereto, and may be an image sensor in which pixels and circuit elements are bonded, a semiconductor device in which memory elements and logic elements different from the above-mentioned semiconductor memory device 1 are bonded, and the like.

[0244] In the above-mentioned embodiment and modification examples 1 and 2, a Ti layer is used as a liner of the conductive layer 22m, 22c, etc. having the function of a barrier metal layer and a function of a reduction oxide layer. However, it is known that a Ti-Mn alloy also has barrier properties. Therefore, a Ti-Mn alloy can also be used as a liner having the function of a barrier metal layer and a function of a reduction oxide layer.

[0245] Thus, in the semiconductor device of the embodiment, as a conductive layer of a Cu material or the like covering the core material that becomes a pad, a conductive layer containing at least any one of Ti, Mn, Al and Mg in a simple or alloyed form and having or not having the function of a barrier metal layer can be appropriately used.

[0246] At this time, when a layer containing a metal that does not function as a barrier metal layer is used as a conductive layer covering a Cu material or the like that is a core material of a pad, a barrier metal layer may be separately provided on the outside of the conductive layer. The separately provided barrier metal layer may be as described above. Fig.12 As in the second modification shown in (c), it may be a single metal layer such as a Ta layer, or it may be a metal nitride layer such as a TaN layer or a TiN layer.

[0247] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: a first chip including a first insulating layer; and a second chip including a second insulating layer and attached to the first chip, The semiconductor device is characterized in that A bonding pad is provided on a bonding surface of the first chip and the second chip, the bonding pad having a first metal layer including a first metal, a second metal layer arranged between the first metal layer and the first insulating layer, and a third metal layer arranged between the first metal layer and the second insulating layer, One or both of the second metal layer and the third metal layer includes a second metal with lower oxidation energy than the first metal, The first metal layer further includes the second metal.

2. The semiconductor device according to claim 1, wherein: At least a portion of the second metal in the first metal layer is offset at a grain boundary of the first metal layer.

3. The semiconductor device according to claim 1, wherein: The first metal is copper, The second metal is one or more of titanium, manganese, aluminum and magnesium.

4. The semiconductor device according to claim 3, wherein: The second metal is contained at least in the second metal layer, The second metal is at least titanium, The second metal layer is a barrier metal layer.

5. The semiconductor device according to claim 3, wherein: The second metal is contained at least in the second metal layer, The pad has a barrier metal layer sandwiched between the second metal layer and the first insulating layer.

6. The semiconductor device according to claim 1, wherein: The semiconductor device comprises: A first via hole, which is a via hole arranged in the first insulating layer and connected to the pad, has a fourth metal layer and a fifth metal layer arranged between the fourth metal layer and the first insulating layer; as well as The second via hole is a via hole arranged in the second insulating layer and connected to the pad, and has a sixth metal layer and a seventh metal layer arranged between the sixth metal layer and the first insulating layer.

7. The semiconductor device according to claim 6, wherein: The second metal layer is also sandwiched between the pad and the first via.

8. The semiconductor device according to claim 1, wherein: The first insulating layer further comprises: A laminated body in which a plurality of conductive layers are stacked one by one and separated from each other; and a column having a semiconductor layer penetrating the stacked body along a stacking direction of the stacked body, The pillar is electrically connected to the pad.

9. The semiconductor device according to claim 8, wherein: The semiconductor device further includes a plurality of transistors arranged in the second insulating layer. The plurality of transistors are electrically connected to the pad.

10. A semiconductor device comprising: a first chip including a first insulating layer; and a second chip including a second insulating layer and attached to the first chip, The semiconductor device is characterized by comprising: A first pad disposed on a bonding surface of the first chip that is bonded to the second chip; and a second pad disposed on a bonding surface of the second chip bonded to the first chip, The first pad and the second pad have a first metal layer including a first metal, The first pad further includes a second metal layer disposed between the first metal layer and the first insulating layer. The second pad further includes a third metal layer disposed between the first metal layer and the second insulating layer. One or both of the second metal layer and the third metal layer includes a second metal with lower oxidation energy than the first metal, The first metal layer further includes the second metal.

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