Semiconductor device package and manufacturing method thereof

Abstract

The invention relates to a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, a first support structure disposed on the substrate, and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed over the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface, and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of June 19, 2019, application number "201910531324.0", and invention name "Semiconductor device packaging and manufacturing method thereof". Technical Field

[0003] The present invention generally relates to a semiconductor device package and a method of manufacturing the same. Background Art

[0004] A wireless communication device such as a mobile phone may include a semiconductor device package having an antenna for signal (e.g., radio frequency (RF) signal) transmission. As the operating frequency increases (e.g., equal to or greater than 5 GHz), signal attenuation or signal loss of the RF signal may become more severe. The antenna may be disposed adjacent to a dielectric layer and the characteristics of the dielectric layer may affect the performance of the antenna. Summary of the invention

[0005] An antenna structure and a manufacturing process thereof are provided. In the proposed antenna structure, at least two surfaces of the antenna structure are not covered by a protective layer or a dielectric layer. A support structure having a stepped structure on which the antenna structure is placed is provided.

[0006] In one or more embodiments, a semiconductor device package is provided. The semiconductor device package includes a substrate and a first support structure disposed on the substrate and having a first surface spaced apart from the substrate by a first distance. The semiconductor device package further includes a first antenna disposed above the first surface of the first support structure, the first antenna having a first surface, a second surface opposite to the first surface, and a third surface extending from the first surface to the second surface. The first surface and the second surface of the first antenna are exposed.

[0007] In one or more embodiments, a method for manufacturing a semiconductor device package is provided. The method includes: (a) providing a carrier; (b) forming an antenna pattern on the carrier; (c) forming a dielectric layer on the carrier to cover the antenna pattern; (d) removing a portion of the dielectric layer to expose a top surface of the antenna pattern; and (e) exposing a bottom surface of the antenna pattern.

[0008] In one or more embodiments, a method for manufacturing a semiconductor device package is provided. The method includes: (a) providing a substrate having an antenna and a feeding element disposed on a first surface of the substrate; (b) forming a first protection layer on the substrate to cover the antenna and the feeding element; (c) forming an opening on the first protection layer to expose a portion of the antenna and the feeding element; and (d) forming a conductive via in the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of the present invention are readily understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that various features may not be drawn to scale and that the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1A Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0011] Figure 1B Perspective views illustrating semiconductor device packages according to some embodiments of the present invention.

[0012] Figure 2A Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0013] Figure 2B Perspective views illustrating semiconductor device packages according to some embodiments of the present invention.

[0014] Figure 3A A cross-sectional view illustrating an antenna according to some embodiments of the present invention.

[0015] Figure 3B A cross-sectional view illustrating an antenna according to some embodiments of the present invention.

[0016] Figure 3C A cross-sectional view illustrating an antenna according to some embodiments of the present invention.

[0017] Figure 4A Illustrated are cross-sectional views of support structures according to some embodiments of the present invention.

[0018] Figure 4B Illustrated are cross-sectional views of support structures according to some embodiments of the present invention.

[0019] Figure 5A Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0020] Figure 5B Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0021] Figure 5C Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0022] Figure 5D Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0023] Figure 5E Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0024] Fig. 5F Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0025] Figure 5G Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0026] Figure 5H Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0027] Fig.5I Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0028] Fig. 6A A top view of a semiconductor device package according to some embodiments of the present invention is illustrated.

[0029] Figure 6B A top view of a semiconductor device package according to some embodiments of the present invention is illustrated.

[0030] Figure 6C A top view of a semiconductor device package according to some embodiments of the present invention is illustrated.

[0031] Fig.6D A top view of an antenna according to some embodiments of the present invention is illustrated.

[0032] Fig. 6E A top view of an antenna according to some embodiments of the present invention is illustrated.

[0033] Fig. 7A , 7B 7C, 7D, 7E, and 7F are cross-sectional views of antennas manufactured at various stages according to some embodiments of the present invention.

[0034] Fig. 8A , 8B 8C, 8D, 8E, and 8F are cross-sectional views of antennas manufactured at various stages according to some embodiments of the present invention.

[0035] Fig.9A , 9B , 9C, 9D, and 9E are cross-sectional views of antennas manufactured at various stages according to some embodiments of the present invention.

[0036] Fig. 10A , 10B , 10C, 10D, 10E, 10F, and 10G are cross-sectional views of semiconductor device packages or portions of semiconductor device packages at various stages of manufacture according to some embodiments of the present invention.

[0037] Fig.11A ,11B , 11C, 11D, 11E, 11F, 11G, 11H, 11I, 11J, and 11K are cross-sectional views of semiconductor device packages manufactured at various stages according to some embodiments of the present invention.

[0038] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. The present invention will become more apparent from the following detailed description made in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0039] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present invention, references to the formation of a first feature on or over a second feature in the following description may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0040] The following is a detailed discussion of embodiments of the present invention. However, it should be understood that the present invention provides many applicable concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present invention.

[0041] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the present invention is illustrated. The semiconductor device package includes a substrate 10, a support structure 11, an antenna 12, an electronic component 14, and electrical contacts 15.

[0042] The substrate 10 may be, for example, a printed circuit board, for example, a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The substrate 10 may include opposing surfaces (e.g., a top surface and a bottom surface). The substrate 10 may include an interconnect structure (e.g., an electrical connection), for example, a redistribution layer (RDL). The substrate 10 may include metal layers 10m1 and 10m2 on its top surface and bottom surface, respectively. In some embodiments, the metal layer 10m1 is a ground layer.

[0043] The support structure 11 is disposed on the top surface of the substrate 10. In some embodiments, the support structure 11 may be formed of or include an insulating material. In some embodiments, the support structure 11 is formed of or includes a photosensitive material, for example, a photoimageable dielectric (PID).

[0044] In some embodiments, the support structure 11 is formed of or includes a dielectric material. For example, the support structure 11 may include a molding compound, pre-impregnated composite fibers (e.g., prepreg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins including fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepreg materials / sheets.

[0045] refer to Figure 1A , the support structure 11 includes a step structure (or ladder structure) defined by surfaces 11s1 and 11s2. Surfaces 11s1 and 11s2 are connected to each other. Surface 11s1 is spaced apart from the top surface of substrate 10 by a certain distance. In some embodiments, the number of step structures can be changed depending on design needs. For example, there may be a number N of step structures, where N is an integer equal to or greater than 1.

[0046] The antenna 12 may be disposed on the stepped structure of the support structure 11. The antenna 12 is disposed on the surface 11s1 of the support structure 11. In some embodiments, the antenna 12 includes an antenna pattern 12a and an opening 12o. In some embodiments, the antenna 12 may be integrally formed without any opening. In some embodiments, the lateral surface of the antenna 12 is in contact with the surface 11s2 of the stepped structure. In some embodiments, the lateral surface of the antenna 12 may be separated from the surface 11s2 of the stepped structure by a gap (not shown). Figure 1A , the opening 12o penetrates from the top surface of the antenna 12 to the bottom surface of the antenna 12. The opening 12o may serve as a passage for electromagnetic waves to be emitted.

[0047] In some embodiments, the top and bottom surfaces of the antenna pattern 12a are exposed. In some embodiments, the top and bottom surfaces of the antenna pattern 12a are not covered. In some embodiments, the top and bottom surfaces of the antenna pattern 12a are exposed to air. In some embodiments, the top and bottom surfaces of the antenna pattern 12a are directly in contact with air. In some embodiments, the semiconductor device package is placed in a vacuum space or vacuum chamber and thus the top and bottom surfaces of the antenna pattern 12a are exposed to vacuum.

[0048] In some embodiments, antenna 12 is or includes a conductive material such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Al, Cu, or alloys thereof.

[0049] refer to Figure 1A, the antenna 12 can be electrically connected to the metal layer 10m1 through the connection structure 12f and the connection element 16. In some embodiments, the connection structure 12f can act as a feeding element to provide a signal to the antenna 12. In some embodiments, the connection structure 12f connects the antenna 12 to the ground by means of the metal layer 10m1. In some embodiments, the connection structure 12f may include but is not limited to a metal column, a bonding wire, or a stacked via. In some embodiments, the connection structure 12f includes Au, Ag, Al, Cu, or an alloy thereof. In some embodiments, the connection element 16 may include but is not limited to a solder ball or any other suitable electrical connection structure.

[0050] In some embodiments, metal layer 10m1 is electromagnetically coupled to antenna 12. In some embodiments, metal layer 10m1 is electrically connected to antenna 12. In some embodiments, metal layer 10m1 and antenna 12 are referred to as an antenna structure.

[0051] Dielectric materials may be used in the manufacturing process of semiconductor packaging devices. Currently available dielectric materials may have a loss tangent or dissipation factor (Df) greater than about 0.003 and a dielectric constant or dissipation constant (Dk) greater than 3. Air or a vacuum may have a Df of approximately "0". Air or a vacuum may have a Dk of approximately "1". The Dk and Df values ​​of a dielectric layer may affect the performance of an antenna placed adjacent to the dielectric layer.

[0052] Experiments can be performed on two antennas, one antenna having a surface exposed to air (or vacuum, with a Dk of approximately 1), and the other antenna having a surface covered by a dielectric material with a Dk of approximately 4. The experimental results show that the antenna having a surface exposed to air (or vacuum, with a Dk of approximately 1) has a peak gain that is 2.3 times the peak gain of the other antenna having a surface covered by a dielectric material with a Dk of approximately 4.

[0053] Experiments can be performed on two antennas, one antenna having a surface covered by a dielectric material having a Dk of approximately 2, and the other antenna having a surface covered by a dielectric material having a Dk of approximately 4. The experimental results show that under the condition that the thickness of the dielectric material covering the two antennas is the same, the antenna having a surface covered by a dielectric material having a Dk of approximately 2 has a peak gain that is 1.3 times the peak gain of the other antenna having a surface covered by a dielectric material having a Dk of approximately 4.

[0054] For example, if Figure 1A As shown in , according to some comparative embodiments of the present application, part of the antenna 12 may be exposed to air (or vacuum), and in this case the performance of the antenna 12 may be about 1.3 to about 2.3 times that of an antenna having a surface covered by a dielectric material.

[0055] Figure 1B Perspective views illustrating semiconductor device packages according to some embodiments of the present invention.

[0056] refer to Figure 1B , the support structure 11 is arranged to surround or partially surround the antenna 12 to support the antenna 12. Figure 1A It can be along the Figure 1B A cross-sectional view taken along the dashed line A-A' shown in FIG. Figure 1B In the embodiment shown in , the opening 12o comprises a substantially rectangular shape. However, it is contemplated that the opening 12o may comprise any other suitable shape. Figure 1B In the embodiment shown in FIG. 1 , antenna 12 includes one or more openings 12 o. In some embodiments, it is contemplated that antenna 12 may be integrally formed without any openings.

[0057] refer to Figure 1B , the support structure 11 is disposed at two opposite corners of the antenna 12. As long as the antenna 12 can be supported by the support structure 11, the support structure 11 can be disposed at different corners or edges of the antenna 12. For example, the support structure 11 can be disposed at three corners of the antenna 12. For example, the support structure 11 can be disposed at four corners of the antenna 12. For example, the support structure 11 can completely surround the antenna 12.

[0058] Figure 2A Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 2A The semiconductor device package shown in FIG. Figure 1A The semiconductor device package shown in FIG. 1 is different in that the antenna 12 further includes a protection layer 12 m.

[0059] refer to Figure 2A , the antenna 12 includes an antenna pattern 12a and a protective layer 12m. The protective layer 12m may be in direct contact with the antenna pattern 12a. The protective layer 12m surrounds the antenna pattern 12a. For example, a lateral surface 12s1 of the antenna pattern 12a may cover or contact the protective layer 12m. The antenna pattern 12a may be embedded in the protective layer 12m, wherein both surfaces of the antenna pattern 12a are not covered by the protective layer 12m.

[0060] The antenna 12 includes an opening 12o penetrating from the top surface of the protective layer 12m to the bottom surface of the protective layer 12m. The opening 12o may serve as a passage for electromagnetic waves to be transmitted.

[0061] The protective layer 12m may be an insulating layer to protect the antenna pattern 12a and prevent the antenna pattern from being short-circuited. In some embodiments, the protective layer 12m may be formed of a dielectric material or include a dielectric material. For example, the protective layer 12m may include a molding compound, a pre-impregnated composite fiber (e.g., a prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins including fillers dispersed therein. Examples of prepregs may include, but are not limited to, a multilayer structure formed by stacking or laminating a plurality of prepreg materials / sheets.

[0062] In some embodiments, the top and bottom surfaces of the antenna pattern 12a are exposed from the protective layer 12m. In some embodiments, the top and bottom surfaces of the antenna pattern 12a are not covered by the protective layer 12m.

[0063] In some embodiments, the top and bottom surfaces of the antenna pattern 12a are substantially coplanar with the top and bottom surfaces of the protective layer 12m, respectively. For example, the thickness of the antenna pattern 12a is substantially the same as the thickness of the protective layer 12m.

[0064] In some embodiments, the top surface of the antenna pattern 12a is recessed from the top surface of the protective layer 12m due to the manufacturing process of the antenna 12. In some embodiments, the bottom surface of the antenna pattern 12a is recessed from the bottom surface of the protective layer 12m due to the manufacturing process of the antenna 12. In some embodiments, the top surface of the antenna pattern 12a may extend beyond the top surface of the protective layer 12m. In some embodiments, the bottom surface of the antenna pattern 12a may extend beyond the bottom surface of the protective layer 12m.

[0065] In some embodiments, a metal surface treatment layer may be disposed on the top surface of the antenna pattern 12a (not shown). In some embodiments, the metal surface treatment layer disposed on the antenna pattern 12a is not coplanar with the top surface of the protective layer 12m. In some embodiments, the metal surface treatment layer disposed on the antenna pattern 12a extends beyond the top surface of the protective layer 12m. The metal surface treatment layer may include, but is not limited to, electroless nickel immersion gold (ENIG) or any other suitable material.

[0066] refer to Figure 2A , the lateral surface of the protection layer 12m contacts the surface 11s2 of the step structure. In some embodiments, the lateral surface of the protection layer 12m may be separated from the surface 11s2 of the step structure by a gap (not shown).

[0067] Figure 2B Perspective views illustrating semiconductor device packages according to some embodiments of the present invention.

[0068] refer to Figure 2B , the support structure 11 is arranged to surround or partially surround the antenna 12 to support the antenna 12. Figure 2A It can be along the Figure 2B A cross-sectional view taken along the dotted line BB' shown in FIG.

[0069] refer to Figure 2B , the support structure 11 is disposed at two opposite corners of the antenna 12. As long as the antenna 12 can be supported by the support structure 11, the support structure 11 can be disposed at different corners or edges of the antenna 12. For example, the support structure 11 can be disposed at three corners of the antenna 12. For example, the support structure 11 can be disposed at four corners of the antenna 12. For example, the support structure 11 can completely surround the antenna 12.

[0070] Figure 3A A cross-sectional view illustrating an antenna according to some embodiments of the present invention. Figure 3A The antenna includes a carrier 30, one or more antenna patterns 31 and a protective layer 32. The antenna further includes one or more connection structures 33 disposed on the antenna pattern 31.

[0071] The protection layer 32 surrounds the antenna pattern 31 . The protection layer 32 encapsulates the carrier 30 . The protection layer 32 encapsulates the antenna pattern 31 .

[0072] Figure 3A The antenna of the embodiment of the present invention comprises an opening 32o penetrating the carrier 30 and the protective layer 32. In some embodiments, the thickness of the antenna pattern 31 is substantially the same as the thickness of the protective layer. In some embodiments, the thickness of the antenna pattern 31 is different from the thickness of the protective layer. In some embodiments, the top surface of the antenna pattern 31 is recessed from the top surface of the protective layer. In some embodiments, the top surface of the antenna pattern 31 protrudes beyond the top surface of the protective layer.

[0073] Figure 3B A cross-sectional view illustrating an antenna according to some embodiments of the present invention. Figure 3B , the antenna includes one or more antenna patterns 31 and a protective layer 32. The antenna includes one or more connection structures 33 disposed on the antenna pattern 31. The antenna further includes a protruding structure 30t. The protruding structure 30t is disposed on the surface of the antenna pattern 31. The protruding structure 30t is in contact with the surface of the antenna pattern 31. The protruding structure 30t is mechanically attached to the antenna pattern 31. The protruding structure 30t is electrically connected to the antenna pattern 31.

[0074] The protruding structure 30t extends from the antenna pattern 31 into the protective layer 32. A gap exists between two adjacent protruding structures 30t. The bottom surface of the protruding structure 30t is substantially coplanar with the bottom surface of the protective layer 32. The protruding structure 30t can prevent the protective layer 32 from being peeled off from the antenna pattern 31.

[0075] Figure 3C A cross-sectional view illustrating an antenna according to some embodiments of the present invention. Figure 3C The antenna includes one or more antenna patterns 31 and a protective layer 32. The antenna includes one or more connection structures 33 disposed on the antenna pattern 31. The antenna further includes a protruding structure 30t. The protruding structure 30t is disposed between the top surface and the bottom surface of the antenna pattern 31. The protruding structure 30t is disposed in a direction parallel to the top surface of the antenna pattern 31.

[0076] The protruding structure 30t is mechanically attached to the antenna pattern 31. The protruding structure 30t is electrically connected to the antenna pattern 31. The protruding structure 30t extends from the antenna pattern 31 into the protective layer 32. The protruding structure 30t can prevent the protective layer 32 from being peeled off from the antenna pattern 31.

[0077] Figure 4A Illustrate a cross-sectional view of a support structure according to some embodiments of the present invention. Figure 4A , the support structure 11-1 can be formed as a whole. In some embodiments, the support structure 11-1 can be formed by, for example, photolithography technology. In some embodiments, the support structure 11-1 can be formed by, for example, three-dimensional printing technology.

[0078] refer to Figure 4A , the support structure 11-2 may be composed of several different components. For example, the support structure 11-2 may include support structures 11a, 11b, and 11c. The support structures 11a, 11b, and 11c are disposed on the substrate 10 and have different heights. The support structure 11a is disposed adjacent to the support structure 11b. The support structure 11b is disposed adjacent to the support structure 11c. The support structures 11a and 11b form a step structure. The support structures 11b and 11c form a step structure.

[0079] Figure 4B Illustrate a cross-sectional view of a support structure according to some embodiments of the present invention. Figure 4B , the support structure 11-3 can be formed by stacking the support structure 11d on the support structure 11e. The adhesive layer 21 is disposed between the substrate 10 and the support structure 11e. The adhesive layer 21 is disposed between the support structure 11d and the support structure 11e. In some embodiments, the adhesive layer 21 may include a gel type or a film type adhesive layer. The adhesive layer 21 may include a thermosetting resin. The adhesive layer 21 may include a thermoplastic resin. The adhesive layer 21 may include one or more of the following: resin, polyester resin, polyether resin, epoxy resin and / or polyolefin composition.

[0080] refer to Figure 4B, the support structure 11-4 may include multiple layers. In some embodiments, the support structure 11-4 includes a layer 11f, a layer 11g, and a layer 11h. The layer 11f includes a protective layer 22 disposed on the top surface of the layer 11f. The layer 11g includes a protective layer 22 disposed on the top surface of the layer 11g. The layer 11h includes a protective layer 22 disposed on the top surface of the layer 11h.

[0081] A protective layer 22 is disposed on each of layers 11f, 11g, and 11h for the purpose of forming a step structure of the support structure 11-4. In some embodiments, the protective layer 22 may be removed from layers 11f, 11g, and 11h after the support structure 11-4 is formed. A process for forming the support structure 11-4 will be described later in subsequent paragraphs.

[0082] Figure 5A Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 5A The semiconductor device package shown in FIG. Figure 2A The semiconductor device package shown in Figure 5A The semiconductor device package shown in FIG further includes an antenna 13. Figure 5A , the antenna 13 includes an antenna pattern 13a, a protective layer 13m and an opening 13o. The antenna 13 is disposed on a surface 11s3 of the support structure 11. The support structure 11 includes a surface 11s4 connected to the surface 11s3. The surfaces 11s3 and 11s4 form a step structure (or a ladder structure).

[0083] In some embodiments, the lateral surface of the protection layer 13m contacts the surface 11s4 of the step structure. In some embodiments, the lateral surface of the protection layer 13m may be spaced apart from the surface 11s4 of the step structure by a gap (not shown).

[0084] refer to Figure 5A , antenna 12 is disposed between antenna 13 and substrate 10. Antenna 12 includes antenna pattern 12a. In some embodiments, antenna pattern 12a is aligned with antenna pattern 13a in a direction perpendicular to the top surface of antenna 12. In some embodiments, antenna pattern 12a is electromagnetically coupled with antenna pattern 13a.

[0085] like Figure 5A As shown in , the signal can be coupled from the metal layer 10m1 to the antenna pattern 13a of the antenna 13 through the opening 12o of the antenna 12, and vice versa. The signal can be radiated upward from the antenna 12 through the opening 13o of the antenna 13. Because the signal can be transmitted between the metal layer 10m1 and the antenna 12 or 13 by coupling, no interconnection structure is required in the support structure 11. In other embodiments, depending on different design requirements, the support structure 11 may also include Figure 5BThe interconnect structure shown in .

[0086] Figure 5B Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 5B The semiconductor device package in Figure 5A The difference between the semiconductor device packaging in Figure 5B The semiconductor device package in the embodiment further includes an interconnection structure 11v. The interconnection structure 11v is disposed within the support structure 11. The interconnection structure 11v is encapsulated or covered by the support structure 11. The interconnection structure 11v provides electrical connection between the antenna package 13 and the substrate 10 and / or between the antenna package 12 and the substrate 10. In some embodiments, the interconnection structure 11v is a through-hole or a copper pillar. A signal can be transmitted from the metal plate 10m1 to the antenna package 13 through the interconnection structure 11v, and vice versa.

[0087] Figure 5C Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 5C The semiconductor device package in Figure 5B The difference between the semiconductor device packaging in Figure 5B The connecting structure 12f shown in FIG. 1 is replaced by the supporting structure 18. Figure 5C The support structure 18 includes a metal layer 18m and an interconnect structure 18v. The support structure 18 surrounds the metal layer 18m and the interconnect structure 18v. The support structure 18 encapsulates the metal layer 18m and the interconnect structure 18v. The metal layer 18m and the interconnect structure 18v are embedded in the support structure 18.

[0088] In the present invention, the metal layer 18m may be referred to as a feeding element. The antenna 12 is electrically connected to the metal layer 10m1 through the metal layer 18m, the interconnection structure 18v and the connecting element 16. In some embodiments, the interconnection structure 18v is a through hole or a copper pillar. The signal can be transmitted from the metal plate 10m1 to the antenna package 12 through the metal layer 18m, the interconnection structure 18v and the connecting element 16, and vice versa.

[0089] Figure 5D Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 5D The semiconductor device package in Figure 5C The difference between the semiconductor device packaging in Figure 5D The semiconductor device package in the embodiment further includes a connection structure 13f. The connection structure 13f is disposed between the antenna pattern 12a and the antenna pattern 13a. The connection structure 13f electrically connects the antenna 12 to the antenna 13.

[0090] In some embodiments, the connection structure 13f is electrically connected to the antenna 13 through the connection element 16. In some embodiments, the connection structure 13f may include but is not limited to metal pillars, bonding wires, or stacked vias. Signals can be transmitted from the antenna 12 to the antenna 13 through the connection structure 13f and the connection element 16, and vice versa.

[0091] Figure 5E Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 5E The semiconductor device package includes a substrate 10 and support structures 11 - 1 , 11 - 2 , and 11 - 3 disposed above the substrate 10 .

[0092] The semiconductor device package includes an antenna 12 disposed between support structures 11-1 and 11-2. The semiconductor device package includes an antenna 13 disposed between support structures 11-2 and 11-3. Antenna 12 is disposed on the step structure of support structure 11-1. Antenna 12 is disposed on the step structure of support structure 11-2. Antenna 13 is disposed on the step structure of support structure 11-2. Antenna 13 is disposed on the step structure of support structure 11-3.

[0093] The semiconductor device package further includes electronic components 14 and electrical contacts 15 .

[0094] Antenna 12 is spaced apart from the top surface of substrate 10 by a distance D1. Antenna 13 is spaced apart from the top surface of substrate 10 by a distance D2. Figure 5E , D2 is greater than D1.

[0095] Antenna 12 is electrically connected to metal layer 10m1 through support structure 18-1. Antenna 13 is electrically connected to metal layer 10m1 through support structure 18-2. Support structure 18-1 has a structure similar to Figure 5C The support structure 18 shown in Figure 5C The support structure 18-2 has a structure similar to that of the support structure 18 shown in FIG. Figure 5C The structure of the support structure 18 shown in FIG.

[0096] Fig. 5F Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Fig. 5F The semiconductor device package includes a substrate 10 and support structures 11 - 1 , 11 - 2 , 11 - 3 , and 11 - 4 disposed over the substrate 10 .

[0097] refer to Fig. 5F, the semiconductor device package includes an antenna 12 disposed between support structures 11-1 and 11-2. The semiconductor device package includes an antenna 13 disposed on support structures 11-1, 11-3, and 11-4. The antenna 12 is disposed on the step structure of the support structure 11-1. The antenna 12 is disposed on the step structure of the support structure 11-2. The antenna 13 is disposed on the step structure of the support structure 11-1. The antenna 13 is disposed on the top surface of the support structure 11-3. The antenna 13 is disposed on the step structure of the support structure 11-4. The top surface of the support structure 11-3 contacts the protective layer 13m of the antenna 13.

[0098] In some embodiments, support structures 11-1, 11-2, 11-3, and 11-4 are formed of or include the same material. In some embodiments, support structures 11-1, 11-2, 11-3, and 11-4 are formed of or include different materials.

[0099] Antenna 12 is electrically connected to metal layer 10m1 through support structure 18-1. Antenna 13 is electrically connected to metal layer 10m1 through support structure 18-2. Support structure 18-1 has a structure similar to Figure 5C The support structure 18 shown in Figure 5C The support structure 18-2 has a structure similar to that of the support structure 18 shown in FIG. Figure 5C The structure of the support structure 18 shown in FIG.

[0100] Figure 5G Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 5G The semiconductor device package in Fig. 5F The difference between the semiconductor device packaging in Fig. 5F The supporting structure 11-3 is replaced by the shielding structure 11-5.

[0101] In some embodiments, shielding structure 11-5 is a conductive component and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel, or a mixture, alloy, or other combination thereof. Shielding structure 11-5 may prevent electromagnetic signals emitted by antenna 12 from adversely affecting antenna 13, and vice versa.

[0102] Figure 5H Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated. Figure 5H The semiconductor device package in Fig. 5F The semiconductor device package in FIG. 1 is different in that the antenna 13 includes an opening 13o penetrating from the top surface of the antenna 13 to the bottom surface of the antenna 13. Figure 5H, the antenna pattern 13a of the antenna 13 includes surfaces 13s1, 13s2, and 13s3. In some embodiments, the surfaces 13s1, 13s2, and 13s3 are not covered by the protective layer 13m. In some embodiments, the surfaces 13s1, 13s2, and 13s3 are exposed to air. In some embodiments, the surfaces 13s1, 13s2, and 13s3 are exposed to vacuum.

[0103] exist Figure 5H In the embodiment shown in , the antenna pattern 13a is not aligned with the antenna pattern 12a. In some embodiments, it is contemplated that the antenna pattern 13a may be aligned with the antenna pattern 12a in a direction parallel to the surface 13s1. In some embodiments, the antenna pattern 13a may be aligned with the antenna pattern 12a in a direction perpendicular to the surface 13s2. In the case where the antenna pattern 13a is not aligned with the antenna pattern 12a, a signal may be transmitted between the antenna 13 and the metal layer 10m1 through coupling. In the case where the antenna pattern 13a is aligned with the antenna pattern 12a, a signal may be transmitted between the antenna 13 and the antenna pattern 12a through coupling.

[0104] Fig.5I Cross-sectional views of semiconductor device packages according to some embodiments of the present invention are illustrated.

[0105] refer to Fig.5I , the semiconductor device package includes a substrate 10, one or more support structures 11, an antenna 12, an antenna 13, and an electronic component 14. A metal layer 10m1 may be disposed on the substrate 10. The metal layer 10m1 may include several patterns. Some of the patterns of the metal layer 10m1 may serve as a conductive pad. Some of the patterns of the metal layer 10m1 may serve as a feeding element for transmitting a signal to / receiving a signal from the antenna 12. Some of the patterns of the metal layer 10m1 may serve as a feeding element for transmitting a signal to / receiving a signal from the antenna 13.

[0106] The semiconductor device package may include a solder resist layer 10r disposed on the top surface of the substrate 10. The solder resist layer 10r may cover the sidewalls of the metal layer 10m1. The solder resist layer 10r may cover at least a portion of the top surface of the metal layer 10m1. The solder resist layer 10r may cover the entire top surface of the metal layer 10m1. The solder resist layer 10r may expose a portion of the top surface of the metal layer 10m1. The solder resist layer 10r may form an opening on the top surface of the metal layer 10m1.

[0107] The antenna 12 includes one or more antenna patterns 12a. The antenna 12 includes a protective layer 12m surrounding the one or more antenna patterns 12a. The antenna 12 includes a protective layer 12m covering the one or more antenna patterns 12a. The antenna 13 includes one or more antenna patterns 13a. The antenna 13 includes a protective layer 13m surrounding the one or more antenna patterns 13a. The antenna 13 includes a protective layer 13m covering the one or more antenna patterns 13a.

[0108] The antenna 12 may include a solder resist layer 12r disposed on the surface of the protective layer 12m. In some embodiments, the solder resist layer 12r may have a thickness of about 15 microns. In some embodiments, the solder resist layer 12r may include an edge aligned with an edge of the protective layer 12m. In some embodiments, the solder resist layer 12r may include two edges aligned with two edges of the protective layer 12m. In some embodiments, the solder resist layer 12r may include an edge that is not aligned with an edge of the protective layer 12m.

[0109] The solder resist layer 12r may expose a portion of the surface of the antenna pattern 12a. The solder resist layer 12r may expose the surface of the antenna pattern 12a. The solder resist layer 12r may form an opening on the surface of the antenna pattern 12a.

[0110] In some embodiments, the solder resist layer 12r may extend beyond the edge of the protective layer 12m and cover at least a portion of the antenna pattern 12a. In some embodiments, both surfaces of the antenna pattern 12a may include the protective layer 12m. When disposed on a portion of the surface of the antenna pattern 12a, the solder resist layer 12r may prevent oxidation (e.g., becoming rusty or corroded) on a portion of the antenna pattern 12a.

[0111] The antenna 13 may include a solder resist layer 13r disposed on the surface of the protective layer 13m. In some embodiments, the solder resist layer 13r may have a thickness of about 15 microns. In some embodiments, the solder resist layer 13r may include an edge aligned with an edge of the protective layer 13m. In some embodiments, the solder resist layer 13r may include two edges aligned with two edges of the protective layer 13m. In some embodiments, the solder resist layer 13r may include an edge that is not aligned with an edge of the protective layer 13m.

[0112] In some embodiments, the solder resist layer 13r may extend beyond the edge of the protective layer 13m and cover at least a portion of the antenna pattern 13a. In some embodiments, the solder resist layer 13r may extend beyond the edge of the protective layer 13m and completely cover the surface of the antenna pattern 13a. In some embodiments, both surfaces of the antenna pattern 13a may include the protective layer 13m. When disposed on a portion of the surface of the antenna pattern 13a, the solder resist layer 13r may prevent oxidation (e.g., becoming rusty or corroded) on a portion of the antenna pattern 13a.

[0113] The solder resist layer 13r may expose a portion of the surface of the antenna pattern 13a. The solder resist layer 13r may expose the surface of the antenna pattern 13a. The solder resist layer 13r may form an opening on the surface of the antenna pattern 13a.

[0114] refer to Fig.5I , the antenna 12 can be supported by two support structures 11. The antenna 12 can be placed on the surface 11s1 of the support structure 11. The antenna 12 can be spaced apart from the substrate 10 by the support structure 11. In some embodiments, the support structure 11 may include but is not limited to solder balls or any other suitable electrical connection structure. In some embodiments, the antenna 12 can be electrically connected to the metal layer 10m1 through the support structure 11. In some embodiments, the support structure 11 can be in direct contact with one or more of the antenna patterns 12a. In some embodiments, the support structure 11 can be in direct contact with the metal layer 10m1. In some embodiments, the antenna 12 can be mechanically attached to the metal layer 10m1 through the support structure 11.

[0115] In some embodiments, the support structure 11 may be placed in an opening defined by the solder resist layer 10r. In some embodiments, the support structure 11 may be placed in an opening defined by the solder resist layer 12r. In some embodiments, the support structure 11 may be placed in an opening defined by the solder resist layer 13r. The support structure 11 may be limited by the opening defined by the solder resist layer 10r. The support structure 11 may be limited by the opening defined by the solder resist layer 12r. The support structure 11 may be limited by the opening defined by the solder resist layer 13r.

[0116] The openings defined by the solder resist layer 10r can provide better positioning for the support structure 11. The openings defined by the solder resist layer 12r can provide better positioning for the support structure 11. The openings defined by the solder resist layer 13r can provide better positioning for the support structure 11. The openings defined by the solder resist layer 10r can prevent undesirable leakage of the support structure 11 during the reflow process. The openings defined by the solder resist layer 12r can prevent undesirable leakage of the support structure 11 during the reflow process. The openings defined by the solder resist layer 13r can prevent undesirable leakage of the support structure 11 during the reflow process.

[0117] Antenna 13 may be supported by one or more support structures 11. Antenna 13 may be disposed on a surface 11s2 of support structure 11. In some embodiments, antenna 13 may be supported by a support structure 11 disposed between substrate 10 and antenna 13. In some embodiments, antenna 13 may be supported by a support structure 11 disposed between antenna 12 and antenna 13.

[0118] In some embodiments, antenna 13 may be electrically connected to metal layer 10m1 through support structure 11. In some embodiments, support structure 11 may be in direct contact with one or more of antenna pattern 13a and metal layer 10m1. In some embodiments, antenna 13 may be mechanically attached to metal layer 10m1 through support structure 11.

[0119] In some embodiments, antenna 13 may be electrically connected to antenna 12 through support structure 11. In some embodiments, support structure 11 may be in direct contact with one or more of antenna patterns 12a and one or more of antenna patterns 13a. In some embodiments, antenna 13 may be mechanically attached to antenna 12 through support structure 11.

[0120] The antenna pattern 12a may be aligned with the antenna pattern 13a by the one or more supporting structures 11. The antenna pattern 12a and the antenna pattern 13a may be aligned in a direction perpendicular to the top surface of the substrate 10 by the one or more supporting structures 11.

[0121] Fig. 6A A top view of a semiconductor device package according to some embodiments of the present invention is illustrated. For simplicity, only a substrate 10 and a support structure 11 are depicted and other components are omitted. Fig. 6A , the support structure 11 completely surrounds the edge of the substrate 10. Fig. 6A , the surface 11s3 and the surface 11s1 are not coplanar. Figure 1A and 2A The illustrated antenna 11 can be arranged on a surface 11 s 1 of a support structure 11 .

[0122] Figure 6B A top view of a semiconductor device package according to some embodiments of the present invention is illustrated. For simplicity, only a substrate 10 and a support structure 11 are depicted and other components are omitted. Figure 6B , support structures 11-1, 11-2, 11-3, and 11-4 are arranged around the four corners of substrate 10. In some embodiments, support structure 11-1 and support structure 11-2 are separated by a gap 11G. In some embodiments, support structure 11-1 and support structure 11-3 are separated by a gap 11G. In some embodiments, support structure 11-2 and support structure 11-4 are separated by a gap 11G. In some embodiments, support structure 11-3 and support structure 11-4 are separated by a gap 11G.

[0123] Figure 6C A top view of a semiconductor device package according to some embodiments of the present invention is illustrated. For simplicity, only a substrate 10 and a support structure 11 are depicted while other components are omitted. Figure 6CThe semiconductor device package includes a support structure 11-5 and a support structure 11-6. The support structure 11-5 includes a top surface 11s1. The support structure 11-6 includes a surface 11s1 and a surface 11s3. The surface 11s1 of the support structure 11-5 is at the same level as the surface 11s1 of the support structure 11-6. The surface 11s3 of the support structure 11-6 is at a level higher than the surface 11s1 of the support structure 11-6. The surface 11s3 of the support structure 11-6 is spaced apart from the top surface of the substrate 10 by a first distance and the surface 11s1 of the support structure 11-6 is spaced apart from the top surface of the substrate 10 by a second distance. The first distance is greater than the second distance.

[0124] In some embodiments, antenna 12 is disposed on surface 11s1 of support structure 11-5. In some embodiments, antenna 12 is disposed on surface 11s1 of support structure 11-6. In some embodiments, antenna 12 is disposed on surfaces 11s1 of support structures 11-5 and 11-6.

[0125] Fig.6D A top view of an antenna according to some embodiments of the present invention is illustrated.

[0126] In some embodiments, Fig.6D Can be similar to Figure 5H 13 is a top view of the antenna shown in FIG. 13. In some embodiments, Fig.6D Can be different from Figure 5H 13 is a top view of the antenna shown in FIG. 13. In some embodiments, Fig.6D It can be Figure 5H 1 is a top view of the antenna 13 shown in FIG.

[0127] refer to Fig.6D , the antenna 13 may include one or more antenna patterns 13a. The antenna 13 includes a protective layer 13m. The antenna 13 may include one or more openings 13o. The protective layer 13m covers at least a portion of the antenna pattern 13a. The protective layer 13m surrounds at least a portion of the antenna pattern 13a. The protective layer 13m exposes at least a portion of the antenna pattern 13a.

[0128] refer to Fig.6D , the antenna pattern 13a may include one or more surfaces that are not covered by the protective layer 13m. The antenna pattern 13a may include one or more surfaces exposed through the protective layer 13m. The antenna pattern 13a may include one or more surfaces exposed to air. The antenna pattern 13a may include one or more surfaces exposed to vacuum.

[0129] In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c that are not covered by the protective layer 13m. In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c exposed by the protective layer 13m. In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c exposed to air. In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c exposed to vacuum.

[0130] Fig. 6E A top view of an antenna according to some embodiments of the present invention is illustrated.

[0131] In some embodiments, Fig. 6E Can be similar to Figure 5H 13 is a top view of the antenna shown in FIG. 13. In some embodiments, Fig. 6E Can be different from Figure 5H 13 is a top view of the antenna shown in FIG. 13. In some embodiments, Fig. 6E It can be Figure 5H 1 is a top view of the antenna 13 shown in FIG.

[0132] refer to Fig. 6E The antenna 13 may include one or more antenna patterns 13a. The antenna 13 may include a protective layer 13m. The antenna 13 may include a patterned conductive layer 13c.

[0133] The protective layer 13m covers at least a portion of the antenna pattern 13a. The protective layer 13m surrounds at least a portion of the antenna pattern 13a. The protective layer 13m exposes at least a portion of the antenna pattern 13a.

[0134] refer to Fig. 6E , the antenna pattern 13a may include one or more surfaces that are not covered by the protective layer 13m. The antenna pattern 13a may include one or more surfaces exposed through the protective layer 13m. The antenna pattern 13a may include one or more surfaces exposed to air. The antenna pattern 13a may include one or more surfaces exposed to vacuum.

[0135] In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c that are not covered by the protective layer 13m. In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c exposed by the protective layer 13m. In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c exposed to air. In some embodiments, the antenna pattern 13a includes surfaces 13s1_a, 13s1_b, and 13s1_c exposed to vacuum.

[0136] refer to Fig. 6E , the patterned conductive layer 13c may include a diamond-shaped pattern, as shown in the dashed circle C. In some embodiments, the patterned conductive layer 13c may include a pattern of any other suitable shape. Some of the patterns of the patterned conductive layer 13c may serve as a conductive pad. Some of the patterns of the patterned conductive layer 13c may serve as a feeding element for transmitting a signal to / receiving a signal from the antenna 13.

[0137] refer to Fig. 6E , the patterned conductive layer 13c may surround the four edges of the antenna 13. The patterned conductive layer 13c may include a portion 13c_1 passing through the antenna 13 from top to bottom. The patterned conductive layer 13c may include a portion 13c_2 passing through the antenna 13 from left to right.

[0138] In some embodiments, the diamond pattern of the patterned conductive layer 13c can prevent bending during the manufacturing process of the antenna 13. In some embodiments, the patterned conductive layer 13c can prevent bending during the manufacturing process of the antenna 13 by surrounding the four edges of the antenna 13. In some embodiments, the portion 13c_1 of the patterned conductive layer 13c can prevent bending during the manufacturing process of the antenna 13. In some embodiments, the portion 13c_2 of the patterned conductive layer 13c can prevent bending during the manufacturing process of the antenna 13.

[0139] Fig. 7A , 7B 7C, 7D, 7E and 7F are cross-sectional views of antennas manufactured at various stages according to some embodiments of the present invention. The figures have been simplified to better understand various aspects of the present invention. In some embodiments, Fig. 7A , 7B , 7C, 7D, 7E and 7F are operations for making Figure 2A , 3A or Figure 5A Alternatively, in Fig. 7A , 7B The operations shown in 7C, 7D, 7E and 7F are methods for manufacturing other antennas.

[0140] refer to Fig. 7A , providing a carrier 30. The carrier 30 may be a metal plate, for example, a copper plate. The antenna pattern 31 is formed on the carrier 30. In some embodiments, the antenna pattern 31 is formed by, for example, sputtering, coating, electroplating, or any other suitable operation.

[0141] refer to Figure 7B, a protection layer 32 is formed on the carrier 30 to cover or encapsulate the antenna pattern 31. The protection layer 32 completely covers or encapsulates the antenna pattern 31. For example, the protection layer 32 is formed on the outer surface of the antenna pattern 31 and within the gap defined by the antenna pattern 31.

[0142] The protective layer 32 is an insulating layer formed of a dielectric material or including a dielectric material. For example, the protective layer 32 may include a molding compound, a pre-impregnated composite fiber (e.g., a prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins including fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepreg materials / sheets. In some embodiments, the protective layer 32 may be formed by molding, laminating, screening, or any other suitable technique.

[0143] refer to Figure 7C , a portion of the protective layer 32 is removed to expose the top surface of the antenna pattern 31. In some embodiments, the top surface of the antenna pattern 31 is substantially coplanar with the top surface of the protective layer 32. In some embodiments, the top surface of the antenna pattern 31 is recessed from the top surface of the protective layer 32. In some embodiments, the top surface of the antenna pattern 31 protrudes beyond the top surface of the protective layer 32.

[0144] In some embodiments, portions of protective layer 32 are removed by, for example, etching, grinding, laser, or any other suitable operation. In other embodiments, carrier 30 may be Figure 7C The operation described in was then removed.

[0145] refer to Fig.7D , a portion of the antenna pattern 31 and a portion of the carrier 30 are removed to form an opening 32o. The opening 32o penetrates the protective layer 32 and the carrier 30. The opening 32o penetrates from the top surface of the protective layer 32 to the bottom surface of the carrier 30. The opening 32o is formed by, for example, etching, grinding, laser or any other suitable operation.

[0146] refer to Fig. 7E One or more connection structures 33 are formed on the antenna pattern 31 by, for example, electroplating, wire bonding, or any other suitable operation. The connection structure 33 may include, but is not limited to, a Cu pillar, a bonding wire, or any other suitable connection element.

[0147] refer to Figure 7F, the carrier 30 is removed from the antenna pattern 31 and the protective layer 32 to expose the bottom surface of the antenna pattern 31. In some embodiments, the carrier 30 may be completely removed. In some embodiments, a portion of the carrier 30 remains on the bottom surface of the protective layer 32. In some embodiments, a portion of the carrier 30 remains on the bottom surface of the antenna pattern 31. In some embodiments, the pattern 30p remains on the bottom surface of the protective layer 32. The pattern 30p can be used for, but is not limited to, signal transmission electromagnetic wave transmission or electrical transmission.

[0148] Fig. 8A , 8B 8C, 8D, 8E and 8F are cross-sectional views of antennas manufactured at various stages according to some embodiments of the present invention. The figures have been simplified to better understand various aspects of the present invention. In some embodiments, Fig. 8A , 8B , 8C, 8D, 8E and 8F are operations for making Figure 2A , 3A or Figure 5A Alternatively, in Fig. 8A , 8B The operations shown in 8C, 8D, 8E and 8F are methods for manufacturing other antennas.

[0149] refer to Fig. 8A , a carrier 30 is provided. The carrier 30 may be a metal plate, for example, a copper plate. A patterned conductive layer 30t is formed on the carrier. A portion of the antenna pattern 31 is formed on the patterned conductive layer 30t. A portion of the antenna pattern 31 is formed on the carrier 30. The patterned conductive layer 30t is also referred to as a protruding structure 30t in the previous paragraph.

[0150] In some embodiments, the patterned conductive layer 30t is formed by, for example, sputtering, coating, electroplating, or any other suitable operation. In some embodiments, the antenna pattern 31 is formed by, for example, sputtering, coating, electroplating, or any other suitable operation.

[0151] The protruding structure 30t is mechanically attached to the antenna pattern 31. The protruding structure 30t is electrically connected to the antenna pattern 31. In some embodiments, the thickness of the antenna pattern 31 is greater than the thickness of the patterned conductive layer 30t. In some embodiments, the thickness of the antenna pattern 31 is substantially the same as the thickness of the patterned conductive layer 30t. In some embodiments, the thickness of the antenna pattern 31 is less than the thickness of the patterned conductive layer 30t.

[0152] refer to Figure 8B, a protective layer 32 is formed on the carrier 30 to cover or encapsulate the antenna pattern 31 and the patterned conductive layer 30t. The protective layer 32 completely covers or encapsulates the antenna pattern 31. The protective layer 32 completely covers or encapsulates the patterned conductive layer 30t. For example, the protective layer 32 is formed on the outer surface of the antenna pattern 31 and within the gap defined by the antenna pattern 31. The protective layer 32 is formed on the outer surface of the patterned conductive layer 30t and within the gap defined by the patterned conductive layer 30t.

[0153] The protective layer 32 is an insulating layer formed of a dielectric material or including a dielectric material. For example, the protective layer 32 may include a molding compound, a pre-impregnated composite fiber (e.g., a prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins including fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepreg materials / sheets. In some embodiments, the protective layer 32 may be formed by molding, laminating, screening, or any other suitable technique.

[0154] refer to Figure 8C , a portion of the protective layer 32 is removed to expose the top surface of the antenna pattern 31. In some embodiments, the top surface of the antenna pattern 31 is substantially coplanar with the top surface of the protective layer 32. In some embodiments, the top surface of the antenna pattern 31 is recessed from the top surface of the protective layer 32. In some embodiments, the top surface of the antenna pattern 31 protrudes beyond the top surface of the protective layer 32.

[0155] In some embodiments, portions of protective layer 32 are removed by, for example, etching, grinding, laser, or any other suitable operation. In other embodiments, carrier 30 may be Figure 8C The operation described in was then removed.

[0156] refer to Fig.8D , a portion of the antenna pattern 31 and a portion of the carrier 30 are removed to form an opening 32o. The opening 32o penetrates the protective layer 32 and the carrier 30. The opening 32o penetrates from the top surface of the protective layer 32 to the bottom surface of the carrier 30. The opening 32o is formed by, for example, etching, grinding, laser or any other suitable operation.

[0157] refer to Fig. 8E One or more connection structures 33 are formed on the antenna pattern 31 by, for example, electroplating, wire bonding, or any other suitable operation. The connection structure 33 may include, but is not limited to, a Cu pillar, a bonding wire, or any other suitable connection element.

[0158] refer to Figure 8F, the carrier 30 is removed from the antenna pattern 31 and the protective layer 32 to expose the bottom surface of the pattern conductive layer 30t. In some embodiments, the carrier 30 can be completely removed. In some embodiments, a portion of the carrier 30 remains on the bottom surface of the protective layer 32 (not shown). In some embodiments, a portion of the carrier 30 remains on the bottom surface of the pattern conductive layer 30t (not shown).

[0159] Fig.9A , 9B 9C, 9D and 9E are cross-sectional views of antennas manufactured at various stages according to some embodiments of the present invention. The figures have been simplified to better understand various aspects of the present invention. In some embodiments, Fig.9A , 9B , 9C, 9D and 9E are operations for making Figure 2A , 3A or Figure 3C Alternatively, in Fig.9A , 9B The operations shown in 9C, 9D and 9E are methods for manufacturing other antennas.

[0160] refer to Fig.9A , a carrier 30 is provided. The carrier 30 may be a metal plate, for example, a copper plate. The antenna pattern 31a is formed on the carrier 30. In some embodiments, the antenna pattern 31a is formed by, for example, sputtering, coating, electroplating, or any other suitable operation.

[0161] refer to Fig. 9B , a protective layer 32 is formed on the carrier 30 to cover or encapsulate the antenna pattern 31a and the patterned conductive layer 30t. The protective layer 32 completely covers or encapsulates the antenna pattern 31a. For example, the protective layer 32 is formed on the outer surface of the antenna pattern 31a and within the gap defined by the antenna pattern 31a.

[0162] refer to Fig. 9B , a patterned conductive layer 30t is formed on the antenna pattern 31a. A portion of the antenna pattern 31a is covered by the patterned conductive layer 30t. A portion of the antenna pattern 31a is exposed through the patterned conductive layer 30t. The patterned conductive layer 30t is also referred to as a protruding structure 30t in the previous paragraph.

[0163] refer to Fig. 9C , the antenna pattern 31b is formed on the antenna pattern 31a. In some embodiments, the antenna pattern 31b is aligned with the antenna pattern 31a in a direction parallel to the top surface of the carrier 30. In some embodiments, the antenna pattern 31b may be shifted relative to the antenna pattern 31a by a distance in a direction parallel to the top surface of the carrier 30.

[0164] refer to Fig. 9C , the protective layer 32 is formed to cover or encapsulate the antenna pattern 31b and the patterned conductive layer 30t. The protective layer 32 completely covers or encapsulates the lateral surface of the antenna pattern 31b. For example, the protective layer 32 is formed on the lateral surface of the antenna pattern 31b and within the gap defined by the antenna pattern 31b. The protective layer 32 exposes the top surface of the antenna pattern 31b.

[0165] refer to Fig. 9C , the patterned conductive layer 30t extends from the lateral surface of the antenna pattern 31b into the protective layer 32. The patterned conductive layer 30t is spaced apart from the bottom surface of the antenna pattern 31a by a distance d1. The patterned conductive layer 30t is spaced apart from the top surface of the antenna pattern 31b by a distance d2. In some embodiments, the distance d1 is substantially the same as the distance d2. In some embodiments, the distance d1 is less than the distance d2. In some embodiments, the distance d1 is greater than the distance d2.

[0166] The antenna pattern 31 a and the antenna pattern 31 b may be collectively referred to as an antenna pattern 31 .

[0167] refer to Fig.9D , a portion of the antenna pattern 31 and a portion of the carrier 30 are removed to form an opening 32o. The opening 32o penetrates the protective layer 32 and the carrier 30. The opening 32o penetrates from the top surface of the protective layer 32 to the bottom surface of the carrier 30. The opening 32o is formed by, for example, etching, grinding, laser or any other suitable operation.

[0168] refer to Fig.9D One or more connection structures 33 are formed on the antenna pattern 31 by, for example, electroplating, wire bonding, or any other suitable operation. The connection structure 33 may include, but is not limited to, a Cu pillar, a bonding wire, or any other suitable connection element.

[0169] refer to Fig.9E , the carrier 30 is removed from the antenna pattern 31 and the protective layer 32 to expose the bottom surface of the antenna pattern 31. In some embodiments, the carrier 30 may be completely removed. In some embodiments, a portion of the carrier 30 remains on the bottom surface of the protective layer 32 (not shown). In some embodiments, a portion of the carrier 30 remains on the bottom surface of the antenna pattern 31 (not shown).

[0170] Fig.11A , 11B , 11C, 11D, 11E, 11F, 11G, 11H, 11I, 11J and 11K are cross-sectional views of semiconductor device packages manufactured at various stages according to some embodiments of the present invention. The figures have been simplified for better understanding of various aspects of the present invention. In some embodiments, Fig.11A , 11B , 11C, 11D, 11E, 11F, 11G, 11H, 11I, 11J and 11K are operations for making Figure 4A or the method of packaging a semiconductor device as shown in 4B. Alternatively, in Fig.11A , 11B The operations shown in FIGS. 11A, 11C, 11D, 11E, 11F, 11G, 11H, 11I, 11J, and 11K are methods for manufacturing other semiconductor device packages.

[0171] refer to Fig.11A , a semiconductor device package is provided. The semiconductor device package includes a substrate 50 and a package body 52 disposed above or covering the substrate 50. In some embodiments, the substrate 50 is a single-layer substrate. In some embodiments, the substrate 50 is a multi-layer substrate.

[0172] Substrate 50 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. Substrate 50 may include interconnect structures, such as a redistribution layer (RDL) or a grounding element.

[0173] In some embodiments, package body 52 includes epoxy with filler, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material with silicone dispersed therein, or a combination thereof. Package body 52 may include interconnect structure 56, such as a redistribution layer (RDL) disposed within or above package body 52. ​​Package body 52 may include conductive element 54, such as a conductive via disposed within or above package body 52.

[0174] refer to Fig. 11B , a protective layer 58 is provided over the package body 52. ​​The protective layer 58 covers or encapsulates the package body 52. ​​The protective layer 58 covers or encapsulates the interconnect structure 56. In some embodiments, the protective layer 58 may include an insulating material. In some embodiments, the protective layer 58 may include a photosensitive material, such as a photoimageable dielectric (PID). In some embodiments, the protective layer 58 includes a dielectric material. For example, the protective layer 58 may include a molding compound, a pre-impregnated composite fiber (e.g., a prepreg), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins including fillers dispersed therein. Examples of prepregs may include, but are not limited to, a multilayer structure formed by stacking or laminating a plurality of prepreg materials / sheets.

[0175] refer to Fig. 11C , a metal layer 60 is provided over the protective layer 58. The metal layer 60 may include an interconnect structure 60v surrounded by the protective layer 58. The metal layer 60 may include an interconnect structure 60v embedded in the protective layer 58. The metal layer 60 may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel, or a mixture, alloy, or other combination thereof.

[0176] refer to Fig.11D , the opening 60o is formed on the metal layer 60. In some embodiments, the opening 60o can be formed by a process including the following operations: (i) forming a photoresist or a mask on the metal layer 60; (ii) defining a predetermined pattern on the photoresist or the mask by, for example, photolithography; (iii) plating or etching a conductive material to form the opening 60o; and (iv) removing the photoresist or the mask.

[0177] refer to Fig.11E , a protective layer 58' is provided over the metal layer 60. The protective layer 58' covers or encapsulates the metal layer 60. The protective layer 58 covers or encapsulates the interconnect structure 60v. In some embodiments, the protective layer 58' comprises a material similar to the material of the protective layer 58. In some embodiments, the protective layer 58' comprises a material that is the same as the material of the protective layer 58. In some embodiments, the protective layer 58' comprises a material that is different from the material of the protective layer 58.

[0178] refer to Fig.11F , a metal layer 60' is provided over the protective layer 58'. The metal layer 60' may include an interconnect structure 60v' surrounded by the protective layer 58'. The metal layer 60' may include an interconnect structure 60v' embedded in the protective layer 58'. In some embodiments, the metal layer 60' includes a material similar to the material of the metal layer 60. In some embodiments, the metal layer 60' includes a material that is the same as the material of the metal layer 60. In some embodiments, the metal layer 60' includes a material that is different from the material of the metal layer 60.

[0179] refer to Fig.11F , the opening 60o' is formed on the metal layer 60'. In some embodiments, the opening 60o' can be formed by a process including the following operations: (i) forming a photoresist or a mask on the metal layer 60'; (ii) defining a predetermined pattern on the photoresist or the mask by, for example, photolithography; (iii) plating or etching a conductive material to form the opening 60o'; and (iv) removing the photoresist or the mask.

[0180] refer to Fig.11G, a protective layer 58" is provided above the metal layer 60'. The protective layer 58" covers or encapsulates the metal layer 60'. The protective layer 58" covers or encapsulates the interconnect structure 60v'. In some embodiments, the protective layer 58" comprises a material similar to the material of the protective layer 58. In some embodiments, the protective layer 58" comprises the same material as the material of the protective layer 58. In some embodiments, the protective layer 58" comprises a material different from the material of the protective layer 58.

[0181] refer to Fig.11H , metal layer 60" is provided above protective layer 58". In some embodiments, metal layer 60" comprises a material similar to the material of metal layer 60. In some embodiments, metal layer 60" comprises a material the same as the material of metal layer 60. In some embodiments, metal layer 60" comprises a material different from the material of metal layer 60.

[0182] refer to Fig.11H , the opening 60o" is formed on the metal layer 60". In some embodiments, the opening 60o" can be formed by a process including the following operations: (i) forming a photoresist or a mask on the metal layer 60"; (ii) defining a predetermined pattern on the photoresist or the mask by, for example, photolithography technology; (iii) plating or etching a conductive material to form the opening 60o"; and (iv) removing the photoresist or the mask.

[0183] refer to Fig.11I , a portion of the protective layer 58" is removed. In some embodiments, a portion of the protective layer 58" that is not covered by the metal layer 60" is removed. In some embodiments, a portion of the protective layer 58" exposed by the opening 60o" is removed. The portion of the protective layer 58" can be removed using, for example, laser, grinding, etching, or any other suitable operation. After a portion of the protective layer 58" is removed, a stepped structure or ladder structure 62 is formed.

[0184] refer to Fig.11J , a portion of the protective layer 58' is removed. In some embodiments, a portion of the protective layer 58' that is not covered by the metal layer 60' is removed. In some embodiments, a portion of the protective layer 58' exposed by the opening 60o' is removed. The portion of the protective layer 58' can be removed using, for example, laser, grinding, etching, or any other suitable operation. After a portion of the protective layer 58' is removed, a stepped structure or ladder structure 64 is formed.

[0185] refer to Figure 11K, a portion of the protective layer 58 is removed. In some embodiments, a portion of the protective layer 58 that is not covered by the metal layer 60 is removed. In some embodiments, a portion of the protective layer 58 exposed by the opening 60o is removed. The portion of the protective layer 58 may be removed using, for example, laser, grinding, etching, or any other suitable operation. After a portion of the protective layer 58 is removed, a step structure or ladder structure 66 is formed.

[0186] Fig. 10A , 10B , 10C, 10D, 10E, 10F, and 10G are cross-sectional views of semiconductor device packages or portions of semiconductor device packages at various stages of manufacture according to some embodiments of the present invention. The figures have been simplified for better understanding of various aspects of the present invention. In some embodiments, Fig. 10A , 10B , 10C, 10D, 10E, 10F and 10G are operations for making Figure 1A or Figure 2A Alternatively, in the method of packaging a semiconductor device as shown in Fig. 10A , 10B The operations shown in 10C, 10D, 10E, 10F and 10G are methods for manufacturing other semiconductor device packages.

[0187] refer to Fig. 10A , providing a substrate 40. The substrate 40 may include an interconnect structure (RDL) 40r covered or encapsulated by a dielectric layer. The substrate 40 may include a conductive layer 40m1 and a conductive pad 40m2 on the top surface of the substrate 40. In some embodiments, the conductive layer 40m1 is grounded. In some embodiments, the conductive layer 40m1 is an antenna. In some embodiments, the conductive layer 40m1 is part of an antenna structure. In some embodiments, the conductive pad 40m2 acts as a feeding element for providing a signal to the antenna structure. In some embodiments, the conductive pad 40m2 acts as a feeding element for receiving a signal from the antenna structure.

[0188] refer to Fig. 10B , an insulating layer 41 is formed on the top surface of the substrate 40 to cover the conductive layer 40m1, the conductive pad 40m2 and the top surface of the substrate 40. In some embodiments, the insulating layer 41 is formed of or includes PID, polyimide (PI) or solder resist. In some embodiments, the insulating layer 41 can be formed by, for example, lamination or other suitable operations.

[0189] refer to Fig. 10C, a portion of the insulating layer 41 is removed to form one or more openings (or chambers) 41h1 and 41h2 to expose the conductive layer 40m1 and the conductive pad 40m2. In some embodiments, the insulating layer 41 is removed by, for example, etching or other suitable operations.

[0190] refer to Fig. 10D , the conductive material is filled in the opening 41h2 to form a conductive via 41v1. In some embodiments, the conductive via 41v1 is formed by plating or other suitable operations. The conductive via 41v1 contacts the conductive pad 40m2 on the top surface of the substrate 40. In some embodiments, the conductive via 41v1 and the conductive pad 40m2 are collectively referred to as a feeding element.

[0191] refer to Fig.10E , an insulating layer 42 is formed on the insulating layer 41 to cover the conductive via 41v1 and the conductive layer 40m1. In some embodiments, the insulating layer 42 may be formed of or include PID, PI, or solder resist. In some embodiments, the insulating layer 42 may be formed by, for example, lamination or other suitable operations. The insulating layer 42 and the insulating layer 41 may be formed of the same or different materials depending on design requirements.

[0192] refer to Fig.10F , a portion of the insulating layer 42 is removed to form a step structure 42s1 (or a ladder structure) and expose the conductive via 41v1 and the conductive layer 40m1. In some embodiments, the insulating layer 42 may be removed by, for example, etching or other suitable operations.

[0193] refer to Figure 10G , the antenna 43 is placed on the step structure 42s1 of the insulating layer 42 by an adhesive (e.g., a conductive adhesive or a non-conductive adhesive). The antenna 43 is electrically connected to the conductive via 41v1 through an electrical contact 41s (e.g., a solder ball). In some embodiments, the conductive via 41v1 may serve as a feed point for the antenna 43. In some embodiments, the antenna 43 is similar to the Figure 2A or Figure 5A In some embodiments, antenna 43 can be connected to antenna 12 or 13 as described in the embodiment of the present invention. Fig. 7A , 7B , 7C, 7D, 7E and 7F. In some embodiments, antenna 43 can be formed by Fig. 8A , 8B , 8C, 8D, 8E and 8F. In some embodiments, antenna 43 can be formed by Fig.9A , 9B , 9C, 9D and 9E are formed by the operations described in.

[0194] In some embodiments, the conductive via 41v1 and the electrical contact 41s may be omitted, and as shown in FIG. Fig. 7E The antenna shown in FIG. 4 is placed on the stepped structure 42s1 of the insulating layer 42 with the connection structure 33 directly connected to the conductive pad 40m2.

[0195] As used herein, spatially relative terms, for example, "under," "below," "lower," "above," "upper," "lower," "left," "right," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it may be directly connected or coupled to the other element, or there may be intermediate elements.

[0196] As used herein, the terms "approximately", "substantially", "substantially" and "about" are used to describe and take into account small changes. When used in conjunction with an event or situation, the term may refer to an example where the event or situation occurs exactly and an example where the event or situation occurs very approximately. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1% or ±0.5% of a given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term "substantially coplanar" may refer to two surfaces within a few microns (μm) positioned along the same plane, for example, within 10 μm, within 5 μm, within 1 μm or within 0.5 μm positioned along the same plane. When referring to a "substantially" identical numerical value or characteristic, the term may refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the value.

[0197] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, for example, less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered "substantially" or "approximately" the same if the difference between them is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%). For example, "substantially" parallel can refer to an angular variation range of less than or equal to ±10° relative to 0°, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" vertical can refer to an angular variation range of less than or equal to ±10° relative to 90°, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0198] For example, two surfaces may be considered coplanar or substantially coplanar if the displacement between the two surfaces is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm. A surface may be considered planar or substantially planar if the displacement between any two points on the surface relative to the plane is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm.

[0199] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to transfer an electric current. Conductive materials generally refer to those materials that present little or no resistance to the flow of electric current. One measure of conductivity is Siemens / meter (S / m). Generally, conductive materials are materials with a conductivity greater than approximately 10 4 S / m (e.g., at least 10 5 S / m or at least 10 6S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0200] As used herein, the singular terms "a", "an" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., physically in contact with) the latter component, as well as the case where one or more intermediate components are located between the former component and the latter component.

[0201] Unless otherwise specified, spatial descriptions such as "above", "below", "up", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "on", "below", "downward", etc. are indicated relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, with the understanding that the advantages of the embodiments of the present invention will not be deviated by such arrangements.

[0202] Although the present invention has been described and illustrated with reference to specific embodiments of the present invention, these descriptions and illustrations do not limit the present invention. It will be clearly understood by those skilled in the art that various changes may be made without departing from the true spirit and scope of the present invention as defined by the appended claims, and equivalent components may be substituted in the embodiments. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction and the actual device in the present invention. There may be other embodiments of the present invention that are not specifically described. This specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material compositions, substances, methods or processes suitable for the goals, spirit and scope of the present invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present invention.

[0203] The foregoing summarizes several embodiments of the present invention and features of the details. The embodiments described in the present invention can be easily used as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present invention, and various changes, substitutions and variations can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device package, comprising: a first antenna comprising a first antenna pattern and a second antenna pattern; and A second antenna is disposed above the first antenna and has an opening exposing the second antenna pattern of the first antenna. 2 . The semiconductor device package of claim 1 , further comprising a connection structure overlapping the opening, the connection structure being configured to feed a signal to the first antenna. 3 . The semiconductor device package according to claim 2 , wherein a width of the opening is greater than a width of the connection structure in a cross-sectional view. 4 . The semiconductor device package of claim 1 , wherein the second antenna comprises a first antenna pattern that overlaps the first antenna pattern of the first antenna. 5 . The semiconductor device package of claim 1 , wherein a distance between the first antenna pattern and the second antenna pattern of the first antenna is smaller than a width of the first antenna pattern of the first antenna or a width of the second antenna pattern of the first antenna. 6 . The semiconductor device package of claim 1 , wherein the first antenna includes an opening having a width, the width of the opening of the first antenna being smaller than a width of the opening of the second antenna in a cross-sectional view.

7. A semiconductor device package, comprising: Circuit structure; a first antenna disposed above the circuit structure and comprising a first dielectric layer; and A second antenna is disposed above the circuit structure and includes a second dielectric layer, wherein the second dielectric layer does not overlap with the first dielectric layer. 8 . The semiconductor device package of claim 7 , wherein the first antenna and the second antenna are located at different heights relative to the circuit structure. 9 . The semiconductor device package of claim 7 , further comprising a first antenna pattern at least partially overlapping the first antenna and electrically coupled to the first antenna. 10 . The semiconductor device package of claim 9 , wherein the first antenna pattern and the second antenna are located at substantially the same height relative to the circuit structure.

11. The semiconductor device package according to claim 7, further comprising: a second antenna pattern, wherein the second antenna pattern and the first antenna are located at substantially the same height relative to the circuit structure; and A connection structure is connected to the second antenna pattern and is configured to feed a signal. 12 . The semiconductor device package of claim 11 , further comprising a solder disposed between the second antenna pattern and the circuit structure, wherein the solder electrically connects the circuit structure to the connection structure.

13. The semiconductor device package according to claim 7, further comprising: a first supporting structure, which is disposed on the circuit structure and supports the first antenna; and A second supporting structure is disposed on the circuit structure and supports the second antenna. 14 . The semiconductor device package of claim 13 , wherein the first support structure and the second support structure are composed of substantially the same material.

15. The semiconductor device package of claim 7, wherein the first antenna comprises a third antenna pattern at least partially covered by the first dielectric layer, wherein the second antenna comprises a fourth antenna pattern at least partially covered by the second dielectric layer, and wherein the fourth antenna pattern does not overlap with the first dielectric layer in a vertical direction.

16. The semiconductor device package of claim 7, wherein the second dielectric layer is spaced apart from the first dielectric layer. 17 . The semiconductor device package of claim 7 , wherein a width of the first antenna is different from a width of the second antenna.

18. A semiconductor device package, comprising: Circuit structure; a first antenna pattern disposed above the circuit structure; and The second antenna pattern at least partially covers the first antenna pattern and has a first side surface vertically overlapping the first antenna pattern. 19 . The semiconductor device package of claim 18 , wherein the second antenna pattern comprises a second side surface that is offset from at least one side surface of the first antenna pattern. 20 . The semiconductor device package of claim 18 , further comprising an electronic component disposed below the circuit structure, and the electronic component at least partially overlaps the first antenna pattern and the second antenna pattern.

21. A method of manufacturing a semiconductor device package, the method comprising: Providing a substrate and a packaging body disposed above or covering the substrate; Providing a first protective layer to cover or encapsulate the package body; providing a metal layer over the protective layer, the metal layer comprising an interconnect structure embedded in the protective layer; providing a second protection layer and a third protection layer above the metal layer; and A portion of the second protection layer and the third protection layer is removed to form a step structure or a ladder structure.

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