Dual mode current sensing in high power driver and switching transistor module

Abstract

The apparatus and associated methods relate to circuit load balancing in a multi-phase power supply system (MPPSS). In an illustrative example, an MPPSS may include a plurality of power phases, each power phase being driven by a respective power phase driver (e.g., a DRMOS). For example, the controller may include a plurality of current balancing inputs, each current balancing input corresponding to one of the power phases. For example, the current balancing input may be generated by a dual mode current sensing circuit (DMCSC). For example, in a data collection mode of the power phase, the DMCSC may store information of the output current. In a sensing mode of the power phase, the DMCSC may generate a current balancing input to the controller based on a DC resistance of the current sensing circuit and an active resistance in the low-side driver circuit. Various embodiments may advantageously measure current imbalance in a cost-effective manner.

Description

Technical Field

[0001] Various embodiments generally relate to load balancing systems and methods for high frequency power converter circuits. Background Art

[0002] A number of direct current (DC)-to-DC power integrated circuits (ICs) may include current sensing circuits. For example, a metal oxide semiconductor field effect transistor (MOSFET) power converter system may utilize current sensing circuits to accurately measure output current for proper operation and to prevent overcurrent conditions. Various current sensing techniques may be implemented. For example, the current sensing circuit may include a shunt resistor, a current transformer, a Hall effect sensor, and a sensing circuit. Various implementations may have different advantages and limitations in terms of accuracy, cost, size, and complexity.

[0003] A driver and MOSFET (DRMOS) module can sometimes be referred to as a power management package that integrates a MOSFET and a driver IC into a single package. This technology has become increasingly popular in recent years due to its numerous advantages over traditional discrete solutions. DRMOS offers better efficiency, thermal performance, and reliability, which can be critical factors in power electronics applications. The integration of the MOSFET and driver IC reduces parasitic inductance and capacitance, which can cause switching losses and electromagnetic interference (EMI) issues. In addition, the single package design simplifies the PCB layout and assembly process, reduces component count and size, and improves thermal management by allowing better heat dissipation. DRMOS modules are commonly used in high-performance desktop and server motherboards, graphics cards, and other power electronics applications that require high efficiency and reliability.

[0004] In some power converter applications (e.g., in a DC power supply for a processor), it may be advantageous to balance the current between phases to ensure an even distribution of the load and to prevent overheating and overloading of the individual phases. For example, some current sensing techniques may be used to accurately measure the current in each phase. Some examples of such techniques include multiphase current sensing circuits and / or interleaved power converter topologies. Summary of the invention

[0005] The apparatus and associated methods relate to circuit load balancing in a multi-phase power supply system (MPPSS). In an illustrative example, the MPPSS may include multiple power phases, each driven by a corresponding power phase driver (e.g., DRMOS). For example, the controller may include multiple current balancing inputs, each corresponding to one of the power phases. For example, the current balancing input may be generated by a dual-mode current sensing circuit (DMCSC). For example, in a data collection mode of the power stage, the DMCSC may store information about the output current. In a sensing mode of the power stage, the DMCSC may generate a current balancing input to the controller based on a DC resistance of the current sensing circuit and an active resistance in a low-side drive circuit. Various embodiments may advantageously measure current imbalance in a cost-effective manner.

[0006] Various embodiments may achieve one or more advantages. For example, some embodiments may advantageously digitally compensate for gain errors of current balancing inputs based on sensing compensation inputs. For example, some embodiments may advantageously measure current balancing inputs relative to power ground to advantageously avoid integration of large ground planes. For example, some embodiments may advantageously balance phase currents of more than twelve power phases. For example, some embodiments may advantageously include an overcurrent protection circuit so that a high-side transistor, a low-side transistor, a sensing field effect transistor circuit, and an overcurrent protection loop may be integrated in a single package. For example, some embodiments may advantageously include a 5mm x 5mm package outline. For example, some embodiments may advantageously control the difference between the load currents of at least two power phase drivers to a maximum of 5%. For example, some embodiments may advantageously adjust the total current output of at least two-phase power drivers to prevent overcurrent of the MPPSS.

[0007] The details of various embodiments are set forth in the drawings and the description that follows. Other features and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An exemplary multi-power stage current sensing circuit (MPSCSC) is shown in an exemplary use case scenario of a power circuit providing power to a load, wherein the MPSCSC may be configured to measure a balanced current signal for each phase in the power circuit.

[0009] Figure 2 As shown in reference Figure 1 An exemplary dual-mode current sensing circuit (DMCSC) in an exemplary MPSCSC is described.

[0010] Figure 3 An exemplary sensing response of an exemplary DMCSC is shown.

[0011] Figure 4 Flowchart of an exemplary current balancing method may be provided.

[0012] The same reference symbols in the various drawings represent the same elements. DETAILED DESCRIPTION

[0013] For ease of understanding, this document can be organized as follows. First, to help introduce the discussion of various embodiments, you can refer to Figure 1 A multi-power stage current sensing circuit (MPSCSC) is introduced. Second, this introduction leads to the reference Figure 2-3 Some exemplary embodiments of dual-mode current sensing circuits (DMCSCs) that can be applied in exemplary MPSCSCs are described. Figure 4 , which describes exemplary apparatus and methods for regulating and controlling the power output of the total phase and each individual phase of a MPSCSC. Finally, the document discusses further embodiments, exemplary applications and various aspects related to the MPSCSC.

[0014] Figure 1 An exemplary multi-power level current sensing circuit (MPSCSC) in an exemplary use case scenario of a power circuit providing power to a load is shown, wherein the MPSCSC can be configured to measure a balanced current signal for each phase in the power circuit. In the depicted illustrative use case scenario 100, a server 105 can be powered by a power circuit 110. For example, the server 105 can be a data center. For example, the server 105 can be a gaming system. The power circuit 110 provides power to a load domain 115 of the server 105 (e.g., via a current output IOUT). By way of example and not limitation, the power circuit 110 can include one or more switching power supplies. As shown, by way of example and not limitation, the load domain 115 of the server 105 includes a processor 120 (e.g., a central processing unit (CPU), a graphics processing unit (GPU)), a memory 125, other associated peripherals 130, or some combination thereof.

[0015] In this example, the load domain 115 receives power from a multi-phase power control circuit (MPPCC 135). For example, the MPPCC 135 may include a multi-phase buck regulator. For example, the MPPCC 135 may provide power to multiple interleaved buck converter stages in parallel in multiple power stages to provide a regulated output voltage (e.g., as Figure 1 In some embodiments, the MPPCC 135 can advantageously provide power with reduced input and output ripple and high efficiency. For example, the regulated power can be used to provide high power applications to the load domain 115. For example, the load domain 115 can include a data center. For example, the load domain 115 can include a high-end video graphics card.

[0016] In some embodiments, the MPPCC 135 may include a power management integrated circuit (PMIC) that includes over-current protection (OCP) and / or negative current protection (NCP). For example, the MPPCC 135 may advantageously prevent damage to the system and ensure safe operation by limiting the current to a safe level in the event of a fault condition (e.g., a short circuit, an overload, an overcurrent in the power circuit 110, a phase imbalance in the power circuit). In various embodiments, the MPPCC 135 may include a small package size. As an example, but not limited to, the MPPCC 135 may be implemented with a 5 mm×5 mm package shape. For example, the MPPCC 135 having a small package size may be suitable for space-constrained applications (e.g., graphics cards, mobile devices, wearable devices, other portable electronic devices).

[0017] The MPPCC 135 includes multiple phases (2, 3, 4, 6, 12, 24 or more phases) of the power phase driver 140. In this example, each power phase driver 140 includes a driver circuit 145 and a sensing field effect transistor circuit 150. For example, each power phase driver 140 can be a DRMOS. For example, each power phase driver 140 can include a driver IC combined with an external switching transistor circuit. For example, the driver circuit 145 can include a driver inverter circuit (e.g., having a pair of power MOS field effect transistors). For example, the sensing field effect transistor circuit 150 can include a pair of sensing MOS field effect transistors. In some embodiments, the driver circuit 145 and the sensing field effect transistor circuit 150 can be integrated in a single package. For example, a single package power stage can advantageously reduce the number of components and improve layout efficiency.

[0018] As shown, driver circuit 145 includes a high-side driver 155 and a low-side driver 160. For example, high-side driver 155 and low-side driver 160 can be driven by PWM controller 165. Sensor field effect tube circuit 150 can, for example, receive a phase control signal from a control circuit (not shown) of a corresponding power level. In some embodiments, high-side driver 155 can include a high-side field effect transistor (FET). In some embodiments, low-side driver 160 can include a low-side FET.

[0019] In this example, the power phase driver 140 receives a phase control signal from a pulse width modulation controller (PWM controller 165). For example, the PWM controller 165 can generate a circuit activation signal based on the duty cycle (e.g., power phase) of each power phase driver 140. For example, when the phase control signal activates the corresponding power stage, the driver circuit 145 of the power stage can provide an output current (Iout) based on Vout. In some examples, Iout can vary between the power phase drivers 140, resulting in a load imbalance between the power phase drivers. For example, load imbalance may cause some components in the power phase driver 140 to be overloaded and / or overheated. In some examples, the imbalance may have a negative impact on the efficiency and / or performance of the power supply circuit 110.

[0020] For example, MPSCSC 170 can use dual-mode current sensing circuit (DMCSC 180) to receive output current information from each power phase driver 140. As shown, MPSCSC 170 can be coupled to the low-side driver 160 of each power phase driver 140 to generate a balanced measurement signal (Ibal1, ..., Ibaln) of the power phase driver. For example, DMCSC 180 can be activated by the low-side switch signal of each power stage to generate a measurement signal related to the relative output current of the power stage. In some embodiments, DMCSC 180 can generate a measurement signal from a power ground reference. For example, using DMCSC 180, MPPCC135 can advantageously reduce the size requirements of the ground plate.

[0021] In some embodiments, the DMCSC 180 can operate in two modes, namely a data collection mode and a sensing mode. In the data collection mode, for example, the controller 175 may not receive information from the DMCSC 180. The controller 175 can switch to the sensing mode to receive phase current information relative to other power levels. For example, when the corresponding power phase driver may be in an off state in the duty cycle (e.g., when the low-side driver 160), the sensing mode can be activated. For example, the DMCSC 180 can include a DC resistance low-side drain source on a resistive sensing circuit to generate a balanced measurement signal in the sensing mode.

[0022] The controller 175 includes a noise cancellation engine 185, a phase compensation engine 190, and a current regulation engine 195. As shown, for n power stages, the controller 175 receives current balancing signals at inputs Ibal1, ..., Ibaln. The controller 175 also receives a current sensing signal Isenn. In some embodiments, the Isenn signal can be used to mitigate noise in the current balancing signal. For example, the noise cancellation engine 185 can use the Isenn signal to mitigate noise generated by parasitic resistance in the MPSCSC 170. In some embodiments, the controller can be configured to use the Isenn signal to compensate for gain errors in all n power stages.

[0023] The controller 175 can determine the current imbalance based on the current balance signal. In some embodiments, the phase compensation engine 190 can generate a relative balance profile of the power phase drivers 140. For example, the controller 175 can determine that any one of the power phase drivers 140 may be overloaded based on the relative balance distribution. In some embodiments, the controller 175 can generate a signal to mitigate the unbalanced output. As shown, the controller 175 can be operably coupled to the PWM controller 165. For example, the controller 175 can generate a feedback signal to the PWM controller 165 to adjust the power phase driver 140 of each power phase.

[0024] For example, when power stage k may be determined to be overloaded, the controller 175 may generate a feedback signal to reduce the phase output current at power stage k by, for example, reducing the duty cycle of power stage k. Thus, for example, the controller 175 may advantageously use the measurement signal to avoid fault development and protect the MPPCC 135.

[0025] In some embodiments, the current regulation engine 195 can regulate the Iout of the power phase driver 140. For example, the current regulation engine 195 can measure the output power provided to the load domain 115 based on the current measurement of Iout (e.g., using a current sensing circuit (not shown) implemented in the MPSCSC 170). For example, when the voltage and / or current may be above a threshold, the current regulation engine 195 can generate a signal to the PWM controller 165 to reduce the power output of each phase.

[0026] In various embodiments, the power control circuit (e.g., MPPCC 135) may include at least two power phase drivers (e.g., power phase driver 140) configured to deliver power in at least two power phases. For example, each of the at least two power phase drivers may generate an output current at a driver circuit (e.g., driver circuit 145). In some embodiments, the power control circuit may include a controller configured to generate a control signal based on a relative load balance between at least two power phase drivers. For example, for each power phase, the controller may receive a current balancing input. For example, the current balancing input may be generated by a dual-mode current sensing circuit (e.g., DMCSC 180). For example, the DMCSC may generate a current balancing input based on a direct current resistance (DCR) current sensing circuit. In some embodiments, in a data collection mode, the DMCSC may store information about the output current of the corresponding at least two power phase drivers. In a sensing mode, for example, the DMCSC may generate a current balancing input related to the output current based on an active resistor in a DCR current sensing circuit and a low-side driver circuit. Upon receiving the current balancing input, the controller may compensate for a relative gain of the current balancing input based on the sensed compensation input. Based on the compensated current balancing input, the controller may determine a load imbalance in the power phases.

[0027] Figure 2 An exemplary DMCSC in a multi-phase power control circuit (e.g., MPPCC 135) is shown. In this example, MPPCC 200 includes a phase 1 DRMOS (DRMOS 205) and a phase 2 DRMOS (DR MOS 210). For example, one of the power phase drivers 140 may include DRMOS 205. For example, one of the power phase drivers 140 may include DRMOS 210. In some embodiments, each of DRMOS 205 and DRMOS 210 may include a driver circuit 145 and a sense field effect transistor circuit 150 in a single package. In this example, the sense field effect transistor circuit 150 includes a low-side sense MOS field effect transistor 250 and a high-side sense MOS field effect transistor 255.

[0028] For example, the power phase driver 140 may receive a control signal from the PWM controller 165. In some embodiments, the PWM controller 165 may control the duty cycle of the DRMOS 205 and the DRMOS 210. For example, during the duty cycle of the DRMOS 205, the high side gate (HSG) of the DRMOS 205 (Phase 1) may be turned on, and the low side gate (LSG) of the DRMOS may be turned off.

[0029] In this example, the controller 175 receives the sense current (Isenn) of the MPPCC 200 at a node 215. In various implementations, the measurement of Isenn at the node 215 can advantageously mitigate the error produced by the parasitic resistor Rpara7.

[0030] MPPCC 200 includes DMCSC 220 connected to DRMOS 205 and DMCSC 225 connected to DRMOS 210. For example, DMCSC 220 may generate a balanced current signal for DRMOS 205 at node 230. For example, DMCSC 225 may generate a balanced current signal for DRMOS 210 at node 235.

[0031] In this example, DMCSC 220 includes a DCR current sensing circuit 240, and DMCSC 225 includes a DCR voltage sensing circuit 245. As shown, DCR current sensing circuit 240 and DCR current sensing circuit 245 each include a DCR inductor (L1 and L2), a DCR resistor (Rdcr1 and Rdcr2), and a sensing capacitor (Csns1 and Csns2). In various embodiments, L1 and L2 can be low-cost inductors. For example, the DCR of L1 and L2 may be very low. For example, L1 and L2 may not match each other (and other phases in MPPCC 200).

[0032] The controller 175 receives the balanced current signal (Ibal1) of the DRMOS 205 at the node 230 and receives the balanced current (Ibal2) of the DRMOS 210 at the node 235. In some embodiments, as an illustrative example focusing on phase 1 (DRMOS 205), the DMCSC 220 can operate in two modes. In the data collection mode, a voltage can be generated across Csns1. For example, when the HSG can be turned on, the DMCSC 220 can operate in the data collection mode. For example, the voltage across Csns1 can correspond to the voltage across the DC resistance (Rdcr) of the output inductor L1.

[0033] For example, when the HSG may be closed and the LSG may be opened, the DMCSC 220 may operate in a sensing mode. For example, Csns1 may be discharged through the power ground (PGND). For example, the controller 175 may measure the response at Ibal1 to determine the phase current of DRMOS 205 relative to the phase current of DRMOS 210. For example, the controller 175 may determine that DRMOS 205 may be overloaded. For example, the controller 175 may generate a signal to the PWM controller 165 to reduce the current output at DRMOS 205 based on the DRMOS 205 being overloaded.

[0034] In some embodiments, the balancing current signal at Ibal1 can be generated as a function of Rdcr (e.g., Rdcr1), the drain-source on-resistance of the low-side transistor 160, and the duty cycle of the power stage (e.g., DRMOS 205). For example, the balancing current signal received at Ibal1 in the sensing mode (e.g., the voltage across Csns1) can be generated by V=I L1 (Rdcr+(1-D)Rds_on) is given. Thus, for example, the accuracy of the balanced current signal can be advantageously independent of the sense resistor (Rsns1) and the parasitic resistors (Rpara4 and Rprar6).

[0035] In some embodiments, the noise cancellation engine 185 may include digital gain compensation to reduce the gain error caused by Rpara1 and Rpara3. For example, the digital control may include static gain compensation to correct the gain error. For example, the digital gain compensation may include dynamic gain control based on Isenn, Ibal1, and Ibal2.

[0036] In some embodiments, MPPCC 200 may include a board layout design that advantageously reduces the resistance of Rpara2. For example, by keeping the resistance of Rpara2 low, cross-phase gain errors introduced by other phases (e.g., signals introduced to Ibal1 from DRMOS 210) may be advantageously reduced.

[0037] In some embodiments, the DMCSCs 220, 225 can provide relative current balance information to the controller 175 without requiring the driver circuit 145 to be connected to Vin. Thus, for example, protection circuitry for protecting the driver circuit 145 to be connected to Vin can be advantageously eliminated.

[0038] Figure 3 2 shows an exemplary sensing response at each node in an exemplary DMCSC. In this example, DRMOS 205 and DMCSC 220 (eg, Figure 2 300 at node 305 of the sensing mode 315). As shown, in the data collection mode 310, the voltage across Csns1 can increase. For example, the voltage can be discharged during the sensing mode 315. In various embodiments, the duration of the data collection mode 310 can be significantly shorter than the duration of the data collection mode 310. For example, in a 24-phase power circuit, the duration of node 305 to the duration of the sensing mode 315 can be 1:23. Therefore, the DMCSC 220 can advantageously measure a large portion of the duty cycle of the DRMOS 205 while maintaining no connection between the driver circuit 145 and Vin.

[0039] In this example, an exemplary response 320 at the node 215 may also be shown. For example, the exemplary response 320 may be an aggregate response of the power phase drivers 140. In various implementations, the controller 175 may use the exemplary response 320 to compensate for gain errors in the current balance input (Ibal) in each power phase driver 140.

[0040] Figure 4 4. may be a flow chart illustrating an exemplary current balancing method 400. For example, the controller 175 may use the noise cancellation engine 185, the phase compensation engine 190, and / or the current regulation engine 195 to perform the exemplary current balancing method 400 to regulate and control the total current and the individual phase output currents of a multi-phase power supply (e.g., the power supply circuit 110).

[0041] The method 400 begins at decision point 405, where it may be determined whether the total output power of the power supply may be within tolerance. For example, the controller 175 may compare the total output current and the output voltage to a predetermined threshold. If the total output power of the power supply may not be within tolerance, then in step 410, a control signal may be sent to adjust the total output power. For example, the controller 175 may send a control signal to the PWM controller 165 to reduce the power output.

[0042] If the total output power of the power supply can be within the tolerance, then the activation of the sensing mode of the power phase can be determined based on the low-side on signal in step 415. For example, when the DRMOS 205 can be in the sensing mode, the controller 175 can receive the voltage drop. In step 420, a current balance signal can be received for each power phase in the sensing mode of the corresponding power phase. For example, for each power phase driver 140, the controller 175 can receive the voltage across Csns, as shown in reference Figure 3 An exemplary response 300 is depicted as shown in sensing pattern 315 .

[0043] Next, in step 425, gain errors may be compensated in each current balance signal. For example, the controller 175 may use the noise cancellation engine 185 to compensate for the received current balance signals. For example, the controller 175 may compensate for the received current balance signals based on Isenn. In step 430, the relative balance profiles of the power phases may be determined based on the error-compensated current balance signals. Next, in step 435, load imbalances in the power phases may be determined. For example, the controller 175 may determine that any of the power phase drivers 140 may be generating overcurrent.

[0044] In decision point 440, it may be determined whether the load balance between the power phases may be within tolerance. For example, the controller 175 may include an unbalance tolerance that the output current of each phase is within 5% (maximum) of each other. If the load balance between the power phases may be within tolerance, decision point 405 may be repeated. If the load balance between the power phases may not be within tolerance, in step 445, a control signal may be sent to adjust the output current in one or more of the power phases, and decision point 405 may be repeated. For example, the controller 175 may send a signal to the PWM controller 165 to reduce the duty cycle of the overcurrent power phase driver, thereby reducing the power phase driver load, which may advantageously protect the power phase driver.

[0045] Although various embodiments have been described with reference to the figures, other embodiments are possible.

[0046] In some embodiments, the high-side driver 155 (and / or the low-side driver 160) may also include other transistors. For example, the high-side driver 155 may include a bipolar junction transistor (BJT). For example, the high-side driver 155 may include an insulated gate bipolar transistor (IGBT). For example, the high-side driver 155 may include a gallium nitride transistor. For example, the high-side driver 155 may include a junction field effect transistor (J field effect transistor).

[0047] Although referenced Figure 1 An exemplary system is described, but other implementations may be deployed in other industrial, scientific, medical, commercial, and / or residential applications. For example, the power circuit 110 with the MPPCC 135 may be used to generate artificial intelligence computing applications (e.g., for pre-training a generative chat model (ChatGPT)). For example, the power circuit 110 with the MPPCC 135 may be used in crypto mining applications. For example, the power circuit 110 with the MPPCC 135 may be used in a high-performance gaming system.

[0048] In various embodiments, some bypass circuit implementations may be controlled in response to signals from analog or digital components, which may be discrete, integrated, or a combination of each. Some embodiments may include programmed, programmable devices, or some combination thereof (e.g., PLA, PLD, ASIC, microcontroller, microprocessor), and may include one or more data memories (e.g., cells, registers, blocks, pages) providing single or multiple digital data storage capabilities, and the data memories may be volatile, non-volatile, or some combination thereof. Some control functions may be implemented in hardware, software, firmware, or a combination of any of them.

[0049] A computer program product may comprise a set of instructions which, when executed by a processor device, cause the processor to perform specified functions. These functions may be performed in conjunction with a controlled device in operable communication with the processor. A computer program product, which may include software, may be stored in a data storage tangibly embedded on a storage medium (e.g., an electronic, magnetic, or rotating storage device), and may be fixed or removable (e.g., hard disk, floppy disk, thumb drive, CD, DVD).

[0050] Some systems may be implemented as computer systems that can be used with various implementations. For example, various implementations may include digital circuits, analog circuits, computer hardware, firmware, software, or a combination thereof. The apparatus may be implemented in a computer program product that is tangibly embodied in an information carrier, such as in a machine-readable storage device, for execution by a programmable processor; and the method may be performed by a programmable processor executing a program of instructions to perform the functions of various embodiments by operating on input data and generating output. Various embodiments may be advantageously implemented in one or more computer programs that may be executed on a programmable system that includes at least one programmable processor coupled to receive data and instructions from a data storage system, at least one input device, and / or at least one output device, and to send data and instructions to a data storage system. A computer program may be a set of instructions that may be used directly or indirectly in a computer to perform a specific activity or produce a specific result. A computer program may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any manner, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0051] Suitable processors for executing a program of instructions include, for example, general and special purpose microprocessors, which may include a single processor or one of multiple processors of any type of computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer may be a processor for executing instructions and one or more memories for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data files, or be operatively coupled to communicate with it; such devices include disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented by or incorporated into an ASIC (Application Specific Integrated Circuit).

[0052] In some embodiments, each system can be programmed with the same or similar information and / or initialized with substantially the same information stored in volatile and / or non-volatile memory. For example, one data interface can be configured to perform auto-configuration, auto-download, and / or auto-update functions when coupled to an appropriate host device (e.g., a desktop computer or server).

[0053] In various embodiments, a computer system may include an Internet of Things (IoT) device. An IoT device may include objects embedded with electronics, software, sensors, actuators, and network connectivity that enable these objects to collect and exchange data. An IoT device may be used with wired or wireless devices by sending data to another device through an interface. An IoT device may collect useful data and then autonomously flow the data between other devices.

[0054] Various examples of modules can be implemented using circuits including various electronic hardware. As an example and not limitation, hardware can include transistors, resistors, capacitors, switches, integrated circuits, other modules, or some combination thereof. In various examples, modules can include analog logic, digital logic, discrete components, traces, and / or memory circuits manufactured on a silicon substrate that includes various integrated circuits (e.g., FPGAs, ASICs), or some combination thereof. In some embodiments, modules can involve the execution of pre-programmed instructions, software executed by a processor, or some combination thereof. For example, various modules can involve both hardware and software.

[0055] In an illustrative aspect, a multiphase power supply system may include a plurality of power phase drivers configured to deliver power in a plurality of power stages. For example, each of the plurality of power phase drivers may include a high-side transistor, a low-side transistor, and a sensing field effect transistor circuit, wherein the high-side transistor has a drain connected to a power input of the corresponding power phase driver and a source connected to a power output of the corresponding power phase driver, the low-side transistor has a drain connected to the power output, and the sensing field effect transistor circuit may include a high-side sensing field effect transistor and a low-side sensing MOS field effect transistor. For example, a drain of a high-side sensing field effect transistor connected to a power output, a source of a high-side sensing field effect transistor connected to a drain of a low-side sensing field effect transistor, and a source of a low-side sensing field effect transistor connected to a source region of a low-side transistor.

[0056] For example, a high-side transistor, a low-side transistor, and a sensing FET circuit can be integrated into a single package. For example, each of a plurality of power phase drivers can include an overcurrent protection circuit, so that a high-side transistor, a low-side transistor, a sensing FET circuit, and an overcurrent protection loop can be integrated into a single package.

[0057] For example, each of the plurality of power phase drivers may include a 5 mm x 5 mm package outline.

[0058] A multiphase power supply system may include, for example, a controller configured to generate a control signal based on a relative load balance between a plurality of power phase drivers. For example, the controller may include a plurality of current balancing inputs, each current balancing input corresponding to one of the power phases. For example, the controller may include a sensing compensation input coupled to the output of the plurality of power phase drivers. The controller may include a dual-mode current sensing circuit coupled to the plurality of power phase drivers and the controller. For example, for each of the plurality of power phases, the dual-mode current sensing circuit may include a direct current resistance (DCR) current sensing current, and the dual-mode current sensing circuit may be configured such that, for example, in a data collection mode, the dual-mode current sensing circuit stores information on the output current of the corresponding power phase. For example, in a sensing mode, the dual-mode current sensing circuit generates a current balancing input, which is a function of the direct current resistance (Rdcr) of the DCR current sensing loop and the low-side drain-source on-resistance of the low-side transistor.

[0059] For example, upon receiving the current balancing input, the controller can be configured to compensate for the relative gain of the current balancing input based on the sensed compensation input. For example, the controller can determine a load imbalance in a plurality of power phases. For example, the controller can generate a load balancing signal to balance a load imbalance in one of a plurality of phase power drivers.

[0060] For example, the controller may further include a digital gain compensation module configured to reduce gain errors in multiple current balancing inputs. For example, the controller may be configured to maintain the difference between the load currents of the multiple power phase drivers at a maximum of 5%. For example, the controller may include a current regulation engine configured to regulate the total current output of the multiple phase power drivers so that overcurrent of the multi-phase power supply can be prevented.

[0061] For example, a multi-phase power system may include multiple dual-mode current sensing circuits, each dual-mode current sensing circuit including a direct current resistance (DCR) current sensing loop having a direct current resistor having a first end connected to an output terminal of an inductor and a sensing resistor connected in series with a sensing capacitor between a source high-side sensing field effect transistor and a second end of the direct current resistor.

[0062] In an illustrative aspect, a multiphase power supply system may include at least two power phase drivers configured to deliver power in at least two power phases. For example, each of the at least two power phase drivers generates an output current through a high-side driver circuit and a low-side driver circuit. For example, a multiphase power supply system may include a controller configured to generate a control signal based on a relative load balance between at least two power phase drivers. For example, the controller may include a plurality of current balancing inputs, each current balancing input corresponding to one of the power phases. For example, the controller may include a sensing compensation input coupled to the output of the at least two power phase drivers. For example, the controller may include a dual-mode current sensing circuit coupled to the at least two power phase drivers and the controller. For example, for each of the at least two power phases, the dual-mode current sensing circuit may include a direct current resistance (DCR) current sensing loop, and the direct current resistance (DCR) current sensing loop is configured to generate the plurality of current balancing inputs for the at least two power phase drivers.

[0063] For example, in a data collection mode, the dual-mode current sensing circuit stores information about the output current of the corresponding at least two power phase drivers. For example, in a sensing mode, based on the DCR current sensing circuit and the active resistor in the low-side driver circuit, the dual-mode current sensing loop generates a current balance input related to the output current. For example, upon receiving the current balance input, the controller can be configured to compensate for the relative gain of the current balance input of multiple power phases based on the sensing compensation input. For example, based on the compensated current balance input, the controller can determine a load imbalance in at least two power phases.

[0064] For example, multiple current balancing inputs can be measured relative to the power supply ground. For example, at least two power phase drivers can include at least six power phase drivers. For example, each of the at least two power phase drivers can include a high-side transistor, a low-side transistor, and a sensing field effect transistor circuit. For example, the sensing field effect transistor circuit can include a high-side sensing field effect transistor and a low-side sensing field effect transistor. For example, the current balancing input of each power phase can be generated as a function of a DC resistance (Rdcr) and a drain-source on-resistance of a low-side transistor.

[0065] For example, the controller can be configured to maintain a difference between the load currents of the at least two power phase drivers at a maximum of 5%. For example, the controller can include a digital gain compensation module configured to reduce a gain error in a current balance input. For example, the controller can be configured to generate a load balance signal to balance an overload in one of the at least two power phase drivers.

[0066] For example, the controller may include a current regulation engine configured to regulate a total current output of at least two power phase drivers such that overcurrent of the multi-phase power system may be prevented.

[0067] In illustrative aspects, a power regulation method in a multiphase power control circuit may include allowing a current sensing circuit to collect data associated with an output current of a power phase in a data collection mode. For example, a power phase may be one of a plurality of power phases in a power supply circuit. For example, a power regulation method may include determining a transition of a power phase associated with a low-side on-signal from a data collection mode to a sensing mode. For example, a power regulation method may include receiving a current balance signal for each power phase in a sensing mode. For example, a current balance signal may be generated based on a DC resistance (Rdcr) of a current sensing circuit of a power phase and a drain-source on-resistance of a low-side transistor of a corresponding power phase.

[0068] For example, the power regulation method may include compensating for a gain error in each power phase as a function of a current balance signal for the corresponding power phase. For example, the power regulation method may include determining a load imbalance in a plurality of power phases. For example, the power regulation method may include sending a control signal to adjust an output current of each of the plurality of power phases.

[0069] For example, the control signal may include an instruction to reduce the duty cycle of the overcurrent power phase.For example, the plurality of power phases may include at least six phases.

[0070] Many implementations have been described herein. However, it should be understood that various modifications may be made. For example, advantageous results may be obtained if the steps of the disclosed technology are performed in a different order, or if the components of the disclosed system are combined in a different manner, or if components are supplemented with other components. Therefore, other implementations are contemplated within the scope of the following claims.

Claims

1. A multiphase power supply system, comprising: A plurality of power phase drivers configured to deliver power in a plurality of power stages, wherein each of the plurality of sub-power phase drivers comprises: a high-side transistor having a drain connected to the power input and a source connected to the power output of the corresponding power phase driver; a low-side transistor having a drain connected to the power output; and A sensing field effect transistor circuit including a high-side sensing field effect transistor and a low-side sensing field effect transistor, Wherein, the drain of the high-side sensing field effect transistor is connected to the power output, the source of the low-side sensing field effect transistor is connected to the drain of the low-side sensing field effect transistor, and the source of the low-side sensing field effect transistor is connected to the source of the low-side transistor.

2. The multi-phase power system of claim 1, wherein the high-side transistor, the low-side transistor and the sensing field effect transistor circuit are integrated into a single package.

3. The multi-phase power supply system of claim 2, wherein each of the plurality of power phase drivers further comprises an overcurrent protection circuit, such that the high-side transistor, the low-side transistor, the sensing field effect transistor circuit, and the overcurrent protection loop are integrated in a single package.

4. The multi-phase power supply system of claim 3, wherein each of the plurality of power phase drivers comprises a 5 mm x 5 mm package outline.

5. The multiphase power supply system of claim 1, further comprising: a controller configured to generate a control signal based on a relative load balance among the plurality of power phase drivers, wherein the controller comprises: a plurality of current balancing inputs, each current balancing input corresponding to one of the plurality of power phases; and a sensor compensation input coupled to the outputs of the plurality of power phase drivers; and a dual-mode current sensing circuit coupled to the plurality of power phase drivers and the controller, wherein, for each of the plurality of sub-power phases, the dual-mode current sensing circuit comprises a direct current resistance (DCR) current sensing circuit and the dual-mode current sensing circuit is configured such that, In a data acquisition mode, the dual-mode current sensing circuit stores information of output current of a corresponding power phase; and In a sensing mode, the dual-mode current sensing circuit generates a current balance input, which is a function of a DC resistance Rdcr of the DCR current sensing loop and a drain-source on-resistance of the low-side transistor; and Upon receiving a plurality of current balancing inputs of the plurality of power phases, the controller is configured to: compensating for a relative gain of the current balancing input based on the sense compensation input, determining a load imbalance among the plurality of power phases, and A load balancing signal is generated to balance a load imbalance in a power phase driver among the plurality of power phase drivers.

6. The multi-phase power system of claim 5, wherein the controller further comprises: A digital gain compensation module is configured to reduce gain errors in the plurality of current balancing inputs.

7. The multi-phase power supply system of claim 5, wherein the controller is configured to maintain a difference between load currents of the plurality of power phase drivers at a maximum of 5%.

8. The multi-phase power system of claim 5, wherein the controller further comprises a current regulation engine configured to regulate a total current output of the plurality of power phase drivers to prevent over-current of the multi-phase power system.

9. The multiphase power supply system of claim 1, further comprising: A plurality of dual-mode current sensing circuits each include a direct current resistance (DCR) current sensing loop having a direct current resistor having a first end connected to an output terminal of an inductor, and a sensing resistor connected in series with a sensing capacitor between a source of the high-side sense field effect transistor and a second end of the direct current resistor.

10. A multiphase power supply system comprising: at least two power phase drivers configured to deliver power in at least two power phases, wherein each of the at least two power phase drivers generates an output current via a high-side driver circuit and a low-side driver circuit; A controller configured to generate a control signal based on a relative load balance between the at least two power phase drivers, wherein the controller comprises: a plurality of current balancing inputs, each current balancing input corresponding to one of the at least two power phases; and a sense compensation input coupled to the outputs of the at least two power phase drivers; and a dual-mode current sensing circuit coupled to the at least two power phase drivers and the controller, wherein, for each of the at least two power phases, the dual-mode current sensing circuit comprises a direct current resistance (DCR) current sensing circuit configured to generate the plurality of current balancing inputs for the at least two power phase drivers, wherein: In a data collection mode, the dual-mode current sensing circuit stores information of the output current of the corresponding at least two power phase drivers, and In a sensing mode, the dual-mode current sensing circuit generates a current balancing input related to the output current based on the DCR current sensing current and an active resistance in the low-side driver circuit, such that upon receiving the current balancing input, the controller is configured to: Relative gains of current balancing inputs of the at least two power phases are compensated based on the sensed compensation input, and a load imbalance in the at least two power phases is determined based on the compensated current balancing input.

11. The multi-phase power supply system of claim 10, wherein the plurality of current balance inputs are measured relative to a power supply ground voltage.

12. The multi-phase power supply system of claim 10, wherein the at least two power phase drivers include at least six power phase drivers.

13. The multiphase power supply system of claim 10, wherein each of the at least two power phase drivers comprises: a high-side transistor; a low-side transistor; as well as The sensing field effect transistor circuit includes a high-side sensing field effect transistor and a low-side sensing MOS field effect transistor, wherein the current balance input of each power phase is generated as a function of a DC resistance Rdcr and a drain-source on-resistance of the low-side transistor.

14. The multi-phase power supply system of claim 10, wherein the controller is configured to maintain a difference between load currents of the at least two power phase drivers at a maximum of 5%.

15. The multi-phase power system of claim 10, wherein the controller further comprises a digital gain compensation module configured to reduce gain errors in the current balance inputs of each of the at least two power phases.

16. The multi-phase power supply system of claim 10, wherein the controller is configured to generate a load balancing signal to balance an overload of one power phase of the at least two power phase drivers.

17. The multi-phase power system of claim 10, wherein the controller further comprises a current regulation engine configured to regulate a total current output of the at least two power phase drivers to prevent overcurrent in the multi-phase power system.

18. A power modulation method in a multi-phase power control circuit, comprising: in a data collection mode, allowing the current sensing circuit to collect data associated with an output current of a power phase, wherein the power phase is one of a plurality of power phases in a power supply circuit; determining a transition from a data collection mode to a sensing mode for a power phase associated with a low-side turn-on signal; For each power phase, receiving a current balance signal in the sensing mode, wherein the current balance signal is generated based on a DC resistance Rdcr of the current sensing circuit of the power phase and a drain-source on-resistance of a low-side transistor of the corresponding power phase; compensating for a gain error in each power phase as a function of a current balance signal for the corresponding power phase; determining a load imbalance among the plurality of power phases; and A control signal is sent to adjust an output current of each of the plurality of power phases.

19. The power modulation method of claim 18, wherein the control signal includes an instruction to reduce the duty cycle of the overcurrent power phase.

20. The power modulation method of claim 18, wherein the plurality of power phases comprises at least six phases.

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