Power distribution network (PDN) system, electronic equipment and board-level network module

Abstract

The invention discloses a power distribution network (PDN) system, electronic equipment and a board-level network module. The PDN system comprises a voltage regulation module (VRM), the board-level network module and a load, the VRM comprises a power supply, the board-level network module comprises a first sampling resistor R1, a second sampling resistor R2 and a first capacitor C1, and the power supply supplies power to a load through the board-level network module; the power supply output end of the VRM is connected with the first end of the R1 and the first end of the R2; the second end of the R1 and the second end of the R2 are connected with the first end of the C1 and the power input end of the load, and the second end of the C1 is grounded. According to the embodiment of the invention, the PDN impedance can be effectively suppressed, and the integration space is saved.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a power distribution network (PDN) system, electronic equipment and a board-level network module. Background Art

[0002] The power distribution network PDN system can transfer power to the load. In order to ensure the stability of the power supply, reduce voltage fluctuations, and ensure that the system can work properly, the PDN system needs to set the target impedance Ztarget so that the PDN reaches the corresponding impedance value within a specific frequency range. In order to achieve the target impedance of the PDN system, capacitors can be connected to both ends of the power plane and the ground plane of the PDN system. However, capacitors will obviously occupy the integration space of the PCB board, reducing the product's time competitiveness. Summary of the invention

[0003] The embodiments of the present application provide a power distribution network PDN system, an electronic device and a board-level network module, which can suppress PDN impedance while saving PCB integration space.

[0004] In a first aspect, an embodiment of the present application provides a method, which is applied to an electronic device, and the method includes: the PDN system includes a voltage regulation module VRM, a board-level network module and a load; the VRM includes a power supply, the board-level network module includes a first sampling resistor R1, a second sampling resistor R2 and a first capacitor C1, and the power supply supplies power to the load through the board-level network module; the power output end of the VRM is connected to the first end of R1 and the first end of R2; the second end of R1 and the second end of R2 are connected to the first end of C1 and the power input end of the load, and the second end of C1 is grounded.

[0005] In the implementation manner of the present application, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0006] In a possible implementation, the PDN system includes a PCB board, the PCB board includes a power plane and a ground plane, the first end of the R1 is connected to the first power pin of the PCB; the first end of the R2 is connected to the second power pin of the PCB; the first power pin and the second power pin are both connected to the first end of the power plane; the second end of the R1 is connected to the third power pin of the PCB; the second end of the R2 is connected to the fourth power pin of the PCB; the third power pin and the fourth power pin are both connected to the second end of the power plane. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0007] In a possible implementation, the first end of C1 is connected to the fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of C1 is connected to the first ground pin. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0008] In a possible implementation, the power supply is a power management chip PMIC module, the power output end of the PMIC is connected to the sixth power pin of the PCB, the sixth power pin is connected to the first end of the power plane; the ground end of the PMIC is connected to the second ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0009] In a possible implementation, the load is a first chip, the power input terminal of the first chip is connected to the seventh power pin of the PCB, the seventh power pin is connected to the second end of the power plane; the ground terminal of the first chip is connected to the third ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0010] In a possible implementation manner, the resistance values ​​of R1 and R2 are both less than 20 mΩ. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0011] In a possible implementation, the equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R1; the equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R2. In this way, the parallel connection of sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0012] In the second aspect, an embodiment of the present application provides a board-level network module, which is applied to a PDN system, and the board-level network module includes a first sampling resistor R1, a second sampling resistor R2 and a first capacitor C1; wherein the first end of R1 and the first end of R2 are used to connect the power output end of the voltage regulation module VRM in the PDN system; the second end of R1 and the second end of R2 are used to connect the first end of C1 and the power input end of the load in the PDN system, and the second end of C1 is grounded.

[0013] In the implementation manner of the present application, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0014] In a possible implementation, the board-level network module includes a PCB board, the PCB board includes a power plane and a ground plane, the first end of the R1 is connected to the first power pin of the PCB; the first end of the R2 is connected to the second power pin of the PCB; the first power pin and the second power pin are both connected to the first end of the power plane; the second end of the R1 is connected to the third power pin of the PCB; the second end of the R2 is connected to the fourth power pin of the PCB; the third power pin and the fourth power pin are both connected to the second end of the power plane. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0015] In a possible implementation, the first end of C1 is connected to the fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of C1 is connected to the first ground pin. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0016] In a possible implementation, the power input terminal of the board-level network module is connected to the power output terminal of the VRM; the VRM includes a power supply, the power supply is a power management chip PMIC module, the power output terminal of the PMIC is connected to the sixth power pin of the PCB, the sixth power pin is connected to the first end of the power plane; the ground terminal of the PMIC is connected to the second ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0017] In a possible implementation, the power output end of the board-level network module is connected to the power input end of the load; the load is a first chip, the power input end of the first chip is connected to the seventh power pin of the PCB, and the seventh power pin is connected to the second end of the power plane; the ground end of the first chip is connected to the third ground pin of the PCB. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0018] In a possible implementation manner, the resistance values ​​of R1 and R2 are both less than 20 mΩ. In this way, the parallel connection of the sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0019] In a possible implementation, the equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R1; the equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R2. In this way, the parallel connection of sampling resistors R1 and R2 can effectively reduce the equivalent resistance, save space integration area, and improve the PDN impedance suppression effect.

[0020] In a third aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes a power distribution network PDN system as described in the first aspect or any possible implementation of the first aspect.

[0021] In a fourth aspect, an embodiment of the present application provides a printed circuit board assembly (PCBA), wherein the printed circuit board assembly includes a power distribution network PDN system as described in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A It is a structural schematic diagram of a power distribution network system provided in an embodiment of the present application; Figure 1B It is a simplified cross-sectional schematic diagram of the structure of a power distribution network system provided by an embodiment of the present application; Figure 1C is a schematic diagram of an equivalent circuit structure of a power distribution network provided in an embodiment of the present application; Figure 2 is a PDN impedance curve diagram proposed in an embodiment of the present application; Figure 3 It is a schematic diagram of various capacitance Z parameter curves proposed in the embodiment of the present application; Figure 4 is a schematic diagram of impedance curves of a PDN system at different frequencies proposed in an embodiment of the present application; Figure 5A is a structural schematic diagram of another power distribution network system provided in an embodiment of the present application; Figure 5B is a schematic diagram of an equivalent circuit structure of a PDN system provided in an embodiment of the present application; Figure 5C It is a simplified schematic diagram of a cross section of a board-level network module and a load in a PDN system provided by an embodiment of the present application; Fig. 6A It is a structural schematic diagram of a power distribution network system provided in an embodiment of the present application; Figure 6B It is a simplified cross-sectional schematic diagram of the structure of a power distribution network system provided by an embodiment of the present application; Figure 6C is a schematic diagram of an equivalent circuit structure of a power distribution network provided in an embodiment of the present application; Figure 7A to Figure 7C is a graph of frequency and impedance when a set of different numbers of sampling resistors are provided in an embodiment of the present application; Figure 8 This is a schematic diagram of a group of PCB board circuit structures provided in an embodiment of the present application; Fig. 9 It is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to be used as limitations to the present application. As used in the specification and appended claims of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear indication to the contrary in the context. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more listed items.

[0024] The following first introduces the terms involved in the embodiments of the present application.

[0025] The power distribution network (PDN) refers to the circuit path that transmits power from the power supply end to the load. The current flows from the power supply end to the load end through the power plane of the PDN, and then flows from the load end back to the power supply end through the ground plane of the PDN. The main function of the PDN is to provide a stable voltage for the load, quickly respond to changes in load current, reduce noise, and ensure the quality of the power waveform.

[0026] The impedance of an ideal power supply system is zero, but in reality there are various noises. For example, there is noise in the output voltage of the power management chip; voltage drops caused by the inability of the load current to respond quickly; voltage fluctuations caused by the impedance of the power supply path and the ground loop, etc. The circuit power supply works within a certain degree of noise tolerance. If the noise of the power supply exceeds the range allowed by the system, the system cannot work normally.

[0027] PDN can include voltage regulator module (VRM), filter capacitors, bypass / decoupling capacitors, vias, interconnects, printed circuit board (PCB) plane capacitors, package solder balls / pins, capacitors in device packages, bonding wires, and load devices. PCB boards can connect various load devices and decoupling capacitors of voltage regulator modules. PCB boards can include power planes, ground planes, wires, cables, interfaces, etc. The power supply path of the power supply is the path from the output voltage of the VRM to the transmission to the load through the PCB.

[0028] Combine the following Figure 1A to Figure 1C The system structure of PDN is described in detail.

[0029] Figure 1A Schematic diagram of a power distribution network system provided by way of example in an embodiment of the present application. Figure 1A As shown, the power distribution network may include a VRM, a board-level network module and a load. Among them, the voltage regulation module includes a power supply, for example, the power supply is a power management integrated chip PMIC module, and the PMIC can supply power to each load through the PDN network. The board-level network module is an intermediate power supply network connecting the VRM and the load, and has the function of PDN suppression impedance. The board-level network module includes a decoupling capacitor, that is, the board-level network module connects the decoupling capacitor between the power plane and the ground plane. The voltage regulation module is connected to the power input end of the board-level network module through the power output end, and the power output end of the board-level network module is connected to the load. The ground wires of the VRM, the board-level network module and the load are connected, that is, the VRM, the board-level network module and the load are all connected to the ground plane of the PCB board.

[0030] Combination Figure 1A The power distribution network system shown in Figure 1B A simplified cross-sectional schematic diagram of the structure of a power distribution network system is specifically provided for the power distribution network system. Figure 1B As shown in FIG. 1 , the PDN system includes VRM, large capacitor C1, small capacitor C2, chip and part of PCB. Among them, each component of the PDN system is packaged on the PCB board, and the chip is the load of the PDN system. The PCB board includes power lines and ground lines. The power lines are Figure 1B The solid line in the figure can also be called the power plane; the ground line is Figure 1BThe dotted line in the figure can also be called the ground plane. The VRM is connected to the PCB board through the power pin and the ground pin. The board-level network module includes a large capacitor and a small capacitor, and the two ends of the large capacitor and the small capacitor are respectively connected to the power line and the ground line of the PCB, wherein both the large capacitor and the small capacitor can be connected to the power line of the PCB through the power pin, and both the large capacitor and the small capacitor can be connected to the ground line of the PCB through the ground pin. The small capacitor can be a ceramic capacitor, and both the large capacitor and the small capacitor are decoupling capacitors. In addition, it should be noted that the large capacitor and the small capacitor are capacitors formed by multiple capacitors connected at both ends of the power line and the ground line. The large capacitor can suppress the PDN impedance in the higher frequency band, and the small capacitor can suppress the PDN impedance in the lower frequency band. Figure 1B The load in the power distribution network is a chip, and the chip can be connected to the power line and ground line of the PCB through different package solder balls. Optionally, multiple pairs of package solder balls of the chip can be connected to the power line and ground line of the PCB board, and this application does not limit the number of connections.

[0031] Figure 1C Schematic diagram of an equivalent circuit structure of a power distribution network provided exemplarily in an embodiment of the present application. Figure 1C As shown, the power distribution network may include VRM, board-level network modules, and package power layers.

[0032] The VRM includes a power supply, the board-level network module includes a large capacitor C1 and a small capacitor C2, and the package power layer includes a package capacitor C3 and an on-chip capacitor C4. Among them, the board-level network module can also be called a PCB power layer, the large capacitor C1 can be a large-capacity capacitor, and the small capacitor C2 can be a ceramic capacitor. The large capacitor C1 can be equivalent to a series structure of a resistor Rc1, a capacitor Cc1, and an inductor Lc1; the small capacitor C2 can be equivalent to a series structure of a resistor Rc2, a capacitor Cc2, and an inductor Lc2; the package capacitor C3 can be equivalent to a series structure of a resistor Rc3, a capacitor Cc3, and an inductor Lc3; the on-chip capacitor C4 can be equivalent to a series structure of a resistor Rc4, a capacitor Cc4, and an inductor Lc4. The plane and through hole of the board-level network module of the PCB are equivalent to an inductor L1. A ball and through hole of the package power layer can be equivalent to a parasitic inductor L2, and a bump can be equivalent to an inductor L3.

[0033] The positive output terminal of the power supply is connected to the first end of Rc1, the first end of Rc2 and the first end of L1. The second end of Rc1 is connected to the first end of Cc1, and the second end of Cc1 is connected to the first end of Lc1; the second end of Rc2 is connected to the first end of Cc2, and the second end of Cc2 is connected to the first end of Lc2; the second end of L1 is connected to the first end of L2; the second end of L2 is connected to the first end of Rc3 and the first end of L3. The second end of Rc3 is connected to the first end of Cc3, and the second end of Cc3 is connected to the first end of Lc3; the second end of L3 is connected to the first end of Rc4 and the power input terminal of the load. The second end of Rc4 is connected to the first end of Cc4, and the second end of Cc4 is connected to the first end of Lc4. The second end of Lc1, the second end of Lc2, the third end of Lc3, the fourth end of Lc4, the ground terminal of the power supply and the ground terminal of the load are all grounded.

[0034] Since the impedance of the PDN network is related to the frequency, the voltage consumed by the PDN changes with the frequency. In order to reduce the voltage fluctuation of the integrated circuit, the impedance of the PDN needs to be controlled within a certain range. Figure 2 and Figure 3 This paper describes the impedance change of the PDN system and the method of suppressing impedance.

[0035] Figure 2 : is a PDN impedance curve diagram exemplarily disclosed in an embodiment of the present application. Figure 2 As shown in the figure, the impedance value of the PDN circuit changes at different frequencies. The horizontal axis is the frequency and the vertical axis is the impedance value. Figure 1B The frequency of the power distribution network can be divided into the following sections based on the modules of the power distribution network. In the frequency range from DC to 10kHz, the VRM can determine the impedance value of the PDN. In the frequency range from 10kHz to several hundred kHz, the large capacitor can determine the impedance value of the PDN. In the range from several hundred kHz to tens of MHz, the impedance value of the PDN can be determined by a small capacitor. In the range greater than one hundred MHz, the impedance value of the PDN can be determined by the capacitance adjustment circuit inside the load, for example, the internal capacitance of the chip, that is, the on-chip capacitor determines the impedance of the power distribution network at the highest frequency band. Among them, the large capacitor can be a bulk cap, for example, a body capacitor; the small capacitor can be an SMT caps, for example, a ceramic decoupling capacitor.

[0036] like Figure 2As shown, there is parasitic inductance in the connection process between the circuit and the chip. For example, parasitic inductance in the package, package leads, vias, and the connection between the vias and the power / ground plane, etc. Parasitic inductance increases the impedance of high-frequency circuits. This makes it impossible to reduce the impedance of the power distribution network below the package pins regardless of the board-level power supply design. Therefore, high frequencies are limited by the influence of chip package parasitic parameters, and it is difficult to suppress the impedance of the PDN through board-level decoupling capacitors, and the PDN impedance in the high-frequency band requires large capacitors to suppress. In addition, the suppression of high-frequency PDN impedance requires the layout of multiple capacitors, and multiple capacitors will take up more space on the PCB board.

[0037] Figure 3 It is a schematic diagram of various capacitance Z parameter curves disclosed exemplarily in an embodiment of the present application. Figure 3 The capacitor types included are: 1uF0201, 22uF0603, 4.7uF0402, 10uF0402, 10uFTri and 4.3uFTri. Among them, the actual capacitor resonant frequency of 4.7uF0402 is 70MHz; the actual capacitor resonant frequency of 1uF0201 and 4.3uFTri is 10MHz; the actual capacitor resonant frequency of 10uFTri is 8MHz; the actual capacitor resonant frequency of 10uF0402 is 5MHz; the actual capacitor resonant frequency of 22uF0603 is 2MHz. It can be seen that in order to meet the impedance requirements of the PDN system, multiple capacitors need to be connected in parallel at both ends of the power line and the ground line to effectively suppress the impedance.

[0038] Figure 4 Schematic diagram of impedance curves of different frequency bands in different situations in a PDN network with an additional sampling resistor according to an embodiment of the present application. Figure 4 The figure shows the impedance curve of the PDN system at different frequencies. Assuming the standard impedance is 0.2Ω, the standard impedance is the impedance critical value that controls the impedance of all frequency bands not to exceed, that is, the target impedance set by the PDN system. When no capacitor is connected, the impedance exceeds the standard impedance at around 10MHz, resulting in the PDN impedance suppression not meeting the standard. When two capacitors are connected, the impedance exceeds the standard impedance at around 60MHz. The imaginary impedance exceeds the standard impedance at around 100MHz. When only a 100nF capacitor is connected, the impedance drops again at 5MHz, and the impedance exceeds the standard impedance at around 100MHz. Combined with Figure 4 From the curve changes, we can see that different capacitors have different effects on PDN impedance, and large capacitors need to be packaged on the PDN system in terminal products. In the face of the impedance increase caused by inductance and IC load packaging, it is further necessary to add multiple large capacitors to suppress the PDN curve in the mid- and high-frequency bands to meet the impedance suppression goal.

[0039] Combined with the above Figure 1A to Figure 1CIn the PDN system shown, in order to protect the load, the board-level network module of the PDN needs to have the ability to detect current. The function of detecting current can prevent the current or voltage from being too high and burning the circuit, or read the current data for the call of other functions of the electronic device, etc. Therefore, in the board-level network module of the PDN, a sampling resistor needs to be connected in series in the power plane. The voltage across the sampling resistor can be measured, so that the current flowing through the power line can be determined, that is, the ratio of the voltage across the sampling resistor to the resistance value of the sampling resistor. Among them, the sampling resistor is also called the current detection resistor. The sampling resistor is a resistor device with high precision and low resistance. Therefore, it has little effect on the impedance at low frequencies when connected in series to the power line, and almost no effect on the impedance at high frequencies.

[0040] Combine the following Figure 5A to Figure 5C Describe the PDN system formed by connecting a sampling resistor in series.

[0041] Figure 5A is another schematic diagram of the PDN system structure provided by the embodiment of the present application. Figure 5A As shown, the board-level network module includes a sampling resistor R1, a first capacitor C1 and a second capacitor C2, and the electronic device can connect the two ends of R1 to the power line. The power output end of the VRM is connected to the first end of R1, and the second end of R1 is connected to the first end of the first capacitor C1 and the first end of the second capacitor C2. The second end of the first capacitor C1 and the second end of the second capacitor C2 are both grounded. Among them, the first capacitor C1 and the second capacitor C2 can be multiple capacitors connected to both ends of the power plane and the ground plane, and the number is not limited. Among them, due to the significant increase in ESL, the curve of the PDN in the high frequency band is raised, and the decoupling capacitors can be added in parallel, and the total capacitance of the decoupling capacitors can be increased, so that the PDN impedance above 25MHz can be suppressed to meet the constraint conditions of the target impedance.

[0042] At high frequencies, the spreading inductance of the power-ground plane pair also affects the PDN impedance. Using larger plane capacitors can provide higher capacitance values, thereby maintaining lower impedance at high frequencies. At high frequencies, the suppression of PDN impedance mainly depends on the selection and configuration of capacitors. Multiple large-value capacitors are required to effectively provide energy compensation at high frequencies and reduce power supply noise and voltage fluctuations.

[0043] Figure 5B yes Figure 5A The equivalent circuit diagram of the board-level network module in the PDN system. Figure 5B As shown, the sampling resistor R1 can be equivalent to the series connection of the resistor Rb and the inductor Lb, and C1 is equivalent to the capacitor C c1 , resistor R c1 and inductor L c1 series; C2 is equivalent to capacitor Cc2 , resistor R c2 and inductor L c2 The power input end of the board-level network module equivalent circuit is connected to the first end of Rb, the second end of Rb is connected to the first end of Lb, and the second end of Lb is connected to C c1 The first end and C c2 The first end, C c1 The second end of the R c1 First end, R c1 The second end of the L c1 First end, L c1 The second end of C is grounded. c2 The second end of the R c2 First end, R c2 The second end of the L c2 First end, L c2 The second end of Lb, C c1 The first end and C c2 The first end of the board-level network module is used as the power output end of the board-level network module and connected to the power input end of the load. In addition, other connections and contents of the VRM, load, and board-level network module can be referred to Figure 1A and Figure 5A The relevant description is not repeated here.

[0044] Combination Figure 5A and Figure 5B The structural diagram of the board-level network module is shown in FIG. Figure 5C A simplified schematic diagram of a cross-section of board-level network modules and loads in a PDN system is provided. Figure 5C As shown, the solid line in the PCB board is the power line, and the dotted line is the ground line. Among them, the two ends of the first resistor R1 are connected to the power line through two power pins, and the first capacitor C1 and the second capacitor C2 are connected to the power pin and the ground pin respectively. The chip device can connect the power line and the ground line of the PCB board through a pair of package solder balls. Optionally, the chip can connect the power line and the ground line through multiple pairs of package solder balls, and the application does not limit the number of connections.

[0045] Combination Figure 5A to Figure 5C In the PDN system shown, the sampling resistor R1 is connected to the power line to detect the current value of the power path. However, due to the non-ideal characteristics of the resistor, that is, the resistor contains equivalent inductance ESL, such as Figure 5B The addition of the sampling resistor in Lb causes the overall impedance of the PDN system to increase, which in turn causes the PDN to be unable to meet the constraint conditions of impedance suppression.

[0046] Specifically, the impedance of the power network is Z=R+jwL+1 / jwC, where R is the equivalent resistance in the PDN network, L is the equivalent inductance in the PDN network, and C is the equivalent capacitance in the PDN network. Due to the addition of the sampling resistor R1, both R and L increase, causing the overall impedance of the power network to increase. The increase in L will affect the voltage in the corresponding high frequency band, causing charging problems. In order to solve the above problems, Figure 1A to Figure 1C On the basis of, continue to connect capacitors of corresponding frequency bands at both ends of the power plane and the ground plane. For example, Figure 5A A third capacitor C3 is connected in parallel with C2, and so on. Among them, Figure 5A C3 is not shown.

[0047] It can be seen that since the sampling resistor introduces equivalent capacitance, the electronic device needs to connect two inductors to effectively suppress the impedance. For example, a high-frequency PDN with limited PCB layout space usually requires multiple 0603 capacitors to suppress the PDN. The 0603 capacitor occupies 1.28mm of the board area. 2 , 0201 sampling resistor occupies 0.18mm board area 2 High-frequency PDN suppression usually requires multiple 0603 capacitors to suppress PDN, so a single sampling branch will bring at least 2*1.28mm 2 =2.56mm 2 Area consumption. Generally speaking, the larger the capacitor volume, the larger the corresponding capacitance value. It can be seen that the higher the frequency of PDN suppression, the larger the parameters of the required capacitor, the larger the volume of the capacitor, and the more integrated space it occupies. Therefore, the PCB layout space consumption is serious. The branch of a single sampling resistor will occupy more PCB area, and the competitiveness of terminal high-density PCBs will be sharply weakened.

[0048] In response to the above problems, the embodiments of the present application propose a PDN system and an electronic device. The board-level network module of the PDN system may include at least two sampling resistors. That is, on the basis of connecting a first sampling resistor to the power line, a second sampling resistor is connected in parallel with the existing first sampling resistor. The parallel structure of the first sampling resistor and the second sampling resistor has reduced equivalent inductance and resistance, which can suppress the PDN impedance and reduce the number of capacitors used. Generally, the integration space of the resistor is smaller than the multi-layer space of the capacitor, which can save the space of the PCB board and improve the space density of the PCB board.

[0049] Combine the following Figure 6A to Figure 6C The PDN system proposed in this application is described.

[0050] Fig. 6A Schematic diagram of a PDN system structure disclosed in an exemplary embodiment of the present application. Fig. 6AAs shown, the board-level network module of the PDN may include a first sampling resistor R1, a second sampling resistor R2 and a first capacitor C1. Among them, the first capacitor C1 can be a large-capacity capacitor. The power input terminal of the board-level network module is connected to the first end of R1 and the first end of R2. The second end of R1 and the second end of R2 are connected to the first end of the first capacitor C1 and serve as the power output terminal of the board-level network module. The second end of C1 is grounded. In an embodiment of the present application, the impedance of the PDN can be effectively suppressed by adding a second sampling resistor in parallel with the first sampling resistor. The number of connections of the first capacitor C1 is not one capacitor, but can be multiple capacitors. The present application does not limit the number of connected capacitors. In addition, Fig. 6A The second sampling resistor R2 is added in Figure 5A The solution reduces the number of connected capacitors in the first capacitor C1, that is, reduces one or more capacitors, which can save the integration space of the PCB board.

[0051] Optionally, the range of R1 and R2 is 0~20mΩ, that is, R1 and R2 are both less than 20mΩ. The inductive reactance value of parasitic inductance increases with the increase of frequency. For example, the inductive reactance at 1MHz is only about 0.4mΩ, the inductive reactance value of ESL at 24MHz is about 58mΩ, and the inductive reactance value of ESL at 200MHz is about 209mΩ. Generally, R1 and R2 use small resistance values ​​under high current conditions, and avoid using too large resistance, because large resistance will cause PDN to rise, which will affect the PDN suppression effect.

[0052] It should be noted that the board-level network module can also increase the number of sampling resistors, that is, the PDN system can include a third sampling resistor R3. The connection method of R3 is connected in parallel with R2 and R1. Please refer to the connection method of R2 and will not be repeated. In this way, the impedance can be further reduced. The number of sampling resistors in the PDN system is at most 3. On the one hand, although increasing the sampling resistor can suppress the PDN impedance, the circuit integration area will also increase; on the other hand, the increase in the sampling resistor will reduce the effect of suppressing the PDN impedance, and the effect of increasing the sampling resistor will be reduced. Therefore, the number of sampling resistors in parallel should be 2 or 3 for the best benefit. Among them, R3 is Fig. 6A Not shown.

[0053] Combination Fig. 6A The PDN system shown, Figure 6B A simplified cross-sectional diagram of the board-level network modules and loads of the disclosed PDN system structure. Figure 6B As shown, the solid line in the PCB board is the power line, and the dotted line is the ground line. The first sampling resistor R1 and the second sampling resistor R2 are connected to the power line through two power pins, and the first capacitor C1 is connected to the power pin and the ground pin respectively. The chip device can be connected to the power line and the ground line of the PCB board through a pair of package solder balls.

[0054] For example, Figure 6B As shown, the PDN system includes a PCB board, and the PCB board includes a power plane and a ground plane. The first end of R1 is connected to the first power pin of the PCB; the first end of R2 is connected to the second power pin of the PCB; the first power pin and the second power pin are both connected to the first end of the power plane; the second end of R1 is connected to the third power pin of the PCB; the second end of R2 is connected to the fourth power pin of the PCB; the third power pin and the fourth power pin are both connected to the second end of the power plane. The first end of C1 is connected to the fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of C1 is connected to the first ground pin. The power supply can be a power management chip PMIC module, the power output end of the PMIC is connected to the sixth power pin of the PCB, and the sixth power pin is connected to the first end of the power plane; the ground end of the PMIC is connected to the second ground pin of the PCB. The load can be a first chip, the power input end of the first chip is connected to the seventh power pin of the PCB, and the seventh power pin is connected to the second end of the power plane; the ground end of the first chip is connected to the third ground pin of the PCB.

[0055] Combination Fig. 6A and Figure 6B The PDN system shown, Figure 6C Schematic diagram of an equivalent circuit of a PDN structure provided by an embodiment of the present application. Figure 6C As shown, R1 is equivalent to the series structure of resistor Rb1 and inductor Lb1, R2 is equivalent to the series structure of resistor Rb2 and inductor Lb2, and C1 is equivalent to capacitor C c1 , resistor R c1 and inductor L c1 Series structure. After the above equivalence, the power input end of the board-level network module is connected to the first end of the resistor Rb1 and the first end of the resistor Rb2. The second end of Rb1 is connected to the first end of Lb1, and the second end of the resistor Rb2 is connected to the first end of Lb2. The second end of Lb1 is connected to the second end of Lb2 and the first end of Cc1. The second end of Cc1 is connected to the first end of Rc1, the second end of Rc1 is connected to the first end of Lc1, and the second end of Lc1 is grounded. The second end of Lb1, the second end of Lb2 and the first end of Cc1 serve as the power output end of the board-level network module.

[0056] It should be noted that, combined with the impedance of the power supply network Z = R + jwL + 1 / jwC, the real impedance affects the low-frequency signal, and the imaginary impedance affects the high-frequency signal. Therefore, the parallel sampling resistor can reduce the size of the equivalent inductance. For example, assuming Figure 6CR1 and R2 are equivalent to inductors Lb1 and Lb2 respectively. The two inductors are connected in parallel, which makes the inductance drop rapidly. That is, the equivalent inductance after parallel connection is Lb=(Lb1×Lb1) / (Lb1+Lb1). If the two inductors are equal, the inductance after parallel connection is reduced by half of the original. In this way, the PDN impedance suppression effect can be significantly improved.

[0057] Figure 7A to Figure 7C It is a curve diagram between frequency and impedance when different numbers of sampling resistors are disclosed in an exemplary embodiment of the present application. Fig. 7A It is a curve diagram of the PDN impedance frequency corresponding to a single 5mΩ resistor and two 5mΩ resistor solutions disclosed in the embodiment of the present application. Among them, the solid line is the curve diagram when a 5mΩ resistor is connected in series on the PDN power line, and the dotted line is the curve diagram when two parallel 5mΩ resistors are connected in series on the PDN power line. After comparison, it can be seen that in the frequency range of 1KHz~500MHz, the PDN impedance in the solution of two 5mΩ resistors is much smaller than the PDN impedance in the solution of one 5mΩ resistor. Therefore, Figure 6A to Figure 6C The embodiments can effectively suppress the impedance of the PDN.

[0058] Figure 7B This is an impedance frequency curve diagram of the real part, imaginary part and Z value corresponding to a PDN system of two 5mΩ resistor solutions disclosed in an embodiment of the present application. Figure 7C This is an impedance frequency curve diagram of the real part, imaginary part and Z value corresponding to a PDN system of a single 5mΩ resistor solution disclosed in an embodiment of the present application. Figure 7B and Figure 7C By comparing the two 5mΩ resistors, it can be found that the equivalent resistance ESL of the imaginary part in the two 5mΩ resistor solution will be greatly reduced in the high frequency band. Figure 6A to Figure 6C The solution can effectively suppress high-frequency PDN impedance.

[0059] go through Figure 7A to Figure 7C The comparison shows that in the range of 25MHz~1GHz, adding a second sampling resistor in parallel with the first sampling resistor can significantly reduce the PDN impedance.

[0060] If according to Figure 5A to Figure 5C As shown in the figure, capacitors are added to suppress PDN impedance. For example, high-frequency PDN with limited PCB layout space usually requires multiple 0603 capacitors to suppress PDN, so a single sampling resistor will bring at least 2*1.28mm 2 =2.56mm 2 Area consumption. This application uses a 0201 sampling resistor in parallel, consuming 0.36mm board area. 2The branch of a single sampling resistor will occupy more PCB area. Therefore, multiple sampling resistors do not occupy more PCB area, no longer add multiple large package capacitance Decaps, and can significantly suppress PDN impedance, which can significantly improve the competitiveness of terminal high-density PCBs.

[0061] For example, Figure 8 It is a schematic diagram of a group of PCB board circuit structures disclosed as an example in the embodiments of the present application. Figure 8 (a) is a PCB structure including two 10mΩ parallel sampling resistors connected to the power line. Figure 8 (a) in the figure shows three pairs of 10 mΩ parallel sampling resistors as an example. Figure 8 (b) is a PCB circuit structure including a 5mΩ sampling resistor connected in series to the power line. Figure 8 (b) shows three 5 mΩ sampling resistors as an example. Figure 8 The sampling resistor in (a) and (b) is the framed part. Figure 8 The PCB circuit structure shown in (a) corresponds to Fig. 6A The PDN system is simulated and found that the impedance is 47.46mΩ at a frequency of 24MHz and 366mΩ at a frequency of 200MHz. Figure 8 The PCB circuit structure shown in (b) corresponds to Figure 5A The PDN system is simulated and found that the impedance is 50.96mΩ at a frequency of 24MHz and 383.3mΩ at a frequency of 200MHz. At this time, the target impedance of the current PDN design is Zspec(f=24MHz)=48.1mΩ and Zspec(f=200MHz)=377mΩ. Figure 8 It can be seen from the actual simulation test that when the PCB layout area is limited, reducing the use of large package capacitors to suppress PDN impedance can reduce the occupancy of large PCB areas, and a smaller PCB footprint can be used to complete PDN high-frequency band ESL suppression and meet the suppression requirements of the target impedance PDNspec, thereby improving product competitiveness.

[0062] The electronic device in the embodiments of the present application can be a tablet computer, a mobile phone, a desktop, a laptop computer, a handheld computer, a smart bracelet, a super mobile personal computer, a netbook, a personal phone, a personal data assistant, an augmented reality (AR) / virtual reality (VR) and other touch screen devices. The present application does not limit the specific form of the electronic device.

[0063] The following is an introduction to the device involved in the embodiments of the present application.

[0064] Fig. 9A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application.

[0065] The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0066] It is to be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0067] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0068] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0069] It is understandable that the interface connection relationship between the modules illustrated in the embodiments of the present application is only a schematic illustration and does not constitute a structural limitation on the electronic device. In other embodiments of the present application, the electronic device may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0070] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the external memory, the display screen 194, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, and battery health status. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device. In the embodiment of the present application, the power management module 141 may include a VRM.

[0071] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integration. The available medium can be a magnetic medium, an optical medium, or a semiconductor medium, etc.

[0072] Those skilled in the art can understand that to implement all or part of the processes in the above-mentioned embodiments, the processes can be completed by computer programs to instruct related hardware, and the programs can be stored in computer-readable storage media. When the programs are executed, they can include the processes of the above-mentioned method embodiments. The aforementioned storage media include: ROM or random access memory RAM, magnetic disk or optical disk and other media that can store program codes.

Claims

1. A power distribution network PDN system, characterized in that: The PDN system includes a voltage regulation module VRM, a board-level network module and a load; The VRM includes a power supply, the board-level network module includes a first sampling resistor R1, a second sampling resistor R2 and a first capacitor C1, and the power supply supplies power to the load through the board-level network module; The power output end of the VRM is connected to the first end of R1 and the first end of R2; the second end of R1 and the second end of R2 are connected to the first end of C1 and the power input end of the load, and the second end of C1 is grounded.

2. The system according to claim 1, characterized in that The PDN system includes a PCB board, which includes a power plane and a ground plane. The first end of the R1 is connected to the first power pin of the PCB; the first end of the R2 is connected to the second power pin of the PCB; the first power pin and the second power pin are both connected to the first end of the power plane; the second end of the R1 is connected to the third power pin of the PCB; the second end of the R2 is connected to the fourth power pin of the PCB; the third power pin and the fourth power pin are both connected to the second end of the power plane.

3. The system according to claim 2, characterized in that The first end of C1 is connected to the fifth power pin; the fifth power pin is connected to the second end of the power plane; the second end of C1 is connected to the first ground pin.

4. The system according to claim 2 or 3, characterized in that: The power supply is a power management chip PMIC module, the power output end of the PMIC is connected to the sixth power pin of the PCB, the sixth power pin is connected to the first end of the power plane; the ground end of the PMIC is connected to the second ground pin of the PCB.

5. The system according to claim 2 or 3, characterized in that: The load is a first chip, a power input end of the first chip is connected to the seventh power pin of the PCB, and the seventh power pin is connected to the second end of the power plane; and a ground end of the first chip is connected to the third ground pin of the PCB.

6. The system according to any one of claims 1 to 3, characterized in that: The resistance values ​​of R1 and R2 are both less than 20 mΩ.

7. The system according to any one of claims 1 to 3, characterized in that: The equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R1; the equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R2.

8. An electronic device, characterized in that: Comprising a PDN system as described in any one of claims 1-7.

9. A board-level network module, characterized in that: The board-level network module is applied to a PDN system, and the board-level network module includes a first sampling resistor R1, a second sampling resistor R2 and a first capacitor C1; Among them, the first end of the R1 and the first end of the R2 are used to connect the power output end of the VRM in the PDN system; the second end of the R1 and the second end of the R2 are used to connect the first end of the C1 and the power input end of the load in the PDN system, and the second end of the C1 is grounded.

10. The module according to claim 9, characterized in that The equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R1; the equivalent inductance ESL of the parallel structure of R1 and R2 is smaller than the equivalent inductance of R2.

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