Power stage of switching voltage regulator and voltage regulation module

Abstract

The invention provides a power stage of a voltage regulator. The power stage comprises a high-side switch, a low-side switch, a gate driver, a power management module, a bootstrap capacitor and a refresh module. The power management module is used for receiving a power control signal, and when the power control signal is in a first state, the high-side switch and the low-side switch are both switched to a closed state. The bootstrap capacitor is used for enabling the high-side switch to be turned on, and the voltage across the two ends of the bootstrap capacitor is equal to or larger than a first threshold voltage. The refreshing module is used for refreshing the bootstrap capacitor to keep the cross voltage of the bootstrap capacitor equal to or greater than the first threshold voltage if the high-side switch and the low-side switch are continuously kept in the closed state when the power supply control signal is in the first state. The cross voltage between the first end and the second end of the bootstrap capacitor is kept equal to or greater than the first threshold voltage, so that the bootstrap capacitor can always provide enough voltage for the on / off of the high-side switch and the low-side switch. In addition, the invention also provides a voltage regulation module.

Description

[0001] Priority declaration

[0002] This application claims priority to Indian Provisional Patent Application No. 202341084703 (Attorney Docket No. AURA-354-INPR), filed on December 12, 2023, entitled “REFRESH ENABLE ON SYNC HI-Z”. The entire contents of the Indian Provisional Patent Application are incorporated herein, except to the extent that they are not inconsistent with the description herein. Technical Field

[0003] The present application generally relates to power supply circuits, and more particularly to a power stage and a voltage regulation module of a voltage regulator. Background Art

[0004] As we all know, a switching converter is a component that uses one or more switches to generate a regulated direct current (DC) voltage from an input power source. It is widely used in devices such as computers and mobile phones.

[0005] As we all know, the power stage is a basic building block of the switching converter, which usually includes a pair of series-connected transistors called high-side switch and low-side switch. These two switches are turned on / off (called "switching") in alternating time periods, so that the power stage produces the required regulated DC voltage.

[0006] A bootstrap capacitor can be used to provide the required voltage level for turning on / off the switch in the power stage. For example, when the high-side switch is an NMOS transistor (N-channel Metal Oxide Semiconductor Field Effect Transistor), a bootstrap capacitor is usually used to help generate the voltage required to turn on the high-side switch.

[0007] In some cases, the bootstrap capacitor may not have enough voltage to perform the required switching operation, and then its voltage may need to be refreshed (ie, restored to the required voltage). The present application relates to the refreshing operation of the bootstrap capacitor. Summary of the invention

[0008] In view of this, the present application provides a power stage and a voltage regulation module of a switching voltage regulator, which can refresh the bootstrap capacitor.

[0009] In a first aspect, the present application provides a power stage of a voltage regulator, comprising: a high-side switch, a low-side switch, a gate driver, a power management module, a bootstrap capacitor, and a refresh module. The high-side switch and the low-side switch are connected in series between an external power supply and a constant reference potential at an input node, and are controlled by a first drive signal and a second drive signal, respectively; wherein the first drive signal and the second drive signal are activated in a high-side phase and a low-side phase, respectively, to drive a corresponding current through an inductor, thereby providing a regulated output voltage. The gate driver is used to generate the first drive signal and the second drive signal based on a control signal received from a phase controller, wherein the control signal received in a first time period and a second time period is a first logic level and a second logic level, respectively. The power management module is used to receive a power control signal, and if the power control signal is in a first state, the power management module switches both the high-side switch and the low-side switch to an off state. The first end of the bootstrap capacitor is connected to the control end of the high-side switch, and the second end is connected to the first current end of the high-side switch. The bootstrap capacitor is used to enable the high-side switch to be turned on; wherein the voltage across the first end and the second end of the bootstrap capacitor is equal to or greater than a first threshold voltage to maintain stable operation of the high-side switch. The refresh module is used to refresh the bootstrap capacitor when the power control signal is in the first state, if the high-side switch and the low-side switch continue to remain in the closed state, so as to keep its voltage across the bootstrap capacitor equal to or greater than the first threshold voltage.

[0010] Further, when the power control signal is in a first state, it indicates that the power stage does not generate the regulated output voltage, and when the power control signal is in the first state, the cross voltage is maintained above the first threshold voltage, so that when the power control signal changes to a second state indicating that the power stage is to generate the regulated output voltage, the high-side switch can quickly start generating the regulated output voltage.

[0011] Furthermore, the power management module receives the power control signal and determines whether the power control signal is in a first state. If the power control signal is in the first state, a shutdown signal is generated to switch both the high-side switch and the low-side switch to a shutdown state.

[0012] Furthermore, the power stage also includes a detection module for detecting whether the voltage at the second end of the bootstrap capacitor is higher than a second threshold voltage. The detection module is used to receive the shutdown signal, and only when the voltage at the second end of the bootstrap capacitor is higher than the second threshold voltage, the refresh module refreshes the bootstrap capacitor to keep the cross-voltage higher than the first threshold voltage.

[0013] Furthermore, the power stage also includes a charging circuit for charging the bootstrap capacitor from a low-voltage power supply; when the power control signal is in a first state, the second threshold voltage represents the maximum voltage value that can be reached at the second end of the bootstrap capacitor, and the maximum voltage value enables the charging circuit to charge the bootstrap capacitor to keep the cross-voltage at least equal to the first threshold voltage, wherein the refresh module uses an external power supply to refresh the bootstrap capacitor, and the output voltage of the external power supply is greater than the output voltage of the low-voltage power supply.

[0014] Furthermore, the detection module includes: an inverter circuit and a logic inverter. The inverter circuit is set to have a flip point equal to the threshold voltage of the MOSFET, and the inverter circuit is connected to the second end of the bootstrap capacitor to receive its voltage; when the voltage of the second end of the bootstrap capacitor is higher than the second threshold voltage, the inverter circuit generates a logic low level signal as its output signal, otherwise it generates a logic high level signal as its output signal; the logic inverter is used to generate a logic inversion signal of the output signal of the inverter circuit.

[0015] Further, the refresh module includes: a first PMOS, a first NMOS and a current sink connected in series between the input node and the constant reference potential; a second PMOS, a second NMOS and a first resistor connected in series between the input node and the second end of the bootstrap capacitor; and a diode, a third NMOS and a second resistor connected in series between the input node and the first end of the bootstrap capacitor. The first PMOS and the second PMOS are connected in a current mirror configuration to form a first current mirror, and the second NMOS and the third NMOS are connected in a current mirror configuration to form a second current mirror; the control end of the first NMOS is used to receive the logic inversion signal.

[0016] Further, the current of the current sink is set to be equal to the ratio of the output voltage of the low-voltage power supply to the resistance value of the first resistor, and the resistance value is set so that the current flowing through the second PMOS generates a voltage drop on the second PMOS, and the voltage drop causes each control terminal of the second NMOS and the third NMOS to be biased at a voltage equal to the sum of the voltage of the second end of the bootstrap capacitor, the output voltage of the low-voltage power supply and the threshold voltage of the third NMOS, so as to limit the charging of the bootstrap capacitor to a voltage equal to the output voltage of the low-voltage power supply.

[0017] Further, the inverter circuit includes: a first circuit, a second circuit, a third circuit and a first capacitor. The first circuit includes a third PMOS and a third resistor connected in series between the low-voltage power supply and the first intermediate node, and the source, drain and gate terminals of the third PMOS are respectively connected to the low-voltage power supply, one end of the third resistor and the second intermediate node. The second circuit includes a fourth PMOS connected between the low-voltage power supply and the first intermediate node, and the source, drain and gate of the fourth PMOS are respectively connected to the low-voltage power supply, the first intermediate node and the shutdown signal. The third circuit includes a fourth NMOS and a fifth NMOS connected in series between the first intermediate node and the constant reference potential, and the source, drain and gate of the fourth NMOS are respectively connected to the drain of the fifth NMOS, the first intermediate node and the shutdown signal, and the source and gate terminals of the fifth NMOS are respectively connected to the constant reference potential and the second intermediate node. The first capacitor is connected between the second intermediate node and the constant reference potential, the first circuit and the second circuit are connected in parallel, and the third circuit is connected in series with the first circuit and the second circuit connected in parallel.

[0018] Further, the inverter circuit receives the voltage of the second end of the bootstrap capacitor through a fourth circuit, and the fourth circuit includes a fourth resistor and a sixth NMOS connected in series, the source of the sixth NMOS is connected to the second intermediate node, the drain is connected to the second end of the bootstrap capacitor through the fourth resistor, and the gate is connected to the low-voltage power supply.

[0019] The second aspect of the present application also provides a voltage regulator module (VRM), comprising: a plurality of power stages and a phase controller. The plurality of power stages provide a regulated output voltage on a power supply line. The phase controller is used to control the operation of each of the plurality of power stages to provide the regulated output voltage. Wherein, the first power stage of the plurality of power stages comprises: a high-side switch, a low-side switch, a gate driver, a power management module, a bootstrap capacitor, and a refresh module. The high-side switch and the low-side switch are connected in series between an external power supply of an input node and a constant reference potential, and are controlled by a first drive signal and a second drive signal, respectively, wherein the first drive signal and the second drive signal are activated in a high-side phase and a low-side phase, respectively, to drive a corresponding current through an inductor, thereby providing a regulated output voltage; the gate driver is used to generate the first drive signal and the second drive signal based on a control signal received from the phase controller, wherein the control signals received in a first time period and a second time period are a first logic level and a second logic level, respectively; the power management module is used to receive a power control signal, and if the power control signal is in a first state, the power management module switches both the high-side switch and the low-side switch to a closed state. The first end of the bootstrap capacitor is connected to the control end of the high-side switch, and the second end is connected to the first current end of the high-side switch. The bootstrap capacitor is used to enable the high-side switch to be turned on; wherein the voltage across the first end and the second end of the bootstrap capacitor is equal to or greater than a first threshold voltage to maintain stable operation of the high-side switch. The refresh module is used to refresh the bootstrap capacitor when the power control signal is in the first state, if the high-side switch and the low-side switch continue to remain in the closed state, so as to keep its voltage across the bootstrap capacitor equal to or greater than the first threshold voltage.

[0020] Further, when the power control signal is in a first state, it indicates that the power stage does not generate the regulated output voltage, and when the power control signal is in the first state, the cross voltage is maintained above the first threshold voltage, so that when the power control signal changes to a second state indicating that the power stage is to generate the regulated output voltage, the high-side switch can quickly start generating the regulated output voltage.

[0021] Furthermore, the power management module receives the power control signal and determines whether the power control signal is in a first state. If the power control signal is in the first state, a shutdown signal is generated to switch both the high-side switch and the low-side switch to a shutdown state.

[0022] Furthermore, the first power stage also includes a detection module for detecting whether the voltage at the second end of the bootstrap capacitor is higher than a second threshold voltage. The detection module is used to receive the shutdown signal, and only when the voltage at the second end of the bootstrap capacitor is higher than the second threshold voltage, the refresh module refreshes the bootstrap capacitor to keep the cross-voltage higher than the first threshold voltage.

[0023] Furthermore, the first power stage also includes a charging circuit for charging the bootstrap capacitor from a low-voltage power supply; when the power control signal is in a first state, the second threshold voltage represents the maximum voltage value that can be reached by the second end of the bootstrap capacitor, and the maximum voltage value enables the charging circuit to charge the bootstrap capacitor to keep the cross-voltage at least equal to the first threshold voltage, wherein the refresh module uses the external power supply to refresh the bootstrap capacitor, and the output voltage of the external power supply is greater than the output voltage of the low-voltage power supply.

[0024] Furthermore, the detection module includes an inverter circuit and a logic inverter. The inverter circuit has a flip point equal to the threshold voltage of the MOSFET, and the inverter circuit is connected to the second end of the bootstrap capacitor to receive its voltage. When the voltage of the second end of the bootstrap capacitor is higher than the second threshold voltage, the inverter circuit generates a logic low level signal as its output signal, otherwise it generates a logic high level signal as its output signal. The logic inverter is used to generate a logic inversion signal of the output signal of the inverter circuit.

[0025] Further, the refresh module includes: a first PMOS, a first NMOS and a current sink connected in series between the input node and the constant reference potential; a second PMOS, a second NMOS and a first resistor connected in series between the input node and the second end of the bootstrap capacitor; and a diode, a third NMOS and a second resistor connected in series between the input node and the first end of the bootstrap capacitor; wherein the first PMOS and the second PMOS are connected in a current mirror configuration to form a first current mirror; the second NMOS and the third NMOS are connected in a current mirror configuration to form a second current mirror; and the control end of the first NMOS is used to receive the logic inversion signal.

[0026] Further, the current of the current sink is set to be equal to the ratio of the output voltage of the low-voltage power supply to the resistance value of the first resistor, and the resistance value is set so that the current flowing through the second PMOS generates a voltage drop on the second PMOS, and the voltage drop causes each control terminal of the second NMOS and the third NMOS to be biased at a voltage equal to the sum of the voltage of the second end of the bootstrap capacitor, the output voltage of the low-voltage power supply and the threshold voltage of the third NMOS, so as to limit the charging of the bootstrap capacitor to a voltage equal to the output voltage of the low-voltage power supply.

[0027] Further, the inverter circuit includes: a first circuit, a second circuit, a third circuit and a first capacitor. The first circuit includes a third PMOS and a third resistor connected in series between the low-voltage power supply and the first intermediate node, the source, drain and gate of the third PMOS are respectively connected to the low-voltage power supply, one end of the third resistor and the second intermediate node; the second circuit includes a fourth PMOS connected between the low-voltage power supply and the first intermediate node, the source, drain and gate of the fourth PMOS are respectively connected to the low-voltage power supply, the first intermediate node and the shutdown signal; the third circuit includes a fourth NMOS and a fifth NMOS connected in series between the first intermediate node and the constant reference potential; the source, drain and gate of the fourth NMOS are respectively connected to the drain of the fifth NMOS, the first intermediate node and the shutdown signal, and the source and gate of the fifth NMOS are respectively connected to the constant reference potential and the second intermediate node; the first capacitor is connected between the second intermediate node and the constant reference potential, the first circuit and the second circuit are connected in parallel, and the third circuit is connected in series with the first circuit and the second circuit connected in parallel.

[0028] Further, the inverter circuit receives the voltage of the second end of the bootstrap capacitor through a fourth circuit, and the fourth circuit includes a fourth resistor and a sixth NMOS connected in series, the source of the sixth NMOS is connected to the second intermediate node, the drain is connected to the second end of the bootstrap capacitor through the fourth resistor, and the gate is connected to the low-voltage power supply.

[0029] The power stage of the voltage regulator in the present application can maintain the voltage between the first terminal and the second terminal of the bootstrap capacitor equal to or greater than the first threshold voltage, so that the bootstrap capacitor can always provide sufficient voltage for turning on / off its switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The embodiments of the present application will be described in conjunction with the following drawings.

[0031] Figure 1 It is a system block diagram provided in an embodiment of the present application.

[0032] Figure 2 It is a specific block diagram of the voltage regulation module provided in the embodiment of the present application.

[0033] Figure 3 It is a specific block diagram of the power level provided in the embodiment of the present application.

[0034] Figure 4 It is a specific block diagram of the power level detection module and the refresh module provided in the embodiment of the present application.

[0035] Figure 5 is a timing diagram of the power stage's bootstrap capacitor being refreshed in response to a signal to shut down the power stage.

[0036] In the drawings, like reference numerals generally indicate like, functionally similar, and / or structurally similar elements. In the drawings, the first appearance of an element is indicated by the leftmost digit (or digit combination) of the corresponding reference numeral. DETAILED DESCRIPTION

[0037] 1. Overview

[0038] The power stage of the voltage regulator includes a high-side switch, a low-side switch, a gate driver, a power management module, a bootstrap capacitor, and a refresh module. The power management module is used to receive a power control signal, and when the power control signal is in a first state, the high-side switch and the low-side switch are switched to an off state. The bootstrap capacitor is used to enable the high-side switch to be turned on; wherein, in order to maintain stable operation (i.e., reliable operation) of the high-side switch, the cross-voltage (cross-terminal voltage) between the first end and the second end of the bootstrap capacitor is ensured to be equal to or greater than a first threshold voltage.

[0039] On the other hand, the refresh module is used to refresh the bootstrap capacitor to keep its cross voltage higher than the first threshold voltage when the power control signal is in the first state if the high-side switch and the low-side switch continue to remain in the off state.

[0040] In one embodiment, when the power control signal is in the first state, the refresh module refreshes the bootstrap capacitor only when the voltage at the connection point between the high-side switch and the low-side switch is greater than a second threshold.

[0041] The present application will be described below in conjunction with a plurality of embodiments. However, it should be clear to those skilled in the art that the present application may be implemented by omitting one or more specific features or by other methods, components, materials, etc. In other embodiments, known structures, materials, or operations are not described in detail one by one to simplify the features of the present application. In addition, although only some combinations are described here for the sake of brevity, the described features / aspects may be implemented in various combinations.

[0042] 2. System implementation

[0043] Figure 1 1 is a block diagram of the system provided in this embodiment. The system 100 includes a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and a peripheral 150. In one embodiment, the system 100 may be a computer (a desktop computer, a laptop computer, etc.), and in other embodiments, the system 100 may represent other types of systems. It is understandable that the modules included in the system 100 may be more than Figure 1 More or fewer modules may be shown.

[0044] The central processor 120 is a processor or a system on chip (SoC), and the central processor 120 receives a pair of supply voltages (Va and Vb) from the power supply 110 through lines 112A and 112B. For example, Va may be smaller than the voltage Vb, and Va may be used to power the core part of the central processor 120, which may include an arithmetic logic unit (ALU), a microcontroller, registers, etc. Vb may be used to power the rest of the central processor 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. The central processor 120 provides various signals (all of which are considered to be included in the bidirectional line / bus 121) to the power supply 110, which specify its power supply requirements and other contents. These signals may be signals that specify a specific operating mode (in terms of power consumption) in some embodiments, such as PS1, PS2, PS3, etc., which means "power saving state to improve efficiency". The central processor 120 receives health information of the power stage from the phase controller 210 through the bidirectional line / bus 121.

[0045] The memory 130 represents a memory, which may include a volatile memory or a non-volatile memory. For example, in a personal computer, the memory may include a magnetic memory (hard disk) and a solid-state memory (RAM, flash memory, etc.). The memory 130 receives a power supply voltage through the line 113 to power various circuits and modules inside it.

[0046] The network interface 140 is used to provide two-way communication between the system 100 and a computer network (or the Internet in a broader sense). The network interface 140 implements the use of a specific physical layer and data link layer standard (such as Ethernet or Wi-Fi). TM) for communication. Network interface 140 may also include a network protocol stack to allow large-scale network communication with other computers on the same local area network (LAN) and through routable protocols such as the Internet Protocol (IP). Network interface 140 receives power from a power source via line 114 to power its internal circuits and modules. Network interface 140 receives data from an external system via line 141 and transmits data to CPU 120 via line 124.

[0047] The peripheral device 150 is one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. The peripheral device 150 receives power from a power source through the line 115 and communicates with external devices through the line 151 .

[0048] The power supply 110 receives power from one or more power sources (e.g., batteries, which in turn may be connected to the main power source for charging via a rectifier and a filter) via line 101, and provides the required supply voltage on lines 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 includes one or more multi-phase DC-DC converters (DC-DC) to generate the supply voltage. The power supply 110 receives signals from the central processor 120 via line 121, which may indicate the power mode in which the central processor 120 is to operate during a specific time period, wherein the power mode indicates the amount of power required / consumed by the central processor 120 from the power supply 110. Based on these signals, the power supply 110 controls the multi-phase converter to reduce / increase the current output, depending on the specific power mode signals (e.g., PS1, PS2, and PS3).

[0049] In one embodiment, the power supply 110 is a voltage regulation module, sometimes also referred to as a processor power module (PPM), which includes one or more step-down switching (buck) converters for generating one or more lower voltages from a high voltage power supply. However, in other embodiments, the power supply 110 can also be other types of DC-DC converters, such as a boost converter, a buck-boost converter, a hysteresis converter, etc., instead of a buck converter. In addition, the power supply 110 can also be an independent switching converter with only one power stage (rather than a multi-phase converter). Using a voltage regulation module, multiple devices / integrated circuits (ICs) requiring different supply voltages can be installed on the same platform (e.g., a computer motherboard of a personal computer).

[0050] Next, we will continue to describe Figure 2 Internal details of the voltage regulator module are shown.

[0051] 3. Voltage regulation module

[0052] Figure 2 What is shown is a specific block diagram of the voltage regulation module provided in an embodiment of the present application. The power supply 110 is a multi-phase voltage regulation module, which uses a phase controller and two groups of power stages (each group corresponds to a power supply line, that is, the regulated voltage Va or Vb) to generate two regulated supply voltages Va and Vb. Therefore, the voltage regulation module 110 includes a phase controller 210, smart power stages (Smart Power Sages, SPS, or simply "power stages") SPSA-1 (220-1) to power stages SPSA-6 (220-6), SPSB-1 ​​(230-1) to SPSB-3 (230-3), inductors 225A-1 to 225A-6, 227B-1 to 227B-3, output capacitors 226A-1 to 226A-6, 228B-1 to 228B-3, and bootstrap capacitors 224A-1 to 224A-6, 224B-1 to 224B-3. Each bootstrap capacitor corresponding to each SPS is connected between a switching node (SW) of the corresponding SPS and a bootstrap (BOOT) node.

[0053] The bootstrap capacitor 224A-1 is connected between the switch node SWA-1 (221) and the bootstrap node BOOTA-1 (215). Although the bootstrap capacitor is connected to the outside of each power stage, typically or in other embodiments, the bootstrap capacitor can be located inside the power stage. For ease of description, the voltage at the switch node SWA-1 (221) is referred to as Vsw in this article. Although the multi-phase switching converter described below has independent power stages and phase controllers (usually implemented in the form of integrated circuits (ICs)), those skilled in the art can understand from the disclosure of this application that the features disclosed in this application are also applicable to independent (single-phase) switching converters.

[0054] The supply voltage Va (240) is generated by a six-phase buck switching converter (including six power stages, namely 220-1 to 220-6), while the supply voltage Vb (250) is generated by a three-phase buck switching converter (including three power stages, namely 230-1 to 230-3). Nodes / lines 240 and 250 correspond to Figure 1 For simplicity, Figure 2 Other power supply circuits providing power on lines 113, 114 and 115 are not shown.

[0055] In this embodiment, the phase controller 210 (and the corresponding circuitry therein), the power stage, the inductor, and the capacitor combine to form a "phase" for each of the two multi-phase buck converters. Thus, for example, the power stage SPSA-1, the inductor 225A-1, the capacitor 226A-1, and the corresponding portions within the phase controller 210 together represent one phase of a six-phase buck converter. It should be noted that although each phase has its own independent capacitor (e.g., capacitor 226A-1), in other embodiments, only one larger capacitor (with a larger capacitance) may be used at node 240 (and node 250). In other embodiments, multiple capacitors are placed in close proximity to loads powered by corresponding supply voltages.

[0056] Each power stage may include a high-side switch, a low-side switch, gate drive circuits for the two switches, and other circuits. In some embodiments, if the power stage only needs to operate in discontinuous current mode (DCM), a diode can be used instead of the low-side switch. Circuits in other embodiments include, but are not limited to, temperature monitoring circuits, inductor current detection (or simulation) circuits, etc., to provide information to the phase controller 210, such as the temperature of the power stage, the amplitude of the inductor current, etc. Each power stage will receive electrical energy as input from a power supply, which is connected to a high-side switch (shown in detail below). In Figure 2 In the embodiment, the voltage provided by the power supply 201 is Vin. In the voltage regulation module, the value of Vin is about 21V. Each power stage is powered by the power supply 202, and the voltage provided by the power supply 202 is Vcc, which can be provided by the phase controller 210. In the voltage regulation module, the value of Vcc is about 3.3V.

[0057] Each power stage communicates with the phase controller 210 via corresponding pulse-width modulated (PWM), synchronous (SYNC), current-sense (CS), and temperature (TMP) signals. Thus, power stage SPSA-1 is connected to the phase controller 210 via signals / lines PWMA-1 (211), SYNC-A (212), CSA-1 (213), and TMPA (214). Power stage SPSA-6 is connected to the phase controller 210 via signals PWMA-6, SYNC-A, CSA-6, and TMPA (214). Similarly, power stage SPSB-1 ​​is connected to the phase controller 210 via signals / lines PWMB-1 (216), SYNC-B (217), CSB-1 (218), and TMPB (219). SPSB-3 is connected to the phase controller 210 via signals PWMB-3, SYNC-B, CSB-3, and TMPB (219). Other power stages may also be connected to the phase controller 210 in a similar manner.

[0058] The PWM signal is a pulse width modulated signal input to the power stage. For example, the PWM signal can be a fixed frequency, variable duty cycle signal, and its frequency can be adjusted by the phase controller 210 according to the load current demand. Alternatively, the PWM signal can also be other types of signals, such as a variable frequency, constant on-time signal.

[0059] The PWM signal controls the opening and closing of the high-side switch and the low-side switch of the power stage. When PWM is a fixed frequency, variable duty cycle signal, the duty cycle of the PWM signal is set by the phase controller 210 to generate the required supply voltage and / or control / change the current provided by the phase. For example, the duty cycle of PWMA-1 is set according to the amplitude of the supply voltage Va and the current to be provided by the power stage SPSA-1. As is well known to those skilled in the art, for each power stage in the same converter, its PWM signals are usually staggered, that is, delayed in phase relative to each other, so that there are usually no overlapping opening times of two (or more) high-side switches or low-side switches in the converter (i.e., in each power stage). The reason for adopting the technical solution of this embodiment is, for example, to ensure that the peak instantaneous current obtained from the power supply 201 is always relatively low (or zero).

[0060] In one embodiment, the PWM signal represents a three-state input from the phase controller 210. When the power stage detects that the PWM signal is at a logic low level, the low-side switch is turned on, and when the power stage detects that the PWM signal is at a logic high level, the high-side switch is turned on. The high impedance (hi-Z) value of the PWM signal (usually a mid-voltage between a logic high level and a logic low level voltage) is set to turn off the high-side switch and the low-side switch of the corresponding power stage.

[0061] The TMP signal is a signal output by the power stage to the phase controller 210, which provides information about the internal temperature of the power stage. The phase controller 210 can process the TMP signal (or the information it includes) to adjust the current provided by the phase, or to shut down the voltage regulation module. The TMP outputs of each phase of the converter are connected together, and only one input is connected to the phase controller 210.

[0062] The SYNC signal is a power control signal and is also a signal input to the power stage. The phase controller 210 can use the SYNC signal to indicate whether the power stage is to generate the regulated voltage Va or Vb (i.e., wake up the power stage) or not to do so (i.e., shut down the power stage), and is also used to indicate the power saving operating mode (e.g., PS2, PS3) of the multi-phase converter, i.e., the output current requirement. Typically, all power stages of the same converter share one SYNC signal.

[0063] When the voltage regulation module is powered on, the SYNC signal is at a logic low level and keeps the power stage powered on but reset. The SYNC signal is at a logic high level to indicate the power stage is awake, that is, to indicate that the power stage can now start working (for example, after the voltage regulation module is powered on) to generate the regulated voltage Va or Vb. Accordingly, after the SYNC signal issues a wake-up indication, the PWM signal starts switching. When the SYNC signal is in a high impedance (hi-Z) state (i.e., an intermediate level, approximately halfway between a logic high level and a logic low level), it is used to indicate that the power stage is turned off, that is, the power stage is not operating to generate the regulated voltage. In the off state, the power stage is used to indicate that most of its internal circuits / modules are turned off and current consumption is reduced as much as possible.

[0064] The current detection signal is a signal input from the power stage to the phase controller 210, which includes information about the magnitude of the inductor current of the phase. This information can be expressed in the form of current, voltage, digital value, etc.

[0065] Each power stage is associated with a corresponding bootstrap capacitor for driving the high-side switch in the power stage. Therefore, the power stage in the present application will be described below.

[0066] 4. Power level

[0067] Figure 3 It is a block diagram of the power level provided in the embodiment of the present application. Figure 3 The power stage SPSA-1 (220-1) is specifically shown. Other power stages may also be similar to the power stage SPSA-1 (220-1). However, in some other embodiments, the power stage may have more or fewer modules. The power stage SPSA-1 includes a gate driver 310, a high-side switch 330, a low-side switch 340, a buffer 317, a power management module 320, a detection module 350, and a refresh module 360. Figure 3 Also shown are an inductor 225A-1, an output capacitor 226A-1, a bootstrap capacitor (Cboot) 224A-1, an AND gate 370, a NOT gate 366, and an OR gate 380. Node 240 provides a supply voltage Va. Gate driver 310, power management module 320, and detection module 350 may be powered by power supply 202. Each of high-side switch 330 and low-side switch 340 may be a power transistor (e.g., a power MOSFET).

[0068] The power management module 320 receives the SYNC-A signal (212) and generates a shutdown signal 345 accordingly based on the logic state of the SYNC-A signal (212). The shutdown signal 345 is associated with the required internal modules (not all of which are present) in the power stage SPSA-1. Figure 3 ) to realize the control of turning on or off these modules. Therefore, the shutdown signal 345 is connected to the gate driver 310 and controls the power on or off of the gate driver 310 through appropriate mechanisms known to those skilled in the art (not described here for brevity). In addition, when the SYNC-A signal is in a high-impedance state (hi-Z state), the shutdown signal 345 is also connected to the detection module 350 to detect certain conditions and then refresh the bootstrap capacitor, as described below.

[0069] When the SYNC-A signal is at a logic high level (e.g., 3.3V), which typically occurs after the voltage regulation module 110 is powered on, the power management module 320 generates a shutdown signal 345 at a logic low level (inactive state) to enable power-on of all internal modules (the power-on / power-off control mechanism is not shown here), except for the detection module 350, which is disabled or turned off. When the SYNC-A signal is at a high-impedance state (also called an intermediate level), the power management module 320 sets the shutdown signal 345 to a logic high level to turn off the desired internal modules. However, for the detection module 350, the logic high state of the shutdown signal 345 indicates that the refresh operation of the bootstrap capacitor can be performed in the off state of the power stage SPSA-1, as described below.

[0070] "Shutdown" generally means that most or all internal modules (including the high-side switch 330 and the low-side switch 340) will be powered off (i.e., in a shut-down / non-operating state). In some embodiments, the logic high level of the shutdown signal is 3.3V and the logic low level is 0V. The power management module 320 also generates a refresh enable signal en-refresh (365), which, when activated (e.g., set to a logic high level), allows the power stage SPSA-1 to refresh the bootstrap capacitor during normal operation (i.e., the power stage SPSA-1 is not in a shut-down state).

[0071] The gate driver 310 receives the shutdown signal 345 and the PWM signal PWMA-1 (211). If the shutdown signal 345 is in a logic low state, the gate driver 310 generates appropriate voltages in response to the PWM signal PWMA-1 (211) to turn on and off the high-side switch 330 and the low-side switch 340 in the corresponding intervals indicated by the PWM signal PWMA-1 (211). Turning on a switch means that the switch is closed, thereby providing a conductive path for current to pass through the switch terminals. The high-side switch 330 and the series-connected low-side switch 340 work together to generate a regulated voltage Va at the node 340 from the power supply 201. When receiving the shutdown signal 345 of a logic high level, the gate driver 310 generates appropriate voltages to turn off the high-side switch 330 and the low-side switch 340. The gate driver 310 controls the on or off state of the high-side switch 330 and the low-side switch 340 through the levels at the nodes en-HS (312) and en-LS (313), respectively. The buffer 317 is powered by the bootstrap node BOOTA-1 (215) and the switch node SWA-1 (221) and is used to convert the signal en-HS to a voltage level required to drive the gate of the high-side switch 330, as will be described in more detail below.

[0072] In the embodiment of the present application, both the high-side switch 330 and the low-side switch 340 are implemented in the form of N-type metal oxide semiconductor field effect transistors (NMOS). This is because the mobility of electrons is higher than that of holes, so that advantages such as greater current capacity can be achieved in a smaller chip area. Other switch implementations with similar characteristics can also adopt the implementation method described in this article.

[0073] exist Figure 3In the example of FIG. 3 , when the shutdown signal 345 is at a logic low level and the PWM signal PWMA-1 is at a logic high level, the gate driver 310 generates appropriate voltages at the node 312 (en-HS) of the line 312 and at the node 313 (en-LS) of the line 313, respectively, to turn on the NMOS 330 and turn off the NMOS 340. When the shutdown signal 345 is at a logic low level and the PWM signal PWMA-1 is at a logic low level, the gate driver 310 generates appropriate voltages at the lines 312 and 313, respectively, to turn off the NMOS 330 and turn on the NMOS 340. When the shutdown signal 345 is at a logic high level, the gate driver 310 is powered off, and the levels at the nodes 312 (en-HS) and 313 (en-LS) are automatically pulled to ground (inside the gate driver 310), thereby turning off the high-side switch 330 (through the buffer 317 in the turned-on state, as described below) and the low-side switch 340, as described below.

[0074] It is clear to those skilled in the art that in order to turn on the N-type MOSFET, its gate must be driven to a voltage whose absolute value is at least a threshold voltage Vt higher than the source voltage. For the low-side switch 340, since the source of the low-side switch is grounded, this requirement can be met. The voltage corresponding to the logic high level on line 313 (en-LS) is sufficient to (substantially) exceed the threshold voltage of the low-side switch, thereby turning on the low-side switch.

[0075] However, for the high-side switch 330, in order to turn on the high-side switch with a very low on-resistance, its gate needs to be driven to a voltage higher than Vin. This is necessary because when the high-side switch 330 starts to turn on, the low-side switch 340 has already turned off, and the voltage of the switch node SWA-1 (221) starts to rise close to Vin and eventually equals Vin (for example, it may be around 21V). Therefore, the gate voltage of the high-side switch 330 needs to reach at least Vin+Vt (the threshold voltage of the high-side switch 330). In order to fully turn on the high-side switch (that is, to have a very low on-resistance so that it can reliably work as a switch), the gate voltage may need to be much higher than the sum of the voltage of Vin and the threshold voltage Vt (Vin+Vt). It will be clear to those skilled in the art that the bootstrap capacitor 224A-1 is used as a buffer 317 to provide a power supply voltage so that when the voltage of the switch node SWA-1 (221) rises to Vin, the buffer 317 can provide the necessary gate drive to fully turn on the high-side switch 330.

[0076] The bootstrap capacitor 224A-1 is connected between the bootstrap node BOOTA-1 (215) and the switch node SWA-1 (221).

[0077] Before the power stage 220-1 starts to work (for example, after the voltage regulator module or the power stage is powered on or reset), the transistor switch 307 is turned on by sending a control signal to the gate node 309 (thereby short-circuiting the diode 306), and the low voltage switch 340 is turned on at the same time, so that the bootstrap capacitor is charged to the required voltage (such as Vcc is 3.3V). In some embodiments, when the SYNC-A signal is high, the circuit ( Figure 3 The transistor switch 307 and the low-side switch 340 are turned on for a sufficient time (not shown) to charge the bootstrap capacitor to 3.3V; then, the transistor switch 307 and the low-side switch 340 are turned off before the normal operation of the power stage 220-1 caused by the PWM signal switching begins. The combination of the transistor switch 307, the diode 306 and the power supply 202 can be regarded as a "charging circuit" for charging the bootstrap capacitor. During the normal operation of the power stage, the "bootstrap capacitor refresh" circuit inside the power stage (described below) Figure 3 The refresh module 360 ​​in the embodiment can periodically refresh the charge of the bootstrap capacitor to replenish the charge lost by the bootstrap capacitor. When the level at the node en-LS (312) is a logic high level, the charge lost by the bootstrap capacitor 224A-1 can be replenished. When the level at the node en-HS (313) is a logic high level, the bootstrap capacitor may lose part of the accumulated charge. In addition, the bootstrap capacitor may also lose charge through the leakage line. Charge loss may occur even if both the high-side and low-side switches are turned off and the power stage is not running to generate the output voltage.

[0078] When the power stage SPSA-1 is in the off state in response to the SYNC-A (212) signal being in the high impedance state, it is desirable that the voltage across the bootstrap capacitor 224A-1 (i.e., the voltage difference between the bootstrap node BOOTA-1 (215) and the switch node SWA-1 (221)) remains at least greater than a first threshold voltage (e.g., at Figure 3 2V) to ensure that when the power stage 220-1 switches from the shutdown mode to the normal mode again, the high-side switch 330 can be reliably turned on, so that the power stage 220-1 can quickly start (or help) to generate the regulated voltage Va. In addition, if the voltage across the bootstrap capacitor is insufficient to reliably turn on the high-side switch 330, it may cause a fault false trigger in the power stage. Furthermore, insufficient voltage may affect the correct operation of the dead time loop (a control mechanism in the power stage that ensures that the high-side switch and the low-side switch are not turned on at the same time during the overlapping time) and damage the power stage.

[0079] Therefore, it is usually desired to keep the voltage across the bootstrap capacitor at a sufficiently high value so that the bootstrap capacitor is always in a ready-to-work state.

[0080] Vcc (3.3V) can be used to replenish the charge lost by the bootstrap capacitor, that is, to charge the bootstrap capacitor to about 2.6V (3.3V minus the 0.7V drop caused by diode 306, when switch 307 is in the off state). However, this operation may only be possible under certain conditions. For example, if the bootstrap capacitor has been completely discharged (to 0V), it can only be recharged to 2.6V using power supply 202 when switch node SWA-1 is at 0V. The first threshold voltage of the bootstrap capacitor (the minimum voltage required for reliable operation of high-side switch 330) is 2V (such as Figure 3 ). This 2V voltage is only guaranteed when the existing voltage across the bootstrap capacitor (before charging) and the voltage of the switch node SWA-1 are within a certain range. For example, if the bootstrap capacitor has been discharged to 1V, then the bootstrap capacitor can be charged to 2.2V by the power supply 202 even if the switch node SWA-1 is at 0.4V. On the other hand, if the bootstrap capacitor has been fully discharged and the voltage of the switch node SWA-1 is 1.5V, then the voltage of the bootstrap capacitor after being charged by the power supply 202 can only reach a maximum of 1.1V.

[0081] In summary, if the voltage at the switch node SWA-1 is not zero, it cannot be guaranteed that the bootstrap capacitor can always be charged from the power supply 202 to a voltage at least equal to the first threshold voltage (2V in the example). One possible way to solve this problem is to completely or substantially discharge the charge of the capacitor 226A-1 by turning on the low-side switch 340 at least for a short time. However, discharging the charge of the capacitor 226A-1 through the low-side switch 340 may not be ideal because the reverse current through the inductor 225A-1 (flowing into the low-side switch 340) may be very high. In addition, the body diode of the high-side switch 330 may be damaged by the excessively high negative inductor current.

[0082] The embodiments of the present application solve the problem of refreshing the bootstrap capacitor by using an independent refresh circuit (refresh module 360), which obtains power from the power supply 201 to charge the bootstrap capacitor and is independent of the power supply 202. In addition, the refresh operation is not affected or limited by the voltage of the switch node SWA-1 not being 0V, but the refresh operation may only be enabled when the voltage on the switch node SWA-1 is within a specific range, as described below.

[0083] Please continue to refer to Figure 3 When the shutdown signal 345 is a logic high signal, the detection module 350 is used to detect whether the voltage of the switch node SWA-1 is greater than 0.7V, and if so, a corresponding signal is sent to the refresh module 360. In response, the refresh module 360 ​​uses Vin to refresh the bootstrap capacitor. Figure 3Also shown are inverter 366, AND gate 370 and OR gate 380, which are optional components. When these optional components are not implemented, signal 355 is directly connected to refresh module 360. When shutdown signal 345 is a logic low signal, detection module 350 is powered off, or, optionally, disabled without powering off.

[0084] In this embodiment, the threshold voltage (second threshold) of the switch node SWA-1 is 0.7V, because as described above, if the voltage of the switch node SWA-1 (approximately) reaches or is higher than 0.7V, it means that the power supply 202 cannot charge the bootstrap capacitor to at least the required threshold voltage of 2V. Because (3.3V-0.7V-0.7V) is only equal to 1.9V, which is less than the voltage of at least 2V required for the bootstrap capacitor. It should be understood that in other environments, if the value of Vcc, the threshold voltage Vt of the high-side switch 330, and the values ​​of other related parameters are different, the selection of the threshold voltage at the switch node SWA-1 that needs to trigger the bootstrap capacitor refresh may be different.

[0085] The detection module 350 receives the voltage from the switch node SWA-1, the power supply 202, and the shutdown signal 345 as inputs, and provides a binary signal as an output signal on line 355, which indicates whether a refresh is to be performed. When the shutdown signal 345 is at a logic high level, the voltage of the switch node SWA-1 is higher than 0.7V, and the detection module 350 generates an output signal at a logic high level on line 355. Otherwise, the detection module 350 generates an output signal at a logic low level on line 355.

[0086] The logic inverter 366 generates a logic inversion signal 367 of the shutdown signal 345. The AND gate 370 receives the refresh enable signal en-refresh (365) and the logic inversion signal 367 as inputs, performs a logic AND operation on the two input signals, and outputs the logic AND result signal of the two input signals on the line 375. The OR gate 380 receives the output signal (the above binary signal) and the logic AND result signal from the line 355 and the line 375, respectively, and performs a logic OR operation on the two input signals to generate a logic OR result signal 385. When the logic OR result signal 385 is set (e.g., a logic high level), the refresh module 360 ​​refreshes the bootstrap capacitor.

[0087] The detection module 350 and the refresh module 360 ​​provided in the embodiment of the present application will be further described below.

[0088] 5. Detection module and refresh module

[0089] Figure 4The detection module 350 and the refresh module 360 ​​provided by the embodiment of the present application are shown. For the sake of clarity, the figure also shows the optional components AND gate 370 and OR gate 380.

[0090] The detection module 350 includes an inverter circuit 400, a resistor 402, an NMOS 405, a logic inverter 440, and a buffer 445. It is obvious to those skilled in the art that in other implementations, the detection module 350 may include more or fewer components and circuits.

[0091] The switch node SWA-1 is connected to the node 438 of the inverter circuit 400 through the resistor 402 and the NMOS 405 connected in series. The gate and the substrate of the NMOS 405 are connected to the power supply 202 and the node 438, respectively. The output signal of the inverter circuit 400 is provided by the node 437, and the node 437 is connected to the logic inverter 440. The logic inverter 440 performs a logic inversion operation on the output signal provided by the node 437 and generates a logic inversion signal 442, and the buffer 445 transmits the logic inversion signal 442 to the line 355.

[0092] The inverter circuit 400 is an inverter based on the NMOS threshold voltage Vt. The flip point of the inverter circuit 400 is equal to the threshold voltage Vt of the NMOS (e.g., 425 in the figure). The flip point refers to the voltage when the logic inverter flips between two logic states: a logic high state and a logic low state. The inverter circuit 400 includes transistors / switches 410, 415, 420, and 425, a resistor 412, and a capacitor 430. Also shown are nodes 437 and 438, also referred to as "first intermediate nodes" and "second intermediate nodes." Transistors 410 and 415 are PMOS transistors, while transistors 420 and 425 are NMOS transistors. Transistor 405 is a high voltage (e.g., 30V) tolerant transistor, while transistors 410, 415, 420, and 425 can be low voltage (e.g., 0V-3.3V or 0V-5V) tolerant elements. As is well known in the art, a high voltage transistor refers to a transistor that can withstand a larger (e.g., 30V) drain-source voltage without breakdown, that is, a transistor with a higher breakdown voltage specification. The above 30V tolerance is only an example, and the specific voltage depends on the maximum voltage value on the switch node SWA-1. Since the voltage Vsw of the switch node SWA-1 can be as high as the voltage provided by the power supply 201, which is about 21V in this example, the transistor 405 needs to support a higher breakdown voltage.

[0093] Transistor 410 and resistor 412 are connected in series between power supply 202 and first intermediate node 437 to form a first circuit. The source, drain and gate of transistor 410 are connected to power supply 202, one end of resistor 412 and second intermediate node 438, respectively. Transistor 415 is connected between power supply 202 and first intermediate node 437 to form a second circuit. The source, drain and gate of transistor 415 are connected to power supply 202, first intermediate node 437 and shutdown signal 345, respectively. Figure 4 It can be easily seen that the first circuit and the second circuit are connected in parallel.

[0094] Transistors 420 and 425 are connected in series between a first intermediate node 437 and ground to form a third circuit. The source, drain and gate of transistor 420 are connected to the drain of transistor 425, the first intermediate node 437 and the shutdown signal 345, respectively. The source and gate of transistor 425 are connected to ground and a second intermediate node 438, respectively. The third circuit is connected in series with the parallel combination of the first circuit and the second circuit.

[0095] The resistor 402 and the transistor 405 form a fourth circuit. The source, drain and gate of the transistor 405 are respectively connected to the second intermediate node 438, the node SWA-1 (221) and the power supply 202. The drain of the transistor 405 is connected to the node SWA-1 (221) through the resistor 402. The capacitor 430 is connected between the second intermediate node 438 and the ground.

[0096] In this embodiment, Figure 4 The logic gates shown in FIG. 1 operate at a low voltage (Vcc is 3.3 V) provided by the power supply 202 .

[0097] The following continues to describe the operation of the detection module 350 in which the detection module 350 operates according to the logic state of the shutdown signal 345. No matter which logic state the shutdown signal 345 is in, the NMOS 405 will be turned on, and the voltage across the capacitor 430 depends on the voltage Vsw. The threshold voltages of all NMOS transistors and all PMOS transistors in the detection module 350 are set to +0.7V and -0.7V respectively.

[0098] When the shutdown signal 345 is a logic high signal, the working condition of the detection module 350 is:

[0099] When the shutdown signal 345 is in a logic high state (eg, 3.3V), the PMOS 415 is turned off, and thus the second circuit is equivalent to an open circuit.

[0100] If Vsw (the voltage of the switch node 221) is greater than 0.7V (the second threshold voltage), the capacitor 430 is charged to the voltage Vsw (up to (3.3V-Vt) of the NMOS 405). The threshold voltage of the NMOS 425 is 0.7V, and if the voltage Vsw is equal to or greater than 0.7V, the NMOS 425 will be turned on. Therefore, the transistor 420 will also be turned on (its gate is already in a logic high state). Since the voltage of the second intermediate node 438 (the voltage of the gate of the PMOS 410) is (3.3V-0.7V) or lower, the PMOS 410 will also enter the on state.

[0101] Therefore, the voltage of the first intermediate node 437 will be approximately zero (logic low signal), and a logic high signal will be generated on line 355, thereby signaling the refresh module 360 ​​to refresh the bootstrap capacitor, as described in detail below.

[0102] If the voltage Vsw is less than 0.7V, transistor 425 is turned off, transistor 420 is turned off, and transistor 410 is turned on. Therefore, the voltage of the first intermediate node 437 is approximately Vcc and a logic high signal is issued. Therefore, a logic low signal is generated on line 355, thereby sending a signal to the refresh module 360 ​​to indicate that the bootstrap capacitor is not refreshed, as described below.

[0103] When the shutdown signal 345 is a logic low signal, the working condition of the detection module 350 is:

[0104] In an embodiment of the present application, when the shutdown signal is a logic low signal, the detection module 350 is powered off. Therefore, the connection between the detection module 350 and the power supply 202 can be disconnected by an appropriate mechanism well known in the art, which will not be repeated here for the sake of brevity. The buffer 445 is configured to have an internal weak pull-down to ground, so that when the detection module 350 is powered off (for example, by disconnecting the connection with the power supply 202, the logic inverter 440 and the buffer 445 will also be powered off, although the connection is not shown), the signal of the detection module 350 on the line 355 is a logic low signal to indicate that the refresh module 360 ​​does not refresh the bootstrap capacitor.

[0105] In other embodiments of the application, the detection module 350 is not powered off. When the shutdown signal 345 is in a logic low state, the transistor 415 is turned on, the transistor 420 is turned off, and no matter what the value of the voltage Vsw is, the voltage of the first intermediate node 437 will be approximately the voltage provided by the power supply 202 (equivalent to a logic high signal). Therefore, the detection module 350 generates a logic low signal on the line 355, thereby sending a signal to the refresh module 360 ​​to indicate that the bootstrap capacitor is not refreshed.

[0106] Therefore, the signal on line 355 (ie, the output of detection circuit 350 ) is in a logic high state only when shutdown signal 345 is in a logic high state and voltage Vsw is greater than 0.7V.

[0107] The following continues to describe the working conditions of the refresh module 360 ​​provided in some embodiments.

[0108] The refresh module 360 ​​includes circuits 450-A and 450-B, NMOS 465, current sink 455, and diode 495. For clarity, the present embodiment also shows the bootstrap capacitor 224A-1, the bootstrap node BOOTA-1, and the switch node SWA-1. The refresh module 360 ​​directly uses the power supply 201 as the power supply for refreshing the bootstrap capacitor.

[0109] Circuit 450-A includes PMOS transistors 460 and 470, and circuit 450-B includes NMOS transistors 475 and 480, and resistors 477 and 487. Circuits 450-A and 450-B represent current mirror circuits. The transistors of each current mirror are matched and the same size, so the ratio of the current through the transistors of each mirror is 1:1. Transistors 465, 475, and 480 are high voltage (e.g., 30V) tolerant transistors, while transistors 460 and 470 are only low voltage (e.g., 0V-3.3V or 0V-5V) tolerant components.

[0110] The current sink 455, NMOS 465 and PMOS 460 are connected in series between the power supply 201 and the ground. The source and drain of the PMOS 460 are connected to the power supply 201 and the drain of the NMOS 465, respectively. The gate of the PMOS 460 is connected to the gate of the PMOS 470 and the drain of the PMOS 460. The source and gate of the NMOS 465 are connected to one terminal of the current sink 455 and the logic or result signal 385 of the OR gate 380, respectively. The second terminal of the current sink 455 is connected to the ground.

[0111] PMOS 470, NMOS 475, and resistor 477 are connected in series between power source 201 and switch node SWA-1 (221). The source and drain of PMOS 470 are connected to power source 201 and the drain of NMOS 475, respectively. The source and gate of NMOS 475 are connected to one end of resistor 477 and the drain of NMOS 475, respectively. The gate of NMOS 475 is also connected to the gate of NMOS 480.

[0112] Diode 495, NMOS 480 and resistor 487 are connected in series between power supply 201 and bootstrap node BOOTA-1 (215). The anode of diode 495 is connected to power supply 201, and the cathode of diode 495 is connected to the drain of NMOS 480. The source of NMOS 480 is connected to node BOOTA-1 through resistor 487.

[0113] The substrates of the NMOS transistors 465, 475, and 480 are connected to the sources of the corresponding NMOS transistors.

[0114] When designed, the sink current (I1) of the current sink 455 is set to be equal to 3.3V / R477, where R477 is the resistance value of the resistor 477. Therefore, the voltage drop across the resistor 477 is also 3.3V (the current through the resistor 477 is equal to I1, as described below). In addition, the resistance value of the resistor R477 is selected so that the current I1 produces a voltage drop across the PMOS 470, so that the drain of the PMOS 470 and the gates of the NMOS 475 and 480 are biased to a voltage equal to (Vsw+3.3V+Vt), where Vt is the threshold voltage of the NMOS 480.

[0115] The working process of the refresh module 360 ​​will be described below.

[0116] When the binary signal on line 385 is in a logic high state, NMOS 465 is turned on and a current of magnitude I1 (equal to the magnitude of the sink current of current sink 455 ) flows through the series circuit formed by PMOS 460 , NMOS 465 , and current sink 455 .

[0117] Since transistors 460 and 470 form a pair of current mirrors with a current ratio of 1:1, the magnitude of the current flowing through the series circuit formed by PMOS 470, NMOS 475 and resistor 477 is also I1. Since transistors 475 and 480 also form a pair of current mirrors with a current ratio of 1:1, the magnitude of the current flowing through the series circuit formed by diode 495, NMOS 480 and resistor 487 is also I1, and this current charges the bootstrap capacitor (Cboot) 224A-1. Resistor 487 is a current limiting resistor.

[0118] The refresh / charge process of the bootstrap capacitor continues until the voltage across the bootstrap capacitor is equal to 3.3V, at which point the refresh / charge process automatically stops (until / unless the voltage across the bootstrap capacitor is lower than 3.3V again). This is because the voltage at the gate of NMOS 480 is biased at a voltage value of (Vsw+3.3V+Vt), and any increase in the voltage across the bootstrap capacitor exceeding 3.3V will cause the gate-source voltage Vgs of NMOS 480 to be lower than the threshold voltage Vt, thereby turning off NMOS 480. Therefore, when the voltage across the bootstrap capacitor reaches 3.3V, the charging process stops until the bootstrap capacitor loses some of its charge and causes the Vgs of NMOS 480 to be greater than the threshold voltage Vt.

[0119] Diode 495 is used to protect power supply 201 to prevent power supply 201 from being affected by reverse current from the bootstrap capacitor, which may cause the bootstrap capacitor to lose charge because during normal operation, the voltage Vsw can be as high as the voltage Vin provided by the power supply 201, and the voltage of the bootstrap node BOOTA-1 can be as high as Vin+3.3V.

[0120] When the binary signal on line 385 is in a logic low state, transistor 465 is turned off, causing the other transistors to also turn off, and refresh module 360 ​​does not refresh.

[0121] Please see Figure 3 It should be noted that the refresh module 360 ​​can also refresh the bootstrap capacitor during normal operation. When the refresh enable signal en-refresh (365) generated by the power management module 320 is a logic high signal, the refresh module 360 ​​performs a refresh. During normal operation, the shutdown signal 345 is a logic low signal, and the logic inversion signal 367 is a logic high signal, resulting in the logic or result signal 385 being a logic high signal, and whenever the refresh enable signal en-refresh (365) is a logic high signal (for example, at a predetermined interval), the refresh module 360 ​​performs an operation of refreshing the bootstrap capacitor.

[0122] Combine the following Figure 5 The waveforms shown in exemplify the working principles of the power management module 320 , the detection module 350 and the refresh module 360 ​​.

[0123] Figure 5 Example waveforms of the SYNC-A signal, the shutdown signal, the voltage Vsw of the switching node SWA- 1 , the signal 355 , and the bootstrap node BOOTA- 1 voltage are shown.

[0124] In the time interval t50-t51, the SYNC-A signal is shown as a logic high signal. Therefore, the shutdown signal 345 and the signal on the line 355 are both logic low signals. For simplicity, the waveform of the switch node SWA-1 voltage Vsw is not shown in the time interval t50-t51, but with the operation of the high-side switch and the low-side switch, the switch node SWA-1 voltage will switch between 0V and Vin. Similarly, the waveform of the voltage of the bootstrap node BOOTA-1 is not shown in the time interval t50-t51, but with the operation of the high-side switch and the low-side switch, the voltage of the bootstrap node BOOTA-1 will switch between 3.3V and Vin+3.3V.

[0125] At t51, the SYNC-signal A is shown as switching to a high impedance state (intermediate level voltage is 1.7V). In response, the shutdown signal 345 and the signal on line 355 are switched to a logic high signal. From t51, the voltage Vsw (the voltage of the SWA-1 node) is shown as 1V. Since the signal on line 355 is switched to a logic high signal, the refresh module 360 ​​refreshes the bootstrap capacitor in the above manner. Therefore, assuming that the bootstrap capacitor has been fully discharged, the voltage across the bootstrap capacitor increases linearly from t51 until it reaches 3.3V. Accordingly, the voltage of the BOOTA-1 node changes linearly from Vsw at t51 to Vsw+3.3V at t52, and since any charge leakage of the bootstrap capacitor is quickly replenished (because the detection module 350 and the refresh module 360 ​​continue to work during the entire power stage SPSA-1 is in the off state), after t52, the voltage of the BOOTA-1 node remains unchanged at a voltage value of Vsw+3.3V.

[0126] However, in other alternative embodiments of the present application, the refresh module 360 ​​is used to detect the voltage across the bootstrap capacitor. When the bootstrap capacitor is fully charged to 3.3V, the refresh module 360 ​​can indicate to the power management module 320 that the bootstrap capacitor is fully charged. After receiving this indication, the power management module 320 can cut off the power supply to the detection module 350. Alternatively, when the bootstrap capacitor is fully charged, the refresh module 360 ​​can directly issue an indication to the detection module 350, and the detection module 350 can stop the power supply using an appropriate mechanism well known in the art.

[0127] In another embodiment provided by the present application, when the output of the logic inverter 400 at the first intermediate node 437 is at a logic high level, a current of about 6uA is consumed. In a typical case, when the supply voltage Va (240) is 0V, the voltage of the switch node SWA-1 is also 0V, and the refresh module 360 ​​does not consume additional current. When the voltage of the switch node SWA-1 is higher than the threshold voltage Vt of the NMOS 425, the refresh module 360 ​​is activated and consumes a current of about 15uA from the power supply 201 and the power supply 202 to maintain the refresh state of the bootstrap capacitor.

[0128] 6. Conclusion

[0129] The phrases "one embodiment", "one specific implementation" or similar language mentioned in the specification means that the specific features, structures or functions related to the embodiment are at least included in at least one embodiment of the present application. Therefore, phrases such as "in one embodiment", "in an implementation" and similar language appearing throughout the specification may all refer to the same embodiment, but not necessarily.

[0130] Although in the illustrations, although the terminals / nodes are shown as being directly connected (i.e., "connected to") various other terminals, it should be understood that there may be other components in the circuit (as appropriate to the particular circumstances), so that these connections can be considered to be "electrically coupled" to the same connection terminal.

[0131] It should be understood that the specific types of transistors mentioned above (e.g., NMOS, PMOS, etc.) are only used as examples. However, for those skilled in the relevant art, by reading the public documents provided herein, alternative embodiments using different design configurations and transistors will be obvious. For example, an NMOS transistor can be replaced by a PMOS (P-type MOS) transistor, while exchanging the connections with the power terminal and the ground terminal.

[0132] Therefore, in this application, the power supply terminal and the ground terminal are referred to as constant reference potentials, the source (emitter) and drain (collector) of the transistor (providing a current path when the transistor is turned on and providing an open circuit when the transistor is turned off) are referred to as current terminals, and the gate (base) is referred to as the control terminal.

[0133] Although various embodiments of the present application have been described above, it should be understood that these embodiments are provided only as examples and are not intended to set limitations. Therefore, the breadth and scope of the present application should not be limited to the description of any specific embodiment above, but should be strictly defined in accordance with the following claims and their equivalent principles.

Claims

1. A power stage of a voltage regulator, characterized in that include: A high-side switch and a low-side switch are connected in series between an external power supply and a constant reference potential at an input node and are controlled by a first drive signal and a second drive signal, respectively; wherein the first drive signal and the second drive signal are activated in a high-side phase and a low-side phase, respectively, to drive a corresponding current through the inductor, thereby providing a regulated output voltage; a gate driver, configured to generate the first drive signal and the second drive signal based on a control signal received from a phase controller, wherein the control signal received in a first time period and a second time period is a first logic level and a second logic level, respectively; A power management module, configured to receive a power control signal, and if the power control signal is in a first state, the power management module switches both the high-side switch and the low-side switch to an off state; a bootstrap capacitor, wherein a first end of the bootstrap capacitor is connected to a control end of the high-side switch, and a second end of the bootstrap capacitor is connected to a first current end of the high-side switch, and the bootstrap capacitor is used to enable the high-side switch to be turned on; wherein a voltage across the first end and the second end of the bootstrap capacitor is equal to or greater than a first threshold voltage to maintain stable operation of the high-side switch; and A refresh module is used for refreshing the bootstrap capacitor to keep its cross voltage equal to or greater than the first threshold voltage if the high-side switch and the low-side switch continue to remain in the off state when the power control signal is in the first state.

2. The power stage according to claim 1, characterized in that When the power control signal is in a first state, it indicates that the power stage does not generate the regulated output voltage, and, when the power control signal is in the first state, the cross voltage is maintained above the first threshold voltage, so that when the power control signal changes to a second state indicating that the power stage is to generate the regulated output voltage, the high-side switch can quickly start generating the regulated output voltage.

3. The power stage according to claim 1, characterized in that The power management module receives the power control signal and determines whether the power control signal is in a first state. If the power control signal is in the first state, a shutdown signal is generated to switch both the high-side switch and the low-side switch to a shutdown state.

4. The power stage according to claim 3, characterized in that The power stage also includes a detection module for detecting whether the voltage at the second end of the bootstrap capacitor is higher than a second threshold voltage. The detection module is used to receive the shutdown signal, and only when the voltage at the second end of the bootstrap capacitor is higher than the second threshold voltage, the refresh module refreshes the bootstrap capacitor to keep the cross-voltage higher than the first threshold voltage.

5. The power stage according to claim 4, characterized in that The power stage also includes a charging circuit for charging the bootstrap capacitor from a low-voltage power supply; when the power control signal is in a first state, the second threshold voltage represents the maximum voltage value that can be reached at the second end of the bootstrap capacitor, and the maximum voltage value enables the charging circuit to charge the bootstrap capacitor to keep the cross-voltage at least equal to the first threshold voltage, wherein the refresh module uses an external power supply to refresh the bootstrap capacitor, and the output voltage of the external power supply is greater than the output voltage of the low-voltage power supply.

6. The power stage according to claim 5, characterized in that The detection module comprises: an inverter circuit, configured to have a flip point equal to the threshold voltage of the MOSFET, the inverter circuit being connected to the second end of the bootstrap capacitor to receive the voltage thereof; when the voltage of the second end of the bootstrap capacitor is higher than the second threshold voltage, the inverter circuit generates a logic low level signal as its output signal, otherwise generates a logic high level signal as its output signal; and A logic inverter is used to generate a logic inversion signal of the output signal of the inverter circuit.

7. The power stage according to claim 6, characterized in that The refresh module comprises: A first PMOS, a first NMOS and a current sink connected in series between the input node and the constant reference potential; a second PMOS, a second NMOS and a first resistor connected in series between the input node and the second end of the bootstrap capacitor; and A diode, a third NMOS and a second resistor connected in series between the input node and the first end of the bootstrap capacitor; The first PMOS and the second PMOS are connected in a current mirror configuration to form a first current mirror, and the second NMOS and the third NMOS are connected in a current mirror configuration to form a second current mirror; the control end of the first NMOS is used to receive the logic inversion signal.

8. The power stage according to claim 7, characterized in that The current of the current sink is set to be equal to the ratio of the output voltage of the low-voltage power supply to the resistance value of the first resistor, and the resistance value is set so that the current flowing through the second PMOS generates a voltage drop on the second PMOS, and the voltage drop causes each control terminal of the second NMOS and the third NMOS to be biased at a voltage equal to the sum of the voltage of the second end of the bootstrap capacitor, the output voltage of the low-voltage power supply and the threshold voltage of the third NMOS, so as to limit the charging of the bootstrap capacitor to a voltage equal to the output voltage of the low-voltage power supply.

9. The power stage according to claim 6, characterized in that The inverter circuit comprises: A first circuit includes a third PMOS and a third resistor connected in series between the low voltage power supply and the first intermediate node, wherein the source, drain and gate terminals of the third PMOS are respectively connected to the low voltage power supply, one end of the third resistor and the second intermediate node; A second circuit comprises a fourth PMOS connected between the low voltage power supply and the first intermediate node, wherein a source, a drain and a gate of the fourth PMOS are respectively connected to the low voltage power supply, the first intermediate node and the shutdown signal; a third circuit, comprising a fourth NMOS and a fifth NMOS connected in series between the first intermediate node and the constant reference potential, a source, a drain and a gate of the fourth NMOS being connected to a drain of the fifth NMOS, the first intermediate node and the shutdown signal, respectively, and a source and a gate terminal of the fifth NMOS being connected to the constant reference potential and the second intermediate node, respectively; and The first capacitor is connected between the second intermediate node and the constant reference potential. The first circuit and the second circuit are connected in parallel. The third circuit is connected in series with the first circuit and the second circuit connected in parallel.

10. The power stage according to claim 9, characterized in that The inverter circuit receives the voltage of the second end of the bootstrap capacitor through a fourth circuit, and the fourth circuit includes a fourth resistor and a sixth NMOS connected in series, the source of the sixth NMOS is connected to the second intermediate node, the drain is connected to the second end of the bootstrap capacitor through the fourth resistor, and the gate is connected to the low-voltage power supply.

11. A voltage regulation module, characterized in that: include: Multiple power stages to provide regulated output voltages on the power line; as well as a phase controller for controlling the operation of each of the plurality of power stages to provide the regulated output voltage, wherein a first power stage of the plurality of power stages comprises: a high-side switch and a low-side switch connected in series between an external power supply and a constant reference potential at an input node, and controlled by a first drive signal and a second drive signal, respectively, the first drive signal and the second drive signal being activated in a high-side phase and a low-side phase, respectively, to drive a corresponding current through the inductor, thereby providing a regulated output voltage; a gate driver, configured to generate the first drive signal and the second drive signal based on a control signal received from a phase controller, wherein the control signal received in a first time period and a second time period is a first logic level and a second logic level, respectively; A power management module, configured to receive a power control signal, and if the power control signal is in a first state, the power management module switches both the high-side switch and the low-side switch to an off state; a bootstrap capacitor, wherein a first end of the bootstrap capacitor is connected to a control end of the high-side switch, and a second end of the bootstrap capacitor is connected to a first current end of the high-side switch, and the bootstrap capacitor is used to enable the high-side switch to be turned on; wherein a voltage across the first end and the second end of the bootstrap capacitor is equal to or greater than a first threshold voltage to maintain stable operation of the high-side switch; and A refresh module is used for refreshing the bootstrap capacitor to keep its cross voltage equal to or greater than the first threshold voltage if the high-side switch and the low-side switch continue to remain in the closed state when the power control signal is in the first state.

12. The voltage regulating module according to claim 11, characterized in that: When the power control signal is in a first state, it indicates that the power stage does not generate the regulated output voltage, and, when the power control signal is in the first state, the cross voltage is maintained above the first threshold voltage, so that when the power control signal changes to a second state indicating that the power stage is to generate the regulated output voltage, the high-side switch can quickly start generating the regulated output voltage.

13. The voltage regulating module according to claim 12, characterized in that: The power management module receives the power control signal and determines whether the power control signal is in a first state. If the power control signal is in the first state, a shutdown signal is generated to switch both the high-side switch and the low-side switch to a shutdown state.

14. The voltage regulating module according to claim 13, characterized in that: The first power stage also includes a detection module for detecting whether the voltage at the second end of the bootstrap capacitor is higher than a second threshold voltage. The detection module is used to receive the shutdown signal, and only when the voltage at the second end of the bootstrap capacitor is higher than the second threshold voltage, the refresh module refreshes the bootstrap capacitor to keep the cross-voltage higher than the first threshold voltage.

15. The voltage regulating module according to claim 13, characterized in that: The first power stage also includes a charging circuit for charging the bootstrap capacitor from a low-voltage power supply; when the power control signal is in a first state, the second threshold voltage represents the maximum voltage value that can be reached at the second end of the bootstrap capacitor, and the maximum voltage value enables the charging circuit to charge the bootstrap capacitor to keep the cross-voltage at least equal to the first threshold voltage, wherein the refresh module uses the external power supply to refresh the bootstrap capacitor, and the output voltage of the external power supply is greater than the output voltage of the low-voltage power supply.

16. The voltage regulating module according to claim 15, characterized in that: The detection module comprises: an inverter circuit, whose flip point is equal to the threshold voltage of the MOSFET, the inverter circuit is connected to the second end of the bootstrap capacitor to receive its voltage, when the voltage of the second end of the bootstrap capacitor is higher than the second threshold voltage, the inverter circuit generates a logic low level signal as its output signal, otherwise it generates a logic high level signal as its output signal; and A logic inverter is used to generate a logic inversion signal of the output signal of the inverter circuit.

17. The voltage regulating module according to claim 16, characterized in that: The refresh module comprises: A first PMOS, a first NMOS and a current sink connected in series between the input node and the constant reference potential; a second PMOS, a second NMOS and a first resistor connected in series between the input node and the second end of the bootstrap capacitor; and A diode, a third NMOS and a second resistor connected in series between the input node and the first end of the bootstrap capacitor; Among them, the first PMOS and the second PMOS are connected in a current mirror configuration to form a first current mirror; the second NMOS and the third NMOS are connected in a current mirror configuration to form a second current mirror; the control end of the first NMOS is used to receive the logic inversion signal.

18. The voltage regulating module according to claim 17, characterized in that: The current of the current sink is set to be equal to the ratio of the output voltage of the low-voltage power supply to the resistance value of the first resistor, and the resistance value is set so that the current flowing through the second PMOS generates a voltage drop on the second PMOS, and the voltage drop causes each control terminal of the second NMOS and the third NMOS to be biased at a voltage equal to the sum of the voltage of the second terminal of the bootstrap capacitor, the output voltage of the low-voltage power supply and the threshold voltage of the third NMOS, so as to limit the charging of the bootstrap capacitor to a voltage equal to the output voltage of the low-voltage power supply.

19. The voltage regulating module according to claim 16, wherein: The inverter circuit comprises: A first circuit includes a third PMOS and a third resistor connected in series between the low voltage power supply and the first intermediate node, wherein the source, drain and gate terminals of the third PMOS are respectively connected to the low voltage power supply, one end of the third resistor and the second intermediate node; A second circuit includes a fourth PMOS connected between the low voltage power supply and the first intermediate node, wherein a source, a drain and a gate of the fourth PMOS are respectively connected to the low voltage power supply, the first intermediate node and a shutdown signal; a third circuit, comprising a fourth NMOS and a fifth NMOS connected in series between the first intermediate node and the constant reference potential; a source, a drain and a gate of the fourth NMOS being connected to a drain of the fifth NMOS, the first intermediate node and the shutdown signal, respectively, and a source and a gate terminal of the fifth NMOS being connected to the constant reference potential and the second intermediate node, respectively; and The first capacitor is connected between the second intermediate node and the constant reference potential. The first circuit and the second circuit are connected in parallel. The third circuit is connected in series with the first circuit and the second circuit connected in parallel.

20. The voltage regulating module according to claim 19, characterized in that: The inverter circuit receives the voltage of the second end of the bootstrap capacitor through a fourth circuit, and the fourth circuit includes a fourth resistor and a sixth NMOS connected in series, the source of the sixth NMOS is connected to the second intermediate node, the drain is connected to the second end of the bootstrap capacitor through the fourth resistor, and the gate is connected to the low-voltage power supply.

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