Logic control and gate drive circuit applied to H bridge

Abstract

The invention discloses a logic control and gate drive circuit applied to an H bridge, and belongs to the field of H-bridge motors. The logic control circuit can receive external brake signals to control the motor to brake, can receive pulse width modulation signals to control the rotating speed of the motor and can receive external signals to control the direction of the motor, and M1, M3, M4 and M2 square wave signals are output after logic operation. The grid drive circuit comprises receivable control signals HAIN, HBIN, LAIN and LBIN, and after power amplification of the grid drive circuit, power control signals HAO, HBO, LAO and LBO are output to control conduction of an external power MOS to finally control rotation of the motor. The problem that the motor easily shakes mistakenly due to the absence of a brake signal when a grid driver is adopted in the existing technology that the H-bridge motor controls the motor to rotate is solved, or the problem that although a motor driving chip has a brake signal, a driving power tube cannot be flexibly matched according to requirements is solved. The drive circuit can be widely applied to H-bridge motor drive circuits.

Description

Technical Field

[0001] The present invention belongs to the field of H-bridge motors, and further relates to the field of motor logic operation control and power amplification, and specifically, to a logic control and gate drive circuit applied to an H-bridge. Background Art

[0002] In the existing motor control field, the methods and strategies of H-bridge control of brushed DC motors are very mature. In the unipolar control strategy, the methods of controlling motor rotation can be roughly divided into two types. The conventional motor control principle block diagram and application circuit are as follows: Figure 1 , Figure 2 As shown. The first is a signal source + gate driver + power tube method, and the second is a signal source + motor driver chip method, in which the signal source is generally a microcontroller or a digital processor. The first requires at least two PWM output ports + two ordinary I / O ports to control the motor speed and motor direction. The second only requires one PWM output, one direction signal and one brake signal to control the motor (the brake signal can be externally connected to a low level). The first requires more I / O port resources than the second, and because there is no brake signal, if the initialization of the microprocessor I / O port is not standardized, when the microprocessor initializes the I / O port, it may occur when the main control chip does not give a start command, and the motor will have an erroneous jitter phenomenon. The second driver chip only requires fewer I / O port resources, but because the power tube is integrated inside the driver chip, the power tube cannot be flexibly matched according to demand. For this reason, the present invention is specially proposed. Summary of the invention

[0003] The technical problem to be solved by the present invention is to solve the problem that in the existing technology for controlling the rotation of a motor, either when a gate driver is used, there is no brake signal, which causes the motor to easily vibrate; or when a motor driver chip is used, although there is a brake signal, the motor driver chip cannot be flexibly matched with the power tube according to demand.

[0004] The inventive concept of the present invention is: using a semiconductor integrated circuit composed of a logic operation circuit and a gate drive circuit to replace the motor control technology of a simple gate driver or motor drive chip, reducing the input ports of the input end, and ensuring that the signal is not distorted while achieving power amplification. The logic operation circuit is composed of a NOT gate circuit, an AND gate circuit, a NAND gate circuit and a resistor and capacitor device, and the gate drive circuit is composed of an NPN transistor, a PNP transistor, an NMOS tube, a PMOS tube and a resistor and capacitor device. To achieve the control of the motor logic signal and power amplification and other functions.

[0005] To this end, the present invention provides a logic control and gate drive circuit for H-bridge, a motor control principle block diagram and an application circuit of the present invention Figure 3-7As shown. It includes a microprocessor, an isolation circuit, a logic operation circuit (logic control circuit), a gate drive circuit, an H bridge, and a motor.

[0006] The logic operation circuit input end (PWM, FR, SHUT) is connected to the corresponding port of the isolation circuit output end (PWM, FR, SHUT), and the isolation circuit input end is connected to the microprocessor signal output end; the logic operation circuit output end (M1, M2, M3, M4) is connected to the corresponding port of the gate drive circuit input end (M1, M2, M3, M4), the gate drive circuit output end is connected to the corresponding gate of the H bridge (gate of Q1, Q2, Q3, Q4), and the output end of the H bridge is connected to the motor connection end (A, B).

[0007] 1. Regarding the logic operation circuit The purpose of the logic operation circuit is to simplify the input signal, while also considering the difference between the theoretical design and the actual circuit to ensure the correctness of the signal. According to the combinational logic design process, the ultimate goal is to express the order of signal transmission with a logic gate circuit. Figure 4 shown.

[0008] Step 1: Logical Abstraction According to the motor control principle, for the logic operation circuit, when the SHUT input is high level 1 (hereinafter referred to as high level 1 and low level 0), the logic operation output M1, M3 (M1, M2, M3, M4 corresponding to power tubes Q1, Q2, Q3, Q4) is 0 (i.e., the upper tubes Q1 and Q3 of the two half bridges of the H bridge are turned off), and M4, M2 is 1 (i.e., the lower tubes Q4 and Q2 of the two half bridges of the H bridge are turned on); when SHUT is 0 and FR is 1, the corresponding output M1 is PWM and M2 is 1; when FR is 0, the corresponding output M3 is PWM and M2 is 1. According to the actual working principle, the logic truth table is abstracted as shown in Table 1.

[0009] Table 1 Truth table of logic operation circuit

[0010] According to the truth table, the minimum term expression of the logic function is: M1 = m1.

[0011] M3 = m3.

[0012] M4 = m2 + m3+ m4 + m5 + m6 + m7.

[0013] M4 = m0 + m1+ m4 + m5 + m6 + m7.

[0014] Step 2: Logical Simplification The Karnaugh map is used to simplify the minimum term expression, as shown in Table 2.

[0015] Table 2 Karnaugh map simplification table of minimum term expression

[0016] By simplifying the minimum term, we can get: .

[0017] .

[0018] .

[0019] .

[0020] Step 3: Logical transformation From the above minimum term simplified expression, we can see that AND gates and NOT gates will inevitably be used. Therefore, all logical expressions are transformed into the form of NAND gates, and the NAND gate logical expression is obtained as follows: .

[0021] .

[0022] .

[0023] .

[0024] Step 4: Draw a logic diagram According to the logic expression of the NAND gate, the principle diagram of the logic operation circuit of the present invention is obtained as follows: Figure 5 As shown, it includes NOT gates G1, G2, and NAND gates U1, U2, U3, and U4.

[0025] The PWM terminal is connected to input terminal 1 of U1 and input terminal 1 of U3, the FR terminal is connected to the input terminal of G1, input terminal 3 of U3, and input terminal 2 of U2, the output terminal of G1 is connected to input terminal 3 of U1 and input terminal 1 of U4, the SHUT terminal is connected to the input terminal of G2, and the output terminal of G2 is connected to input terminal 2 of U1, input terminal 2 of U3, input terminal 2 of U4, and input terminal 1 of U2.

[0026] The output end of U1 is connected to the M1 end, the output end of U2 is connected to the M2 end, the output end of U3 is connected to the M3 end, and the output end of U4 is connected to the M4 end.

[0027] The operation mechanism of the logic operation circuit is: The logic operation circuit includes a receivable brake signal (SHUT) to control the motor to stop and self-lock, a receivable pulse width modulation signal (PWM) to control the motor speed, and a receivable direction signal (FR) to control the direction of rotation of the motor.

[0028] The brake signal (SHUT) controls the motor self-locking, which means that when the brake signal (SHUT) is at a high level, the upper tubes (Q1, Q3) of the two half bridges of the H bridge are turned off, and the lower tubes (Q2, Q4) of the two half bridges are turned on, realizing the motor Brake state.

[0029] The pulse width modulation signal (PWM) controls the speed of the motor's rotation. When the input PWM duty cycle changes from small to large, the motor speed changes from slow to fast, and when the duty cycle changes from large to small, the motor speed changes from fast to slow.

[0030] The direction control signal (FR) controls the direction of the motor rotation. When FR is at a low level, the motor rotates in a certain direction, and when FR is at a high level, the motor rotates in the opposite direction.

[0031] The brake signal (SHUT) controls the motor to stop and lock. It means that the brake signal (SHUT) controls the upper tubes (Q1, Q3) of the two half bridges of the H bridge to turn off through isolation, level conversion, and logical operations such as AND gates and OR gates, cuts off the conduction loop from the power supply to the ground, and turns on the lower tubes (Q2, Q4) of the two half bridges, so that the A and B phases of the inverter bridge are short-circuited and form a conduction loop with Q2 and Q4. At this time, the motor, as an inductive load, will quickly discharge the stored energy through the Q2 and Q4 loop, causing the motor to stop quickly. The brake signal has the highest priority. When the brake signal is high, the motor will remain in the brake state regardless of how the PWM and FR signals are modulated.

[0032] The pulse width modulation signal (PWM) controls the motor speed, which means that when the brake signal is at a low level, the external signal source outputs PWM modulation. After the PWM signal is logically operated and the power amplifier circuit controls the on and off time of the subsequent power MOS tube (Q1, Q3) to control the rotation speed of the motor. If SHUT remains at a low level, FR remains unchanged, and the PWM signal is at a certain frequency, theoretically, when the PWM duty cycle is 100%, Q1 or Q3 is continuously turned on, and the current will continue to flow through the motor. At this time, the direction of rotation of the motor remains unchanged, and the speed reaches the fastest speed under the power supply voltage. Otherwise, the motor stops.

[0033] The direction control signal (FR) controls the direction of motor rotation. After the level conversion and NAND gate, OR gate and other gate circuit operations, the FR control signal controls the order of complementary alternating conduction of power tubes Q1, Q2, Q3, and Q4 (that is, Q1 and Q4, Q3 and Q2 are alternately turned on), controls the direction of current passing through the motor, and thus controls the direction of rotation of the motor.

[0034] The purpose of the gate drive circuit is to amplify the control signal and ensure that it is as distortion-free as possible. The present invention adopts the form of an inverter + a transistor push-pull circuit + a field effect transistor push-pull circuit.

[0035] The principle block diagram of the gate drive circuit is as follows: Figure 7 As shown. It includes an inverter, a triode push-pull circuit, and a field effect tube push-pull circuit.

[0036] The inverter input terminal IN is connected to the external square wave control signal terminal (HAIN, LAIN, HBIN, LBIN), and the output terminal is connected to the input terminal of the transistor push-pull circuit.

[0037] The output end of the triode push-pull circuit is connected to the input end of the field effect transistor push-pull circuit.

[0038] The output terminal OUT of the field effect tube push-pull circuit is connected to the output drive control signal terminal (HAO, LAO, HBO, LBO).

[0039] The power supply end of the inverter, the transistor push-pull circuit and the field effect transistor push-pull circuit is connected to the power supply VCC, and the ground end is connected to the ground GND.

[0040] The operation mechanism of the gate drive circuit is as follows: The gate drive circuit belongs to a power amplifier circuit, which includes an external square wave control signal (HAIN, LAIN, HBIN, LBIN) that can be received, and outputs a drive control signal after the circuit power amplification. Its main function is to amplify the power of the input signal so that it can drive a larger load. The square wave control signal is amplified by the push-pull circuit and outputs a power signal of the same frequency to control the sequence and frequency of the subsequent power tubes (Q1, Q3, Q4, Q2) to turn on and off, control the direction and duration of the current flowing through the motor, and finally control the direction and speed of the motor.

[0041] The receivable external square wave control signal (HAIN, LAIN, HBIN, LBIN) outputs the driving control signal (HAO, LAO, HBO, LBO) after the circuit power amplification. It means that the front-stage logic operation circuit outputs a square wave signal of a certain frequency. After level conversion and push-pull power amplification, the original low-amplitude square wave signal that can only provide a small current is amplified into a square wave signal of the same frequency with a larger amplitude and a larger current capacity, thereby controlling the opening and closing of the power tube of the subsequent stage. Its function is only to amplify the voltage and current of the input signal, and there is no other logical operation. Since the transmission of electrical signals takes time, the amplified signal has a certain phase difference with the original input signal. Its amplification capacity depends on the voltage resistance and over-current capacity of the complementary MOS tube of the push-pull output stage. The flexible selection of complementary MOS tubes with different voltage resistance and over-current capacity can control its amplification capacity.

[0042] The present invention solves the problem that in the existing technology for controlling the rotation of a motor, either when a gate driver is used, there is no brake signal, causing the motor to easily vibrate; or when a motor driver chip is used, although there is a brake signal, the motor driver chip cannot be flexibly matched with a power tube according to demand.

[0043] It can be widely used in H-bridge motor drive circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Schematic diagram of the circuit principle for motor control using gate drivers for existing applications.

[0045] Figure 2 A schematic diagram of the circuit principle for controlling a motor using an existing motor driver chip.

[0046] Figure 3 Schematic diagram of logic operation and gate drive circuit structure.

[0047] Figure 4 Design a flow chart for the logic.

[0048] Figure 5 This is a schematic diagram of the principle structure of the logic operation circuit.

[0049] Figure 6 This is a schematic diagram of the improved structure of the logic operation circuit.

[0050] Figure 7 This is a schematic diagram of the push-pull output gate drive circuit principle block diagram.

[0051] Figure 8 This is a schematic diagram of the structure of a single push-pull output gate drive circuit.

[0052] Fig. 9 This is a schematic diagram of the dual push-pull output gate drive circuit structure.

[0053] Fig.10 It is a schematic diagram of the structure of an H-bridge motor drive circuit with a gate drive circuit.

[0054] Fig.11 This is the M1 / M2 output waveform when the square wave frequency is 30Hz (FR=1, SHUT=3.3V).

[0055] Fig.12 This is the M1 / M3 output waveform when the square wave frequency is 300Hz (SHUT=0, FR=3.3V).

[0056] Fig.13 This is the output waveform of M1 / M3 / M4 / M2 when the square wave frequency is 300Hz (SHUT=0, FR=3.3V).

[0057] Fig.14 This is the gate drive signal waveform.

[0058] In the figure: M is a DC motor, Q1, Q2, Q3, Q4, Q8, Q13 are NMOSFETs, Q9, Q14 are PMOSFETs, Q5, Q7, Q10, Q12 are NPN transistors, Q6, Q11 are PNP transistors, C1, C2, C3, C4, C5, C6 are capacitors, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10 are resistors, D1, D2 are diodes, G1, G2 are NOT gates, U1, U2, U3, U4, U5, U6, U7, U8, U9, and U10 are NAND gates, U11 and U12 are dual-channel gate drive integrated circuits, PWM is a pulse width modulation signal, FR is a direction signal, SHUT is a brake signal, HAIN, LAIN, HBIN, and LBIN are external square wave control signals, HAO, LAO, HBO, and LBO are output drive control signals, and M1, M2, M3, and M4 are H-bridge gate driver input signals.

[0059] Explanation of symbols in the figure: HAIN is the input control signal of the upper bridge on the left side of the driving circuit H bridge, LAIN is the input control signal of the lower bridge on the left side of the driving circuit H bridge, HBIN is the input control signal of the upper bridge on the right side of the driving circuit H bridge, LBIN is the input control signal of the lower bridge on the right side of the driving circuit H bridge, HAO is the output drive signal of the upper bridge on the left side of the driving circuit H bridge, LAO is the output drive signal of the lower bridge on the left side of the driving circuit H bridge, HBO is the output drive signal of the upper bridge on the right side of the driving circuit H bridge, LBO is the output drive signal of the lower bridge on the right side of the driving circuit H bridge, VP is the positive power supply for the load motor, PGND is the negative power supply for the load motor, GND is the reference ground plane for the control signal, VB is the floating power supply voltage on the high voltage side, VS is the floating power supply offset voltage on the high voltage side, VCC is the fixed power supply voltage on the low voltage side, COM is the common terminal on the low voltage side; VSS is the logic power supply offset voltage. DETAILED DESCRIPTION

[0060] like Figure 3-14 As shown, the logic control and gate drive circuit applied to the H-bridge is specifically implemented as follows: 1. For logic operation circuits: In actual situations, the transmission delay of the gate circuit must be considered. If M1 outputs PWM, M2 outputs 1, and M3 and M4 are all 0, then when FR jumps, theoretically M1 should jump from 1 to 0 and M4 should jump from 0 to 1 at the same time. Since M1 and M4 are on the same bridge arm, considering the different transmission delays of the logic gates, it is possible that M4 jumps from 0 to 1 before M1 jumps from 1 to 0. Therefore, during the transmission delay difference, M1 and M4 may output 1 at the same time. If this signal is transmitted to the next stage, it is very likely that Q1 and Q4 will be turned on at the same time, which will cause the bridge arm to pass through. This phenomenon is fatal to the H-bridge driver. Therefore, a timing adjustment circuit is added to the circuit to obtain the schematic diagram of the logic operation circuit as shown below. Figure 6 shown.

[0061] Including NOT gates G1, G2, NAND gates U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, resistors R1, R2, and capacitors C1, C2.

[0062] The PWM terminal is connected to input terminal 1 of U5 and input terminal 1 of U7.

[0063] The FR terminal is connected to the input terminal of G1, the input terminal 3 of U3, and the input terminal 2 of U2, and the output terminal of G1 is connected to the input terminal 3 of U1 and the input terminal 1 of U4.

[0064] The SHUT terminal is connected to the input terminal of G2, and the output terminal of G2 is connected to the input terminal 2 of U1, the input terminal 2 of U3, the input terminal 2 of U4, and the input terminal 1 of U2.

[0065] The output end of U1 is connected to the input terminal 2 of U5, the output end of U5 is connected to the input terminal 1 and input terminal 2 of U6, and the output end of U6 is connected to the M1 terminal.

[0066] The output end of U2 is connected to the input terminal 1 of U10 and one end of R2, the other end of R2 is connected to one end of C2 and the input terminal 2 of U10, the other end of C2 is grounded, and the output end of U10 is connected to the M2 end.

[0067] The output end of U3 is connected to the input terminal 2 of U7, the output end of U7 is connected to the input terminal 1 and input terminal 2 of U8, and the output end of U8 is connected to the M3 terminal.

[0068] The output end of U4 is connected to the input terminal 1 of U5 and one end of R1. The other end of R1 is connected to one end of C1 and the input terminal 2 of U9. The other end of C1 is grounded. The output end of U9 is connected to the M4 end.

[0069] Depend on Figure 6 It can be seen that the three-input AND gate of the upper bridge M1 and M3 is replaced by two two-output AND gates in cascade, adding a gate circuit transmission link and reducing the types of gate circuits. The lower bridge M4 and M2 add a two-input AND gate on the basis of the original circuit, and add an RC delay circuit. This structure of the circuit will only delay the rising edge and will not affect the timing of the falling edge. At the same time, in order to match the transmission delay, a two-input AND gate is also added to the output of the upper bridge. Analysis of the timing shows that the M1 and M3 signals of the upper bridge pass through more gate circuits than the M4 and M2 signals of the lower bridge. Considering the transmission delay of the gate circuit, it is inevitable that the rising and falling edges of the upper tube M1 and M3 signals lag behind the lower tube M4 and M2, and the lag time is a constant T (inherent parameter of the gate circuit). Take the M1 and M4 bridge arms as an example: that is, the rising edge of M1 arrives after the falling edge of the lower tube M4 arrives. Under this condition, the upper and lower tubes of a bridge arm are prevented from being turned on at the same time. However, at this time, the falling edge of the upper tube may arrive after the rising edge of the lower tube M4 arrives. Therefore, an RC delay circuit is designed in the lower tube, and the appropriate R and C values ​​are selected to make the time constant τ of the RC circuit greater than the transmission delay T between the rising edge of the lower tube and the falling edge of the upper tube. In this way, the possibility of a bridge arm outputting 1 at the same time is eliminated.

[0070] 2. For the gate drive circuit: The specific circuit principle is as follows Figure 8 As shown. Including Q5, Q6, Q7, Q8, Q9, C3, R3, R4.

[0071] The base of Q5 is connected to one end of R3 and one end of C3, the other end of R3 is connected to the IN terminal (HAIN), the collector of Q5 is connected to one end of R4, the base of Q6, and the base of Q7, the collector of Q6 is connected to the emitter of Q7, the gate of Q8, and the gate of Q9, the drain of Q8 is connected to the drain of Q9 and the output terminal OUT (HAOUT), the power supply VCC terminal is connected to the other end of R4, the collector of Q7, and the source of Q9, and the ground terminal GND is connected to the other end of C3, the emitter of Q5, the emitter of Q6, and the source of Q8.

[0072] Q5, C3, R3 and R4 constitute a transistor reverse circuit.

[0073] Q6 and Q7 form a triode push-pull circuit.

[0074] Q8 and Q9 constitute a field effect tube push-pull circuit.

[0075] The function of Q5 is to convert the range of input level HAIN into 0-VCC, and R3 and R4 are current limiting resistors. In theory, the waveform power amplification can be achieved by only using the combination of Q5+Q8 and Q9, but considering that R4 is a current limiting resistor, its resistance value cannot be too small. When Q5 is turned off, R4 is the turn-on resistor of Q8. If R4 is too large, Q8 will turn on too slowly, and therefore the falling edge will be too slow when HAOUT outputs a low level, which will eventually cause waveform distortion. Adding the intermediate stages Q6 and Q7 will significantly increase the slope of the falling edge of the HAOUT output.

[0076] The role of R3 and C3 is to shape the circuit. Since the transistors of the entire circuit are working in saturation and cut-off states. When the HAIN output signal changes from 0V to about 0.7V, the circuit output begins to jump, and this rising process is T1. Similarly. When the input signal drops from a high level to 0.7V, the output begins to jump, and this falling process is T2. The general output signal level range is 3-10V, but no matter what the input high level is, since the flip levels of the rising edge and the falling edge are different, T2 is generally greater than T1. Taking the square wave with an input signal amplitude of 3.3V, a frequency of 10kHz, and a duty cycle of 50% as an example, the frequency of the output signal is 10kHz, the amplitude is VCC, and the duty cycle may be greater than 50%. Therefore, the RC circuit is added to make the input signal reach 0.7V more slowly. Since the falling edge of the input signal is a low-impedance discharge, it will hardly affect the output falling edge (that is, it will hardly affect the frequency of the output waveform). Therefore, this design can correct the duty cycle of the output waveform as much as possible.

[0077] The power driver uses two sets of push-pull circuits to form one arm of the H bridge, and its schematic diagram is as follows: Fig. 9As shown, semiconductor integrated circuit technology is used for integration to form a dual-channel gate drive integrated circuit (U11, U12).

[0078] The typical application circuit of the dual gate driver integrated circuit (U11, U12) is as follows: Fig.10 As shown. Includes: U11, U12, Q1, Q2, Q3, Q4, R7, R8, R9, R10, D1, D2, C5, C6, M.

[0079] The VB terminal of U11 is connected to one end of C5 and the cathode end of D1, the HAO terminal of U11 is connected to one end of R7, the other end of R7 is connected to the gate of Q1, the VS terminal of U11 is connected to the other end of C5, the source of Q1, the drain of Q4, and the A terminal of the motor M, the LAO terminal of U11 is connected to one end of R10, and the other end of R10 is connected to the gate of Q4.

[0080] The VB terminal of U12 is connected to one end of C6 and the cathode end of D2, the HBO terminal of U12 is connected to one end of R8, the other end of R8 is connected to the gate of Q3, the VS terminal of U12 is connected to the other end of C6, the drain of Q2, the source of Q3, and the B terminal of the motor M, the LBO terminal of U12 is connected to one end of R9, and the other end of R9 is connected to the gate of Q2.

[0081] The power supply VCC terminal is connected to the anode terminal of D1, the anode terminal of D2, the VCC terminal of U11, and the VCC terminal of U12.

[0082] The power supply VP terminal is connected to the drain of Q1 and the drain of Q3.

[0083] The ground terminal PGND is connected to the COM terminal of U11, the COM terminal of U12, the source of Q4, and the source of Q2.

[0084] The D1 and D2 function as bootstrap diodes, and the C5 and C6 function as bootstrap capacitors.

[0085] The multisim simulation waveforms of the logic operation circuit and the gate drive circuit are as follows: Figure 11-14 .

[0086] Fig.11 Shown are: FR=1, SHUT is 3.3V, square wave frequency is 30Hz, and the output waveforms of M1 and M2.

[0087] Fig.12 Shown are: SHUT=0, FR is 3.3V, frequency is 300Hz square wave, and output waveforms of M1 and M3.

[0088] Fig.13Shown are: SHUT=0, FR is 3.3V, square wave frequency is 300Hz, and the output waveforms of M1, M3, M4, and M2.

[0089] Fig.14 Shown is: Gate drive circuit waveform.

[0090] The truth table of the logic operation circuit is shown in Table 3: Table 3 Truth table of logic operation circuit

[0091] Finally, it should be noted that the above embodiments are merely examples for the purpose of clear explanation. The present invention includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods exhaustively. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. All implementation methods that meet the requirements of the present invention belong to the protection scope of the present invention.

Claims

1. A logic control and gate drive circuit for an H-bridge, characterized in that: Including microprocessor, isolation circuit, logic operation circuit, gate drive circuit, H bridge, motor; The input end of the logic operation circuit is connected to the corresponding port of the output end of the isolation circuit, and the input end of the isolation circuit is connected to the signal output end of the microprocessor; The output end of the logic operation circuit is connected to the corresponding port of the input end of the gate drive circuit; The output end of the gate driving circuit is connected to the corresponding gate of the H bridge, and the output end of the H bridge is connected to the corresponding port of the motor.

2. A logic control and gate drive circuit for an H-bridge as claimed in claim 1, characterized in that: The logical expression of the NAND gate of the logic operation circuit is: ， ， ， ， The PWM is a pulse width modulation signal, FR is a direction signal, SHUT is a brake signal, and the H-bridge gate driver input signal.

3. A logic control and gate drive circuit for an H-bridge as claimed in claim 2, characterized in that: The logic operation circuit includes NOT gates G1, G2, and NAND gates U1, U2, U3, and U4; The PWM terminal is connected to the input terminal 1 of U1 and the input terminal 1 of U3, the FR terminal is connected to the input terminal of G1, the input terminal 3 of U3, and the input terminal 2 of U2, the output terminal of G1 is connected to the input terminal 3 of U1 and the input terminal 1 of U4, the SHUT terminal is connected to the input terminal of G2, and the output terminal of G2 is connected to the input terminal 2 of U1, the input terminal 2 of U3, the input terminal 2 of U4, and the input terminal 1 of U2; The output end of U1 is connected to the M1 end, the output end of U2 is connected to the M2 end, the output end of U3 is connected to the M3 end, and the output end of U4 is connected to the M4 end.

4. A logic control and gate drive circuit for an H-bridge as claimed in claim 3, characterized in that: The logic operation circuit includes NOT gates G1 and G2, NAND gates U1, U2, U3, U4, U5, U6, U7, U8, U9 and U10, resistors R1 and R2, and capacitors C1 and C2; The PWM terminal is connected to input terminal 1 of U5 and input terminal 1 of U7; The FR terminal is connected to the input terminal of G1, the input terminal 3 of U3, and the input terminal 2 of U2, and the output terminal of G1 is connected to the input terminal 3 of U1 and the input terminal 1 of U4; The SHUT terminal is connected to the input terminal of G2, and the output terminal of G2 is connected to the input terminal 2 of U1, the input terminal 2 of U3, the input terminal 2 of U4, and the input terminal 1 of U2; The output of U1 is connected to the input terminal 2 of U5, the output of U5 is connected to the input terminals 1 and 2 of U6, and the output of U6 is connected to the terminal of M1; The output end of U2 is connected to the input end 1 of U10 and one end of R2, the other end of R2 is connected to one end of C2 and the input end 2 of U10, the other end of C2 is grounded, and the output end of U10 is connected to the end of M2; The output end of U3 is connected to the input end 2 of U7, the output end of U7 is connected to the input end 1 and input end 2 of U8, and the output end of U8 is connected to the M3 end; The output end of U4 is connected to the input terminal 1 of U5 and one end of R1. The other end of R1 is connected to one end of C1 and the input terminal 2 of U9. The other end of C1 is grounded. The output end of U9 is connected to the M4 end.

5. The logic control and gate drive circuit for H-bridge according to claim 1, characterized in that: The gate drive circuit includes an inverter, a triode push-pull circuit, and a field effect transistor push-pull circuit; The inverter input terminal IN is connected to the external square wave control signal terminal, and the output terminal is connected to the input terminal of the transistor push-pull circuit; The output end of the triode push-pull circuit is connected to the input end of the field effect transistor push-pull circuit; The output terminal OUT of the field effect tube push-pull circuit is connected to the output drive control signal terminal; The power supply end of the inverter, the transistor push-pull circuit and the field effect transistor push-pull circuit is connected to the power supply VCC, and the ground end is connected to the ground GND.

6. A logic control and gate drive circuit for an H-bridge as claimed in claim 5, characterized in that: The gate drive circuit includes Q5, Q6, Q7, Q8, Q9, C3, R3, and R4; The base of Q5 is connected to one end of R3 and one end of C3, the other end of R3 is connected to the IN end, the collector of Q5 is connected to one end of R4, the base of Q6, and the base of Q7, the collector of Q6 is connected to the emitter of Q7, the gate of Q8, and the gate of Q9, the drain of Q8 is connected to the drain of Q9 and the output end OUT, the power supply VCC end is connected to the other end of R4, the collector of Q7, and the source of Q9, and the ground end GND is connected to the other end of C3, the emitter of Q5, the emitter of Q6, and the source of Q8.

7. The logic control and gate drive circuit for H-bridge according to claim 6, characterized in that: The power driver uses two groups of the power drivers to form a bridge arm gate driving circuit of an H bridge.

8. The logic control and gate drive circuit for H-bridge according to claim 7, characterized in that: The one bridge arm gate drive circuit is integrated by using semiconductor integrated circuit technology to form a dual-path gate drive integrated circuit (U11, U12).

9. A logic control and gate drive circuit for an H-bridge as claimed in claim 8, characterized in that: The application circuit of the dual gate drive integrated circuit (U11, U12) includes: U11, U12, Q1, Q2, Q3, Q4, R7, R8, R9, R10, D1, D2, C5, C6 and motor M; The VB terminal of U11 is connected to one end of C5 and the cathode end of D1, the HAO terminal of U11 is connected to one end of R7, the other end of R7 is connected to the gate of Q1, the VS terminal of U11 is connected to the other end of C5, the source of Q1, the drain of Q4, and the A terminal of the motor M, the LAO terminal of U11 is connected to one end of R10, and the other end of R10 is connected to the gate of Q4; The VB terminal of U12 is connected to one end of C6 and the cathode end of D2, the HBO terminal of U12 is connected to one end of R8, the other end of R8 is connected to the gate of Q3, the VS terminal of U12 is connected to the other end of C6, the drain of Q2, the source of Q3, and the B terminal of the motor M, the LBO terminal of U12 is connected to one end of R9, and the other end of R9 is connected to the gate of Q2; The power supply VCC terminal is connected to the anode terminal of D1, the anode terminal of D2, the VCC terminal of U11, and the VCC terminal of U12; The power supply VP terminal is connected to the drain of Q1 and the drain of Q3; The ground terminal PGND is connected to the COM terminal of U11, the COM terminal of U12, the source of Q4, and the source of Q2.

10. The combinational logic design method of logic control according to claim 1, characterized in that: The steps include: Step 1: Logical Abstraction Abstract the logic truth table based on the actual working principle; Step 2: Logical Simplification According to the logic truth table, the logic expression is obtained, and then all the logic expressions are transformed into the form of NAND gates to obtain the NAND gate logic expression; Step 4: Draw a logic diagram According to the logic expression of the NAND gate, the logic operation principle block diagram is obtained, and then the circuit schematic diagram is designed based on the logic operation principle block diagram.

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