Low power flip-flop and integrated circuit including same

Abstract

A low power flip-flop and an integrated circuit including the same are provided. The flip-flop includes: a main latch; and a slave latch. The master latch includes: a first circuit configured to generate a second data signal complementary to a data input signal based on a clock signal, the data input signal, and a first data signal; a second circuit configured to generate a first data signal complementary to the inverted data input signal based on the clock signal, the inverted data input signal, and a second data signal; and a third circuit configured to generate a latch signal from the input of the latch and the second data signal based on the clock signal. The slave latch is configured to latch an input of the slave latch based on the clock signal and the latch signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application Nos. 10-2023-0110793 and 10-2023-0185065 filed on August 23, 2023 and December 18, 2023, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] The present disclosure relates to a trigger, and more particularly, to a low-power trigger and an integrated circuit including the low-power trigger. Background Art

[0004] An integrated circuit for processing a digital signal may include a trigger. The trigger may latch an input based on a clock signal and output the latched input. The trigger may include a transistor and may have various structures depending on the application. Depending on the requirements of the integrated circuit, a trigger designed to have low power consumption may reduce the operating speed. The operating speed of the integrated circuit may depend on the operating speed of the trigger. Accordingly, a trigger with low power and limited operating speed reduction is needed. Summary of the invention

[0005] Example embodiments provide a low power flip-flop having limited operation speed reduction, and an integrated circuit including the low power flip-flop.

[0006] According to one aspect of an example embodiment, a trigger includes: a master latch; and a slave latch. The master latch includes: a first circuit configured to generate a second data signal complementary to the data input signal based on a clock signal, a data input signal, and a first data signal; a second circuit configured to generate a first data signal complementary to the inverted data input signal based on the clock signal, the inverted data input signal, and the second data signal; and a third circuit configured to generate a latch signal based on the clock signal, an input of the slave latch, and the second data signal. The slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal.

[0007] According to another aspect of an example embodiment, a trigger includes: a slave latch; and a master latch configured to generate a first data signal and a second data signal based on a clock signal, a data input signal, and an inverted data input signal, and to generate a latch signal based on the clock signal, an input of the slave latch, and the second data signal, wherein the first data signal is complementary to the inverted data input signal, and the second data signal is complementary to the data input signal. The slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal.

[0008] According to another aspect of the example embodiment, a method for latching a data input signal based on a clock signal includes: generating a first data signal complementary to the inverted data input signal and a second data signal complementary to the data input signal based on the clock signal, the data input signal and the inverted data input signal; generating a latch signal based on the clock signal, the input of a slave latch and the second data signal; and latching the input of the slave latch based on the clock signal and the latch signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features will become more apparent from the following description of example embodiments in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a trigger according to an example embodiment;

[0011] Figure 2 is a block diagram illustrating a master latch according to an example embodiment;

[0012] Figure 3 is a circuit diagram showing a first circuit according to an example embodiment;

[0013] Figure 4 is a circuit diagram showing a second circuit according to an example embodiment;

[0014] Figure 5 is a circuit diagram showing a third circuit according to an example embodiment;

[0015] Fig. 6A and Figure 6B is a circuit diagram showing an example of a fourth circuit according to an example embodiment;

[0016] Figure 7 is a block diagram illustrating a slave latch according to an example embodiment;

[0017] Figure 8 is a circuit diagram showing a second inverter according to an example embodiment;

[0018] Fig. 9 is a circuit diagram showing a flip-flop according to an example embodiment;

[0019] Fig.10 is a timing diagram illustrating the operation of a flip-flop according to an example embodiment;

[0020] Fig.11 is a circuit diagram showing a flip-flop according to an example embodiment;

[0021] Fig.12 is a flow chart illustrating the operation of a trigger according to an example embodiment;

[0022] Fig.13 is a flow chart illustrating the operation of a trigger according to an example embodiment;

[0023] Fig.14 is a flow chart illustrating the operation of a trigger according to an example embodiment;

[0024] Fig.15 is a flowchart illustrating a method of manufacturing an integrated circuit according to an example embodiment; and

[0025] Fig.16 is a block diagram illustrating a system on chip according to example embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, the embodiment will be described in detail with reference to the accompanying drawings.Throughout the specification, similar components are represented by similar reference numerals, and their repeated description is omitted.It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element may be directly on, directly connected to or coupled to the other element or layer, or there may be an intermediate element or layer.On the contrary, when an element is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer.The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms.Each example embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment provided herein or not provided herein but consistent with the present disclosure.

[0027] Figure 1 1 is a block diagram showing a trigger 10 according to an example embodiment. In some example embodiments, the trigger 10 may be included in an integrated circuit manufactured using a semiconductor process. Figure 1 As shown, the flip-flop 10 may include a master latch 11 and a slave latch 12. It should be noted herein that, unless otherwise described, a signal is assumed to be a high activation signal having a logic high when activated and a logic low when deactivated, but example embodiments are not limited thereto. Herein, a logic high may correspond to a positive power supply voltage VDD and may be represented as "1". Similarly, a logic low may correspond to a negative power supply voltage VSS and may be represented as "0".

[0028] like Figure 1As shown, the flip-flop 10 may latch the data input D (i.e., the data input signal) based on the clock signal CK, and may generate a data output Q corresponding to the latched data input D. In some example embodiments, the flip-flop 10 may be a single-ended type, and may generate an inverted data input DB (i.e., an inverted data input signal) based on the data input D by an inverter included in the flip-flop 10. In some example embodiments, the flip-flop 10 may be a differential type, may receive the data input D and the inverted data input DB, and may generate a data output Q and an inverted data output. The flip-flop 10 may be a positive edge-triggered flip-flop that latches the data input D in response to the rising edge of the clock signal CK, or may be a negative edge-triggered flip-flop that latches the data input D in response to the falling edge of the clock signal CK. Herein, it should be noted that the flip-flop 10 is assumed to be a positive edge-triggered flip-flop, but example embodiments are not limited thereto.

[0029] The master latch 11 can receive the data input D, the inverted data input DB and the clock signal CK, and can generate the slave input QN and the latch signal LAT. The slave input QN can have a logic level corresponding to the data input D, and can be synchronized with the rising edge of the clock signal CK. Herein, the slave input QN can be referred to as the input of the slave latch 12, the output of the master latch 11, or the master output. The latch signal LAT and the clock signal CK can be used for the slave latch 12 to latch the slave input QN. As shown below with reference Fig.10 As described above, the switching frequency of the latch signal LAT can be lower than the clock signal CK, thereby reducing the power consumption of the flip-flop 10. For example, a flip-flop (e.g., a transmission gate flip-flop (TGFF)) can use a clock and an inverted clock to control a master latch and a slave latch. The clock and the inverted clock can switch at the same frequency. In this regard, since the inverted clock switches as frequently as the clock, the flip-flop may have relatively high power consumption.

[0030] The master latch 11 can generate the first data signal DT and the second data signal DN to generate the slave input QN and the latch signal LAT. Fig.10 As described above, the first data signal DT may be complementary to the inverted data input DB, and the second data signal DN may be complementary to the data input D. As described below with reference to the accompanying drawings, the master latch 11 may generate the first data signal DT and the second data signal DN independently of the latch signal LAT, and the first data signal DT and the second data signal DN may not be floating. Accordingly, the flip-flop 10 may operate statically and without contention, and delays caused by incomplete driving of the signal may be eliminated. Figure 2 An example of the master latch 11 will be described.

[0031] The slave latch 12 may receive a slave input QN, a latch signal LAT, and a clock signal CK. The slave latch 12 may latch the slave input QN based on the latch signal LAT and the clock signal CK, and may generate a data output Q. Figure 7 An example of the slave latch 12 will be described.

[0032] Figure 2 is a block diagram showing a master latch 20 according to an example embodiment. For example, Figure 2 The block diagram shows Figure 1 An example of the master latch 11. As shown in reference Figure 1 As described above, the master latch 20 can receive the data input D, the inverted data input DB and the clock signal CK, and can generate the slave input QN and the latch signal LAT. Figure 2 As shown, the master latch 20 may include a first circuit 21 , a second circuit 22 , a third circuit 23 and a fourth circuit 24 .

[0033] The first circuit 21 can generate a second data signal DN based on the clock signal CK, the data input D and the first data signal DT. Figure 2 As shown, the first circuit 21 can receive a clock signal CK and a data input D from the outside of the master latch 20, and can receive a first data signal DT from the second circuit 22. Figure 3 As described above, the first circuit 21 can statically generate the second data signal DN based on the clock signal CK, the data input D and the first data signal DT. For example, the second data signal DN can be generated independently of the latch signal LAT and can be non-floating. In this regard, the second data signal DN can be fully driven. The first circuit 21 may include at least one transistor, and the following will refer to Figure 3 An example of the first circuit 21 is described.

[0034] The second circuit 22 can generate a first data signal DT based on the clock signal CK, the inverted data input DB and the second data signal DN. Figure 2 As shown, the second circuit 22 can receive the clock signal CK and the inverted data input DB from the outside of the master latch 20, and can receive the second data signal DN from the first circuit 21. Figure 4 As described above, the second circuit 22 can statically generate the first data signal DT based on the clock signal CK, the inverted data input DB and the second data signal DN. For example, the first data signal DT can be generated independently of the latch signal LAT and can not be floated. In this regard, the first data signal DT can be fully driven. The second circuit 22 can include at least one transistor, and the following will refer to Figure 4 An example of the second circuit 22 is described.

[0035] The third circuit 23 can generate a latch signal LAT based on the clock signal CK, the second data signal DN and the slave input QN. Figure 2 As shown, the third circuit 23 can receive the clock signal CK from the outside of the master latch 20, can receive the second data signal DN from the first circuit 21, and can receive the slave input QN from the fourth circuit 24. Figure 5 As described above, the latch signal LAT can have a simple pull-up path and a pull-down path, and therefore, the delay caused by the latch signal LAT can be eliminated. The third circuit 23 may include at least one transistor, and will be referred to below. Figure 5 An example of the third circuit is described.

[0036] The fourth circuit 24 can update the slave input QN based on the first data signal DT, the clock signal CK and the latch signal LAT. Figure 2 As shown, the fourth circuit 24 can receive the clock signal CK from the outside of the master latch 20, can receive the latch signal LAT from the third circuit 23, and can receive the first data signal DT from the second circuit 22. Fig. 6A and Figure 6B As described above, the fourth circuit 24 can update the slave input QN by inverting the first data signal DT based on the clock signal CK and the latch signal LAT. The fourth circuit 24 may include at least one transistor, and will be referred to below. Fig. 6A and Figure 6B An example of the fourth circuit 24 is described.

[0037] In some example embodiments, at least two of the first circuit 21, the second circuit 22, the third circuit 23, and the fourth circuit 24 may share at least one transistor. In some example embodiments, at least one of the first circuit 21, the second circuit 22, the third circuit 23, and the fourth circuit 24 may be connected to a Figure 1 The slave latch 12 shares at least one transistor. Accordingly, Figure 1 The flip-flop 10 may include a reduced number of transistors. Fig.11 An example is described in which at least one transistor is shared by at least two circuits.

[0038] Figure 3 is a circuit diagram showing a first circuit 30 according to an example embodiment. For example, Figure 3 The circuit diagram shows Figure 2 An example of the first circuit 21. As shown in reference Figure 2 As described above, the first circuit 30 may generate the second data signal DN based on the clock signal CK, the data input D and the first data signal DT.

[0039] like Figure 3As shown, the first circuit 30 may include a first transistor M11 to a sixth transistor M16. The first transistor M11 to the third transistor M13 may be a p-channel field effect transistor (PFET), and the fourth transistor M14 to the sixth transistor M16 may be an n-channel field effect transistor (NFET). Each of the first transistor M11 to the sixth transistor M16 may include a gate receiving one of the clock signal CK, the data input D, and the first data signal DT.

[0040] The first transistor M11 and the second transistor M12 may receive a clock signal CK and a data input D, respectively, and may be connected in series with each other between a node (referred to as a first power node) to which a positive power supply voltage VDD is applied and a first node N11 generating a second data signal DN. In some example embodiments, the first transistor M11 and the second transistor M12 may be connected in series with each other. Figure 3 The third transistor M13 may receive the first data signal DT and may be connected between the first power supply node and the first node N11. The fourth transistor M14 and the fifth transistor M15 may receive the data input D and the clock signal CK, respectively, and may be connected in parallel to each other between the first node N11 and the second node N12. The sixth transistor M16 may receive the first data signal DT and may be connected between the second node N12 and a node (referred to as a second power supply node) to which a negative power supply voltage is applied. In some example embodiments, as described below with reference to Fig.11 As described above, the first transistor M11 can be composed of Figure 2 The second circuit 22 is shared.

[0041] Figure 4 is a circuit diagram showing a second circuit 40 according to an example embodiment. For example, Figure 4 The circuit diagram shows Figure 2 An example of the second circuit 22. As shown in reference Figure 2 As described above, the second circuit 40 may generate the first data signal DT based on the clock signal CK, the inverted data input DB, and the second data signal DN.

[0042] like Figure 4 As shown, the second circuit 40 may include first to sixth transistors M21 to M26. The first to third transistors M21 to M23 may be PFETs, and the fourth to sixth transistors M24 to M26 may be NFETs. Each of the first to sixth transistors M21 to M26 may include a gate receiving one of the clock signal CK, the inverted data input DB, and the second data signal DN.

[0043] The first transistor M21 and the second transistor M22 may receive the clock signal CK and the inverted data input DB, respectively, and may be connected in series with each other between a first power supply node to which a positive power supply voltage VDD is applied and a first node N21 generating a first data signal DT. In some example embodiments, the first transistor M21 and the second transistor M22 may be connected in series with each other. Figure 4 . The third transistor M23 may receive the second data signal DN and may be connected between the first power supply node and the first node N21. The fourth transistor M24 and the fifth transistor M25 may receive the inverted data input DB and the clock signal CK, respectively, and may be connected in parallel to each other between the first node N21 and the second node N22. The sixth transistor M26 may receive the second data signal DN and may be connected between the second node N22 and the second power supply node to which the negative power supply voltage VSS is applied. In some example embodiments, as described below with reference to Fig.11 As described above, the first transistor M21 can be composed of Figure 2 In some example embodiments, as shown below, Fig.11 As described above, the sixth transistor M26 can be composed of Figure 2 The third circuit 23 is shared.

[0044] Figure 5 is a circuit diagram showing a third circuit 50 according to an example embodiment. For example, Figure 5 The circuit diagram shows Figure 2 An example of the third circuit 23. As shown in reference Figure 2 As described above, the third circuit 50 may generate the latch signal LAT based on the clock signal CK, the slave input QN, and the second data signal DN.

[0045] like Figure 5 As shown, the third circuit 50 may include first to fifth transistors M31 to M35. The first to third transistors M31 to M33 may be PFETs, and the fourth and fifth transistors M34 and M35 may be NFETs. Each of the first to fifth transistors M31 to M35 may include a gate receiving one of the clock signal CK, the slave input QN, and the second data signal DN.

[0046] The first transistor M31 and the second transistor M32 may receive the clock signal CK and the slave input QN, respectively, and may be connected in series with each other between a first power supply node to which a positive power supply voltage VDD is applied and a first node N31 generating a latch signal LAT. In some example embodiments, the first transistor M31 and the second transistor M32 may be connected in series with each other. Figure 5The third transistor M33 may receive the second data signal DN and may be connected in series with each other in an order different from the order shown. The fourth transistor M34 and the fifth transistor M35 may receive the clock signal CK and the second data signal DN, respectively, and may be connected in series with each other between the first node N31 and the second power supply node to which the negative power supply voltage VSS is applied. In some example embodiments, the fourth transistor M34 and the fifth transistor M35 may be connected in series with each other in an order different from the order shown. Figure 5 In some example embodiments, as shown below, Fig.11 As described above, the first transistor M31 can be composed of Figure 1 The slave latch 12 is shared. In some example embodiments, as shown below with reference to Fig.11 As described above, the fifth transistor M35 can be Figure 2 The second circuit 22 is shared.

[0047] Fig. 6A and Figure 6B is a circuit diagram showing an example of a fourth circuit according to an example embodiment. For example, Fig. 6A and Figure 6B The circuit diagram shows Figure 2 An example of the fourth circuit 24. As shown in reference Figure 2 As described above, the fourth circuits 60a and 60b can update the slave input QN based on the first data signal DT, the clock signal CK, and the latch signal LAT.

[0048] refer to Fig. 6A , the fourth circuit 60a may include first to fourth transistors M41 to M44. The first transistor M41 and the second transistor M42 may be PFETs, and the third transistor M43 and the fourth transistor M44 may be NFETs. Each of the first to fourth transistors M41 to M44 may include a gate receiving one of the clock signal CK, the latch signal LAT, and the first data signal DT.

[0049] The first transistor M41 and the second transistor M42 may receive the latch signal LAT and the first data signal DT, respectively, and may be connected in series with each other between a first power supply node to which the positive power supply voltage VDD is applied and a first node N41 generating a slave input QN. In some example embodiments, the first transistor M41 and the second transistor M42 may be connected in series with each other. Fig. 6A The third transistor M43 and the fourth transistor M44 may receive the first data signal DT and the clock signal CK, respectively, and may be connected in series with each other between the first node N41 and the second power supply node to which the negative power supply voltage VSS is applied. In some example embodiments, the third transistor M43 and the fourth transistor M44 may be connected in series with each other in an order different from the order shown. Fig. 6A Sequences that are different in order are connected in series with each other.

[0050] refer to Figure 6B , the fourth circuit 60b may include a fifth transistor M45 to a seventh transistor M47. Fig. 6A Compared with the fourth circuit 60a, the fourth circuit 60b may not include Fig. 6A The fifth transistor M45 may be a PFET, and the sixth transistor M46 and the seventh transistor M47 may be NFETs. Each of the fifth transistor M45 to the seventh transistor M47 may include a gate receiving one of the clock signal CK, the latch signal LAT, and the first data signal DT.

[0051] The fifth transistor M45 may receive the latch signal LAT and may be connected between the first power supply node to which the positive power supply voltage VDD is applied and the first node N41 generating the slave input QN. The sixth transistor M46 and the seventh transistor M47 may receive the first data signal DT and the clock signal CK, respectively, and may be connected in series with each other between the first node N41 and the second power supply node to which the negative power supply voltage VSS is applied. In some example embodiments, the sixth transistor M46 and the seventh transistor M47 may be connected in series with the first node N41. Figure 6B Sequences that are different in order are connected in series with each other.

[0052] Figure 7 is a block diagram showing a slave latch 70 according to an example embodiment. For example, Figure 7 The block diagram shows Figure 1 An example of a slave latch 12. As shown in reference Figure 1 As described above, the slave latch 70 may receive the slave input QN, the latch signal LAT, and the clock signal CK, and may generate a data output Q. Figure 7 As shown, the slave latch 70 may include first to third inverters INV1 to INV3.

[0053] The first inverter INV1 may receive a slave input QN and may generate an internal data output QI. The first inverter INV1 may generate an internal data output QI by inverting the slave input QN. The third inverter INV3 may receive a slave input QN and may generate a data output Q. The third inverter INV3 may generate a data output Q by inverting the slave input QN. In some example embodiments, each of the first inverter INV1 and the third inverter INV3 may include a PFET and an NFET connected in series to each other between a first power supply node to which a positive power supply voltage VDD is applied and a second power supply node to which a negative power supply voltage VSS is applied.

[0054] The second inverter INV2 may be cross-coupled to the first inverter INV1. That is, the second inverter INV2 may receive the internal data output QI as the output of the first inverter INV1, and may generate the slave input QN as the input of the first inverter INV1. Figure 7 As shown, the second inverter INV2 can receive the clock signal CK and the latch signal LAT. The second inverter INV2 can update the slave input QN based on the internal data output QI, the clock signal CK and the latch signal LAT. For example, when the clock signal CK is 0 and the internal data output QI is 0, the second inverter INV2 can update the slave input QN to 1. In addition, when the latch signal LAT is 1 and the internal data output QI is 1, the second inverter INV2 can update the slave input QN to 0. The second inverter INV2 may include at least one transistor, and the following will refer to Figure 8 An example of the second inverter INV2 is described.

[0055] Figure 8 is a circuit diagram showing a second inverter 80 according to an example embodiment. For example, Figure 8 The circuit diagram shows Figure 7 An example of the second inverter INV2. Figure 7 As described above, the second inverter 80 can update the slave input QN based on the internal data output QI, the clock signal CK, and the latch signal LAT.

[0056] like Figure 8 As shown, the second inverter 80 may include first to fourth transistors M51 to M54. The first transistor M51 and the second transistor M52 may be PFETs, and the third transistor M53 and the fourth transistor M54 may be NFETs. Each of the first to fourth transistors M51 to M54 may include a gate receiving one of the clock signal CK, the latch signal LAT, and the internal data output QI.

[0057] The first transistor M51 and the second transistor M52 may receive the clock signal CK and the internal data output QI, respectively, and may be connected in series with each other between a first power supply node to which a positive power supply voltage VDD is applied and a first node N51 of an update slave input QN. In some example embodiments, the first transistor M51 and the second transistor M52 may be connected in series with each other. Figure 8 The third transistor M53 and the fourth transistor M54 may receive the internal data output QI and the latch signal LAT, respectively, and may be connected in series with each other between the first node N51 and the second power supply node to which the negative power supply voltage VSS is applied. In some example embodiments, the third transistor M53 and the fourth transistor M54 may be connected in series with each other in an order different from the order shown. Figure 8In some example embodiments, as shown below, Fig.11 As described above, the first transistor M51 can be composed of Figure 2 The third circuit 23 is shared.

[0058] Fig. 9 is a circuit diagram showing a flip-flop 90 according to an example embodiment. As described above with reference to the accompanying drawings, the flip-flop 90 may include a master latch 91 and a slave latch 92. Fig. 9 In the description, the same description as that made above with reference to the accompanying drawings will be omitted.

[0059] refer to Fig. 9 , the master latch 91 may include first to fourth circuits CKT1 to CKT4. The first circuit CKT1 may correspond to Figure 3 The first circuit 30. For example, Fig. 9 As shown, the first circuit CKT1 may include first to sixth transistors M11 to M16. The second circuit CKT2 may correspond to Figure 4 The second circuit 40. For example, Fig. 9 As shown, the second circuit CKT2 may include a first transistor M21 to a sixth transistor M26. The third circuit CKT3 may correspond to Figure 5 The third circuit 50. For example, Fig. 9 As shown, the third circuit CKT3 may include first to fifth transistors M31 to M35. The fourth circuit CKT4 may correspond to Fig. 6A For example, Fig. 9 As shown, the fourth circuit CKT4 may include first to fourth transistors M41 to M44.

[0060] The slave latch 92 may correspond to Figure 7 The slave latch 70 of FIG. 1 and the second inverter INV2 of the slave latch 70 may correspond to Figure 8 The second inverter 80. For example, Fig. 9 As shown, the slave latch 92 may include a first inverter INV1, a third inverter INV3, and first to fourth transistors M51 to M54.

[0061] In some example embodiments, the first transistor M11 and the second transistor M12 of the first circuit CKT1 may be connected to Fig. 9 In some example embodiments, the first transistor M21 and the second transistor M22 of the second circuit CKT2 may be connected in series with each other in an order different from the order shown. Fig. 9 In some example embodiments, the first transistor M31 and the second transistor M32 of the third circuit CKT3 may be connected in series with each other in an order different from the order shown. Fig. 9 In some example embodiments, the fourth transistor M34 and the fifth transistor M35 of the third circuit CKT3 may be connected in series with each other in an order different from the order shown. Fig. 9 In some example embodiments, the first transistor M41 and the second transistor M42 of the fourth circuit CKT4 may be connected in series with each other in an order different from the order shown. Fig. 9 In some example embodiments, the third transistor M43 and the fourth transistor M44 of the fourth circuit CKT4 may be connected in series with each other in an order different from the order shown. Fig. 9 In some example embodiments, the first transistor M51 and the second transistor M52 of the slave latch 92 may be connected in series with each other in a different order than the order shown. Fig. 9 The third transistor M53 and the fourth transistor M54 of the slave latch 92 may be connected in series with each other in an order different from the order shown. Fig. 9 Sequences that are different in order are connected in series with each other.

[0062] Fig.10 is a timing diagram illustrating the operation of a trigger according to an example embodiment. For example, Fig.10 The timing diagram shows Fig. 9 An example of the operation of the trigger 90. Fig. 9 describe Fig.10 .

[0063] refer to Fig.10 , before time t01, each of the clock signal CK, the data input D, and the data output Q may be 0. The first circuit CKT1 may generate the second data signal DN of 1 due to the clock signal CK of 0 and the data input D of 0. The second circuit CKT2 may generate the first data signal DT of 0 due to the inverted data input DB of 1 and the second data signal DN of 1. The third circuit CKT3 may generate the floating latch signal LAT due to the clock signal CK of 0, the second data signal DN of 1, and the slave input QN of 1. The fourth circuit CKT4 may not drive the slave input QN due to the clock signal CK of 0 and the floating latch signal LAT, but the second inverter INV2 may generate the slave input QN of 1 due to the internal data output QI and the clock signal CK of 0. The third inverter INV3 may generate the data output Q of 0 due to the slave input QN of 1.

[0064] At time t01, the data input D may be converted to 1, and the inverted data input DB may be converted to 0. The second circuit CKT2 may generate the first data signal DT of 1 due to the clock signal CK of 0 and the inverted data input DB of 0. The first circuit CKT1 may generate the second data signal DN of 0 due to the data input D of 1 and the first data signal DT of 1. The third circuit CKT3 may generate the latch signal LAT of 1 due to the second data signal DN of 0. The second inverter INV2 may maintain the slave input QN at 1, and the third inverter INV3 may maintain the data output Q at 0.

[0065] At time t02, a rising edge of the clock signal CK may occur. The first circuit CKT1 may maintain the second data signal DN at 0 due to the clock signal CK being 1 and the first data signal DT being 1. The second circuit CKT2 may maintain the first data signal DT at 1 due to the second data signal DN being 0. The third circuit CKT3 may maintain the latch signal LAT at 1 due to the second data signal DN being 0. The fourth circuit CKT4 may generate a slave input QN of 0 due to the first data signal DT being 1 and the clock signal CK being 1. The first inverter INV1 may generate an internal data output QI of 1 due to the slave input QN of 0. The second inverter INV2 may maintain the slave input QN of 0 due to the slave input QN of 0 and the latch signal LAT of 1. The third inverter INV3 may generate a data output Q of 1 due to the slave input QN of 0.

[0066] At time t03, a falling edge of the clock signal CK may occur. The second circuit CKT2 may maintain the first data signal DT at 1 due to the clock signal CK being 0 and the inverted data input DB being 0. The first circuit CKT1 may maintain the second data signal DN at 0 due to the data input D being 1 and the first data signal DT being 1. The third circuit CKT3 may maintain the latch signal LAT at 1 due to the second data signal DN being 0. The second inverter INV2 may maintain the slave input QN at 0. The third inverter INV3 may maintain the data output Q at 1.

[0067] At time t04, a rising edge of the clock signal CK may occur. The first circuit CKT1 may maintain the second data signal DN at 0 due to the clock signal CK being 1 and the first data signal DT being 1. The second circuit CKT2 may maintain the first data signal DT at 1 due to the second data signal DN being 0. The third circuit CKT3 may maintain the latch signal LAT at 1 due to the second data signal DN being 0. The fourth circuit CKT4 may generate a slave input QN of 0 due to the first data signal DT being 1 and the clock signal CK being 1. The first inverter INV1 may generate an internal data output QI of 1 due to the slave input QN of 0. The second inverter INV2 may maintain the slave input QN of 0 due to the slave input QN of 0 and the latch signal LAT of 1. The third inverter INV3 may generate a data output Q of 1 due to the slave input QN of 0.

[0068] At time t05, a falling edge of the clock signal CK may occur. The second circuit CKT2 may maintain the first data signal DT at 1 due to the clock signal CK being 0 and the inverted data input DB being 0. The first circuit CKT1 may maintain the second data signal DN at 0 due to the data input D being 1 and the first data signal DT being 1. The third circuit CKT3 may maintain the latch signal LAT at 1 due to the second data signal DN being 1. The second inverter INV2 may maintain the slave input QN at 0, and the third inverter INV3 may maintain the data output Q at 1.

[0069] At time t06, the data input D may be converted to 0, and the inverted data input DB may be converted to 1. Since the clock signal CK is 0 and the data input D is 0, the first circuit CKT1 may generate the second data signal DN as 1. Since the inverted data input DB is 1 and the second data signal DN is 1, the second circuit CKT2 may generate the first data signal DT as 0. The third circuit CKT3 may maintain the latch signal LAT as 1 due to the clock signal CK of 0 and the slave input QN of 0. The fourth circuit CKT4 may not drive the slave input QN due to the clock signal CK of 0 and the latch signal LAT of 1, but the second inverter INV2 may maintain the slave input QN as 0 due to the clock signal CK of 0, the latch signal LAT of 1, and the internal data output QI of 1. The third inverter INV3 may generate the data output Q as 1 due to the slave input QN of 0.

[0070] At time t07, a rising edge of the clock signal CK may occur. The second circuit CKT2 may maintain the first data signal DT at 0 due to the clock signal CK being 1 and the inverted data input DB being 1. The first circuit CKT1 may maintain the second data signal DN at 1 due to the first data signal DT being 0. The third circuit CKT3 may generate a latch signal LAT being 0 due to the first data signal DT and the clock signal CK being 1. The fourth circuit CKT4 may generate a slave input QN being 1 based on the first data signal DT being 0, the clock signal CK being 1, and the latch signal LAT being 0. The first inverter INV1 may generate an internal data output QI being 0 based on the slave input QN being 1. The third inverter INV3 may generate a data output Q being 0 based on the slave input QN being 1.

[0071] At time t08, a falling edge of the clock signal CK may occur. The first circuit CKT1 may maintain the second data signal DN at 1 due to the clock signal CK being 0 and the data input D being 0. The second circuit CKT2 may maintain the first data signal DT at 0 due to the inverted data input DB being 1 and the second data signal DN being 1. Since the clock signal CK is 0, the second data signal DN is 1, and the slave input QN is 1, the third circuit CKT3 may generate a floating latch signal LAT. The fourth circuit CKT4 may not drive the slave input QN due to the clock signal CK being 0 and the floating latch signal LAT, but the second inverter INV2 may generate a slave input QN of 1 due to the internal data output QI of 0 and the clock signal CK of 0. The third inverter INV3 may generate a data output Q of 0 due to the slave input QN of 1.

[0072] At time t09, a rising edge of the clock signal CK may occur. The second circuit CKT2 may maintain the first data signal DT at 0 due to the clock signal CK being 1 and the second data signal DN being 1. The first circuit CKT1 may maintain the second data signal DN at 1 due to the first data signal DT being 0. The third circuit CKT3 may generate a latch signal LAT at 0 due to the clock signal CK being 1 and the second data signal DN being 1. The fourth circuit CKT4 may generate a slave input QN at 1 due to the first data signal DT being 0 and the latch signal LAT being 0. The first inverter INV1 may generate an internal data output QI at 0 due to the slave input QN being 1. The third inverter INV3 may maintain the data output Q at 0 due to the slave input QN being 1.

[0073] At time t10, the data input D may be converted to 1, and the inverted data input DB may be converted to 0. The first circuit CKT1 may maintain the second data signal DN as 1 due to the first data signal DT being 0. The second circuit CKT2 may maintain the first data signal DT as 0 due to the clock signal CK being 1 and the second data signal DN being 1. The third circuit CKT3 may maintain the latch signal LAT as 0 due to the clock signal CK being 1 and the second data signal DN being 1. The fourth circuit CKT4 may maintain the slave input QN as 1 due to the first data signal DT being 0 and the latch signal LAT being 0. The first inverter INV1 may generate the internal data output QI as 0 due to the slave input QN being 1. The third inverter INV3 may maintain the data output Q as 0 due to the slave input QN being 1.

[0074] At time t11, a falling edge of the clock signal CK may occur. The second circuit CKT2 may generate a first data signal DT of 1 due to the clock signal CK of 0 and the inverted data input DB of 0. The first circuit CKT1 may generate a second data signal DN of 0 due to the data input D of 1 and the first data signal DT of 1. The third circuit CKT3 may generate a latch signal LAT of 1 due to the second data signal DN of 0. The second inverter INV2 may maintain the slave input QN of 1 due to the internal data output QI of 0 and the clock signal CK of 0. The third inverter INV3 may maintain the data output Q of 0 due to the slave input QN of 1.

[0075] At time t12, a rising edge of the clock signal CK may occur. The first circuit CKT1 may maintain the second data signal DN at 0 due to the clock signal CK being 1 and the first data signal DT being 1. The second circuit CKT2 may maintain the first data signal DT at 1 due to the second data signal DN being 0. The third circuit CKT3 may maintain the latch signal LAT at 1 due to the second data signal DN being 0. The fourth circuit CKT4 may generate a slave input QN of 0 due to the first data signal DT being 1 and the clock signal CK being 1. The first inverter INV1 may generate an internal data output QI of 1 due to the slave input QN of 0. The second inverter INV2 may maintain the slave input QN of 0 due to the internal data output QI of 1 and the latch signal LAT of 1. The third inverter INV3 may generate a data output Q of 1 due to the slave input QN of 0.

[0076] Fig.11 is a circuit diagram showing a flip-flop 110 according to an example embodiment. For example, Fig.11 The circuit is shown having at least one transistor composed of Fig. 9The flip-flop 90 is a flip-flop 110 of a structure shared by the circuit in the flip-flop 90. Fig. 9 describe Fig.11 , and the same description as that made above with reference to the accompanying drawings will be omitted. It should be noted that only some transistors described below as being shared may be shared by two or more circuits.

[0077] refer to Fig.11 , the trigger 110 may include a plurality of transistors. For example, the trigger 110 may include a master latch, and the master latch may include a first transistor M11 to a sixth transistor M16 corresponding to the first circuit CKT1, a second transistor M22 to a sixth transistor M26 corresponding to the second circuit CKT2, a second transistor M32 to a fourth transistor M34 corresponding to the third circuit CKT3, and a first transistor M41, a third transistor M43, and a fourth transistor M44 corresponding to the fourth circuit CKT4. In some example embodiments, the third transistor M43 and the fourth transistor M44 may be connected in a manner similar to that of the first transistor M11 to the sixth transistor M16 corresponding to the first circuit CKT1, a second transistor M22 to a sixth transistor M26 corresponding to the second circuit CKT2, a second transistor M32 to a fourth transistor M34 corresponding to the third circuit CKT3, and a first transistor M41, a third transistor M43, and a fourth transistor M44 corresponding to the fourth circuit CKT4. Fig.11 Similarly, the flip-flop 110 may include a slave latch, and the slave latch may include a first inverter INV1, first to fourth transistors M51 to M54 corresponding to the second inverter INV2, and a third inverter INV3. In some example embodiments, the third transistor M53 and the fourth transistor M54 may be connected in series with each other in a sequence different from the sequence shown. Fig.11 Sequences that are different in order are connected in series with each other.

[0078] In some example embodiments, the first circuit CKT1 and the second circuit CKT2 may share at least one transistor. For example, the first transistor M11 may be shared by the first circuit CKT1 and the second circuit CKT2. Fig.11 As shown, the node A to which the first transistor M11 and the second transistor M12 are connected can be connected to the second transistor M22. Fig. 9 In the embodiment, the first transistor M11 of the first circuit CKT1 and the first transistor M21 of the second circuit CKT2 can be formed by one transistor (ie, Fig.11 M11) instead.

[0079] In some example embodiments, the second circuit CKT2 and the third circuit CKT3 may share at least one transistor. For example, the sixth transistor M26 may be shared by the second circuit CKT2 and the third circuit CKT3. Fig.11 As shown, the node C to which the sixth transistor M26 and the fifth transistor M25 (or the fourth transistor M24) are connected can be connected to the fourth transistor M34. That is, Fig. 9In the embodiment, the sixth transistor M26 of the second circuit CKT2 and the fifth transistor M35 of the third circuit CKT3 can be replaced by one transistor (ie, Fig.11 M26) instead.

[0080] In some example embodiments, the third circuit CKT3 and the second inverter INV2 may share at least one transistor. For example, the first transistor M51 may be shared by the third circuit CKT3 and the second inverter INV2. Fig.11 As shown, the node B to which the first transistor M51 and the second transistor M52 are connected can be connected to the second transistor M32. Fig. 9 In the embodiment, the first transistor M31 of the third circuit CKT3 and the first transistor M51 of the second inverter INV2 can be replaced by one transistor (ie, Fig.11 M51) instead.

[0081] In some example embodiments, the Fig. 9 At least one transistor can be omitted from the fourth circuit CKT4 of the embodiment. For example, the trigger 110 can be omitted Fig. 9 The second transistor M42 is used as a PFET for receiving the first data signal DT. Due to the shared transistor, the trigger 110 may include a Fig. 9 The flip-flop 90 has fewer transistors and, therefore, can have a smaller area.

[0082] Figure 1 2 is a flow chart showing the operation of a trigger according to an example embodiment. Fig.12 The operation of can be referred to as a method of inputting data into D latch based on the clock signal CK. Fig.12 As shown, the method of latching data input D based on the clock signal CK may include a plurality of operations S10 to S40. In some example embodiments, Fig.12 The method can be composed of Figure 2 The master latch 20 and Figure 7 The slave latch 70 is used to perform the flip-flop. Figure 2 and Figure 7 describe Fig.12 .

[0083] refer to Fig.12 In operation S10, a first data signal DT and a second data signal DN may be generated. For example, the master latch 20 may generate the first data signal DT and the second data signal DN as internal signals of the master latch 20 based on the clock signal CK, the data input D, and the inverted data input DB. The first data signal DT may be complementary to the inverted data input DB, and the second data signal DN may be complementary to the data input D. Fig.13An example of operation S10 is described.

[0084] In operation S20, a latch signal LAT may be generated. For example, the master latch 20 may generate the latch signal LAT based on the clock signal, the slave input QN, and the second data signal DN. The latch signal LAT and the clock signal CK may be used to determine the timing of the master latch 20 and the slave latch 70 updating the slave input QN.

[0085] In operation S30, the slave input QN may be updated based on the first data signal DT. For example, the master latch 20 may update the slave input QN based on the clock signal CK and the latch signal LAT. The slave input QN may be the output of the master latch 20 and the input of the slave latch 70, and the slave latch 70 may generate the data output Q by inverting the slave input QN.

[0086] In operation S40, the slave input QN may be latched. For example, the slave latch 70 may latch the slave input QN based on the clock signal CK and the latch signal LAT. Fig.14 An example of operation S40 is described.

[0087] Fig.13 is a flow chart illustrating the operation of a trigger according to an example embodiment. For example, Fig.13 The flowchart shows Fig.12 An example of operation S10 is shown in FIG. Fig.12 As described above, in operation S10', a first data signal DT and a second data signal DN may be generated. Fig.13 As shown, operation S10' may include operation S11 and operation S12. In some example embodiments, operation S11 and operation S12 may be performed in parallel. In some example embodiments, operation S10' may be performed by Figure 2 The master latch 20 is executed. Figure 2 describe Figure 1 3.

[0088] refer to Fig.13 In operation S11, the second data signal DN may be generated based on the clock signal CK, the data input D, and the first data signal DT. For example, the first circuit 21 may receive the clock signal CK, the data input D, and the first data signal DT, and may generate a second data signal DN complementary to the data input D. As described above with reference to the accompanying drawings, the second data signal DN may be generated independently of the latch signal LAT and may be fully driven.

[0089] In operation S12, a first data signal DT may be generated based on the clock signal CK, the inverted data input DB, and the second data signal DN. For example, the second circuit 22 may receive the clock signal CK, the inverted data input DB, and the second data signal DN, and may generate a first data signal DT complementary to the inverted data input DB. As described above with reference to the accompanying drawings, the first data signal DT may be generated independently of the latch signal LAT and may be fully driven.

[0090] Fig.14 is a flow chart illustrating the operation of a trigger according to an example embodiment. For example, Fig.14 The flowchart shows Fig.12 As an example of operation S40. Fig.12 As described above, in operation S40', the slave input QN may be latched. Fig.14 As shown, operation S40' may include operation S41 and operation S42. In some example embodiments, operation S40' may be performed by Figure 7 The slave latch 70 executes. Figure 7 describe Fig.14 .

[0091] refer to Fig.14 In operation S41, an internal data output QI may be generated by inverting a slave input QN. For example, the first inverter INV1 may receive the slave input QN and may generate an internal data output QI. The internal data output QI may have the same polarity as the data output Q generated by inverting the slave input QN.

[0092] In operation S42, the slave input QN may be updated by inverting the internal data output QI. For example, the second inverter INV2 may invert the internal data output QI based on the clock signal CK and the latch signal LAT. When the clock signal CK is 0 and the latch signal LAT is 1, the second inverter INV2 may invert the internal data output QI and may update the slave input QN.

[0093] Fig.15 is a flow chart showing a method for manufacturing an integrated circuit IC according to an example embodiment. In detail, Fig.15 The flowchart of FIG. 1 shows an example of a method of manufacturing an integrated circuit IC including a standard cell. A standard cell is a unit of layout included in an integrated circuit and can be designed to perform a predefined function. Fig.15 As shown, the method of manufacturing an integrated circuit IC may include a plurality of operations S51 to S55 .

[0094] The cell library (or standard cell library) D12 may include information related to the standard cell (e.g., information related to the function, characteristics, and layout of the standard cell). In some example embodiments, the trigger described above with reference to the accompanying drawings (i.e., a trigger including a master latch and a slave latch) may be included as a standard cell in the integrated circuit IC. For example, the cell library D12 may include information related to a cell corresponding to the trigger described above with reference to the accompanying drawings. Accordingly, the integrated circuit IC may reduce power consumption and increase operating speed.

[0095] The design rule D14 may include requirements for the layout of the integrated circuit IC. For example, the design rule D14 may include requirements for the space between patterns in the same layer, the minimum width of the pattern, the routing direction of the wiring layer, etc. In some example embodiments, the design rule D14 may define the minimum separation distance in the same track of the wiring layer.

[0096] In operation S51, a logic synthesis operation of generating netlist data D13 from RTL data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis from RTL data D11 written in a hardware description language (HDL) (e.g., VHSIC hardware description language (VHDL), or Verilog) with reference to a cell library D12, and may generate netlist data D13 including a bitstream or a netlist. Netlist data D13 may correspond to inputs of placement and routing described below.

[0097] In operation S52, standard cells may be placed. For example, a semiconductor design tool (e.g., a P&R tool) may place standard cells used in the netlist data D13 with reference to the cell library D12. In some example embodiments, the semiconductor design tool may place the standard cells in rows extending parallel to each other, and the placed standard cells may receive power from a power rail extending along a boundary of the row.

[0098] In operation S53, the pins of the standard cell may be routed. For example, the semiconductor design tool may generate an interconnection that electrically connects the output pins and input pins of the placed standard cell, and may generate layout data D15 that defines the placed standard cell and the generated interconnection. The interconnection may include a via of a via layer and / or a pattern of a wiring layer. In some example embodiments, the wiring layer may include not only a front wiring layer located on the gate electrode, but also a back wiring layer located below the gate electrode. The layout data D15 may have a format such as GDSII, and may include geometric information of the cell and the interconnection. The semiconductor design tool may refer to the design rule D14 while routing the pins of the cell. The layout data D15 may correspond to the output of placement and routing. Operation S53 may be performed separately, or operations S52 and S53 may be collectively referred to as a method for designing an integrated circuit.

[0099] In operation S54, an operation of manufacturing a mask may be performed. For example, optical proximity correction (OPC) for correcting distortion such as refraction caused by the characteristics of light in photolithography may be applied to the layout data D15. A pattern on the mask may be defined based on the data to which the OPC is applied to form a pattern arranged on a plurality of layers, and at least one mask (or photomask) for forming a pattern for each of the plurality of layers may be manufactured. In some example embodiments, the layout of the integrated circuit IC may be limitedly modified in operation S54. The limited modification of the integrated circuit IC in operation S54 may be a post-processing for optimizing the structure of the integrated circuit IC, and may be referred to as design polishing.

[0100] In operation S55, an operation of manufacturing an integrated circuit IC may be performed. For example, an integrated circuit IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S54. The front end process (FEOL) may include, for example, planarizing and cleaning the wafer, forming a groove, forming a well, forming a gate electrode, and forming a source and a drain. A single device (e.g., a transistor, a capacitor, and a resistor) may be formed by the FEOL. Similarly, the back end process (BEOL) may include: silicide of the gate and source and drain regions, adding a dielectric, planarizing, forming a hole, adding a metal layer, forming a via, and forming a passivation layer. A single device (e.g., a transistor, a capacitor, and a resistor) may be interconnected to each other by the BEOL. In some example embodiments, an intermediate process (MOL) may be performed between the FEOL and the BEOL, and a contact may be formed in a single device. Next, the integrated circuit IC may be packaged in a semiconductor package and may be used as a component for various applications.

[0101] Fig.161 is a block diagram illustrating a system on chip (SoC) 160 according to an example embodiment. SoC 160 may refer to an integrated circuit in which components of a computing system or another electronic system are integrated. For example, an application processor (AP) as an example of SoC 160 may include a processor and components for other functions. Fig.16 As shown, SoC 160 may include core 161, digital signal processor (DSP) 162, graphics processing unit (GPU) 163, embedded memory 164, communication interface 165, and memory interface 166. The elements of SoC 160 may communicate with each other through bus 167.

[0102] The elements of SoC 160 may include the triggers described above with reference to the accompanying drawings. Accordingly, these elements may have low power consumption and improved operating speed. As a result, the efficiency and performance of SoC 160 may be improved.

[0103] The core 161 may process instructions and may control the operation of the elements included in the SoC 160. For example, the core 161 may drive an operating system by processing a series of instructions and may execute an application on the operating system. The DSP 162 may generate useful data by processing a digital signal (e.g., a digital signal provided from the communication interface 165). The GPU 163 may generate data for an image output by a display device from image data provided by the embedded memory 164 or the memory interface 166, or may encode the image data. The embedded memory 164 may store data required by the core 161, the DSP 162, and the GPU 163 for operation. The communication interface 165 may provide an interface for one-to-one communication or a communication network. The memory interface 166 may provide an interface for an external memory (e.g., a dynamic random access memory (DRAM) or a flash memory) of the SoC 160.

[0104] As described above, example embodiments have been shown and described in the accompanying drawings. Although example embodiments have been described by using specific terms, these terms are only used to explain the technical ideas of the inventive concept and should not be interpreted as limiting the scope of the inventive concept defined by the claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent example embodiments can be made therefrom.

[0105] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A trigger, comprising: Master latch; as well as From the latch, Wherein, the master latch comprises: A first circuit configured to generate a second data signal complementary to the data input signal based on a clock signal, a data input signal and a first data signal; a second circuit configured to generate the first data signal complementary to the inverted data input signal based on the clock signal, the inverted data input signal and the second data signal; and a third circuit configured to generate a latch signal based on the clock signal, the input of the slave latch and the second data signal, and The slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal.

2. The trigger according to claim 1, wherein: The first circuit comprises: a first p-channel field effect transistor PFET, a second PFET, and a third PFET configured to receive the clock signal, the data input signal, and the first data signal, respectively; and The first n-channel field effect transistor NFET, the second NFET and the third NFET are configured to receive the data input signal, the clock signal and the first data signal respectively.

3. The trigger according to claim 2, wherein: The first PFET and the second PFET are connected in series with each other between a first power supply node to which a positive power supply voltage is applied and a first node at which the second data signal is generated, wherein the third PFET is connected between the first power supply node and the first node, wherein the first NFET and the second NFET are connected in parallel to each other between the first node and the second node, and The third NFET is connected between the second node and a second power supply node to which a negative power supply voltage is applied.

4. The trigger according to claim 1, wherein: The second circuit comprises: A first PFET, a second PFET, and a third PFET configured to receive the clock signal, the inverted data input signal, and the second data signal, respectively; and The first NFET, the second NFET and the third NFET are configured to receive the inverted data input signal, the clock signal and the second data signal respectively.

5. The trigger according to claim 4, wherein: The first PFET and the second PFET are connected in series with each other between a first power supply node to which a positive power supply voltage is applied and a first node at which the first data signal is generated, wherein the third PFET is connected between the first power supply node and the first node, wherein the first NFET and the second NFET are connected in parallel to each other between the first node and the second node, and The third NFET is connected between the second node and a second power supply node to which a negative power supply voltage is applied.

6. The trigger according to claim 5, wherein: The first PFET is shared by the first circuit.

7. The trigger according to claim 1, wherein: The third circuit comprises: a first PFET, a second PFET, and a third PFET configured to receive the clock signal, the input of the slave latch, and the second data signal, respectively; and The first NFET and the second NFET are configured to receive the clock signal and the second data signal, respectively.

8. The trigger according to claim 7, wherein: The first PFET and the second PFET are connected in series with each other between a first power supply node to which a positive power supply voltage is applied and a first node at which the latch signal is generated, wherein the third PFET is connected between the first power supply node and the first node, and The first NFET and the second NFET are connected in series between the first node and a second power supply node to which a negative power supply voltage is applied.

9. The trigger according to claim 8, wherein: The second NFET is shared by the second circuit.

10. The trigger according to claim 1, wherein: The master latch also includes a fourth circuit configured to update the input of the slave latch based on the first data signal, the clock signal, and the latch signal.

11. The trigger according to claim 10, wherein: The fourth circuit comprises: a first PFET and a second PFET configured to receive the latch signal and the first data signal, respectively, wherein the first PFET and the second PFET are connected in series with each other between a first power supply node to which a positive power supply voltage is applied and a first node generating the input of the slave latch; and The first NFET and the second NFET are configured to receive the first data signal and the clock signal respectively, wherein the first NFET and the second NFET are connected in series with each other between the first node and a second power supply node to which a negative power supply voltage is applied.

12. The trigger according to claim 10, wherein: The fourth circuit comprises: a first PFET configured to receive the latch signal and connected between a first power supply node to which a positive power supply voltage is applied and a first node generating the input of the slave latch; and The first NFET and the second NFET are configured to receive the first data signal and the clock signal respectively, wherein the first NFET and the second NFET are connected in series with each other between the first node and a second power supply node to which a negative power supply voltage is applied.

13. The trigger according to claim 1, wherein: The slave latch comprises: an inverter configured to receive the input of the slave latch; a first PFET and a second PFET configured to receive the clock signal and the output of the inverter, respectively, wherein the first PFET and the second PFET are connected in series with each other between a first power supply node to which a positive power supply voltage is applied and a first node generating the input of the slave latch; and A first NFET and a second NFET are configured to receive the output of the inverter and the latch signal, respectively, wherein the first NFET and the second NFET are connected in series with each other between the first node and a second power supply node to which a negative power supply voltage is applied.

14. The trigger according to claim 13, wherein: The first PFET is shared by the third circuit.

15. A trigger, comprising: Slave latch; as well as a master latch configured to generate a first data signal and a second data signal based on a clock signal, a data input signal and an inverted data input signal, and to generate a latch signal based on the clock signal, an input of the slave latch and the second data signal, wherein the first data signal is complementary to the inverted data input signal and the second data signal is complementary to the data input signal, The slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal.

16. The trigger according to claim 15, wherein: The master latch is further configured to generate the first data signal based on the clock signal, the inverted data input signal, and the second data signal.

17. The trigger according to claim 15, wherein: The master latch is further configured to generate the second data signal based on the clock signal, the data input signal, and the first data signal.

18. The trigger according to claim 15, wherein: The master latch is further configured to update the input of the slave latch based on the first data signal, the clock signal, and the latch signal.

19. The trigger according to claim 15, wherein: The slave latch comprises: a first inverter configured to receive the input of the slave latch; and The second inverter is configured to update the input of the slave latch by inverting the output of the first inverter based on the clock signal and the latch signal.

20. A method for latching a data input signal based on a clock signal, the method comprising: Based on the clock signal, the data input signal and the inverted data input signal, generating a first data signal complementary to the inverted data input signal and a second data signal complementary to the data input signal; generating a latch signal based on the clock signal, an input from the latch, and the second data signal; as well as The input of the slave latch is latched based on the clock signal and the latch signal.

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