Capacitance detection system and method

Abstract

The present invention provides a capacitance detection system and method, which relates to the field of electronic circuit technology, including: converting the capacitance value of the chip pin capacitance into a capacitance clock signal; periodically acquiring the capacitance clock signal as a real-time capacitance clock signal, calculating the capacitance value difference between the real-time capacitance clock signal and the latched historical capacitance clock signal each time the real-time capacitance clock signal is acquired, updating the latched historical capacitance clock signal to the real-time capacitance clock signal when the capacitance value difference is judged to be greater than a first resolution, and outputting an indication signal indicating a capacitance change when the capacitance value difference is judged to be greater than a second resolution. The beneficial effect is that the precise calculation method helps to accurately capture small changes in capacitance; the multi-resolution judgment mechanism improves the flexibility and accuracy of the system, and by setting a reasonable resolution threshold, the system can effectively reduce the false alarm rate caused by small fluctuations in capacitance, and improve the stability and reliability of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a capacitance detection system and method. Background Art

[0002] An airflow sensor is a device used to detect the flow state of gas. Its core working principle is usually based on the change of physical quantities to reflect the existence, speed or direction of airflow. Among the many designs of airflow sensors, there is a special design that uses a vibrating film as a sensitive element. This film can be made of highly elastic materials such as plastic or silicon. When the airflow acts on the surface of the film, it causes the film to vibrate.

[0003] In order to accurately capture and measure the vibration of the membrane caused by the airflow, the capacitance detection circuit came into being. The capacitance detection circuit indirectly senses and quantifies the changes in the airflow by monitoring the changes in the capacitance value generated by the vibrating membrane during the vibration process. When the membrane vibrates, the capacitance between it and the fixed electrode changes, and this change is closely related to the characteristics of the airflow. Therefore, by accurately measuring the changes in the capacitance value, we can accurately infer the state of the airflow.

[0004] In application scenarios such as electronic cigarettes, airflow sensors that combine capacitance detection circuits with vibrating films play an important role. They can sensitively detect the user's blowing or inhaling movements, thereby triggering the corresponding functions of the electronic cigarette. However, despite the high accuracy and sensitivity of this sensor, the existing capacitance detection circuit still faces problems such as high cost, large size, and complex algorithms, which to some extent limits the further miniaturization and cost optimization of products such as electronic cigarettes. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a capacitance detection system, comprising: a capacitance sampling module, connected to a chip pin capacitance, and used to convert the capacitance value of the chip pin capacitance into a capacitance clock signal; a main control module, connected to the capacitance sampling module, and used to periodically obtain the capacitance clock signal as a real-time capacitance clock signal, and calculate the capacitance value difference between the real-time capacitance clock signal and a latched historical capacitance clock signal each time the real-time capacitance clock signal is obtained, and when it is judged that the capacitance value difference is greater than a first resolution, the latched historical capacitance clock signal is updated to the real-time capacitance clock signal, and when it is judged that the capacitance value difference is greater than a second resolution, an indication signal indicating a capacitance change is output.

[0006] Preferably, the capacitance sampling module is an operational amplifier loop, the positive end of the operational amplifier loop receives a reference voltage, the reverse end of the operational amplifier loop receives a reference current and is connected to the chip pin capacitance, and is used to charge and discharge the chip pin capacitance and convert the capacitance value of the chip pin capacitance into a capacitance clock signal.

[0007] Preferably, the operational amplifier loop includes: a differential comparator, wherein the reference end of the differential comparator receives the reference voltage, the capacitor end of the differential comparator is connected to the chip pin capacitor, the source of the discharge switch tube and the drain of the charging switch tube, and the source of the charging switch tube receives the reference current; a common-gate current mirror, wherein the first source and the second source of the common-gate current mirror are respectively connected to the first drain and the second drain of the differential comparator; and a secondary operational amplifier circuit, wherein the input end of the secondary operational amplifier circuit is connected to the first drain of the common-gate current mirror, and the output end of the secondary operational amplifier circuit is sequentially connected in series with a first inverter and a second inverter, the output end of the first inverter is connected to the gate of the discharge switch tube, and the output end of the second inverter is connected to the main control module to output the capacitor clock signal.

[0008] Preferably, the operational amplifier loop also includes a hysteresis circuit, including: a hysteresis resistor, which is connected in series to the common source end of the differential comparator, and the two ends of the hysteresis resistor are also connected to the drain of the first switch tube and the drain of the second switch tube respectively; the gate of the first switch tube is connected to the output end of the first inverter, the gate of the second switch tube is connected to the output end of the second inverter, the source of the first switch tube and the source of the second switch tube are connected to the drain of the power supply switch tube, and the source of the power supply switch tube receives a reference current.

[0009] Preferably, the main control module includes: a difference calculation unit, which is used to perform frequency division counting on the real-time capacitor clock signal acquired for the first time to obtain a latched counting result and latch it as the historical capacitor clock signal, and to perform frequency division counting on the real-time capacitor clock signal acquired not for the first time to obtain a real-time counting result, and obtain the capacitance value difference between the real-time capacitor clock signal and the historical capacitor clock signal according to the real-time counting result and the latched counting result.

[0010] Preferably, the difference calculation unit includes: a standard clock subunit, which is used to continuously output a standard clock signal with a standard duty cycle; a latch subunit, which is used to latch the latch count result as the historical capacitor clock signal; a frequency division count subunit, which is connected to the standard clock unit and the latch unit, and is used to record the number of cycles of the real-time capacitor clock signal during the period when the standard clock signal is at a low level as the latch count result when the real-time capacitor clock signal is first acquired, and is also used to record the number of cycles of the real-time capacitor clock signal during the period when the standard clock signal is at a low level as the real-time count result when the real-time capacitor clock signal is acquired non-for the first time.

[0011] Preferably, the difference calculation unit also includes: a full adder subunit, used to invert the real-time counting result each time the real-time counting result is obtained, and then perform full addition and summation with the latch counting result stored in the latch subunit; a difference calculation subunit, connected to the full adder subunit, used to perform XOR operation on the value of the highest bit in the full addition result and the values ​​of each other bit in sequence to output the capacitance value difference.

[0012] Preferably, the main control module normally outputs an indication signal indicating that the capacitance has not changed, and the main control module also includes: a resolution storage unit, used to store the first resolution and the second resolution respectively; a resolution comparison unit, connected to the resolution storage unit, used to sum the capacitance value difference with the first resolution to obtain a first summation result, and when the highest bit of the first summation result is 1, the latched historical capacitance clock signal is updated to the real-time capacitance clock signal, and the capacitance value difference is summed with the second resolution to obtain a second summation result, and when the highest bit of the second summation result is 1, the normally output indication signal indicating that the capacitance has not changed is flipped to output an indication signal indicating a capacitance change.

[0013] The present invention also provides a capacitance detection method, which is applied to the above-mentioned capacitance detection system, including: step S1, the capacitance detection system controls the capacitance sampling module to convert the capacitance value of the chip pin capacitance into a capacitance clock signal; step S2, the capacitance detection system regularly obtains the capacitance clock signal as a real-time capacitance clock signal, and calculates the capacitance value difference between the real-time capacitance clock signal and the latched historical capacitance clock signal each time the real-time capacitance clock signal is obtained; step S3, the capacitance detection system determines whether the capacitance value difference is greater than a first resolution: if so, the latched historical capacitance clock signal is updated to the real-time capacitance clock signal; if not, return to step S2 to wait for the next capacitance clock signal to be obtained; step S4, the capacitance detection system determines whether the capacitance value difference is greater than a second resolution: if so, output an indication signal indicating a capacitance change; if not, return to step S2 to wait for the next capacitance clock signal to be obtained.

[0014] Preferably, the capacitance difference calculation process in step S2 includes: performing frequency division counting on the real-time capacitance clock signal acquired for the first time to obtain a latched counting result and latching it as the historical capacitance clock signal, and performing frequency division counting on the real-time capacitance clock signal acquired not for the first time to obtain a real-time counting result, and obtaining the capacitance value difference between the real-time capacitance clock signal and the historical capacitance clock signal according to the real-time counting result and the latched counting result.

[0015] The above technical solution has the following advantages or beneficial effects:

[0016] 1. The capacitance sampling module converts the capacitance value of the chip pin capacitance into a capacitance clock signal; the main control module obtains the real-time capacitance clock signal regularly and compares it with the latched historical capacitance clock signal to calculate the capacitance value difference. This sophisticated calculation method helps to accurately capture small changes in capacitance.

[0017] 2. The system makes different judgments on the capacitance difference by setting the first resolution and the second resolution. When the capacitance difference is greater than the first resolution, the latched historical capacitance clock signal is updated; when the capacitance difference is greater than the second resolution, an indication signal indicating the capacitance change is output. This multi-resolution judgment mechanism improves the flexibility and accuracy of the system. Furthermore, by setting a reasonable resolution threshold, the system can effectively reduce the false alarm rate caused by small fluctuations in capacitance and improve the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A structural schematic diagram of a capacitance detection system in a preferred embodiment of the present invention;

[0019] Figure 2 A circuit diagram of an operational amplifier loop in a preferred embodiment of the present invention;

[0020] Figure 3 The figure is a flow chart of a capacitance detection method in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0022] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a capacitance detection system is provided. Figure 1 As shown, it includes: a capacitance sampling module 1, connected to a chip pin capacitance 2, and used to convert the capacitance value of the chip pin capacitance 2 into a capacitance clock signal; a main control module 3, connected to the capacitance sampling module 1, and used to periodically obtain the capacitance clock signal as a real-time capacitance clock signal, and calculate the capacitance value difference between the real-time capacitance clock signal and the latched historical capacitance clock signal each time the real-time capacitance clock signal is obtained, and when it is judged that the capacitance value difference is greater than a first resolution, the latched historical capacitance clock signal is updated to the real-time capacitance clock signal, and when it is judged that the capacitance value difference is greater than a second resolution, an indication signal indicating a capacitance change is output.

[0023] Specifically, a chip is usually set in the airflow sensor, and the chip is responsible for receiving and processing the original signals from the sensor, which usually reflect parameters such as the speed, pressure or direction of the airflow. Through the built-in signal processing algorithm, the chip can convert these original signals into digital data that are easy to understand and use. The capacitance sampling module in this embodiment is connected to the chip pin capacitor in the airflow sensor to convert the capacitance value of the chip pin capacitor into a capacitance clock signal; the main control module obtains the real-time capacitance clock signal regularly and compares it with the latched historical capacitance clock signal to calculate the capacitance value difference. This sophisticated calculation method helps to accurately capture small changes in capacitance.

[0024] The system makes different judgments on the capacitance difference by setting the first resolution and the second resolution. When the capacitance difference is greater than the first resolution, the latched historical capacitance clock signal is updated; when the capacitance difference is greater than the second resolution, an indication signal indicating the capacitance change is output. This multi-resolution judgment mechanism improves the flexibility and accuracy of the system. Furthermore, by setting a reasonable resolution threshold, the system can effectively reduce the false alarm rate caused by small fluctuations in capacitance and improve the stability and reliability of the system.

[0025] The capacitance sampling module 1 and the main control module 3 in this embodiment can be integrated on a separate capacitance detection chip, which can be set in the gas sensor and connected to the original chip pin capacitance in the gas sensor, or directly integrated on the original chip in the gas sensor and connected to the chip pin capacitance, which can save the space and cost of the gas sensor, and further promote the miniaturization and cost optimization of products such as electronic cigarettes.

[0026] In a preferred embodiment of the present invention, the capacitance sampling module 1 is an operational amplifier loop, the positive end of the operational amplifier loop receives a reference voltage, the reverse end of the operational amplifier loop receives a reference current and is connected to the chip pin capacitor, and is used to charge and discharge the chip pin capacitor and convert the capacitance value of the chip pin capacitor into a capacitance clock signal.

[0027] In a preferred embodiment of the present invention, the operational amplifier loop includes: a differential comparator 11, a reference end of the differential comparator 11 receives a reference voltage Vref, a capacitor end of the differential comparator 11 is connected to the chip pin capacitor 2, the source of the discharge switch tube Q10 and the drain of the charging switch tube Q6, and the source of the charging switch tube Q6 receives the reference current Iref; a common-gate current mirror 12, a first source and a second source of the common-gate current mirror 12 are respectively connected to the first drain and the second drain of the differential comparator 11; a secondary operational amplifier circuit 13, an input end of the secondary operational amplifier circuit 13 is connected to the first drain of the common-gate current mirror 12, an output end of the secondary operational amplifier circuit 13 is connected in series with a first inverter 14 and a second inverter 15 in sequence, an output end of the first inverter 14 is connected to the gate of the discharge switch tube Q10, and an output end of the second inverter 15 is connected to the main control module 3 to output a capacitor clock signal.

[0028] In a preferred embodiment of the present invention, the operational amplifier loop also includes a hysteresis circuit 16, including: a hysteresis resistor R1, which is connected in series to the common source end of the differential comparator 11, and the two ends of the hysteresis resistor R1 are also connected to the drain of the first switch tube Q2 and the drain of the second switch tube Q3 respectively; the gate of the first switch tube Q2 is connected to the output end of the first inverter 14, the gate of the second switch tube Q3 is connected to the output end of the second inverter 15, the source of the first switch tube Q2 and the source of the second switch tube Q3 are connected to the drain of the power supply switch tube Q1, and the source of the power supply switch tube Q1 receives the reference current Iref.

[0029] Specifically, Figure 2The circuit diagram of the capacitor sampling module 1 (operational amplifier loop) is shown, which includes multiple MOS tubes, which are marked as Q1-Q15 in sequence; the differential comparator 11 is composed of Q4 and Q5, and the gate of Q4 serves as the reference end of the differential comparator and also as the positive end of the entire operational amplifier loop to receive the reference voltage Vref; the gate of Q5 serves as the capacitor end of the differential comparator and also as the reverse end of the entire operational amplifier loop to connect the chip pin capacitor; Q6 is a charging switch tube, which provides a charging current Iref for the chip pin capacitor when it is turned on; Q10 is a discharge switch tube, which provides a discharge path for the chip pin capacitor when it is turned on.

[0030] The common-gate current mirror 12 is composed of Q8 and Q9, the gates of Q8 and Q9 are interconnected, the source of Q8 (i.e., the first source of the common-gate current mirror) is connected to the drain of Q4 (i.e., the first drain of the differential comparator), and the source of Q9 (i.e., the second source of the common-gate current mirror) is connected to the drain of Q5 (i.e., the second drain of the differential comparator). The main function of the common-gate current mirror is to achieve accurate copying or mirroring of current. In the circuit, it can accurately copy the current of one current source to another current source, and the current values ​​of the two current sources are almost exactly the same.

[0031] The secondary operational amplifier circuit 13 is composed of Q7 and Q11. The gate of Q11 is connected to the source of Q5 (ie, the second source of the differential comparator). The current output by the differential comparator is amplified and then output to two inverters.

[0032] The first inverter 14 is composed of Q12 and Q13, and the second inverter 15 is composed of Q14 and Q15. The current output by the secondary operational amplifier circuit is inverted twice, and the output of the second inverter is a capacitor clock signal; the capacitance value of the chip pin capacitor is converted into a capacitor clock signal through the differential comparator 11, the common-gate current mirror 12, the secondary operational amplifier circuit 13, the first inverter 14, and the second inverter 15 in the operational amplifier loop. The operational amplifier loop also includes a hysteresis circuit 16, which is composed of It is composed of Q1, Q2, Q3 and R1, R1 is connected in series with the common source end of the differential comparator (between the sources of Q4 and Q5), the gate of Q2 is connected to the output end of the first inverter to receive the CLK_cap_n signal, and the gate of Q3 is connected to the output end of the second inverter to receive the CLK_cap signal (i.e., the capacitor clock signal); Q2 and Q3 in the hysteresis circuit are alternately turned on switches, and R1 is used to introduce hysteresis into the operational amplifier loop to avoid oscillation of the output signal when the gate voltage of Q5 is near the reference voltage.

[0033] The CLK_cap_n signal is the opposite of the CLK_cap signal.

[0034] .

[0035] In a preferred embodiment of the present invention, the main control module 3 includes: a difference calculation unit 31, which is used to divide and count the real-time capacitor clock signal when it is first acquired to obtain a latched counting result and latch it as a historical capacitor clock signal, and divide and count the real-time capacitor clock signal that is not acquired for the first time to obtain a real-time counting result, and obtain the capacitance value difference between the real-time capacitor clock signal and the historical capacitor clock signal according to the real-time counting result and the latched counting result.

[0036] In a preferred embodiment of the present invention, the main control module 3 normally outputs an indication signal indicating that the capacitance has not changed, and the main control module 3 also includes: a resolution storage unit 32, used to store a first resolution and a second resolution respectively; a resolution comparison unit 33, connected to the resolution storage unit 32, used to sum the capacitance value difference with the first resolution to obtain a first summation result, and when the highest bit of the first summation result is 1, the latched historical capacitance clock signal is updated to a real-time capacitance clock signal, and the capacitance value difference is summed with the second resolution to obtain a second summation result, and when the highest bit of the second summation result is 1, the normally output indication signal indicating that the capacitance has not changed is flipped to output an indication signal indicating a capacitance change.

[0037] Specifically, the system in this embodiment continuously collects the capacitor clock signal. During the first operation, the real-time capacitor clock signal collected is latched as the historical capacitor clock signal. During the subsequent operation, the real-time capacitor clock signal is collected regularly and the latched historical capacitor clock signal is used to calculate the difference to obtain the capacitance value difference. The capacitance value difference is summed with the first resolution to obtain the first summation result. When the highest bit of the first summation result is 1 (indicating that the capacitance value difference is greater than the first resolution), the historical capacitor clock signal is updated to the real-time capacitor clock signal collected this time to avoid false triggering caused by environmental changes; when the capacitance value difference is summed with the second resolution to obtain the second summation result, when the highest bit of the second summation result is 1 (indicating that the capacitance value difference is greater than the second resolution), it is considered that the capacitance value has changed. It can adapt to environmental changes such as ambient temperature and humidity, and flip the normally output indication signal indicating that the capacitance has not changed to output the indication signal indicating that the capacitance has changed. It can accurately detect changes in the capacitance value of the chip pin capacitor.

[0038] In a preferred embodiment of the present invention, the difference calculation unit 31 includes: a standard clock subunit 311, which is used to continuously output a standard clock signal with a standard duty cycle; a latch subunit 312, which is used to latch the latch count result as a historical capacitor clock signal; a frequency division counting subunit 313, which is connected to the standard clock unit 311 and the latch unit 312, and is used to record the number of cycles of the real-time capacitor clock signal during the period when the standard clock signal is at a low level as the latch count result when the real-time capacitor clock signal is first acquired, and is also used to record the number of cycles of the real-time capacitor clock signal during the period when the standard clock signal is at a low level as the real-time counting result when the real-time capacitor clock signal is acquired non-secondly.

[0039] In a preferred embodiment of the present invention, the difference calculation unit 31 also includes: a full adder subunit 314, which is used to invert the real-time counting result each time the real-time counting result is obtained, and then fully add and sum it with the latch counting result stored in the latch subunit; a difference calculation subunit 315, which is connected to the full adder subunit 314 and is used to perform an XOR operation on the value of the highest bit in the full addition result and the values ​​of each other bit in sequence to output the capacitance value difference.

[0040] Specifically, in this embodiment, the standard clock subunit mainly adjusts the clock signal (the independent clock signal is different from the capacitor clock signal of the capacitor sampling module) to a standard clock signal with a standard duty cycle. For example: through the signal synthesis unit composed of a frequency division circuit composed of a D flip-flop and a logic gate circuit, the independent clock signal is adjusted to a standard clock signal of 1024*Tosc (Tosc is the original output independent clock signal period), wherein the low level duty cycle is 1018*Tosc, and the high level duty cycle is 6*Tosc. During the low level period, the counting result will be read, and this time can adjust the low level time of the clock module according to the range of the capacitor. After outputting the high level of the standard clock signal, the standard clock subunit will also output a reset signal, that is, after every 1024*Tosc, the reset signal is output to the difference calculation unit for the next capacitor clock signal acquisition to ensure that the circuit is updated regularly.

[0041] The frequency division counting sub-unit divides and counts the capacitance clock signal of the capacitance sampling module (through the D-flip-flop frequency division circuit) (the capacitance clock signal is divided 14 times in the module). Its essence is to calculate the number of cycles of the capacitance clock signal within the low level 1018*Tosc of the standard clock signal. For example: Take Tosc=23.4us. When the system is running for the first time, the cycle of the real-time capacitance clock signal collected for the first time is 20us. The counting result is 1192 (the process is 23.4 / 20*1018=1191.06, which is rounded up to 1192). The latch counting result of the circuit is 00010010101000 (binary). The latch counting result is latched in the latch sub-unit as the historical capacitance clock signal.

[0042] In the subsequent operation process, the next real-time capacitor clock is collected. For example, if the capacitance change causes the capacitor clock signal period to change from 20us to 20.66us, the frequency division counting subunit divides and counts the capacitor clock signal, and the real-time counting result is 1154 (decimal, the process is 23.4 / 20.66*1018≈1153.74, which is rounded up to 1154), which is converted to 10010000010 (binary). The full adder subunit inverts the real-time counting result to obtain 11101101111101 (binary), and the inversion process is 16383-1154=15229 (decimal) (16383 is the maximum value of 14-bit binary after 14 frequency divisions) The maximum value is 111111111111111 (binary). The inverted real-time counting result 11101101111101 (binary) is then fully added and summed (the full addition is the bit-wise addition of each bit plus the adjacent low-bit carry) with the latched counting result 00010010101000 (binary). The full addition result is 100000000100101 (binary). The highest bit value in the full addition result is ORed with the values ​​of each other bit in turn to obtain the capacitance value difference 11111111011010 (binary), which is 16346 (decimal), equivalent to 16383-(1192-1154).

[0043] The resolution storage unit stores the first resolution and the second resolution; the value of the first resolution is 00000C 14 0C 14 C 13 C 12 C 11 C 10 C9C8 (binary); value of second resolution is 000C 14 0C 14 C 13 C 12 C 11 C 10C9C8C7C6 (binary); C in the resolution value xx It is the value of the corresponding bit of the latch counting result. For example, if the latch counting result is 00010010101000 (binary), then C4, C6, C8, and C11 are 1, and the rest are 0.

[0044] In this embodiment, the capacitance difference 11111111011010 (binary) and the first resolution 00000000001 (C 11 )001(C8)(binary) is summed to obtain the first summation result 111111111100010(binary). It can be seen that the highest bit result is 1, indicating that the capacitance value difference is greater than the first resolution. When the highest bit of the first summation result is 1, the latched historical capacitance clock signal is updated to the real-time capacitance clock signal. The specific situation is shown in Table 1. It can be seen from Table 1 that when the difference between the two counting results is greater than 1 / 128, the latch can be guaranteed to be unlocked and updated, and the minimum resolution that can identify the capacitance change to unlock the latch is 1 / 128.

[0045] Table 1: Relationship between count value and resolution

[0046]

[0047] In this embodiment, the capacitance difference 11111111011010 (binary) and the second resolution 0000000001 (C 11 )001(C8)01(C6) are summed to obtain the second summation result 111111111111110 (binary). It can be seen that the highest bit result is 1, indicating that the capacitance value difference is greater than the second resolution. When the highest bit of the second summation result is 1, the normal output indicating that the capacitance has not changed is flipped to output an indication signal indicating that the capacitance has changed.

[0048] The specific situation is shown in Table 1. It can be seen from Table 1 that when the difference between two counting results is greater than 1 / 32, the output result can be guaranteed to be flipped, and the minimum resolution that can identify the capacitance change to cause the output to flip is 1 / 32.

[0049] The system makes different degrees of judgment on the capacitance difference by setting the first resolution and the second resolution. When the capacitance difference is greater than the first resolution, the latched historical capacitance clock signal is updated; when the capacitance difference is greater than the second resolution, an indication signal indicating the capacitance change is output. This multi-resolution judgment mechanism improves the flexibility and accuracy of the system. Furthermore, by setting a reasonable resolution threshold, the system can effectively reduce the false alarm rate caused by small fluctuations in capacitance and improve the stability and reliability of the system. In this capacitance detection system, the circuit structure is simple, the algorithm is simple, and the detection accuracy is high. This sophisticated calculation method helps to accurately capture small changes in capacitance.

[0050] The present invention also provides a capacitance detection method, which is applied to the above capacitance detection system, such as Figure 3 As shown, it includes: step S1, the capacitance detection system controls the capacitance sampling module to convert the capacitance value of the chip pin capacitance into a capacitance clock signal; step S2, the capacitance detection system regularly obtains the capacitance clock signal as the real-time capacitance clock signal, and calculates the capacitance value difference between the real-time capacitance clock signal and the latched historical capacitance clock signal each time the real-time capacitance clock signal is obtained; step S3, the capacitance detection system determines whether the capacitance value difference is greater than the first resolution: if so, the latched historical capacitance clock signal is updated to the real-time capacitance clock signal; if not, return to step S2 to wait for the next capacitance clock signal; step S4, the capacitance detection system determines whether the capacitance value difference is greater than the second resolution: if so, output an indication signal indicating the capacitance change; if not, return to step S2 to wait for the next capacitance clock signal.

[0051] In this embodiment, step S3 and step S4 are parallel determination processes.

[0052] In a preferred embodiment of the present invention, the capacitance difference calculation process in step S2 includes: performing frequency division counting on the real-time capacitance clock signal acquired for the first time to obtain a latched counting result and latching it as a historical capacitance clock signal, and performing frequency division counting on the real-time capacitance clock signal acquired not for the first time to obtain a real-time counting result, and obtaining the capacitance value difference between the real-time capacitance clock signal and the historical capacitance clock signal according to the real-time counting result and the latched counting result.

[0053] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A capacitance detection system, characterized in that: include: A capacitance sampling module, connected to the chip pin capacitance, for converting the capacitance value of the chip pin capacitance into a capacitance clock signal; a main control module, connected to the capacitance sampling module, and configured to periodically acquire the capacitance clock signal as a real-time capacitance clock signal, calculate a capacitance value difference between the real-time capacitance clock signal and a latched historical capacitance clock signal each time the real-time capacitance clock signal is acquired, update the latched historical capacitance clock signal to the real-time capacitance clock signal when it is determined that the capacitance value difference is greater than a first resolution, and output an indication signal indicating a capacitance change when it is determined that the capacitance value difference is greater than a second resolution; The capacitance sampling module is an operational amplifier loop, the positive end of the operational amplifier loop receives a reference voltage, the reverse end of the operational amplifier loop receives a reference current and is connected to the chip pin capacitor, and is used to charge and discharge the chip pin capacitor and convert the capacitance value of the chip pin capacitor into a capacitance clock signal; The operational amplifier loop includes: A differential comparator, wherein the reference terminal of the differential comparator receives the reference voltage, the capacitor terminal of the differential comparator is connected to the chip pin capacitor, the source of the discharge switch tube and the drain of the charge switch tube, the source of the charge switch tube receives the reference current, and the drain of the discharge switch tube is grounded; A common-gate current mirror, wherein a first source and a second source of the common-gate current mirror are respectively connected to a first drain and a second drain of the differential comparator, a first gate and a second gate of the common-gate current mirror are connected to each other and to a first drain of the differential comparator, and a first drain and a second drain of the common-gate current mirror are grounded; A two-stage operational amplifier circuit, wherein the input end of the two-stage operational amplifier circuit is connected to the first drain of the common-gate current mirror, the output end of the two-stage operational amplifier circuit is connected in series with a first inverter and a second inverter in sequence, the output end of the first inverter is connected to the gate of the discharge switch tube, and the output end of the second inverter is connected to the main control module to output the capacitor clock signal.

2. The capacitance detection system according to claim 1, characterized in that: The op amp loop also includes hysteresis circuits, including: A hysteresis resistor is connected in series to the common source end of the differential comparator, and two ends of the hysteresis resistor are also connected to the drain of the first switch tube and the drain of the second switch tube respectively; The gate of the first switch tube is connected to the output end of the first inverter, the gate of the second switch tube is connected to the output end of the second inverter, the source of the first switch tube and the source of the second switch tube are connected to the drain of the power supply switch tube, and the source of the power supply switch tube receives a reference current.

3. The capacitance detection system according to claim 1, characterized in that: The main control module comprises: The difference calculation unit is used to perform frequency division counting on the real-time capacitor clock signal obtained for the first time to obtain a latched counting result and latch it as the historical capacitor clock signal, and to perform frequency division counting on the real-time capacitor clock signal not obtained for the first time to obtain a real-time counting result, and obtain the capacitance value difference between the real-time capacitor clock signal and the historical capacitor clock signal according to the real-time counting result and the latched counting result.

4. The capacitance detection system according to claim 3, characterized in that: The difference calculation unit comprises: A standard clock subunit, used for continuously outputting a standard clock signal with a standard duty cycle; A latch subunit, used for latching the latch counting result as the historical capacitor clock signal; The frequency division counting subunit is connected to the standard clock subunit and the latch subunit, and is used to record the number of cycles of the real-time capacitor clock signal during the period when the standard clock signal is at a low level as the latch counting result when the real-time capacitor clock signal is acquired for the first time, and is also used to record the number of cycles of the real-time capacitor clock signal during the period when the standard clock signal is at a low level as the real-time counting result when the real-time capacitor clock signal is acquired for a non-second time.

5. The capacitance detection system according to claim 4, characterized in that: The difference calculation unit also includes: A full adder subunit, configured to invert the real-time counting result each time the real-time counting result is obtained, and then perform a full addition and summation with the latch counting result stored in the latch subunit; The difference calculation subunit is connected to the full adder subunit and is used to perform XOR operation on the highest bit value in the full addition result and the values ​​of each bit in turn to output the capacitance value difference.

6. The capacitance detection system according to claim 1, characterized in that: The main control module normally outputs an indication signal indicating that the capacitance has not changed, and the main control module further includes: a resolution storage unit, used to store the first resolution and the second resolution respectively; A resolution comparison unit, connected to the resolution storage unit, is used to sum the capacitance value difference with the first resolution to obtain a first summation result, update the latched historical capacitance clock signal to the real-time capacitance clock signal when the highest bit of the first summation result is 1, and sum the capacitance value difference with the second resolution to obtain a second summation result, and flip the normally output indication signal indicating no capacitance change to an indication signal output indicating capacitance change when the highest bit of the second summation result is 1.

7. A capacitance detection method, characterized in that: A capacitance detection system as claimed in any one of claims 1 to 6, comprising: Step S1, the capacitance detection system controls the capacitance sampling module to convert the capacitance value of the chip pin capacitance into a capacitance clock signal; Step S2, the capacitance detection system periodically acquires the capacitance clock signal as a real-time capacitance clock signal, and calculates a capacitance value difference between the real-time capacitance clock signal and a latched historical capacitance clock signal each time the real-time capacitance clock signal is acquired; Step S3, the capacitance detection system determines whether the capacitance value difference is greater than a first resolution: If yes, updating the latched historical capacitor clock signal to the real-time capacitor clock signal; If not, return to step S2 to wait for obtaining the next capacitor clock signal; Step S4, the capacitance detection system determines whether the capacitance value difference is greater than a second resolution: If so, an indication signal indicating the capacitance change is output; If not, the process returns to step S2 to wait for obtaining the next capacitor clock signal.

8. The capacitance detection method according to claim 7, characterized in that: The capacitance difference calculation process in step S2 includes: The real-time capacitor clock signal obtained for the first time is divided and counted to obtain a latched counting result and latched as the historical capacitor clock signal, and the real-time capacitor clock signal obtained not for the first time is divided and counted to obtain a real-time counting result, and the capacitance value difference between the real-time capacitor clock signal and the historical capacitor clock signal is obtained according to the real-time counting result and the latched counting result.

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