A high voltage level conversion circuit with symmetrical pulse current auxiliary structure

Abstract

The application discloses a high-voltage level conversion circuit with a symmetrical pulse current structure and belongs to the technical field of integrated circuits.The circuit comprises a level conversion module, a symmetrical pulse current auxiliary module and a latch output module.The level conversion module of the application improves the defect that the circuit may be mis-triggered when the power voltage rapidly jumps in the prior art, and the noise immunity of the circuit is improved.The symmetrical pulse current auxiliary module of the application overcomes the defect that the transmission delay of the rising edge and the falling edge of an input signal is asymmetric in the prior art, so that the application can guarantee a high transmission speed while maintaining high transmission delay symmetry, and effectively suppresses the problem that the digital signal input and output may be distorted in a high-speed circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and further relates to a high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure in the technical field of conversion circuits. The present application can be used in high-voltage level conversion in high-speed circuits such as DC-DC converters, motor drivers, and gate drivers. BACKGROUND

[0002] With the rapid development of modern microelectronics technology, high-voltage switching power supplies, especially DC-DC step-down converters, are widely used in various industrial and consumer electronic products. A high-voltage DC-DC power chip is usually composed of a low-voltage logic circuit and a high-voltage drive circuit. The low-voltage logic is usually around 5V, while the high-voltage drive signal can be as high as tens of volts or even hundreds of volts. Therefore, a level conversion circuit is needed to realize the conversion from the low-voltage power rail to the high-voltage power rail. As a transmission bridge between the low-voltage control signal and the high-voltage drive signal, the level conversion circuit plays a crucial role in the performance of the entire power chip system

[0003] Traditional high-voltage level conversion circuits mostly use cross-coupled structures. This structure can avoid the generation of static current, helping to reduce system power consumption. However, due to the existence of the parasitic capacitance of high-voltage transistors, the traditional cross-coupled structure has the disadvantages of slow conversion speed and asymmetric transmission delay of rising and falling edges, which can cause distortion of high-frequency digital signals during transmission. In addition, in high-voltage DC-DC power chips, the voltage variation rate of the switching node VSW is very high, i.e. dVSW / dt is high. The high-voltage level conversion circuit of the traditional cross-coupled structure may have an output signal error problem, leading to abnormal closing of the power switch and causing disorder of the converter system function.

[0004] Guilin University of Electronic Technology disclosed a wide-range high-speed dual-output level shift circuit in its applied patent document "A Wide-Range High-Speed Dual-Output Level Shift Circuit" (Application No. 202310762526.2, Publication No. CN 116633340 A). The circuit uses a cross-coupled structure and introduces a transient enhancement structure to reduce time delay, quickly convert the input signal, and further increase the response speed using a pull-up and pull-down circuit to achieve high-speed level shifting. The design of the dual-output structure allows the circuit to output two logically opposite signals. However, the circuit still has the following deficiencies: the pull-up structure in the transient enhancement structure is composed of a resistor and a PMOS, and the pull-down structure is composed of an NMOS, which has a large difference in pull-up and pull-down speed. The transmission delay of the circuit is asymmetric at the rising and falling edges, which can cause distortion of high-frequency digital signals during transmission.

[0005] A high-voltage level conversion circuit is disclosed in the patent document "Level Shifting Circuit, Level Shifter and Buck DC-DC Converter" (Application No. 202310628578.0, Publication No. CN 116722859 A) applied by Changgong Microelectronics Co., Ltd. The circuit includes a signal input port, a rising edge trigger circuit, a falling edge trigger circuit, a first current mirror, a second current mirror, a latch circuit, and a shielding circuit. The technology uses the shielding circuit to make the first current mirror and the second current mirror cut off when dVSW / dt is high, so that current does not flow to the latch circuit, achieving the effect of current shielding, thereby ensuring that the output of the latch circuit does not error due to excessive dVSW / dt, and improving the reliability of the level conversion circuit. However, the circuit still has two shortcomings, first, the introduction of more transmission gates by the shielding circuit slows down the level conversion speed; in addition, the circuit has the problem of asymmetric transmission delay of signal rising and falling edges, which still has a great limitation on high-speed signal conversion.

[0006] A high-speed low-power high-voltage level conversion circuit is disclosed in the patent document "High-speed low-power high-voltage level conversion circuit" (Application No. 202310680026.4, Publication No. CN 116599517 A) applied by Nanjing Weiliang Electronics Co., Ltd. The circuit uses a double-pulse generation circuit to output a pulse signal according to the input signal, turns on the corresponding path, and transmits the corresponding signal to the double-pulse latch circuit, which is mainly used for level conversion and output of the received signal. The circuit effectively reduces power consumption by pulling up through a resistor with a large resistance, and uses the source-drain parasitic diode of the clamp NMOS tube to speed up the pull-down speed, so that the level conversion has a high conversion speed and a low power loss. However, the circuit still has two shortcomings, the circuit has poor noise immunity, and when dVsw / dt is too high, it may introduce a lot of noise, causing output logic errors; at the same time, due to the large difference between the pull-up speed of the resistor and the pull-down speed of the NMOS, the asymmetric transmission delay problem of the rising and falling edges of the circuit is more serious. SUMMARY

[0007] The present application aims to solve the problems of slow level conversion speed, poor noise immunity, and asymmetric transmission delay in existing level converter circuits by providing a high-voltage level conversion circuit with a symmetric pulse current auxiliary structure.

[0008] The idea for achieving the object of the present application is that the present application improves the traditional high voltage level conversion circuit by adding a symmetrical pulse current auxiliary structure, which generates corresponding pulse currents at the rising and falling edges of the input signal, and quickly changes the high and low states of the output node level of the level conversion circuit, thereby solving the slow level conversion speed in the existing level converter circuit. The present application adds a symmetrical pulse current auxiliary structure, which is completely symmetrical, and generates pulse currents of the same size at the rising and falling edges of the input signal, so that the output node level conversion speed of the level conversion circuit is the same, solving the problem of asymmetric transmission delay in the prior art. The present application adds a clamping diode in the level conversion circuit, which limits the gate-source voltage of the transistor within the breakdown voltage range of the diode, avoiding the problem of high voltage breakdown, and improving the noise immunity of the level conversion circuit.

[0009] In order to achieve the above object, the high voltage level conversion circuit of the present application comprises a level conversion module, a symmetrical pulse current auxiliary module and a latching output module.

[0010] The level conversion module is used to convert the input signal from a low voltage domain to a high voltage domain.

[0011] The symmetrical pulse current auxiliary module generates pulse currents of the same size at the rising and falling edges of the input signal, and quickly changes the high and low states of the output node level of the level conversion circuit.

[0012] The latching output module is used to receive and shape the output signal of the level conversion module and output as an output signal.

[0013] The two input terminals of the level conversion module are connected to the input signal VIN, and the other input terminal is connected to the output terminal of the symmetrical pulse current auxiliary module; the output terminal of the level conversion module is connected to the input terminal of the latching output module; the input terminal of the symmetrical pulse current auxiliary module is connected to the input signal VIN, and the output terminal of the symmetrical pulse current auxiliary module is connected to one input terminal of the level conversion module; the input terminal of the latching output module is connected to the output terminal of the level conversion module, and the output terminal of the latching output module is connected to the output signal VOUT.

[0014] Compared with the prior art, the present application has the following advantages:

[0015] First, the present application introduces a pulse current auxiliary structure in a high voltage level conversion circuit, which generates corresponding pulse currents at the rising and falling edges of the input signal, and quickly changes the high and low states of the output node level of the level conversion circuit, overcoming the slow level conversion speed defect in the existing level converter circuit, and improving the level conversion speed.

[0016] Secondly, since the pulse current auxiliary structure introduced by the present application is completely symmetrical, the generated pulse current is equal in size, thus the pull-up and pull-down speed of the level conversion module output node is consistent at the rising and falling edges of the input signal, overcoming the defect that the transmission delay of the prior art level conversion circuit is not equal at the rising and falling edges of the input signal, effectively suppressing the problem that the digital signal input and output may be distorted in the high-speed circuit, so that the present application maintains high transmission delay symmetry while ensuring high level conversion speed.

[0017] Thirdly, since the present application adds a clamping diode in the level conversion circuit, the transistor gate-source voltage is limited within the breakdown voltage range of the diode, avoiding the problem that high voltage breakdown may occur in the prior art, so that the present application has high anti-interference performance. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is the circuit of the present application;

[0019] Figure 2 is the circuit diagram of the embodiment of the present application;

[0020] Figure 3 is the waveform diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings described below are only part of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0023] Reference Figure 1 Further description is made on the electrical principle of the overall circuit of the present application.

[0024] The high-voltage level conversion circuit of the present application comprises a level conversion module, a symmetrical pulse current auxiliary module and a latching output module.

[0025] The level conversion module is used to convert the input signal from the low-voltage domain to the high-voltage domain.

[0026] Symmetrical pulse current auxiliary module: used to generate pulse currents of the same magnitude on the rising and falling edges of the input signal, which are input into the level conversion module to improve the speed of level conversion and the symmetry of transmission delay.

[0027] Latch output module: used to receive the output signal of the level conversion module and output it as an output signal after shaping.

[0028] The level conversion module in the high-voltage level conversion circuit has two input terminals, one of which is connected to the input signal VIN, and the other input terminal is connected to the output terminal of the symmetrical pulse current auxiliary module. The output terminal of the level conversion module is connected to the input terminal of the latch output module, the input terminal of the symmetrical pulse current auxiliary module is connected to the input signal VIN, and the output terminal of the symmetrical pulse current auxiliary module is connected to an input terminal of the level conversion module. The input terminal of the latch output module is connected to the output terminal of the level conversion module, and the output terminal of the latch output module is connected to the output signal VOUT.

[0029] Reference Figure 2 , the structure of a high-voltage level conversion circuit disclosed in an embodiment of the present invention is further described in detail.

[0030] The level conversion module includes a first inverter I1 of a low-voltage power rail, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first resistor R1, a second resistor R2, a first diode Z1, and a second diode Z2.

[0031] The input of the first inverter I1 is connected to the input signal VIN, and the output is connected to the gate of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to the output of the inverter I1, the source is connected to the low-voltage domain ground VSSL, and the drain is connected to the source of the third NMOS transistor MN3. The gate of the second NMOS transistor MN2 is connected to the input signal VIN, the source is connected to the low-voltage domain ground VSSL, and the drain is connected to the source of the fourth NMOS transistor MN4. The gate of the third NMOS transistor MN3 is connected to the low-voltage domain power supply VDDL, the source is connected to the drain of the first NMOS transistor MN1, and the drain is connected to the drain of the first PMOS transistor MP1. The gate of the fourth NMOS transistor MN4 is connected to the low-voltage domain power supply VDDL, the source is connected to the drain of the second NMOS transistor MN2, and the drain is connected to the drain of the second PMOS transistor MN2.

[0032] The gate of the first PMOS tube MP1 is connected with the ground VSSH of the high voltage domain, the source is connected with node A, and the drain is connected with the drain of the third NMOS tube MN3; the gate of the second PMOS tube MP2 is connected with the ground VSSH of the high voltage domain, the source is connected with node B, and the drain is connected with the drain of the fourth NMOS tube MN2; the gate of the third PMOS tube MP3 is connected with node B, and the drain is connected with node A; the gate of the fourth PMOS tube MP4 is connected with node A, the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with node B.

[0033] The anode of the first diode Z1 is connected with node A, and the cathode is connected with the power supply VDDH of the high voltage domain; the anode of the second diode Z2 is connected with node B, and the cathode is connected with the power supply VDDH of the high voltage domain.

[0034] Specifically, the third NMOS tube MN3, the fourth NMOS tube MN4, the first PMOS tube MP1 and the second PMOS tube MP2 are high-voltage tubes, and the diodes Z1 and Z2 are Zener diodes.

[0035] The node A and the node B are output ends of the level conversion module and are also input ends of the latch type output module. The node A includes the source of the first PMOS tube MP1, the drain of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4, the drain of the tenth NMOS tube MN10, the drain of the ninth PMOS tube MP9, the anode of the first diode Z1 and one input end of the first NAND gate N1. The node B includes the source of the second PMOS tube MP2, the gate of the third PMOS tube MP3, the drain of the fourth PMOS tube MP4, the drain of the ninth NMOS tube MP9, the drain of the tenth PMOS tube MP10, the anode of the second diode Z2 and one input end of the second NAND gate N2.

[0036] In one embodiment of the embodiment of the present application, the symmetrical pulse current auxiliary module includes a first pulse generator, a second pulse generator, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a second inverter I2 of a low voltage domain, a first resistor R1 and a second resistor R2.

[0037] The input end of the first pulse generator is connected with the input signal VIN, and the output end is connected with the gate of the fifth NMOS tube MN5.

[0038] The gate and the drain of the fifth PMOS transistor MP5 are connected with the drain of the fifth NMOS transistor MN5 and the gate of the ninth PMOS transistor MP9 respectively, and the source is connected with the power supply VDDH of the high voltage domain. The gate of the seventh PMOS transistor MP7 is connected with the drain of the fifth NMOS transistor MN5, the drain and the gate of the fifth PMOS transistor MP5 and the gate of the ninth PMOS transistor MP9 respectively, and the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the gate and the drain of the seventh NMOS transistor MN7 and the gate of the ninth NMOS transistor MN9. The gate of the ninth PMOS transistor MP9 is connected with the gate of the seventh PMOS transistor MP7, the drain of the fifth NMOS transistor MN5 and the drain and the gate of the fifth PMOS transistor MP5, and the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the node A. The first resistor R1 is connected between the source of the fifth NMOS transistor MN5 and the ground of the low voltage domain.

[0039] The gate and the drain of the fifth PMOS transistor MP5 are connected with the drain of the fifth NMOS transistor MN5 and the gate of the ninth PMOS transistor MP9 respectively, and the source is connected with the power supply VDDH of the high voltage domain. The gate of the seventh PMOS transistor MP7 is connected with the drain of the fifth NMOS transistor MN5, the drain and the gate of the fifth PMOS transistor MP5 and the gate of the ninth PMOS transistor MP9 respectively, and the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the gate and the drain of the seventh NMOS transistor MN7 and the gate of the ninth NMOS transistor MN9. The gate of the ninth PMOS transistor MP9 is connected with the gate of the seventh PMOS transistor MP7, the drain of the fifth NMOS transistor MN5 and the drain and the gate of the fifth PMOS transistor MP5, and the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the node A. The first resistor R1 is connected between the source of the fifth NMOS transistor MN5 and the ground of the low voltage domain.

[0040] The input of the second inverter I2 is connected with the input signal VIN, and the output is connected with the input of the second pulse generator. The input of the second pulse generator 2 is connected with the output of the inverter I2, and the output is connected with the gate of the sixth NMOS transistor MN6.

[0041] The gate of the sixth NMOS transistor MN6 is connected with the output of the second pulse generator, the source is connected with one end of the second resistor R2, and the drain is connected with the drain of the sixth PMOS transistor MP6. The gate and the drain of the eighth NMOS transistor MN8 are connected with the drain of the eighth PMOS transistor MP8 and the gate of the tenth NMOS transistor MN10 respectively, and the source is connected with the ground VSSH of the high voltage domain. The gate of the tenth NMOS transistor MN10 is connected with the gate and the drain of the eighth NMOS transistor MN8 and the drain of the eighth PMOS transistor MP8 respectively, the source is connected with the ground VSSH of the high voltage domain, and the drain is connected with the node A.

[0042] The gate and the drain of the sixth PMOS transistor MP6 are connected with the drain of the sixth NMOS transistor MN6, the gate of the eighth PMOS transistor MP8 and the gate of the tenth PMOS transistor MP10 respectively, and the source is connected with the power supply VDDH of the high voltage domain. The gate of the eighth PMOS transistor MP8 is connected with the drain of the sixth NMOS transistor MN6, the drain and the gate of the sixth PMOS transistor MP6 and the gate of the tenth PMOS transistor MP10 respectively, the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the gate and the drain of the eighth NMOS transistor MN8 and the gate of the tenth NMOS transistor MN10. The gate of the tenth PMOS transistor MP10 is connected with the gate of the sixth PMOS transistor MP6, the drain of the sixth NMOS transistor MN6 and the drain and the gate of the sixth PMOS transistor MP6, the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the node B. The second resistor R2 is connected between the source of the sixth NMOS transistor MN6 and the ground of the low voltage domain.

[0043] Specifically, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are high voltage transistors. The first pulse generator and the second pulse generator are both rising edge triggered, that is, a high level pulse is generated at the rising edge of the input signal.

[0044] The latch type output module comprises a first NAND gate N1 and a second NAND gate N2 in the high voltage domain, and a third inverter I3 in the high voltage domain.

[0045] One input end of the first NAND gate N1 is connected with the node A, the other input end is connected with the output end of the second NAND gate N2, and the output end is connected with the input end of the third inverter I3. One input end of the second NAND gate N2 is connected with the node B, the other input end is connected with the output end of the first NAND gate N1, and the output end is connected with one input end of the first NAND gate N1. The input end of the third inverter I3 is connected with the output end of the first NAND gate N1, and the output end serves as the final output signal VOUT.

[0046] The technical scheme adopted by the embodiment of the present application is based on the traditional high voltage level conversion circuit, and a symmetrical pulse current auxiliary module is introduced to accelerate the speed of level conversion and improve the transmission delay symmetry of rising edge and falling edge. Therefore, the circuit has the advantages of fast conversion speed and high transmission delay symmetry.

[0047] The function of the embodiment of the present application is to convert a low voltage input signal into a high voltage output signal. As shown in the above description of the embodiment of the present application, Figure 2 when the high voltage power supply rails VDDH and VSSH and the low voltage power supply rails VDDL and VSSL are constant values, the Figure 3 .

[0048] Figure 3is a waveform diagram of input signal state flip-flop of the embodiment of the present application. By Figure 3 It can be seen that the input end VIN voltage works between VSSL and VDDL, and the output end VOUT voltage works between VSSH and VDDH.

[0049] In combination with Figure 3 the input signal state flip-flop waveform diagram, the working principle of the embodiment of the present application is described in detail.

[0050] When the input end jumps from low level VSSL to high level VDDL, the second NMOS tube MN2 is turned on, slowly pulling down the node B, and at the same time, the input signal generates a high level pulse through the first pulse generator in the symmetrical pulse current auxiliary module and turns on the fifth NMOS tube MN5, and then generates a pulse current Ipulse1. The seventh NMOS tube MN7, the ninth NMOS tube MN9, the fifth PMOS tube MP5, the seventh PMOS tube MP7, and the ninth PMOS tube MP9 form a current mirror, which copies the pulse current and quickly pulls up the node A through the ninth PMOS tube MP9 and quickly pulls down the node B through the ninth NMOS tube MN9. At this point, the two input ends of the latch output module are pulled up to VDDH and pulled down to VSSH respectively, and through the latch output structure, the output signal jumps from low level VSSH to high level VDDH. After the pulse current disappears, the high and low level state of the input end of the latch output structure is maintained, the pulse current duration is short, and the overall power consumption is low.

[0051] When the input end jumps from high level VDDL to low level VSSL, the first NMOS tube MN1 is turned on, slowly pulling down the node A, and at the same time, the input signal generates a high level pulse through the pulse generator 2 in the symmetrical pulse current auxiliary module and turns on the sixth NMOS tube MN6, and then generates a pulse current Ipulse2. The eighth NMOS tube MN8, the tenth NMOS tube MN10, the sixth PMOS tube MP6, the eighth PMOS tube MP8, and the tenth PMOS tube MP10 form a current mirror, which copies the pulse current and quickly pulls up the node B through the tenth PMOS tube MP10 and quickly pulls down the node A through the tenth NMOS tube MN10. At this point, the second and first input ends of the latch output structure are pulled up to VDDH and pulled down to VSSH respectively, and through the latch output structure, the output signal jumps from high level VDDH to low level VSSH. After the pulse current disappears, the high and low level state of the input end of the latch output structure is maintained, and similarly, the pulse current duration is short, and the overall power consumption is low.

[0052] For the application of the DC-DC power chip, when the high-voltage power rail VSSH jumps from high voltage to low voltage suddenly, due to the existence of the parasitic capacitance, the difference between the gate potential of the third PMOS tube MP3 and the fourth PMOS tube MP4 and VDDH may increase suddenly, at this time, the first diode Z1 and the second diode Z2 are reversely broken down, the gate-source voltage of the third PMOS tube MP3 and the fourth PMOS tube MP4 is clamped at about 6V, and the device will not be damaged, and the anti-interference degree of the level conversion circuit is improved.

[0053] The above embodiments are only one implementation of the present application, and it should be understood that those skilled in the art can make changes in form and details without creative labor according to the basic principles and structure of the present application. Therefore, the modifications and changes derived from the idea of the present application are still within the protection scope of the claims of the present application.

Claims

1. A high voltage level shifting circuit having a symmetric pulsed current assist structure, comprising: The level conversion module, the latch type output module are characterized by further comprising symmetrical pulse current auxiliary module, wherein, The level conversion module is used for converting the input signal from the low voltage domain to the high voltage domain; The symmetrical pulse current auxiliary module generates the pulse current with the same size at the rising edge and the falling edge of the input signal respectively, and rapidly changes the high and low states of the level conversion circuit output node level; The symmetrical pulse current auxiliary module comprises a first pulse generator, a second pulse generator, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a second inverter I2 in the low voltage domain, a first resistor R1 and a second resistor R2; The input end of the first pulse generator is connected with the input signal VIN, and the output end is connected with the gate of the fifth NMOS tube MN5; the source of the fifth NMOS tube MN5 is connected with one end of the first resistor R1, and the drain is connected with the drain of the fifth PMOS tube MP5; the gate and the drain of the seventh NMOS tube MN7 are connected with the drain of the seventh PMOS tube MP7 and the gate of the ninth NMOS tube MN9 respectively, and the source is connected with the ground VSSH of the high voltage domain; the gate of the ninth NMOS tube MN9 is connected with the gate and the drain of the seventh NMOS tube MN7 and the drain of the seventh PMOS tube MP7, the source is connected with the ground VSSH of the high voltage domain, and the drain is connected with the node B; The gate and the drain of the seventh PMOS tube MP7 are connected with the drain of the fifth NMOS tube MN5, the drain and the gate of the fifth PMOS tube MP5 and the gate of the ninth PMOS tube MP9, the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the gate and the drain of the seventh NMOS tube MN7 and the gate of the ninth NMOS tube MN9; the gate of the ninth PMOS tube MP9 is connected with the gate of the seventh PMOS tube MP7, the drain of the fifth NMOS tube MN5, the drain and the gate of the fifth PMOS tube MP5, the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the node A; the first resistor R1 is connected between the source of the fifth NMOS tube MN5 and the ground of the low voltage domain; The input end of the second inverter I2 is connected with the input signal VIN, and the output end is connected with the input end of the second pulse generator; the output end of the second pulse generator is connected with the gate of the sixth NMOS tube MN6; The gate and the drain of the sixth PMOS transistor MP6 are connected with the drain of the sixth NMOS transistor MN6 and the gate of the eighth PMOS transistor MP8 and the tenth PMOS transistor MP10 respectively, and the source is connected with the power supply VDDH of the high-voltage domain; the gate of the eighth PMOS transistor MP8 is connected with the drain of the sixth NMOS transistor MN6, the drain and the gate of the sixth PMOS transistor MP6 and the gate of the tenth PMOS transistor MP10 respectively, and the source is connected with the power supply VDDH of the high-voltage domain, and the drain is connected with the gate and the drain of the eighth NMOS transistor MN8 and the gate of the tenth NMOS transistor MN10; the gate of the tenth PMOS transistor MP10 is connected with the gate of the sixth PMOS transistor MP6, the drain of the sixth NMOS transistor MN6 and the drain and the gate of the sixth PMOS transistor MP6, and the source is connected with the power supply VDDH of the high-voltage domain, and the drain is connected with the node B; the second resistor R2 is connected between the source of the sixth NMOS transistor MN6 and the ground of the low-voltage domain; The latch type output module is used for receiving the output signal of the level conversion module and outputting the shaped output signal as an output signal. The level conversion module in the high-voltage level conversion circuit has two input ends, one of which is connected with the input signal VIN, and the other input end is connected with the output end of the symmetrical pulse current auxiliary module; the output end of the level conversion module is connected with the input end of the latch type output module; the input end of the symmetrical pulse current auxiliary module is connected with the input signal VIN, and the output end of the symmetrical pulse current auxiliary module is connected with one input end of the level conversion module; the input end of the latch type output module is connected with the output end of the level conversion module, and the output end of the latch type output module is connected with the output signal VOUT.

2. The high voltage level shifting circuit having a symmetric pulse current assist structure according to claim 1, wherein, The level conversion module comprises a first inverter I1 of a low-voltage power supply rail, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first diode Z1 and a second diode Z2.

3. The high voltage level shifting circuit having a symmetric pulsed current assist structure of claim 1, wherein, ​ The input end of the first inverter I1 is connected with the input signal VIN, and the output end is connected with the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is connected with the ground VSSL of the low voltage domain, and the drain is connected with the source of the third NMOS transistor MN3; the gate of the second NMOS transistor MN2 is connected with the input signal VIN, the source is connected with the ground VSSL of the low voltage domain, and the drain is connected with the source of the fourth NMOS transistor MN4; the gate of the third NMOS transistor MN3 is connected with the power supply VDDL of the low voltage domain, the source is connected with the drain of the first NMOS transistor MN1, and the drain is connected with the drain of the first PMOS transistor MP1; the gate of the fourth NMOS transistor MN4 is connected with the power supply VDDL of the low voltage domain, the source is connected with the drain of the second NMOS transistor MN2, and the drain is connected with the drain of the second PMOS transistor MN2; The gate of the first PMOS transistor MP1 is connected with the ground VSSH of the high voltage domain, the source is connected with the node A, and the drain is connected with the drain of the third NMOS transistor MN3; the gate of the second PMOS transistor MP2 is connected with the ground VSSH of the high voltage domain, the source is connected with the node B, and the drain is connected with the drain of the fourth NMOS transistor MN4; the gate of the third PMOS transistor MP3 is connected with the node B, and the drain is connected with the node A; the gate of the fourth PMOS transistor MP4 is connected with the node A, the source is connected with the power supply VDDH of the high voltage domain, and the drain is connected with the node B; The anode of the first diode Z1 is connected with the node A, and the cathode is connected with the power supply VDDH of the high voltage domain; the anode of the second diode Z2 is connected with the node B, and the cathode is connected with the power supply VDDH of the high voltage domain.

4. The high voltage level shifting circuit having a symmetric pulsed current assist structure according to claim 3, wherein, The third NMOS transistor MN3, the fourth NMOS transistor MN4, the first PMOS transistor MP1 and the second PMOS transistor MP2 are all high voltage transistors.

5. The high voltage level shifting circuit having a symmetric pulsed current assist structure according to claim 3, wherein, The first diode Z1 and the second diode Z2 are both Zener diodes.

6. The high voltage level shifting circuit having a symmetric pulsed current assist structure of claim 1, wherein, The seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are both high voltage transistors.

7. The high voltage level shifting circuit having a symmetric pulsed current assist structure according to claim 1, wherein, The first pulse generator and the second pulse generator are both rising edge triggered, that is, a high level pulse is generated at the rising edge of the input signal.

8. The high voltage level shifting circuit having a symmetric pulsed current assist structure of claim 1, wherein, The latch type output module comprises a first NAND gate N1 and a second NAND gate N2 of the high voltage domain, and a third inverter I3 of the high voltage domain; One input end of the first NAND gate N1 is connected with the node A, the other input end is connected with the output end of the second NAND gate N2, the output end of the first NAND gate N1 is connected with the input end of the third inverter I3; one input end of the second NAND gate N2 is connected with the node B, the other input end is connected with the output end of the first NAND gate N1, and the output end of the second NAND gate N2 is connected with one input end of the first NAND gate N1; the input end of the third inverter I3 is connected with the output end of the first NAND gate N1, and the output end of the third inverter I3 serves as the final output signal VOUT.

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