A multi-channel analog pulse amplitude sampling circuit

Abstract

The present invention discloses a multi-channel analog pulse amplitude sampling circuit, comprising: an analog circuit, a signal sampling circuit, and a digital circuit, wherein multiple signal processing circuits in the analog circuit share a signal sampling circuit and a digital circuit. Each signal processing circuit includes a preamplifier, a pole-zero cancellation circuit, a filter shaping circuit, and a signal triggering and extraction circuit. The signal triggering and extraction circuit is composed of a peak holding circuit, a proportional amplification circuit, and a voltage comparator, which completes signal peak acquisition and compares the signals before and after acquisition to obtain the signal amplitude and trigger signal. The trigger signal of each channel instructs the digital circuit to control the ADC to sample its signal amplitude. The multi-channel analog pulse amplitude sampling circuit is powered by a single power supply and uses a DAC to adjust the DC offset and signal baseline, thereby improving the voltage utilization range of signal amplification. By reducing the number of operational amplifiers used in the analog circuit, power consumption and cost are reduced.

Description

Technical Field

[0001] The invention belongs to the field of nuclear signal detection and processing, and in particular relates to a multi-channel analog pulse amplitude sampling circuit. Background Art

[0002] In the current context of globalization, nuclear technology has been widely applied in key areas such as energy, industry, agriculture, and healthcare, significantly promoting socioeconomic development. Nuclear technology is inseparable from energy spectrum measurement. Nuclear energy spectrum measurement technology is primarily used to measure and analyze the energy distribution of particles emitted by nuclear radiation sources, thereby obtaining information about the type, abundance, reaction mechanism, and material composition of radionuclides. Energy spectrum acquisition is typically achieved through statistical analysis of pulse amplitude histograms. Pulse amplitude refers to the height of the pulse signal and is generally proportional to the energy of the incident particle or radiation. A multichannel pulse amplitude analyzer is an instrument used to measure the amplitude distribution of pulse signals and is a key component of nuclear energy spectrum measurement systems.

[0003] Multi-channel pulse amplitude analyzers are generally categorized as analog or digital, differing primarily in their signal processing methods. Digital multi-channel pulse amplitude analyzers convert received analog signals into digital form for processing, typically offering higher accuracy and flexibility, facilitating data storage and analysis. However, these analyzers often consume high power and have complex circuitry. Analog multi-channel pulse amplitude analyzers process analog signals directly. While their accuracy is relatively low, they typically offer a simpler circuit structure, faster response speed, lower power consumption, and lower cost, making them difficult to replace in systems with a large number of channels.

[0004] Multi-channel analog pulse amplitude analyzers typically include a preamplifier, a filter shaping circuit, a peak hold circuit, and the like. The operational amplifiers in existing multi-channel analog pulse amplitude sampling circuits generally use dual power supplies, allowing the signal to be amplified in both the positive and negative half cycles. However, dual power supplies increase power consumption and may require more space to accommodate additional power components and wiring. At the same time, in the peak hold circuit, a trigger signal needs to be generated by a fast shaping circuit and transmitted to a microcontroller or FPGA. The microcontroller or FPGA compares the output signal of the fast shaping circuit with the set detection threshold. If a signal higher than the set threshold is detected, the peak hold is controlled to discharge after a delay, thereby resetting it. With this circuit design, the entire circuit requires too many chips, making the circuit design more complex, resulting in increased circuit power consumption and cost. Summary of the Invention

[0005] To address the technical problems encountered in the prior art, the present invention provides a multi-channel analog pulse amplitude sampling circuit. Compared to existing multi-channel analog pulse amplitude analyzers, this circuit features a simpler circuit structure, lower power consumption, and lower cost. The circuit comprises an analog circuit, a signal sampling circuit, and a digital circuit. The analog circuit's signal processing circuit processes N signals (N ≥ 1) via N signal processing circuits. Each signal processing circuit consists of a preamplifier, a pole-zero cancellation circuit, a filter shaping circuit, and a signal triggering and extraction circuit. Each signal triggering and extraction circuit comprises a peak hold circuit, a proportional amplifier circuit, and a voltage comparator. When a pulse signal arrives, a trigger is generated by comparing the signals before and after the peak hold circuit, eliminating the need for additional signal processing circuits. After receiving the trigger signal, the FPGA or MCU outputs a delayed reset signal to discharge the peak hold circuit, thereby resetting the circuit. The signal sampling circuit comprises a multi-channel analog switch and an ADC. The N signal processing circuits share a single signal sampling circuit and a digital circuit. Time-sharing sampling reduces the number of ADCs required for the signal sampling circuit. The digital circuit consists of FPGA or MCU and DAC. The DAC is used to adjust the DC offset and signal baseline of the op amp in the signal processing circuit to maximize the voltage range of the signal amplification.

[0006] In order to solve the technical problem, the technical solution of the present invention is:

[0007] A multi-channel analog pulse amplitude sampling circuit, comprising: an analog circuit, a signal sampling circuit, and a digital circuit; the analog circuit interacts with the digital circuit, the analog circuit is connected to the signal sampling circuit, the signal sampling circuit is connected to the digital circuit, and the digital circuit is connected to a host computer;

[0008] The analog circuit includes N signal processing circuits, N≥1, each including: a preamplifier, a pole-zero cancellation circuit, a filter shaping circuit, a signal triggering and extraction circuit; the signal triggering and extraction circuits each include a peak holding circuit, a proportional amplification circuit and a voltage comparator; the digital circuit includes: an FPGA or an MCU, a DAC, and the DAC is used to adjust the DC offset and signal baseline of the operational amplifier in the signal processing circuit; when a pulse signal arrives, a trigger is generated by comparing the signals before and after the peak holding circuit. After receiving the trigger signal, the FPGA or MCU outputs a signal after a delay to control the discharge of the peak holding circuit, thereby resetting; the signal sampling circuit includes a multi-channel analog switch and an ADC, and the N signal processing circuits share one signal sampling circuit and one digital circuit.

[0009] Furthermore, the preamplifier is connected to an external signal, the input end of the pole-zero cancellation circuit is connected to the output end of the preamplifier, the output end of the pole-zero cancellation circuit is connected to the input end of the filter shaping circuit, the output end of the filter shaping circuit is connected to the signal triggering and extraction circuit, and the signal triggering and extraction circuit outputs.

[0010] Furthermore, the signal output from the filter shaping circuit enters the peak holding circuit. At this stage, the amplitude of the signal is maintained until the FPGA or MCU controls its discharge; the maintained signal then flows into the proportional amplifier circuit to further amplify the signal; wherein, the two input terminals of the voltage comparator are connected to the signal: the negative input terminal is connected to the input of the peak holding circuit; the positive input terminal is connected to the output of the proportional amplifier circuit; the peak holding circuit is connected to a switch, and the other end of the switch is grounded. When the FPGA or MCU receives a trigger signal, the switch is controlled to be turned on, that is, grounded, completing the discharge and reset of the peak holding circuit; or the output terminal of each peak holding circuit is grounded through a field effect transistor. When the FPGA or MCU receives a trigger signal, a high level is output to the gate of the field effect transistor, causing the peak holding circuit to discharge and reset through the field effect transistor.

[0011] Furthermore, when the nuclear pulse signal arrives, it specifically includes: first arriving at the negative input terminal of the voltage comparator after the filter shaping circuit, and then arriving at the positive input terminal of the voltage comparator after the proportional amplifier circuit, generating a region where the filter shaping signal is higher than the peak hold shaping signal. At this time, the voltage comparator outputs a negative signal for triggering, that is, a trigger signal. After the FPGA or MCU detects the trigger signal, it delays the peak hold shaping signal to maintain it for a period of time, and then delays the output of a reset signal to control the peak hold circuit to discharge and reset its state; when the peak hold shaping signal discharges, a second region where the filter shaping signal is higher than the peak hold shaping signal is generated, and the voltage comparator will output a negative signal again, that is, an acquisition end flag signal, indicating that the signal acquisition is completed.

[0012] Furthermore, the digital circuit includes: a first DAC, a second DAC, and a third DAC; one end of the first DAC is connected to the FPGA or MCU, and the other end is connected to the preamplifier; one end of the second DAC is connected to the FPGA or MCU, and the other end is connected to the filter shaping circuit; one end of the third DAC is connected to the FPGA or MCU, and the other end is connected to the proportional amplifier circuit;

[0013] The first DAC is used to adjust the DC offset of the preamplifier, the second DAC is used to adjust the signal baseline in the filter shaping circuit, and the third DAC is used to adjust the trigger threshold of the proportional amplifier circuit.

[0014] Furthermore, the multi-channel analog switch inputs the signal amplitude sent by the signal processing circuit and the control signal sent by the FPGA or MCU, and the ADC samples the signal of the channel of the multi-channel analog switch and sends it to the digital circuit after analog-to-digital conversion.

[0015] Furthermore, when the FPGA or MCU receives a trigger signal from a certain channel, it controls the multi-channel analog switch to connect the channel where the signal is located, so that the ADC samples the signal of the channel; when the ADC is sampling the signal of a certain channel, if other channels also detect trigger signals, the FPGA or MCU will extend the peak hold time of other channels and wait for the ADC to sample them one after another. When the ADC completes sampling the signal of a certain channel, the FPGA or MCU controls the peak hold circuit of this channel to discharge and reset; when multiple channels generate trigger signals at the same time, the FPGA or MCU controls the multi-channel analog switch to enable the ADC to sample the signals in order from the smallest number of channels to the largest number of channels.

[0016] Compared with the prior art, the advantages of the present invention are:

[0017] A new minimalist circuit structure is proposed. A signal triggering and extraction circuit is composed of a peak hold circuit, a proportional amplifier circuit and a voltage comparator. The trigger is generated by comparing the signals before and after the peak hold circuit. No additional signal processing circuit is required, which greatly simplifies the circuit structure and reduces power consumption and cost.

[0018] The DAC is used to adjust the DC offset and signal baseline of the op amp in the signal processing circuit to maximize the voltage range of the signal amplification and avoid signal distortion when the op amp is powered by a single power supply. All op amps in the circuit use a single power supply, which simplifies the circuit structure and reduces power consumption and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 , a framework diagram of a complete circuit according to an embodiment of the present invention;

[0020] Figure 2 , a circuit diagram of a signal processing circuit in an embodiment of the present invention;

[0021] Figure 3 , input signal and output signal waveforms of the voltage comparator of the signal triggering and extraction circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The specific implementation of the present invention is described below in conjunction with examples:

[0023] It should be noted that the structures, proportions, sizes, etc. shown in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention.

[0024] At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships should be regarded as the scope of implementation of the present invention without substantially changing the technical content.

[0025] Example 1:

[0026] Figure 1 This is a complete block diagram of a multi-channel analog pulse amplitude sampling circuit. It consists of N signal processing circuits (N ≥ 1), a multi-channel analog switch, an ADC, a DAC, an FPGA or MCU, and a PC. The signal amplitude from each signal processing circuit passes through the multi-channel analog switch and is sampled by the ADC. The ADC then samples the signal and sends it to the FPGA or MCU, which then sends it to the PC via a serial port. During this process, the FPGA or MCU also controls the multi-channel analog switch for routing, sends a reset signal to the peak hold circuit in each channel, controls the DAC to apply a DC offset to the preamplifier, adjusts the signal baseline in the Gaussian filter circuit, and adjusts the trigger threshold of the proportional amplifier circuit.

[0027] like Figure 2 Figure 1 shows the schematic diagram of the signal processing circuit, which consists of a preamplifier, a pole-zero cancellation circuit, a filter shaping circuit, and a signal triggering and extraction circuit. The first-stage preamplifier can be connected in different ways to function as an in-phase or inverting amplifier circuit, and can input a DC offset via a DAC.

[0028] The preamplifier signal obtained after the signal passes through the preamplifier has a long attenuation time.

[0029] The attenuation time of the pole-zero cancellation signal obtained after the preamplifier signal passes through the pole-zero cancellation circuit becomes shorter.

[0030] After the pole-zero cancellation signal passes through the filtering and shaping circuit, the noise in the signal is effectively removed, making the signal smooth.

[0031] The signal baseline of the filter shaping circuit can be adjusted using a DAC. The signal triggering and extraction circuit consists of a peak hold circuit, a proportional amplifier circuit, and a voltage comparator. After the signal passes through the peak hold circuit and maintains its peak value for a period of time, the FPGA or MCU controls its discharge. The proportional amplifier circuit can adjust the trigger threshold using the DAC. After amplifying the peak hold signal, the signal sampling circuit can better measure the signal amplitude. The two inputs of the voltage comparator are connected before the peak hold circuit and after the proportional adjustment circuit, respectively. Whenever a nuclear pulse signal arrives, the voltage comparator generates a signal that is sent to the FPGA or MCU. After a delay, the FPGA or MCU outputs a signal that controls the discharge of the peak hold circuit, thereby resetting it. The signal amplitude output by the signal triggering and extraction circuit is then input to the ADC via a multi-channel analog switch for sampling.

[0032] The locations of the voltage comparator input terminals used in this example are merely illustrative. That is, the locations of the voltage comparator used to generate the trigger signal are not limited to those shown in the schematic diagram. The connection method and number of the ADC and DAC used are also merely illustrative. That is, the connection method and number of the ADC used for sampling and the DACs used to adjust the DC offset, signal baseline, and trigger threshold are not limited to those shown in the schematic diagram. Persons skilled in the art may make appropriate adjustments based on actual needs.

[0033] like Figure 3 The following diagram shows the waveforms of the voltage comparator's input and output. The filter-shaped signal is the negative input signal, and the peak-hold-shaped signal is the positive input signal. When there is no nuclear pulse signal, the negative voltage is slightly higher than the positive voltage. When a nuclear pulse signal arrives, it first reaches the negative input of the voltage comparator after the filter-shaped circuit and then the positive input of the voltage comparator after the proportional amplifier circuit. This results in a region where the filter-shaped signal is higher than the peak-hold-shaped signal. At this point, the voltage comparator outputs a negative signal for triggering, known as the trigger signal. After detecting this signal, the FPGA or MCU delays the peak-hold-shaped signal for a period of time before controlling the peak-hold circuit to discharge. When the peak-hold-shaped signal discharges, a second region where the filter-shaped signal is higher than the peak-hold-shaped signal is generated. The voltage comparator then outputs a negative signal, known as the acquisition end flag signal, indicating the end of signal acquisition.

[0034] The waveform diagram of the voltage comparator in this example is merely an example. That is, the waveform diagram may vary depending on the connection position of the voltage comparator.

[0035] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in this field without departing from the scope of the present invention.

[0036] Many other changes and modifications can be made without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments, and the scope of the present invention is defined by the appended claims.

Claims

1. A multi-channel analog pulse amplitude sampling circuit, characterized in that: The circuit includes: an analog circuit, a signal sampling circuit and a digital circuit; the analog circuit interacts with the digital circuit, the analog circuit is connected to the signal sampling circuit, the signal sampling circuit is connected to the digital circuit, and the digital circuit is connected to the host computer; The analog circuit includes N signal processing circuits, where N is greater than or equal to 1, each including: a preamplifier, a pole-zero cancellation circuit, a filter shaping circuit, and a signal triggering and extraction circuit; each of the signal triggering and extraction circuits includes a peak holding circuit, a proportional amplifier circuit, and a voltage comparator; the digital circuit includes: an FPGA or an MCU, and a DAC, and the DAC is used to adjust the DC offset and signal baseline of the operational amplifier in the signal processing circuit; when a pulse signal arrives, a trigger is generated by comparing the signals before and after the peak holding circuit. After receiving the trigger signal, the FPGA or MCU outputs a delayed signal to control the discharge of the peak holding circuit, thereby resetting it; the signal sampling circuit includes a multi-channel analog switch and an ADC, and the N signal processing circuits share one signal sampling circuit and one digital circuit; The multi-channel analog switch inputs the signal amplitude sent by the signal processing circuit and the control signal sent by the FPGA or MCU, and the ADC samples the signal of the channel of the multi-channel analog switch and sends it to the digital circuit after analog-to-digital conversion.

2. A multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: The preamplifier is connected to the external signal, the input end of the pole-zero cancellation circuit is connected to the output end of the preamplifier, the output end of the pole-zero cancellation circuit is connected to the input end of the filter shaping circuit, the output end of the filter shaping circuit is connected to the signal triggering and extraction circuit, and the signal triggering and extraction circuit outputs.

3. The multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: The signal output from the filter shaping circuit enters the peak hold circuit. At this stage, the amplitude of the signal is maintained until the FPGA or MCU controls its discharge; the maintained signal then flows into the proportional amplifier circuit to further amplify the signal; wherein, the two input terminals of the voltage comparator are connected to the signal: the negative input terminal is connected to the input of the peak hold circuit; the positive input terminal is connected to the output of the proportional amplifier circuit; the peak hold circuit is connected to a switch, and the other end of the switch is grounded. When the FPGA or MCU receives a trigger signal, the switch is controlled to be turned on, that is, grounded, completing the discharge and reset of the peak hold circuit; or the output terminal of each peak hold circuit is grounded through a field effect transistor. When the FPGA or MCU receives a trigger signal, a high level is output to the gate of the field effect transistor, causing the peak hold circuit to discharge and reset through the field effect transistor.

4. The multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: When the nuclear pulse signal arrives, it specifically includes: first arriving at the negative input terminal of the voltage comparator after the filter shaping circuit, and then arriving at the positive input terminal of the voltage comparator after the proportional amplifier circuit, generating a region where the filter shaping signal is higher than the peak hold shaping signal. At this time, the voltage comparator outputs a negative signal for triggering, that is, a trigger signal. After the FPGA or MCU detects the trigger signal, it delays the peak hold shaping signal to maintain it for a period of time, and then delays the output of a reset signal to control the peak hold circuit to discharge and reset its state; when the peak hold shaping signal discharges, a second filter shaping signal will be generated in a region where the peak hold shaping signal is higher than the peak hold shaping signal, and the voltage comparator will output a negative signal again, that is, the acquisition end flag signal, indicating that the signal acquisition is completed.

5. The multi-channel analog pulse amplitude sampling circuit according to claim 3, characterized in that: The digital circuit includes: a first DAC, a second DAC, and a third DAC; one end of the first DAC is connected to the FPGA or MCU, and the other end is connected to the preamplifier; one end of the second DAC is connected to the FPGA or MCU, and the other end is connected to the filter shaping circuit; one end of the third DAC is connected to the FPGA or MCU, and the other end is connected to the proportional amplification circuit; The first DAC is used to adjust the DC offset of the preamplifier, the second DAC is used to adjust the signal baseline in the filter shaping circuit, and the third DAC is used to adjust the trigger threshold of the proportional amplifier circuit.

6. The multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: When the FPGA or MCU receives a trigger signal from a certain channel, it controls the multi-channel analog switch to connect the channel where the signal is located, so that the ADC samples the signal of the channel; When the ADC is sampling a channel signal, if other channels also detect a trigger signal, the FPGA or MCU will extend the peak hold time of other channels and wait for the ADC to sample one after another. When the ADC completes sampling a channel signal, the FPGA or MCU controls the peak hold circuit of this channel to discharge and reset. When multiple channels generate trigger signals at the same time, the FPGA or MCU controls the multi-channel analog switch to make the ADC sample signals in order from the smallest number of channels to the largest number of channels.

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