A method for derivation of the initial state of cyclic redundancy check code register

Abstract

The present invention discloses a method for inversely calculating the initial state of a cyclic redundancy check code register, which uses the cyclic redundancy check code generator polynomial g(x) and the encoded code word c to reversely calculate the initial bit of the cyclic redundancy check code encoder register bit by bit. First, from the code word c = [c0, c1, ..., c N‑1 ,c N ,c N+1 ,…,c N+n‑1 ] to separate the message bits m=[c0,c1,…,c N‑1 ]=[m0,m1,…,m N‑1 ] and check bit c N ,c N+1 ,…,c N+n‑1 , where N is the message bit length and n is the register length; secondly, the separated message bits are used to construct the sequence m′=[m0′,m1′,…,m′ N+n‑1 ]=[0,…,0,m0,m1,…,m N‑1 ]; Then, the encoder shift register r is initialized using the separated check bits k =c N+k , k = 0, 1, ..., n-1; finally, data is extracted bit by bit from the sequence m' in reverse order and derivation is performed to obtain the initial value of the encoder shift register. Based on the known generator polynomial g(x), the present invention uses a codeword to separate the message bits and check bits, thereby performing derivation. This derivation is fast, and the register structure used for derivation is similar to that of the encoder, facilitating hardware implementation.

Description

Technical Field

[0001] The present invention relates to the field of code recognition, and in particular to a method for derivation of the initial state of a cyclic redundancy check code register. Background Art

[0002] Cyclic redundancy check (CRC) is a widely used error-detecting code. Its checksum depends not only on the generator polynomial but also on the initial register state. Currently, cyclic redundancy check (CRC) identification relies solely on the generator polynomial, and no public documentation discusses how to determine the initial register state. Without knowing the initial register state, data verification is impossible, especially when the data is variable in length. Summary of the Invention

[0003] Under the premise that the generator polynomial is known, the present invention proposes a method for inverting the initial state of a register using a check word and message bits according to the coding principle of a cyclic redundancy check code. This method only requires one code word for inversion, has a high inversion speed, and the register structure used for inversion is similar to that of an encoder, which is conducive to hardware implementation.

[0004] The technical solutions of the present invention are as follows:

[0005] A method for derivation of the initial state of a cyclic redundancy check code register, comprising the following steps:

[0006] A) For a set of message bits to be encoded, m = [m0, m1, ..., m N-1 ], N is the message length, and the generating polynomial g(x) of the cyclic redundancy check code is:

[0007] g(x)=g n x n +g n-1 x n-1 +…+g1x+g0 (1)

[0008] In formula (1): g n ,g n-1 ,…,g1,g0 are the coefficients of the generator polynomial; where: n is the order of the cyclic redundancy check code;

[0009] The codeword c after the encoder is: c=[c0,c1,…,c N-1 ,c N ,c N+1 ,…,c N+n-1 ](2)

[0010] B) Separate the message bits and check bits from the codeword c:

[0011] The message bits are m=[c0,c1,…,c N-1]=[m0,m1,…,m N-1 ], c i =m i ; where i = 0, 1, ..., N-1;

[0012] The check bit is c N ,c N+1 ,…,c N+n-1 ;

[0013] C) Using the message bits separated in step B) to construct the sequence m', we can get:

[0014] m′=[m0′,m1′,…,m′ N+n-1 ]=[0,…,0,m0,m1,…,m N-1 ] (3)

[0015] D) Initialize the shift register in the encoder to obtain:

[0016] r k =c N+k ; (4)

[0017] Where: r k Indicates the value of the kth register, k = 0, 1, ..., n-1;

[0018] E) Take data bit by bit from sequence m' in reverse order, and reverse derive step by step according to the following formula:

[0019] r0=xor(r n-1 ·g0,m i ′) (5)

[0020] r k+1 =xor(xor(m i ′,r0)·g n-k-1 ,r k ) (6)

[0021] Among them, the values ​​of i and k are: i=N+n-1,N+n-2,…,1; k=n-2,n-3,…,0;

[0022] F) When i=0, the initial values ​​d0 and d k+1 ,

[0023] d0=xor(r n-1 ·g0,m i ′) (7)

[0024] d k+1 =xor(xor(m i ′,d0)·g n-k-1 ,r k) (8)

[0025] Where k = n-2, n-3,…, 0.

[0026] The method is applicable to an encoder comprising n shift registers r0, r1, ..., r n-2 ,r n-1 The n registers are connected according to a known generating polynomial g(x). In the encoder, terminal A is connected to the input message bits, terminal B is connected to the output of the 0th register, and terminal C is connected to the input of an XOR device that combines the message bits and the output of the 0th register. Due to the equivalence between encoders, encoders with different structures can be converted to the described structure, and the same parity bits can be generated for the same input message bits.

[0027] The encoding steps of the encoder are as follows:

[0028] 1. First, set the switch to terminal C and input n consecutive 0s;

[0029] 2. Then set the switch to the A terminal and input m bit by bit. i , m i While participating in the encoding, it is output as the message bits of the codeword;

[0030] 3. Finally, set the switch to terminal B, output the contents of the shift register as the check bit, and append it to the end of the message bit part to complete the encoding.

[0031] From the above encoding steps, we can see that under the condition determined by the generator polynomial, the check bit is composed of the initial state of the shift register, the input n 0s and the message bit m i The only certainty.

[0032] Furthermore, the check bit is uniquely determined by the initial state of the shift register and the sequence m'.

[0033] According to the structure of the encoder, the i-th step encoding can be obtained, that is,

[0034] r k =xor(xor(m i ′,r0)·g n-k-1 ,r k+1 )

[0035] r n-1 =xor(m i ′,r0)·g0

[0036] Where: xor(,) represents the exclusive OR operation; the values ​​of k and i are, k = 0, 1, ..., n-2;

[0037] i=0,1,…,N+n-1.

[0038] For the initial state of the shift register d=[d0,d1,…,d n-1 ]:

[0039] 1) When i=0, the values ​​of k are k=0, 1, ..., n-2,

[0040] r k =xor(xor(m′0,d0)·g n-k-1 ,d k+1 )

[0041] r n-1 =xor(m′0,d0)·g0

[0042] 2) When i=N+n-1, the values ​​of k are k=0, 1, ..., n-2,

[0043] c N+k =xor(xor(m′ N+k ,r0)·g n-k-1 ,r k+1 )

[0044] c N+n-1 =xor(m′ N+n-1 ,r0)·g0

[0045] Therefore, by using the recognition principle of forward coding and performing reverse operation and derivation, the initial state of the register can be obtained.

[0046] The principle of the present invention is to analyze the encoder structure and encoding method of the cyclic redundancy check code shift register, and then use the obtained check bits and message bits to reverse the encoding process to obtain the initial state of the cyclic redundancy check code register.

[0047] The beneficial effects of the present invention are as follows:

[0048] The present invention mainly uses a check word and a message bit to realize a method of derivation register initial state. Only one code word is needed to derivation the initial state of the encoder register in the derivation process. Moreover, the derivation process is also expressed as a shift register operation, which is easy to implement in hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a schematic diagram of the structure of a cyclic redundancy check code encoder of the present invention. DETAILED DESCRIPTION

[0050] The method for derivation of the initial state of a cyclic redundancy check code register specifically implemented by the present invention comprises the following steps:

[0051] A) For a set of message bits to be encoded, m = [m0, m1, ..., m N-1], N is the message length, and the generating polynomial g(x) of the cyclic redundancy check code is:

[0052] g(x)=g n x n +g n-1 x n-1 +…+g1x+g0 (1)

[0053] In formula (1): g n ,g n-1 ,…,g1,g0 are the coefficients of the generator polynomial; where: n is the order of the cyclic redundancy check code;

[0054] The codeword c after the encoder is: c=[c0,c1,…,c N-1 ,c N ,c N+1 ,…,c N+n-1 ](2)

[0055] B) Separate the message bits and check bits from the codeword c:

[0056] The message bits are m=[c0,c1,…,c N-1 ]=[m0,m1,…,m N-1 ], c i =m i ; where i = 0, 1, ..., N-1;

[0057] The check bit is c N ,c N+1 ,…,c N+n-1 ;

[0058] C) Using the message bits separated in step B) to construct the sequence m', we can get:

[0059] m′=[m0′,m1′,…,m′ N+n-1 ]=[0,…,0,m0,m1,…,m N-1 ] (3)

[0060] D) Initialize the shift register in the encoder to obtain:

[0061] r k =c N+k ; (4)

[0062] Where: r k Indicates the value of the kth register, k = 0, 1, ..., n-1;

[0063] E) Take data bit by bit from sequence m' in reverse order, and reverse derive step by step according to the following formula:

[0064] r0=xor(r n-1·g0,m i ′) (5)

[0065] r k+1 =xor(xor(m i ′,r0)·g n-k-1 ,r k ) (6)

[0066] Among them, the values ​​of i and k are: i=N+n-1,N+n-2,…,1; k=n-2,n-3,…,0;

[0067] F) When i=0, the initial values ​​d0 and d k+1 ,

[0068] d0=xor(r n-1 ·g0,m i ′) (7)

[0069] d k+1 =xor(xor(m i ′,d0)·g n-k-1 ,r k ) (8)

[0070] Where k = n-2, n-3,…, 0.

[0071] According to this step, the generator polynomial for the known cyclic redundancy check code is g(x)=x 8 +x 2 +1, that is, n=8, g8=g2=g0=1, and the other coefficients are 0; the message length N=10, the initial state d of the register is "00010111"; the codeword obtained after encoding is "110101100010000011", and the generating polynomial and codeword can be used to obtain the initial state of the register.

[0072] The process of obtaining is as follows:

[0073] a) Separate the message bits m=“1101011000” and the check bits “10000011” from the code word “110101100010000011”;

[0074] b) construct sequence m' = "000000001101011000";

[0075] c) Initialize register state d to "10000011";

[0076] d) Input m' in reverse order bit by bit and perform inverse derivation. The register status of the calculation process is shown in Table 1.

[0077] step Input bits Register status initialization 10000011 1 0 11000011 2 0 11100011 3 0 11110011 4 1 01111011 5 1 00111111 6 0 10011101 7 1 01001100 8 0 00100110 9 1 10010011 10 1 01001011 11 0 10100111 12 0 11010001 13 0 11101010 14 0 01110101 15 0 10111000 16 0 01011100 17 0 00101110 18 0 00010111

[0078] Table 1

[0079] e) From Table 1, we can see that the initial state of the encoder register is "00010111".

Claims

1. A method for derivation of the initial state of a cyclic redundancy check code register, characterized in that: The steps of back-derivation are: A) For a set of message bits to be encoded, m = [m0, m1, ..., m N-1 ], N is the message length, and the generating polynomial g(x) of the cyclic redundancy check code is: g(x)=g n x n +g n-1 x n-1 +…+g1x+g0 (1) In formula (1): g n ,g n-1 ,…,g1,g0 are the coefficients of the generator polynomial; where: n is the order of the cyclic redundancy check code; The codeword c after the encoder is: c=[c0,c1,…,c N-1 ,c N ,c N+1 ,…,c N+n-1 ] (2) B) Separate the message bits and check bits from the codeword c: The message bits are m=[c0,c1,…,c N-1 ]=[m0,m1,…,m N-1 ], c i =m i ; where i = 0, 1, ..., N-1; The check bit is c N ,c N+1 ,…,c N+n-1 ; C) Using the message bits separated in step B) to construct the sequence mc', we can get: m′=[m′0,m′1,…,m′ N+n-1 ]=[0,…,0,m0,m1,…,m N-1 ] (3) D) Initialize the shift register in the encoder to obtain: r k ＝c N+k ； (4) Where: r k Indicates the value of the kth register, k = 0, 1, ..., n-1; E) Take data bit by bit from sequence m' in reverse order, and reverse derive step by step according to the following formula: r0=xor(r n-1 ·g0,m′ i ) (5) r k+1 =xor(xor(m′ i ,r0)·g n-k-1 ,r k ) (6) Among them, the values ​​of i and k are: i=N+n-1,N+n-2,…,1; k=n-2,n-3,…,0; F) When i=0, the initial values ​​d0 and d k+1 , d0=xor(r n-1 ·g0,m′ i ) (7) d k+1 =xor(xor(m′ i ,d0)·g n-k-1 ,r k ) (8) Where k = n-2, n-3,…, 0.

2. The method for derivation of the initial state of a cyclic redundancy check code register according to claim 1, wherein: The method is applicable to an encoder comprising n shift registers r0, r1, ..., r n-2 ,r n-1 , and the n registers are connected according to the known generating polynomial g(x). The A end of the encoder is connected to the input message bit, the B end is connected to the output of the 0th register, and the C end is connected to the input end of the XOR device with the message bit and the output of the 0th register.

3. The method for derivation of the initial state of a cyclic redundancy check code register according to claim 2, wherein: The encoding steps of the encoder are as follows: First, set the switch to terminal C and input n consecutive 0s; Then, set the switch to terminal A and input m bit by bit. i , m i While participating in the encoding, it is output as the message bits of the codeword; Finally, the switch is set to the B terminal to output the contents of the shift register as the check bit, which is attached to the end of the message bit part to complete the encoding.

4. The method for derivation of the initial state of a cyclic redundancy check C-code register according to claim 3, characterized in that: From the above encoding steps, we can see that under the condition determined by the generator polynomial, the check bit is composed of the initial state of the shift register, the input n 0s and the message bit m i The only certainty.

5. The method for derivation of the initial state of a cyclic redundancy check code register according to claim 4, characterized in that: The check bit is uniquely determined by the initial state of the shift register and the sequence m'.

6. The method for derivation of the initial state of a cyclic redundancy check code register according to claim 3, wherein: According to the structure of the encoder, the i-th step encoding can be obtained, that is, r k =xor(xor(m′ i ,r0)·g n-k-1 ,r k+1 ) r n-1 =xor(m′ i ,r0)·g0 Where: xor(,) represents the exclusive OR operation; the values ​​of k and i are, k = 0, 1, ..., n-2; i=0,1,…,N+n-1.

7. The method for derivation of the initial state of a cyclic redundancy check code register according to claim 6, characterized in that: For the initial state of the shift register d=[d0,d1,…,d n-1 ]: 1) When i=0, the values ​​of k are k=0, 1, ..., n-2, r k =xor(xor(m′0,d0)·g n-k-1 ,d k+1 ) r n-1 =xor(m′0,d0)·g0 2) When i=N+n-1, the values ​​of k are k=0, 1, ..., n-2, c N+k =xor(xor(m′ N+k ,r0)·g n-k-1 ,r k+1 ) c N+n-1 =xor(m′ N+n-1 ,r0)·g0 Therefore, by using the recognition principle of forward coding and performing reverse operation and derivation, the initial state of the register can be obtained.

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