A device and method for testing the performance of RFID chips after bump processing.

Abstract

This disclosure relates to the field of RFID chip testing technology, specifically to an RFID chip performance testing device and method after bump processing. The device includes: a host computer, an RFID reader, a dielectric structure array, and a motion control system. The dielectric structure array includes a base and multiple dielectric structures mounted on the base. Each dielectric structure includes a microstrip antenna disposed on its outer surface. The motion control system includes a robotic arm and a driving device. The robotic arm is used to move the dielectric structure array, and the driving device is used to move the dielectric structures relative to the base. This disclosure achieves non-destructive, rapid, and low-cost electrical performance testing of RFID chips after bump processing, significantly reducing production costs caused by defective chips at the factory.

Description

Technical Field

[0001] This disclosure relates to the field of RFID chip testing, specifically to an RFID chip performance testing device and method after bump processing. Background Technology

[0002] In current RFID chip manufacturing processes, during the wafer fabrication stage, chip probing (CP) is primarily used to test the chip's electrical performance to confirm its electrical properties during manufacturing. For the packaging stage, after the bumping process, optical imaging and other methods are mainly used to examine the physical structural changes caused by the bumping process. The chip yield is confirmed by monitoring these changes and controlling tolerances. For mature designs and processes, this testing method is highly efficient and cost-effective. However, for exploratory designs and process optimization stages, the high temperatures involved in the bumping process, coupled with insufficient process optimization, can lead to functional defects in the packaged chip. Currently, there is no method for testing the electrical performance of chips after the bumping process; defective chips can only be detected during subsequent product-level packaging verification. This defective product rejection process increases material, time, and cost, resulting in significant waste of resources and time. Summary of the Invention

[0003] To address the problems in related technologies, this disclosure provides an RFID chip performance testing device and method after bump processing.

[0004] In a first aspect, this disclosure provides an RFID chip performance testing device after bump processing, used to test multiple RFID chips on a wafer under test, characterized in that it includes: a host computer, an RFID reader, a dielectric structure array, and a motion control system, wherein:

[0005] The dielectric structure array includes a base and multiple dielectric structures, which are mounted on the base. Each dielectric structure includes a microstrip antenna disposed on its outer surface.

[0006] The motion control system includes a robotic arm and a drive device. The robotic arm is used to move the media structure array, and the drive device is used to move the media structure relative to the base.

[0007] The host computer is used to perform the following operations:

[0008] S1: Control the robotic arm to move the medium structure array and / or control the drive device to move the specified medium structure, so that the microstrip antenna of the specified medium structure is connected to the bump on the specified RFID chip on the wafer under test to form the tag antenna of the specified RFID chip.

[0009] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0010] S3: Determine whether the area where the specified RFID chip is located is a defective area based on the specified information;

[0011] When the defective area includes multiple RFID chips, the host computer iteratively executes operations S1-S3 for the defective area, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips, until the defective area contains only one RFID chip, at which point the RFID chip is identified as a defective chip.

[0012] According to an embodiment of this disclosure, during the initial testing of the wafer under test, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer under test, thereby identifying one or more defective areas.

[0013] According to embodiments of this disclosure, reducing the extent of the defective area by decreasing the number of media structures connected to the RFID chip includes:

[0014] The defective area is divided into a first sub-region and a second sub-region;

[0015] A medium structure corresponding to the number of RFID chips in the first sub-region is connected to the RFID chips in the first sub-region to determine whether the first sub-region is a defective region.

[0016] A media structure corresponding to the number of RFID chips in the second sub-region is connected to the RFID chips in the second sub-region to determine whether the second sub-region is a defective region.

[0017] According to embodiments of this disclosure, the first sub-region and the second sub-region have the same number of RFID chips.

[0018] According to embodiments of this disclosure, the specified information includes: RFID chip TID and / or carrier signal waveform.

[0019] According to embodiments of this disclosure, the medium structure has any one or more of the following shapes: cuboid, cube, cylinder, sphere, ellipsoid;

[0020] The microstrip antenna is disposed on the bottom and side surfaces of the dielectric structure;

[0021] The microstrip antenna includes a first segment and a second segment that are disconnected from each other on the bottom surface of the dielectric structure.

[0022] The first segment and the second segment extend longitudinally upward along the side of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

[0023] According to embodiments of this disclosure, the width W of the first segment and the second segment of the microstrip antenna is: 0.2mm ≤ W ≤ 2mm;

[0024] The distance between the first segment and the second segment on the bottom surface is 10μm to 30μm smaller than the distance between the bumps on the RFID chip;

[0025] The first and second segments are bent at a distance of 3 mm to 10 mm from the top surface of the medium structure on the side.

[0026] According to embodiments of this disclosure, the first segment and the second segment are respectively connected to a metal patch structure to form a radiating dipole arm structure, thereby forming a broadband tag antenna.

[0027] According to embodiments of this disclosure, the microstrip antenna is made of any one or more of the following materials: copper, aluminum, silver paste, and conductive ink.

[0028] According to embodiments of this disclosure, the microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920MHz to 925MHz: phased array antenna, horn antenna, waveguide antenna.

[0029] According to embodiments of this disclosure, the material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass.

[0030] According to embodiments of this disclosure, a method for performance testing of RFID chips after bumping processing is provided, which uses a post-bumping RFID chip performance testing device to perform performance testing on multiple RFID chips on a wafer under test. The RFID chip performance testing device comprises: a host computer, an RFID reader, a dielectric structure array, and a motion control system, wherein:

[0031] The dielectric structure array includes a base and multiple dielectric structures, which are mounted on the base. Each dielectric structure includes a microstrip antenna disposed on its outer surface.

[0032] The motion control system includes a robotic arm and a drive device. The robotic arm is used to move the media structure array, and the drive device is used to move the media structure relative to the base.

[0033] The method includes performing the following operations via the host computer:

[0034] S1: Control the robotic arm to move the medium structure array and / or control the drive device to move the specified medium structure, so that the microstrip antenna of the specified medium structure is connected to the bump on the specified RFID chip on the wafer under test to form the tag antenna of the specified RFID chip.

[0035] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0036] S3: Determine whether the area where the specified RFID chip is located is a defective area based on the specified information;

[0037] When the defective area includes multiple RFID chips, the host computer iteratively executes operations S1-S3 for the defective area, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips, until the defective area contains only one RFID chip, at which point the RFID chip is identified as a defective chip.

[0038] According to an embodiment of this disclosure, during the initial testing of the wafer under test, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer under test, thereby identifying one or more defective areas.

[0039] According to embodiments of this disclosure, reducing the extent of the defective area by decreasing the number of media structures connected to the RFID chip includes:

[0040] The defective area is divided into a first sub-region and a second sub-region;

[0041] A medium structure corresponding to the number of RFID chips in the first sub-region is connected to the RFID chips in the first sub-region to determine whether the first sub-region is a defective region.

[0042] A media structure corresponding to the number of RFID chips in the second sub-region is connected to the RFID chips in the second sub-region to determine whether the second sub-region is a defective region.

[0043] According to embodiments of this disclosure, the first sub-region and the second sub-region have the same number of RFID chips.

[0044] According to embodiments of this disclosure, the specified information includes: RFID chip TID and / or carrier signal waveform.

[0045] According to embodiments of this disclosure, the medium structure has any one or more of the following shapes: cuboid, cube, cylinder, sphere, ellipsoid;

[0046] The microstrip antenna is disposed on the bottom and side surfaces of the dielectric structure;

[0047] The microstrip antenna includes a first segment and a second segment that are disconnected from each other on the bottom surface of the dielectric structure.

[0048] The first segment and the second segment extend longitudinally upward along the side of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

[0049] According to embodiments of this disclosure, the width W of the first segment and the second segment of the microstrip antenna is: 0.2mm≤W≤2mm;

[0050] The distance between the first segment and the second segment on the bottom surface is 10μm to 30μm smaller than the distance between the bumps on the RFID chip;

[0051] The first and second segments are bent at a distance of 3 mm to 10 mm from the top surface of the medium structure on the side.

[0052] According to embodiments of this disclosure, the first segment and the second segment are respectively connected to a metal patch structure to form a radiating dipole arm structure, thereby forming a broadband tag antenna.

[0053] According to embodiments of this disclosure, the microstrip antenna is made of any one or more of the following materials: copper, aluminum, silver paste, and conductive ink.

[0054] According to embodiments of this disclosure, the microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920MHz to 925MHz: phased array antenna, horn antenna, waveguide antenna.

[0055] According to embodiments of this disclosure, the material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass.

[0056] Compared with the prior art, the beneficial effects of this disclosure are as follows:

[0057] This disclosure utilizes a robotic arm to control the adjustment of the medium structure, connecting the miniaturized microstrip antenna port to the RF pins of the RFID wafer chip after the long bump process. An RFID reader with an external antenna simultaneously verifies the electrical performance of multiple RFID chips connected to the microstrip antenna, enabling the detection of faults such as TID switching, protocol inconsistency, and communication function anomalies. This disclosure allows for non-destructive, rapid, and low-cost electrical performance testing of RFID chips after the bump process. It simultaneously detects electrical defects in multiple RFID chips on a wafer, complementing existing physical testing equipment and significantly reducing production costs caused by defective chips leaving the factory. Furthermore, this disclosure avoids applying localized high voltage and strong force to the wafer bumps, unlike current market testing methods where probes are placed close to the wafer structure, easily causing physical damage. This protects the chip structural integrity and reduces the possibility of physical damage to the wafer from testing equipment. Attached Figure Description

[0058] Figure 1 A schematic diagram of an RFID chip performance testing device after bump processing according to an embodiment of the present disclosure is shown.

[0059] Figure 2 A schematic diagram of the dielectric structure array of an RFID chip performance testing apparatus after bump fabrication according to an embodiment of the present disclosure is shown.

[0060] Figure 3 A schematic diagram of the dielectric structure of an RFID chip performance testing device after bump processing according to an embodiment of the present disclosure is shown.

[0061] Figure 4 This diagram illustrates the identification of one or more defective regions during the initial testing of a wafer under test according to an embodiment of the present disclosure.

[0062] Figure 5 The flowchart illustrates a process of gradually narrowing down the defective area according to an embodiment of the present disclosure until the defective chip is identified. Detailed Implementation

[0063] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0065] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0066] As mentioned earlier, in the current RFID chip manufacturing process, the main electrical performance testing during the wafer manufacturing stage is performed using ChipProbing-CP to confirm the chip's electrical performance during manufacturing. For the packaging stage, after the bumping process, optical imaging and other methods are mainly used to examine the physical structural changes caused by the bumping process. The chip production yield is confirmed by monitoring these changes and controlling tolerances. For mature designs and processes, this testing method is highly efficient and cost-effective. However, for exploratory designs and process optimization stages, the high temperatures experienced during the bumping process, coupled with insufficient process optimization, can lead to functional defects in the packaged chip. Currently, there is no method for testing the electrical performance of chips after the bumping process; defective chips can only be detected during subsequent product-level packaging verification. The rejection process for defective products at this stage increases material, time, and cost, resulting in significant waste of materials and time.

[0067] To address the aforementioned technical problems, this invention discloses a device and method for testing the performance of RFID chips after bump processing. The device for testing the performance of RFID chips after bump processing includes: a host computer, an RFID reader, a dielectric structure array, and a motion control system, wherein:

[0068] The dielectric structure array includes a base and multiple dielectric structures, which are mounted on the base. Each dielectric structure includes a microstrip antenna disposed on its outer surface.

[0069] The motion control system includes a robotic arm and a drive device. The robotic arm is used to move the media structure array, and the drive device is used to move the media structure relative to the base.

[0070] The host computer is used to perform the following operations:

[0071] S1: Control the robotic arm to move the medium structure array and / or control the drive device to move the specified medium structure, so that the microstrip antenna of the specified medium structure is connected to the bump on the specified RFID chip on the wafer under test to form the tag antenna of the specified RFID chip.

[0072] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0073] S3: Determine whether the area where the specified RFID chip is located is a defective area based on the specified information;

[0074] When the defective area includes multiple RFID chips, the host computer iteratively executes operations S1-S3 for the defective area, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips, until the defective area contains only one RFID chip, at which point the RFID chip is identified as a defective chip.

[0075] This disclosure utilizes a robotic arm to control the adjustment of the medium structure, connecting the miniaturized microstrip antenna port to the RF pins of the RFID wafer chip after the long bump process. A reader with an external antenna simultaneously verifies the electrical performance of multiple RFID chips connected to the microstrip antenna, enabling the detection of faults such as TID switching, protocol inconsistency, and communication function anomalies. This disclosure allows for non-destructive, rapid, and low-cost electrical performance testing of RFID chips after the bump process. It simultaneously detects electrical defects in multiple RFID chips on a wafer, complementing existing physical testing equipment and significantly reducing production costs caused by defective chips leaving the factory. Furthermore, this disclosure avoids applying localized high voltage and strong force to the wafer bumps, unlike current market testing methods where probes are placed close to the wafer structure, easily causing physical damage. This protects the chip structural integrity and reduces the possibility of physical damage to the wafer from testing equipment.

[0076] The following is for reference. Figures 1-3 This invention provides a detailed description of the RFID chip performance testing device and method following the bump processing technology according to embodiments of this disclosure.

[0077] like Figure 1 As shown, the RFID chip performance testing device after bump processing according to an embodiment of this disclosure includes: a host computer, an RFID reader, a media structure array, and a motion control system.

[0078] like Figure 2 As shown, the dielectric structure array includes a base and multiple dielectric structures, which are mounted on the base.

[0079] like Figure 3 As shown, the dielectric structure includes a microstrip antenna disposed on the outer surface of the dielectric structure. According to embodiments of this disclosure, the dielectric structure has any one or more of the following shapes: cuboid, cube, cylinder, sphere, ellipsoid, and the material of the dielectric structure includes any one or more of the following: glass, ceramic, fiberglass.

[0080] like Figure 3 As shown, according to an embodiment of this disclosure, the microstrip antenna is disposed on the bottom and side surfaces of the dielectric structure; the microstrip antenna includes a first segment and a second segment that are disconnected from each other on the bottom surface of the dielectric structure; the first segment and the second segment respectively extend longitudinally upward along the side surface of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

[0081] According to an embodiment of this disclosure, the microstrip antenna includes a first segment and a second segment that are disconnected from each other on the bottom surface of the dielectric structure; the first segment and the second segment are respectively extended longitudinally along the side surface of the dielectric structure and bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

[0082] According to embodiments of this disclosure, the width W of the first and second segments of the microstrip antenna is: 0.2mm≤W≤2mm; the distance between the first and second segments on the bottom surface is 10μm to 30μm smaller than the RFID chip bump spacing; the first and second segments are bent at a distance of 3mm to 10mm from the top surface of the dielectric structure on the side.

[0083] like Figure 3 As shown, the first segment and the second segment are respectively connected to the metal patch structure to form the radiating dipole arm structure, thereby forming a broadband tag antenna.

[0084] According to embodiments of this disclosure, the microstrip antenna is made of any one or more of the following materials: copper, aluminum, silver paste, and conductive ink.

[0085] According to embodiments of this disclosure, the microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920MHz to 925MHz: phased array antenna, horn antenna, waveguide antenna.

[0086] According to embodiments of this disclosure, the motion control system includes a robotic arm and a drive device. The robotic arm is used to move the medium structure array as a whole, and the drive device is used to move the medium structure relative to the base. Specifically, as Figure 2 As shown, the drive unit can drive one or multiple media structures to move perpendicular to the base. During testing, the motion control system can move the array of media structures so that the media structures are aligned with the protrusions to be connected. Then, the drive unit drives the media structure corresponding to the protrusion to be connected, so that it contacts the protrusion and achieves electrical connection.

[0087] According to embodiments of this disclosure, the host computer is used to perform the following operations:

[0088] S1: Control the robotic arm to move the medium structure array and / or control the drive device to move the specified medium structure, so that the microstrip antenna of the specified medium structure is connected to the bump on the specified RFID chip on the wafer under test to form the tag antenna of the specified RFID chip.

[0089] S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer;

[0090] S3: Determine whether the area where the specified RFID chip is located is a defective area based on the specified information;

[0091] When the defective area includes multiple RFID chips, the host computer iteratively executes operations S1-S3 for the defective area, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips, until the defective area contains only one RFID chip, at which point the RFID chip is identified as a defective chip.

[0092] According to an embodiment of this disclosure, during the initial testing of the wafer under test, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer under test, thereby identifying one or more defective areas.

[0093] like Figure 4 As shown, the dielectric structure array comprises M*N structure arrays, i.e., N rows, with M dielectric structures in each row. Therefore, when the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the bumps of the corresponding RFID chips, M*N tag antennas can be formed simultaneously. The wafer under test comprises N*n rows, with M*m RFID chips in each row, which can be divided into m*n regions, each region containing M*N RFID chips. The dielectric structure array is moved so that it aligns with one region at a time, and each dielectric structure array is connected to the bumps of the M*N chips to form tag antennas. Figure 4 This is a schematic diagram of a 2*2 media structure array according to an embodiment of this disclosure.

[0094] The RFID reader acquires designated information for each of the M*N RFID chips via their tag antennas. According to embodiments of this disclosure, the designated information includes the RFID chip's TID and / or carrier signal waveform to detect faults such as TID transitions, protocol inconsistencies, and communication function anomalies. When the designated information received from any area is abnormal, that area is identified as a problematic area.

[0095] After identifying the defective area, if the defective area includes multiple RFID chips, the host computer iteratively executes operations S1-S3 for the defective area, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips, until the defective area contains only one RFID chip, at which point the RFID chip is identified as a defective chip.

[0096] According to embodiments of this disclosure, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips includes: dividing the defective area into a first sub-region and a second sub-region; connecting media structures corresponding to the number of RFID chips in the first sub-region to the RFID chips in the first sub-region to determine whether the first sub-region is a defective area; and connecting media structures corresponding to the number of RFID chips in the second sub-region to the RFID chips in the second sub-region to determine whether the second sub-region is a defective area. According to embodiments of this disclosure, the first sub-region and the second sub-region have the same number of RFID chips.

[0097] like Figure 5 As shown, the defective area is first divided into two sub-regions and tested separately. If either sub-region is defective, it is then divided into two more sub-regions and tested separately, and so on, until the sub-region identified as defective contains only one chip, in which case the chip is considered defective.

[0098] According to embodiments of this disclosure, after identifying a defective area during the initial test, the scope of that defective area can be gradually narrowed down in the manner described above until all defective chips within that area are identified. Then, the test can be moved to the next area. For example, assuming a wafer is divided into m*n areas, each containing M*N RFID chips, the area in the first row and first column can be tested first. If this area is defective, its scope can be gradually narrowed down until all defective chips within it are identified. Then, the area in the first row and second column can be tested, and so on. Existing chip testing processes often involve dividing the wafer into functional testing areas, adding inter-chip metal structures, and avoiding direct solder joints for electrical connection. Instead, probes are used to indirectly connect to the functional testing areas, and external equipment is used to test the chip's electrical performance. This method may lead to changes in chip manufacturing processes and an increase in defects due to the addition of inter-chip testing area structures. This disclosure does not change the original wafer production process and technology; all testing processes are completely independent, preventing changes in chip manufacturing processes and an increase in defects caused by the addition of inter-chip testing area structures. It is simple, easy to implement, and readily applicable in the industry.

[0099] Existing chip testing often uses a combination of probes and high-frequency readers. Due to the size limitations of the chip and probe structures, using a probe structure to test the wafer may cause localized damage to the chip solder joints due to concentrated pressure from the probe, thus affecting the accuracy of the test and easily causing physical damage to the wafer. This disclosure utilizes a microstrip antenna on the surface of a dielectric structure to electrically connect to the chip solder joints after the bumping process, forming a tag together with an RFID chip. The tag's performance is tested and verified by an external antenna connected to the dielectric structure and an RFID reader, enabling the detection and screening of defective chips such as TID transitions, protocol consistency, and communication function abnormalities. This eliminates the need for localized high-voltage force on the wafer bumps, making it easier to protect the integrity of the chip structure. It achieves non-destructive, rapid, and low-cost electrical performance testing of ultra-high frequency wafer chips after the bumping process, greatly reducing the production costs caused by defective chips leaving the factory.

[0100] The above description is merely a preferred embodiment of this disclosure; however, the scope of protection of this disclosure is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this disclosure, based on the technical solutions and improved concepts of this disclosure, should be covered within the scope of protection of this disclosure.

Claims

1. A device for testing the performance of RFID chips after bump processing, used to test multiple RFID chips on a wafer under test, characterized in that, include: The system includes a host computer, an RFID reader, a media structure array, and a motion control system, among which: The dielectric structure array includes a base and multiple dielectric structures, which are mounted on the base. Each dielectric structure includes a microstrip antenna disposed on its outer surface. The motion control system includes a robotic arm and a drive device. The robotic arm is used to move the media structure array, and the drive device is used to move the media structure relative to the base. The host computer is used to perform the following operations: S1: Control the robotic arm to move the medium structure array and / or control the drive device to move the specified medium structure, so that the microstrip antenna of the specified medium structure is connected to the bump on the specified RFID chip on the wafer under test to form the tag antenna of the specified RFID chip. S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer; S3: Determine whether the area where the specified RFID chip is located is a defective area based on the specified information; When the defective area includes multiple RFID chips, the host computer iteratively executes operations S1-S3 for the defective area, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips, until the defective area contains only one RFID chip, at which point the RFID chip is identified as a defective chip.

2. The apparatus according to claim 1, wherein, During the initial test of the wafer under test, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer under test, thereby identifying one or more defective areas.

3. The apparatus according to claim 1, wherein, The method of reducing the extent of the defective area by decreasing the number of media structures connected to the RFID chip includes: The defective area is divided into a first sub-region and a second sub-region; A medium structure corresponding to the number of RFID chips in the first sub-region is connected to the RFID chips in the first sub-region to determine whether the first sub-region is a defective region. A media structure corresponding to the number of RFID chips in the second sub-region is connected to the RFID chips in the second sub-region to determine whether the second sub-region is a defective region.

4. The apparatus according to claim 3, wherein, The first sub-region and the second sub-region have the same number of RFID chips.

5. The apparatus according to claim 1, wherein, The specified information includes: RFID chip TID and / or carrier signal waveform.

6. The apparatus according to claim 1, characterized in that: The medium structure has any one or more of the following shapes: cuboid, cube, cylinder, sphere, ellipsoid; The microstrip antenna is disposed on the bottom and side surfaces of the dielectric structure; The microstrip antenna includes a first segment and a second segment that are disconnected from each other on the bottom surface of the dielectric structure. The first segment and the second segment extend longitudinally upward along the side of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

7. The apparatus according to claim 6, characterized in that: The width W of the first segment and the second segment of the microstrip antenna is: 0.2mm≤W≤2mm; The distance between the first segment and the second segment on the bottom surface is 10μm to 30μm smaller than the distance between the bumps on the RFID chip; The first and second segments are bent at a distance of 3 mm to 10 mm from the top surface of the medium structure on the side.

8. The apparatus according to claim 7, characterized in that, The first segment and the second segment are respectively connected to the metal patch structure to form a radiating dipole arm structure, thereby forming a broadband tag antenna.

9. The apparatus according to claim 1, characterized in that: The microstrip antenna is made of any one or more of the following materials: copper, aluminum, silver paste, and conductive ink.

10. The apparatus according to claim 1, characterized in that: The microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920MHz to 925MHz: phased array antenna, horn antenna, waveguide antenna.

11. The apparatus according to claim 1, characterized in that: The material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass.

12. A method for performance testing of RFID chips after bumping processing, used to perform performance testing on multiple RFID chips on a wafer under test using a device for performance testing of RFID chips after bumping processing, characterized in that, The RFID chip performance testing device includes: a host computer, an RFID reader, a media structure array, and a motion control system, wherein: The dielectric structure array includes a base and multiple dielectric structures, which are mounted on the base. Each dielectric structure includes a microstrip antenna disposed on its outer surface. The motion control system includes a robotic arm and a drive device. The robotic arm is used to move the media structure array, and the drive device is used to move the media structure relative to the base. The method includes performing the following operations via the host computer: S1: Control the robotic arm to move the medium structure array and / or control the drive device to move the specified medium structure, so that the microstrip antenna of the specified medium structure is connected to the bump on the specified RFID chip on the wafer under test to form the tag antenna of the specified RFID chip. S2: Control the RFID reader to communicate with the designated RFID chip via the tag antenna of the designated RFID chip, obtain designated information from the designated RFID chip, and send the designated information to the host computer; S3: Determine whether the area where the specified RFID chip is located is a defective area based on the specified information; When the defective area includes multiple RFID chips, the host computer iteratively executes operations S1-S3 for the defective area, reducing the range of the defective area by decreasing the number of media structures connected to the RFID chips, until the defective area contains only one RFID chip, at which point the RFID chip is identified as a defective chip.

13. The method according to claim 12, wherein, During the initial test of the wafer under test, the host computer controls the motion control system so that the microstrip antennas of all dielectric structures in the dielectric structure array are connected to the corresponding RFID chips, and moves the dielectric structure array to traverse the entire wafer under test, thereby identifying one or more defective areas.

14. The method according to claim 12, wherein, The method of reducing the extent of the defective area by decreasing the number of media structures connected to the RFID chip includes: The defective area is divided into a first sub-region and a second sub-region; A medium structure corresponding to the number of RFID chips in the first sub-region is connected to the RFID chips in the first sub-region to determine whether the first sub-region is a defective region. A media structure corresponding to the number of RFID chips in the second sub-region is connected to the RFID chips in the second sub-region to determine whether the second sub-region is a defective region.

15. The method according to claim 14, wherein, The first sub-region and the second sub-region have the same number of RFID chips.

16. The method according to claim 12, wherein, The specified information includes: RFID chip TID and / or carrier signal waveform.

17. The method according to claim 12, characterized in that: The medium structure has any one or more of the following shapes: cuboid, cube, cylinder, sphere, ellipsoid; The microstrip antenna is disposed on the bottom and side surfaces of the dielectric structure; The microstrip antenna includes a first segment and a second segment that are disconnected from each other on the bottom surface of the dielectric structure. The first segment and the second segment extend longitudinally upward along the side of the dielectric structure and are bent to form an inductor coil structure for matching the capacitive impedance of the RFID chip.

18. The method according to claim 17, characterized in that: The width W of the first segment and the second segment of the microstrip antenna is: 0.2mm≤W≤2mm; The distance between the first segment and the second segment on the bottom surface is 10μm to 30μm smaller than the distance between the bumps on the RFID chip; The first and second segments are bent at a distance of 3 mm to 10 mm from the top surface of the medium structure on the side.

19. The method according to claim 18, characterized in that, The first segment and the second segment are respectively connected to the metal patch structure to form a radiating dipole arm structure, thereby forming a broadband tag antenna.

20. The method according to claim 12, characterized in that: The microstrip antenna is made of any one or more of the following materials: copper, aluminum, silver paste, and conductive ink.

21. The method according to claim 12, characterized in that: The microstrip antenna is any one or more of the following antennas with an operating frequency band covering 920MHz to 925MHz: phased array antenna, horn antenna, waveguide antenna.

22. The method according to claim 12, characterized in that: The material of the medium structure includes any one or more of the following: glass, ceramic, and fiberglass.

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