An ultra-low power physically unclonable function device based on multiple programmable non-volatile memory and working method

Abstract

The application discloses a kind of ultra-low power physical unclonable function devices based on multiple programmable nonvolatile memory, including two identical multiple programmable storage arrays, transmission gate array and sensing amplifier array;The randomness distribution of bit line read current after programming of multiple programmable memory cell caused by manufacturing process deviation is used to generate response value.The ultra-low power physical unclonable function structure designed by the application is suitable for resource-limited internet of things edge devices containing multiple programmable memory, with extremely low power consumption and high security.

Description

Technical Field

[0001] This invention relates to the field of hardware encryption technology for IoT edge devices, and in particular to an ultra-low power physical non-clonable function device and its operating method based on a multiple programmable non-volatile memory. Background Technology

[0002] Physically unclonable functions (PUFs) offer a novel approach to addressing hardware security challenges in the Internet of Things (IoT). Due to inherent process mismatches in silicon-based chip manufacturing, the physical differences between each component and unit are unclonable and unpredictable. Once manufactured, these random physical differences are embedded within each chip. PUFs extract, amplify, and characterize these random process differences between chips, thus obtaining a unique "digital fingerprint" for each chip. As a hardware security primitive, PUFs are frequently used in applications such as identity recognition, device key generation, and authentication. Because of their unique "power-on, power-off" response, they effectively address the hardware security vulnerabilities inherent in traditional encryption schemes that require storing keys in non-volatile memory (NVM).

[0003] Several memory-based PUF (Programmable Array of Elements) solutions have been proposed. For example, PUF technology based on Static Random-Access Memory (SRAM) is a typical hardware security scheme that utilizes SRAM memory cells and architecture to generate PUF responses. This scheme places SRAM cells in a metastable state and uses the final state of each cell (whether it represents "0" or "1") to obtain the PUF response. Due to process mismatch, the difference in the tendency of cells to ultimately represent 0 or 1 is random, but the tendency of each individual cell is deterministic. Therefore, an SRAM array can generate random and unique binary sequences. However, SRAM PUF often requires a continuous power loop to generate the response, which is not suitable for all IoT devices. Furthermore, there are currently few PUF schemes designed based on Non-Virtual Machine (NVM). PUF technology based on the emerging Resistive Random-Access Memory (RRAM) is a novel NVM-based PUF scheme. The entropy source of this scheme mainly comes from the resistive state configuration of the RRAM. However, the high-energy-efficiency implementation of RRAM in standard CMOS processes is not yet mature enough to widely replace multiple-programmable memory (NVM) in edge devices. Therefore, the design of PUF for highly secure and low-power multiple-programmable memory is urgently needed for use in IoT edge devices with mature processes but limited resources that include multiple-programmable memory. Summary of the Invention

[0004] This invention addresses the shortcomings of existing memory-based PUFs by proposing an ultra-low-power physically unclonable function device and operating method based on a repeatedly programmable non-volatile memory. It exhibits excellent uniqueness and reliability, and extremely low power consumption. Furthermore, as an intrinsic memory-based PUF design, this invention does not alter or add any additional circuit structure, significantly avoiding unnecessary hardware overhead while providing robust security design. This invention is suitable for resource-constrained IoT edge devices containing repeatedly programmable memory, offering extremely low power consumption and high security.

[0005] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0006] An ultra-low power physically non-cloning function device based on a multiple programmable non-volatile memory, the ultra-low power physically non-cloning function device comprising two identical multiple programmable memory arrays, a transmission gate array, and a sense amplifier array;

[0007] Four of the transmission gates in the transmission gate array are deployed in pairs on two identical multiple programmable memory arrays, and the other transmission gates are connected in pairs to the two input terminals of one of the sense amplifiers in the sense amplifier array.

[0008] The multiple programmable memory array includes multiple multiple programmable basic differential memory cells, all of which have consistent programming and erasure settings;

[0009] When the physical non-cloning function is executed, the multiple programmable memory array is fully erased, and then fully programmed to complete the preprocessing process. After that, the excitation signal is used as the input signal to act on the row and column addresses of the two multiple programmable memory arrays respectively. The selected programming terminal BL has a programmed read current output, which enters the corresponding sensing amplifier through the corresponding transmission gate. The sensing amplifier senses, amplifies and compares the two programmed BL read currents input.

[0010] Furthermore, each row of the multiple programmable memory array has m multiple programmable basic differential memory cells, and the cells in each row share the floating gate terminal TUN, the read terminal RDL, and the select terminal SL; each column has n multiple programmable basic differential memory cells, and the cells in each column share the left control terminal CG0, the right control terminal CG1, the left bit line BL0, and the right bit line BL1; the shared floating gate terminal TUN, the read terminal RDL, the select terminal SL, the left control terminal CG0, and the right control terminal CG1 are used to control the cells in the array to perform programming, erasing, reading, and standby operations, and the shared left bit line BL0 and right bit line BL1 are used to output the read current after programming or erasing; the shared programming terminal BL of each column is pulled out to the transmission gate array.

[0011] Furthermore, the multiple programmable basic differential memory cell is composed of two completely mirror-symmetrical single-ended structures forming a differential memory structure. The MOS capacitors of the two floating gate TUNs are connected to one TUN terminal, and the two select transistors PMOS transistors are connected to one SL terminal.

[0012] Each single-ended structure consists of a basic three-transistor structure and a selector structure. The storage transistors of the basic three-transistor structure include PMOS transistors PM0, PM1, and PM2. PMOS transistor PM0 is the control gate-floating gate MOS capacitor, and PMOS transistor PM2 is the floating gate channel-TUN terminal MOS capacitor. The gates of PMOS transistors PM0, PM1, and PM2 are connected as floating gates through polycrystalline connections.

[0013] Furthermore, the transmission gate array includes 4m+4 transmission gates; wherein the 4m transmission gates are connected in pairs to the two input terminals of the sensing amplifier respectively; the other 4 transmission gates are located on both sides of two identical multiple programmable memory arrays. When the current reading function is executed, the 4 transmission gates are opened accordingly to complete the current detection.

[0014] Furthermore, the sensing amplifier array includes 2m sensing amplifiers, wherein each amplifier has a transmission gate connected to each of its two input terminals.

[0015] Furthermore, the sensing amplifier compares the magnitudes of the programmed read currents at the two input terminals and outputs a high or low level based on the comparison result.

[0016] Secondly, the present invention discloses a method for operating an ultra-low power physically unclonable function device based on a multiple programmable non-volatile memory, wherein the ultra-low power physically unclonable function device adopts the device described above.

[0017] The working method includes the following steps:

[0018] Step 1: Preprocessing stage:

[0019] Before implementing the PUF function, perform a full erase operation on all memory cells in the multiple programmable memory array according to the settings. After confirming that the original storage state has been completely erased, perform a full programming operation on all memory cells in the multiple programmable memory array according to the settings.

[0020] Step Two: Incentive Configuration Phase

[0021] Input X+Y bit excitation. Apply the X bit excitation to the row decoder and enable the common SL line and RDL line of the corresponding row cell to select the row path of the corresponding row. The selection transistor of the corresponding cell on the unselected row line is not turned on. Then apply the Y bit excitation to the transmission gate array and enable the transmission gate connected to the corresponding two column cells. If the excitation is 1, the transmission gate at the corresponding position is turned on, and if the excitation is 0, the transmission gate at the corresponding position remains closed.

[0022] Step 3, Response Generation Phase:

[0023] Enable the sense amplifier connected to the corresponding conduction gate. The process deviation of the two selected cells in the multiple programmable memory array is manifested as a random BL current value after programming, which enters the sense amplifier for comparison and amplification; a unique 1-bit response value is generated in each comparison cycle.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] This invention discloses an ultra-low-power physically unclonable function (PUF) device and operating method based on a reprogrammable non-volatile memory (RNM). It utilizes the different read currents after programming the RMF to achieve the physically unclonable function functionality. Due to the manufacturing process differences in the transistors, floating gates, and other circuit structures of the reprogrammable basic differential memory (RPM) cells, the read current after programming exhibits random variations under the same conditions. An enable signal controls a sensing amplifier to compare the current values, achieving efficient generation of the PUF response. Tape-out results demonstrate that the physically unclonable function structure based on RMF of this invention possesses excellent uniqueness and reliability, with an average single-bit energy consumption of only 0.04–0.09 pJ / bit, representing zero redundant hardware overhead compared to storage functions. Therefore, this invention effectively reduces the energy consumption of PUF response generation based on non-volatile memory, simplifies circuit design, and ensures security. This physically unclonable function implementation method can be extended to other application scenarios containing similar types of RMFs to achieve low-power and low-overhead designs with PUF security hardening. Attached Figure Description

[0026] Figure 1 This is a structural diagram of the ultra-low power physically unclonable function device based on a multiple-programmable non-volatile memory according to the present invention.

[0027] Figure 2 This is a structural diagram of the multiple programmable basic differential memory cell of the present invention;

[0028] Figure 3 This is a block diagram of the physical non-cloning function based on a repeatedly programmable non-volatile memory according to the present invention.

[0029] Figure 4 This is an example diagram of the excitation configuration of the present invention. Detailed Implementation

[0030] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0031] The structural diagram of the ultra-low power physically unclonable function device based on multiple programmable non-transferability of the present invention is shown below. Figure 1 As shown, Figure 1It includes two identical multiple programmable memory arrays, transmission gate arrays, and sense amplifier arrays. The multiple programmable memory array performs programming, erasing, reading, and standby operations through control signals and row / column decoding. Each row of the multiple programmable memory array has 8 multiple programmable basic differential memory cells, and the cells in each row share the floating gate terminal TUN, the read terminal RDL, and the select terminal SL. Each column has 128 multiple programmable basic differential memory cells, and the cells in each column share the left control terminal CG0, the right control terminal CG1, the left bit line BL0, and the right bit line BL1. The shared floating gate terminal TUN, the read terminal RDL, the select terminal SL, the left control terminal CG0, and the right control terminal CG1 are used to control the cells in the array to perform programming, erasing, reading, and standby operations, and the shared left bit line BL0 and right bit line BL1 are used to output the read current after programming or erasing. All cells within the array maintain consistent programming and erasing settings. When BL0 is set as the programming endpoint, BL1 is the corresponding erase endpoint; conversely, when BL0 is set as the erase endpoint, BL1 is the corresponding programming endpoint. The shared programming endpoint BL for each column is pulled out to the transmission gate array. When the physically unclonable function is executed, the array is first subjected to a full erase, followed by a full programming operation to complete the preprocessing. Afterward, the excitation signal is applied as an input signal to the row and column addresses of the memory array, and the selected programming endpoint BL outputs a post-programming read current.

[0032] The transmission gate array comprises 36 transmission gates. 32 of these gates are paired and connected to the two input terminals of the sensing amplifier, while the remaining four gates are located on either side of two identical multiple-programmable memory arrays. When the physically non-cloning function is executed, the transmission gate corresponding to the selected programming terminal BL opens, allowing the programmed current to flow through the gate into the corresponding sensing amplifier. When the current reading function is executed, the four transmission gates open accordingly to complete current detection.

[0033] The sense amplifier array comprises 16 sense amplifiers, each with two input terminals connected to a transmission gate. When the physical no-cloning function is executed, the sense amplifier senses, amplifies, and compares the two input programmed BL read currents. The comparison result is set as follows: when the programmed read current at the left input terminal is greater than that at the right input terminal, the sense amplifier outputs a high level ("1"); when the programmed read current at the left input terminal is less than that at the right input terminal, the sense amplifier outputs a low level ("0"). The relative relationship between the comparison result and "0" and "1" can be changed, and is not intended to limit the scope of the invention. Without substantial changes to the technical content, it is considered within the scope of the invention. Specifically, when the physical no-cloning function is executed, the transmission gate corresponding to the selected programming terminal BL opens, and the programmed read current enters the corresponding sense amplifier through the transmission gate. Enabling the sense amplifier connected to the corresponding conducting transmission gate, the process deviation of the two selected array cells ultimately manifests as random programmed BL current values, which are then compared and amplified in the sense amplifier. A unique 1-bit response value is generated in each comparison cycle. This process is repeated until a sufficient number of binary response sequences are obtained.

[0034] Figure 2 The diagram shows the basic differential memory cell structure, which consists of two perfectly mirror-symmetrical single-ended structures. Two floating-gate TUN MOS capacitors are connected to a TUN terminal, and two select PMOS transistors are connected to an SL terminal. Each single-ended structure comprises a basic three-transistor structure and a select transistor structure. The basic three-transistor structure uses three PMOS transistors for memory. PM0 is the control gate-floating gate MOS capacitor, and PM2 is the floating gate channel-TUN terminal MOS capacitor. The gates of PM0, PM1, and PM2 are connected via polysilicon to form a floating gate. When performing the preprocessing for the physically unclonable function, the first step involves applying high voltages to CG1, SL, and TG, while CG0 and RDL are grounded. Electrons in the left-hand floating gate tunnel out through the floating gate tube from the TUN terminal, and electrons in the right-hand floating gate tunnel into the floating gate structure from the RDL, completing the defined "erasure." The second step involves applying high voltages to CG0, SL, and TG, while CG1 and RDL are grounded. Electrons in the left-hand floating gate tunnel into the floating gate structure from the RDL, and electrons in the right-hand floating gate tunnel out through the floating gate tube from the TUN terminal, completing the defined "programming." The third step involves applying high voltages to RDL, while CG0, CG1, SL, and TG are grounded, and the programming terminal BL0 outputs the post-programming read current. The defined "programming" and "erasure" can be mirrored on both sides, and are not intended to limit the scope of this invention. Changes in their relative relationships without substantial alteration of the technical content should also be considered within the scope of this invention.

[0035] Figure 3The diagram shows a block diagram of a physically unclonable function based on a reproducible programmable nonvolatile memory (RPN). The diagram includes a working method for an ultra-low-power physically unclonable function structure based on the aforementioned RPN, as described in this invention. The working method includes the following steps:

[0036] Step 1: Preprocessing stage:

[0037] Before implementing the PUF function, perform a full erase operation on all cells in the array according to the settings. After confirming that the original storage state has been completely erased, perform a full programming operation on all cells in the array according to the settings.

[0038] Step Two: Incentive Configuration Phase

[0039] Input X+Y bit excitation. Apply the X bit excitation to the row decoder and enable the common SL and RDL lines of the corresponding row cell, selecting the row path of the corresponding row. The selection transistors of the corresponding cells on the unselected row lines are not turned on. Then apply the Y bit excitation to the transmission gate array and enable the transmission gates connected to the corresponding two column cells. An excitation of "1" turns on the transmission gate at that position, and an excitation of "0" keeps the transmission gate at that position closed.

[0040] Step 3, Response Generation Phase:

[0041] Enable the sense amplifier connected to the corresponding conduction gate. The process deviation of the two selected array cells is ultimately manifested as a random programmed BL current value, which is then compared and amplified in the sense amplifier. A unique 1-bit response value is generated in each comparison cycle.

[0042] Figure 4 This is an example diagram of the stimulus configuration for this invention. When the input stimulus is the example "Challenge 1", i.e., "0000000000000011", the first 8 bits indicate that the selected row address is the first row, and the two cells corresponding to "1" in the last 8 bits are the selected comparison cells. Therefore, this stimulus indicates that the programmed BL current values ​​of the 7th and 8th adjacent memory cells at the first row address are compared, such as... Figure 4 The process is illustrated in red and green. For example, when the input stimulus is "Challenge 2" ("1111111100000101"), the first 8 bits indicate that the selected row address is the last row, and the two cells corresponding to "1" in the last 8 bits are the selected comparison cells. Therefore, this stimulus indicates that the programmed BL current values ​​of the 6th and 8th separated memory cells at row address 128 are compared. Figure 4 The process is illustrated in orange and blue.

[0043] After tape-out verification, this ultra-low-power physically unclonable function structure based on reproducible non-volatile memory utilizes the randomness of the programmed BL current as an entropy source. The method designed, controlled by an excitation signal and using a sensing amplifier to compare currents to obtain the response, can be applied to resource-constrained scenarios containing similar reproducible non-volatile memory. When no excitation signal is applied, the memory performs normal storage functions; when an excitation signal containing multiple specific enable signals is applied, the reproducible memory array, transmission gate array, and sensing amplifier array form an intrinsic and low-power memory-like physically unclonable function.

[0044] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0045] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, produce instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0046] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0047] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment, causing a series of operational steps to be executed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that run on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0048] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0049] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An ultra-low power physically unclonable function device based on a repeatedly programmable non-volatile memory, characterized in that, The ultra-low power physically unclonable function device includes two identical multiple programmable memory arrays, a transmission gate array, and a sense amplifier array. Four of the transmission gates in the transmission gate array are deployed in pairs on two identical multiple programmable memory arrays, and the other transmission gates are connected in pairs to the two input terminals of one of the sense amplifiers in the sense amplifier array. The multiple programmable memory array includes multiple multiple programmable basic differential memory cells, all of which have consistent programming and erasure settings; When the physically unclonable function is executed, the multiple programmable memory array is subjected to a full erase, and after the erase is complete, a full programming is applied to complete the preprocessing process. Subsequently, the excitation signal is used as the input signal to apply to the row and column addresses of the two multiple programmable memory arrays respectively. The selected programming terminal BL has a programmed read current output, which enters the corresponding sensing amplifier through the corresponding transmission gate. The sensing amplifier senses, amplifies and compares the two programmed BL read currents input.

2. The ultra-low power physically unclonable function device based on a repeatedly programmable non-volatile memory according to claim 1, characterized in that, Each row of the multiple programmable memory array has m multiple programmable basic differential memory cells. The cells in each row share the floating gate terminal TUN, the read terminal RDL, and the select terminal SL. Each column has n multiple programmable basic differential memory cells. The cells in each column share the left control terminal CG0, the right control terminal CG1, the left bit line BL0, and the right bit line BL1. The shared floating gate terminal TUN, the read terminal RDL, the select terminal SL, the left control terminal CG0, and the right control terminal CG1 are used to control the cells in the array to perform programming, erasing, reading, and standby operations. The shared left bit line BL0 and right bit line BL1 are used to output the read current after programming or erasing. The shared programming terminal BL of each column is pulled out to the transmission gate array.

3. The ultra-low power physically unclonable function device based on a repeatedly programmable non-volatile memory according to claim 2, characterized in that, The multiple programmable basic differential memory cell consists of two completely mirror-symmetrical single-ended structures forming a differential memory structure. The MOS capacitors of the two floating gate TUNs are connected to one TUN terminal, and the two select transistors PMOS transistors are connected to one SL terminal. Each single-ended structure consists of a basic three-transistor structure and a selector structure. The storage transistors of the basic three-transistor structure include PMOS transistors PM0, PM1, and PM2. PMOS transistor PM0 is the control gate-floating gate MOS capacitor, and PMOS transistor PM2 is the floating gate channel-TUN terminal MOS capacitor. The gates of PMOS transistors PM0, PM1, and PM2 are connected as floating gates through polycrystalline connections.

4. The ultra-low power physically unclonable function device based on a repeatedly programmable non-volatile memory according to claim 1, characterized in that, The transmission gate array comprises 4m+4 transmission gates; Four transmission gates are paired and connected to the two input terminals of the sensing amplifier; the other four transmission gates are located on both sides of two identical multiple programmable memory arrays. When the current reading function is executed, the four transmission gates open accordingly to complete the current detection.

5. The ultra-low power physically unclonable function device based on a repeatedly programmable non-volatile memory according to claim 1, characterized in that, The sensing amplifier array comprises 2m sensing amplifiers, each of which has a transmission gate connected to each of its two input terminals.

6. The ultra-low power physically unclonable function device based on a repeatedly programmable non-volatile memory according to claim 5, characterized in that, The sensing amplifier compares the magnitude of the programmed read current at the two input terminals and outputs a high or low level based on the comparison result.

7. A method for operating an ultra-low power physically non-cloning function device based on a repeatedly programmable non-volatile memory, characterized in that, The ultra-low power physical non-clonable function device employs the device described in any one of claims 1-6; The working method includes the following steps: Step 1: Preprocessing stage: Before implementing the PUF function, perform a full erase operation on all memory cells in the multiple programmable memory array according to the settings. After confirming that the original storage state has been completely erased, perform a full programming operation on all memory cells in the multiple programmable memory array according to the settings. Step Two: Incentive Configuration Phase Input X+Y bit excitation. Apply the X bit excitation to the row decoder and enable the common SL line and RDL line of the corresponding row cell to select the row path of the corresponding row. The selection transistor of the corresponding cell on the unselected row line is not turned on. Then apply the Y bit excitation to the transmission gate array and enable the transmission gate connected to the corresponding two column cells. If the excitation is 1, the transmission gate at the corresponding position is turned on, and if the excitation is 0, the transmission gate at the corresponding position remains closed. Step 3, Response Generation Phase: Enable the sense amplifier connected to the corresponding conduction gate. The process deviation of the two selected cells in the multiple programmable memory array is manifested as a random BL current value after programming, which enters the sense amplifier for comparison and amplification; a unique 1-bit response value is generated in each comparison cycle.

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