A multi-channel communication-based hyper-converged gateway

Abstract

The application discloses a kind of based on multi-channel communication super fusion gateway, including power module, central processing unit, RS485 channel unit, LAN ethernet isolation circuit, ethernet external interface unit, 4G communication module, 5G communication module.Central processing unit accesses the power module, and the central processing unit is used to process gateway data;RS485 channel unit is electrically connected to the central processing unit, and the RS485 channel unit is connected to two-way RS485 conversion IC circuit by an isolation IC, and is output with RS485 interface;LAN ethernet isolation circuit is electrically connected to the central processing unit, and the LAN ethernet isolation circuit is output with LAN ethernet interface after being isolated by double transformer;4G communication module, 5G communication module are accessed to the central processing unit.The gateway of the application can improve data transmission efficiency and reduce cloud data processing pressure.

Description

Technical Field

[0001] This invention relates to the field of gateway technology, and more specifically to a hyperconverged gateway based on multi-channel communication. Background Technology

[0002] A gateway is a "gateway" connecting one network to another; it is also called an internetwork connector or protocol converter. An IoT gateway acts as the link between a sensing network and a traditional communication network. It also has device management functions, allowing operators to manage the underlying sensing nodes, understand their information, and remotely control them.

[0003] The Internet of Things (IoT) is transforming our production and lifestyles at an unprecedented pace. The Industrial Internet of Things (IIoT) has become the link between the physical and digital worlds. In this network, the IIoT gateway acts like a smart traffic policeman, directing the busy data flow between devices and cloud systems. Gateway IoT and industrial control systems are key networking devices, widely used, highly versatile, and with high requirements for domestic production. A gateway acts as a "translator" of communication protocols, a hub for device interconnection, and a bridge between lower-level and upper-level machines. Integrating routers with gateway functions, or with switches, is a trend, offering multiple uses in one device. Through its high integration, communication design capabilities, security measures, and reliability, it demonstrates significant advantages in enhancing network intelligence, ensuring data security, and improving system operating efficiency. The design and implementation of smart gateways embody high flexibility and security, allowing for customized configuration according to actual needs, adapting to different network environments and application scenarios. Simultaneously, through intelligent algorithms and optimization strategies, it improves data processing efficiency and network response speed, ensuring overall network performance and user experience.

[0004] With the development of network technology, higher demands are being placed on network throughput to ensure the normal operation of IoT devices. Business acceleration is one way to improve processing efficiency, and software acceleration is an effective way to reduce costs and has good versatility. However, software acceleration consumes a lot of CPU resources, which can affect other services. Therefore, given the limited CPU processing power, how to specifically improve its business processing capabilities to improve the overall operating efficiency of IoT devices is one of the problems that needs to be solved. To solve the above problems, this invention provides the following technical solution. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a multi-channel communication hyperconverged gateway. The purpose of designing this multi-channel communication hyperconverged gateway is to solve key problems in Internet of Things (IoT) systems and ensure effective data transmission, secure management, and protocol conversion.

[0006] To solve the above technical problems, the present invention provides the following solution: A multi-channel communication-based hyper-converged gateway, comprising a power supply module, further includes:

[0007] A central processing unit is connected to the power module, and the central processing unit is used to process gateway data.

[0008] The RS485 channel unit is electrically connected to the central processing unit. The RS485 channel unit is connected to two RS485 conversion IC circuits by an isolation IC and outputs through an RS485 interface.

[0009] A LAN Ethernet isolation circuit is electrically connected to the central processing unit. After being isolated by a dual transformer, the LAN Ethernet isolation circuit outputs a LAN Ethernet interface.

[0010] The Ethernet expansion interface unit has an Ethernet physical layer processor, which is electrically connected to an Ethernet isolation circuit. The Ethernet isolation circuit is also connected to a central processing unit. The Ethernet expansion interface unit also has a WAN / LAN Ethernet electrical port circuit connected to the output of the Ethernet isolation circuit and a WAN / LAN Ethernet optical port circuit connected to the output of the Ethernet isolation circuit. The WAN / LAN Ethernet electrical port circuit and the WAN / LAN Ethernet optical port circuit are switched by a WAN / LAN optoelectronic switching circuit to prevent the WAN / LAN Ethernet electrical port circuit and the WAN / LAN Ethernet optical port circuit from being connected at the same time.

[0011] The 4G communication module is connected to the central processing unit;

[0012] The 5G communication module is connected to the central processing unit.

[0013] Furthermore, the power module has a protection circuit to prevent overcurrent and overvoltage, and a DC-to-DC circuit electrically connected to the output terminal of the protection circuit. The DC-to-DC circuit splits into two step-down circuits, one of which supplies power to the system and the other of which supplies power to the 4G module.

[0014] Furthermore, the power supply circuit of the power module to the central processing unit is provided with a voltage regulator circuit, which provides a stable voltage to the central processing unit and suppresses current fluctuations to prevent voltage fluctuations.

[0015] Furthermore, the multi-channel communication-based hyperconverged gateway also includes a TF card circuit connected to the mid-level processing unit, and the TF card circuit is equipped with an electrostatic discharge protection circuit.

[0016] Furthermore, the LAN Ethernet isolation circuit is equipped with surge and electrostatic discharge protection circuits.

[0017] Furthermore, the WAN / LAN Ethernet port circuit is equipped with an auxiliary power supply. The front-end circuit of the auxiliary power supply has a protocol adaptation processing chip, and the rear-end circuit has a power regulator chip. The interface of the WAN / LAN Ethernet port circuit is an RJ45 crystal head interface.

[0018] Furthermore, the WAN / LAN Ethernet optical port circuit adopts a single-port SFP interface structure.

[0019] Furthermore, the LAN Ethernet interface is provided in multiple ways, all of which are RJ45 interfaces.

[0020] Furthermore, the Ethernet physical layer processor is also connected to an isolation filter circuit.

[0021] Furthermore, the multi-channel communication-based hyperconverged gateway also includes a SIM card interface circuit, which is electrically connected to the 4G communication module and the 5G communication module respectively, and the SIM card interface circuit is equipped with an ESD protection circuit.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] 1. Efficient Data Transmission via the Gateway of the Invention: IoT devices generate a large amount of data, and directly transmitting it to the cloud may consume a significant amount of network bandwidth and increase the data processing burden. The IoT gateway can preprocess and filter the data locally, such as removing redundant data and transmitting only useful data, thereby improving data transmission efficiency and reducing the data processing pressure on the cloud.

[0024] 2. Security Management of the Gateway in this Invention: The security of IoT devices and data is paramount. The IoT gateway provides functions such as data encryption, device authentication, and access control to protect devices and data from cyberattacks, ensuring data security and privacy.

[0025] 3. Protocol Conversion of the Gateway in this Invention: IoT devices may use different communication protocols, such as Modbus, LoRa, or custom proprietary protocols, while the Internet typically uses the IP protocol. The IoT gateway can convert between these different protocols, enabling seamless communication between different devices.

[0026] 4. Local storage and processing of the gateway in this invention: In some cases, network connections may be unstable or temporarily disconnected. The IoT gateway can store data locally and transmit the data to the cloud after the connection is restored. This ensures that data is not lost and enables rapid response in applications with high real-time requirements.

[0027] 5. Device Management of the Gateway in this Invention: The IoT gateway monitors and manages connected devices, including device status, configuration updates, fault detection and repair, etc. This helps ensure the normal operation and maintenance of the system.

[0028] Through these inventions, IoT gateways play a crucial bridging role in IoT systems, connecting devices and cloud services to ensure efficient, secure, and accurate data transmission. Attached Figure Description

[0029] Figure 1 This is a circuit diagram of the central processing unit of this invention.

[0030] Figures 2-6 They are respectively Figure 1 The circuit magnification diagrams for areas A, B, C, D, and E.

[0031] Figure 7 This is a protection circuit for the input terminal of the power module of the present invention.

[0032] Figure 8-9 This is a DC-to-DC circuit diagram in the power module of the present invention.

[0033] Figure 10-11 This is a diagram of the two-channel step-down circuit in the power module of the present invention.

[0034] Figure 12 This is the circuit diagram of the TF card of the present invention.

[0035] Figure 13 This is a voltage regulator circuit diagram for providing a voltage regulator circuit for the central processing unit according to the present invention.

[0036] Figure 14 This is a circuit diagram of the external button of the present invention.

[0037] Figure 15 This is the circuit diagram of the indicator light of the present invention.

[0038] Figure 16 This is a circuit diagram of the electrostatic discharge protection circuit for the TF card circuit of the present invention.

[0039] Figure 17 This is an extended UART circuit diagram for the present invention.

[0040] Figure 18 This is a circuit diagram of the expansion module connected to the extended UART of the present invention.

[0041] Figure 19-20 This is a circuit diagram of the two RS485 indicator lights of the present invention.

[0042] Figure 21 This is a diagram of the DC-DC boost circuit of the present invention.

[0043] Figure 22 This is a circuit diagram of the DC-DC isolated power supply of the present invention.

[0044] Figure 23-25 This is the circuit diagram for the UART to RS485 converter of this invention.

[0045] Figure 26-27 This is a LAN Ethernet isolation circuit diagram of the present invention.

[0046] Figure 28 This is a circuit diagram of the Ethernet physical layer processor of the present invention.

[0047] Figures 29-30 for Figure 28 The circuit diagrams for the K and L regions are enlarged.

[0048] Figure 31 This is the isolation filter circuit for the Ethernet physical layer processor of the present invention.

[0049] Figure 32 This is a circuit diagram of the Ethernet isolation circuit of the present invention.

[0050] Figure 33 This is a circuit diagram of the WAN / LAN Ethernet optical port of this invention.

[0051] Figure 34 This is the WAN / LAN Ethernet port circuit diagram of the present invention.

[0052] Figure 35 This is a circuit diagram of the WAN / LAN optoelectronic switching circuit of the present invention.

[0053] Figures 36-37 This is a circuit diagram of the auxiliary power supply for the WAN / LAN electrical port of the present invention.

[0054] The attached diagram is labeled: Protection Circuit 1. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0057] Example 1: The specific structure of the present invention is as follows:

[0058] Please refer to the appendix. Figure 1-37 The present invention provides a multi-channel communication-based hyper-converged gateway, which includes a power supply module. The multi-channel communication-based hyper-converged gateway also includes a central processing unit, an RS485 channel unit, a LAN Ethernet isolation circuit, an Ethernet expansion interface unit, a 4G communication module, and a 5G communication module.

[0059] like Figure 1-6 As shown, the central processing unit is connected to the power module and is used to process gateway data. The central processing unit of this invention is an MT7621A processor, which has strong processing capabilities for gateway data. The central processing unit is chip U5.

[0060] The Ethernet expansion interface unit has an Ethernet physical layer processor. Figure 28 The chip U12 is an Ethernet physical layer processor, model 3.3V VCCIO RGMII / SMI. The Ethernet physical layer processor is electrically connected to an Ethernet isolation circuit, which is also connected to the central processing unit. The Ethernet expansion interface unit also has a WAN / LAN Ethernet electrical port circuit connected to the output of the Ethernet isolation circuit and a WAN / LAN Ethernet optical port circuit connected to the output of the Ethernet isolation circuit. The WAN / LAN Ethernet electrical port circuit and the WAN / LAN Ethernet optical port circuit are switched via a WAN / LAN opto-switching circuit to prevent simultaneous access of the WAN / LAN Ethernet electrical port circuit and the WAN / LAN Ethernet optical port circuit.

[0061] like Figure 7 As shown, Figure 7This is a protection circuit for the input terminal of the power module of the present invention. The power module has a protection circuit to prevent overcurrent and overvoltage, and a DC-to-DC circuit electrically connected to the output terminal of the protection circuit. The DC-to-DC circuit branches into two step-down circuits: one step-down circuit supplies power to the system, and the other step-down circuit supplies power to the 4G module. Protection circuit: Pin 2 of the power interface CN1 is connected to the positive terminal of Zener diode D3 and pin 1 of the first coil of inductor L1. The negative terminal of Zener diode D3 is connected to one end of fuse TP1, and the other end of fuse TP1 is connected to DCIN_24 voltage. The negative terminal of Zener diode D3 is also connected to pin 2 of the second coil of inductor L1. Pin 4 of the first coil of inductor L1 is grounded and connected to the negative terminal of a polarized capacitor C1. Pin 3 of the second coil of inductor L1 outputs VDD_24 voltage and is connected to the positive terminal of polarized capacitor C1. The current passes through the protection of fuse TP1 and Zener diode D3 to prevent overcurrent and overvoltage, thereby preventing damage to subsequent circuits.

[0062] Figure 8-9 The DC-DC converter transforms the input 12-24V voltage into a 5V output voltage. The voltage regulator chip U3 is model LMR16030PDDAR, a voltage regulator chip. The 12-24V voltage enters the voltage regulator chip U3 through the Zener diode, and then is filtered by the inductor L2 to output a stable 5V voltage. Figure 9 right end).

[0063] like Figure 10 The diagram shows the first step-down circuit. This first step-down circuit is connected to a 5V voltage output from a DC-to-DC converter, which then passes through a Zener diode and enters regulators U1 and U2, before outputting a 3.3V voltage to power the system.

[0064] like Figure 11 The diagram shows the second step-down circuit, which is connected to a 5V voltage output from a DC-to-DC converter circuit. Figure 11 The voltage entering from the right end is filtered by inductor L3 and then enters the JW5357 buck regulator switch U4. After being divided by resistor R6, it outputs a 4.0V voltage, which powers the 4G module.

[0065] like Figure 13 As shown, Figure 13This invention provides a voltage regulator circuit diagram for the central processing unit (CPU). The power supply circuit of the power module supplying the CPU includes a voltage regulator circuit. This voltage regulator circuit provides a stable voltage to the CPU, suppressing current fluctuations and preventing voltage fluctuations. A 3.3V voltage is supplied to the CPU. This 3.3V voltage is connected to the first terminal of inductor FB1. The second terminal of inductor FB1 is connected to the positive terminal of a polarized capacitor C25. The negative terminal of polarized capacitor C25 is grounded. Polarized capacitor C25 is connected in parallel with capacitors C26, C27, and C28. Through inductor FB1 and multiple capacitors, current fluctuations are suppressed, and a stable 3.3V voltage is output to the CPU.

[0066] Figure 14 This is the circuit diagram of the external button of the present invention. Figure 14 A button SW1 is provided, with a capacitor C29 connected between its two terminals. One end of capacitor C29 is grounded, and the other end is connected to a resistor R24, which is connected to a 3.3V voltage. An ESD5341N electrostatic discharge protector is connected in parallel with capacitor C29. The function of button SW1 is defined by software. Pin 1 of button SW1 is connected to pin 112 (SYS KEY I) of chip U5.

[0067] Figure 15 This is the circuit diagram for the indicator lights of the present invention. The indicator light circuit includes three light-emitting diodes (LEDs): an indicator light for system operation, an indicator light for optical port data transmission, and an indicator light for 4G data transmission. The three LEDs are controlled by a transistor Q1. The emitter of transistor Q1 is connected to one end of resistor R27, and the other end of resistor R27 is connected to a 3.3V voltage. The base of transistor Q1 is connected to resistors R28 and R31. The other end of resistor R28 is connected to pin 121 (SYS LED 0) of chip U5, and the other end of resistor R31 is grounded. The collector of transistor Q1 is connected to the indicator light for system operation. The positive terminal of the optical port data transmission indicator light is connected to resistor R30, and the other end of resistor R30 is connected to pin 37 (PHY LED 2) of chip U12. The negative terminals of both the indicator light for system operation and the optical port data transmission indicator light are grounded. The positive terminal of the 4G data transmission indicator light is connected to a 3.3V voltage, and its negative terminal is connected to one end of resistor R29. The other end of resistor R29 is connected to the WWAN LED pin of the 4G module.

[0068] Figure 16 This is a circuit diagram of the electrostatic discharge (ESD) protection circuit for the TF card circuit of the present invention. The multi-channel communication-based hyperconverged gateway also includes a TF card circuit connected to the mid-level processing unit, and the TF card circuit is equipped with an ESD protection circuit. The ESD protection circuit consists of an ESD5341N ESD protector connected to each circuit.

[0069] Figure 17To extend the UART circuit diagram of this invention, Figure 18 This is a circuit diagram of the expansion module connected to the extended UART of the present invention. Figure 17 and Figure 18 Circuit connection, Figure 17 The U18 chip is a USB extended UART, which is used to connect to... Figure 18 The extended modules in [the system]. Among them, Figure 17 The U18 model is CH340N. Figure 18 The U19 chip is an expansion chip.

[0070] Figure 19-20 The circuit diagram for the two RS485 indicator lights of this invention is shown below. Each RS485 indicator light has three LEDs. These three LEDs are a power indicator, a data transmission indicator, and a data reception indicator. Both RS485 indicator lights are connected to chip U5.

[0071] Figure 21 The present invention is a DC-DC boost circuit diagram. The DC-DC boost circuit is connected to a boost chip U10 of model number TX4314. The boost chip U10 boosts the input 3.3V voltage to 5V output and isolates the primary power supply.

[0072] Figure 22 This is a circuit diagram of the DC-DC isolated power supply of the present invention. The input terminal of the DC-DC isolated power supply is connected to the VCC_ISO output terminal of the DC-DC boost circuit. VCC_ISO outputs a 5V voltage. The DC-DC isolated power supply includes an isolation chip U11, model number B0505S-1WR3, whose output terminal outputs VCC_485, which is... Figures 23-25 Provides partial power.

[0073] Figure 23-25 This is a circuit diagram of the UART to RS485 converter of the present invention. The RS485 channel unit of the present invention is electrically connected to the central processing unit. This RS485 channel unit is connected to two RS485 conversion IC circuits through an isolation IC, and outputs through an RS485 interface. In the RS485 circuit, the input terminal of chip U8 is connected to a 3.3V voltage and chip U5. Chip U8 is an isolation IC, and its model is π162U31. The output terminal of chip U8 is divided into two paths and connected to chip U7 and chip U9 respectively. Chips U7 and U9 are UART to RS485 converter chips. The UART signal is isolated by chip U8 and then converted into RS485 output by chips U7 and U9.

[0074] Figure 26-27This is a circuit diagram of the LAN Ethernet isolation circuit of the present invention. The LAN Ethernet isolation circuit includes surge and electrostatic discharge (ESD) protection circuits. The LAN Ethernet isolation circuit is electrically connected to the central processing unit. After isolation by a dual transformer, the output is via a LAN Ethernet interface. The LAN Ethernet isolation circuit has 16 isolation channels, each requiring isolation via a T1 / T2 transformer. Each of the 16 isolation channels has surge and ESD protection circuits in its front-end circuit, specifically a BV03C type anti-static bidirectional diode in each isolation channel. Each of the 16 isolation channels also has a P0640SC type bidirectional diode for ESD protection in its rear-end circuit. The LAN Ethernet interface has multiple RJ45 interfaces; in this embodiment, four are used, each connected to one of the 16 isolation channels in its rear-end circuit.

[0075] Figure 28 This is a circuit diagram of the Ethernet physical layer processor of the present invention. Figures 29-30 for Figure 28 The circuit diagrams for areas K and L are enlarged. The Ethernet physical layer processor is a chip U12, which is used to expand the WAN / LAN optical ports and electrical ports.

[0076] Figure 31 This invention provides an isolation filter circuit for an Ethernet physical layer processor, which is further connected to the processor. The isolation filter circuit includes resistor R129, capacitors C86 and C87, resistor R130, capacitors C88, C89, and C96. One end of resistor R129 is connected to a 3.3V voltage, and its other end is connected to capacitor C86, resistor R130, and pin 30 (PHY_VDD3V3) of chip U12. The other end of capacitor C86 is grounded, and capacitors C87 and C86 are connected in parallel. The other end of resistor R130 is connected to capacitor C88 and pin 1 (PHY_AVDD3V3) of chip U12. The other end of capacitor C88 is grounded, and capacitor C89 is connected in parallel with it. A capacitor C96 is also connected to the circuit node between resistors R130 and R129, with the other end of capacitor C96 grounded. The circuit node between resistors R130 and R129 is also connected to pin 29 (PHY_VDDIO3V3) of chip U12. This isolation filter circuit uses RC filtering to prevent voltage fluctuations.

[0077] Figure 32 This is a circuit diagram of the Ethernet isolation circuit of the present invention. Figure 33 This is a circuit diagram of the WAN / LAN Ethernet optical port of this invention. Figure 34 This is the WAN / LAN Ethernet port circuit diagram of the present invention. Figure 35This is a circuit diagram of the WAN / LAN photoelectric switching circuit of the present invention. The Ethernet isolation circuit and... Figure 26-27 It serves the same purpose, isolating WAN / LAN Ethernet optical port circuits and WAN / LAN Ethernet electrical port circuits. Figure 32 The Ethernet isolation circuit diagram has 8 isolation channels.

[0078] The WAN / LAN Ethernet electrical port circuit is equipped with an auxiliary power supply. The front-end circuit of this auxiliary power supply has a protocol adaptation processing chip, and the rear-end circuit has a power regulator chip. The interface of the WAN / LAN Ethernet electrical port circuit is an RJ45 connector. The WAN / LAN Ethernet optical port circuit adopts a single-port SFP interface structure.

[0079] A 4G communication module is connected to the central processing unit, and a 5G communication module is connected to the central processing unit.

[0080] The multi-channel communication-based hyper-converged gateway also includes a SIM card interface circuit, which is electrically connected to the 4G communication module and the 5G communication module respectively, and the SIM card interface circuit is equipped with an ESD protection circuit.

[0081] In summary, the present invention addresses the efficient transmission of gateway data: IoT devices generate massive amounts of data, and directly transmitting this data to the cloud can consume significant network bandwidth and increase the data processing burden. The IoT gateway can preprocess and filter data locally, such as removing redundant data and transmitting only useful data, thereby improving data transmission efficiency and reducing the data processing pressure on the cloud.

[0082] This invention addresses the security management of gateways: the security of IoT devices and data is paramount. IoT gateways provide functions such as data encryption, device authentication, and access control to protect devices and data from cyberattacks, ensuring data security and privacy.

[0083] The protocol conversion of the gateway in this invention: IoT devices may use different communication protocols, such as Modbus, LoRa, or custom proprietary protocols, while the Internet typically uses the IP protocol. The IoT gateway can convert between these different protocols, enabling seamless communication between different devices.

[0084] The local storage and processing of data in the gateway of this invention addresses the issue that network connections may be unstable or temporarily disconnected in certain situations. The IoT gateway can store data locally and transmit it to the cloud once the connection is restored. This ensures no data loss and enables rapid response in applications with high real-time requirements.

[0085] This invention relates to gateway device management: the IoT gateway monitors and manages connected devices, including device status, configuration updates, fault detection, and repair. This helps ensure the normal operation and maintenance of the system.

[0086] Through these inventions, IoT gateways play a crucial bridging role in IoT systems, connecting devices and cloud services to ensure efficient, secure, and accurate data transmission.

[0087] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A hyperconverged gateway based on multi-channel communication, comprising a power supply module, characterized in that... The multi-channel communication-based hyperconverged gateway also includes: A central processing unit is connected to the power module, and the central processing unit is used to process gateway data. The RS485 channel unit is electrically connected to the central processing unit. The RS485 channel unit is connected to two RS485 conversion IC circuits by an isolation IC and outputs through an RS485 interface. A LAN Ethernet isolation circuit is electrically connected to the central processing unit. After being isolated by a dual transformer, the LAN Ethernet isolation circuit outputs a LAN Ethernet interface. The Ethernet expansion interface unit has an Ethernet physical layer processor, which is electrically connected to an Ethernet isolation circuit. The Ethernet isolation circuit is also connected to a central processing unit. The Ethernet expansion interface unit also has a WAN / LAN Ethernet electrical port circuit connected to the output of the Ethernet isolation circuit and a WAN / LAN Ethernet optical port circuit connected to the output of the Ethernet isolation circuit. The WAN / LAN Ethernet electrical port circuit and the WAN / LAN Ethernet optical port circuit are switched by a WAN / LAN optoelectronic switching circuit to prevent the WAN / LAN Ethernet electrical port circuit and the WAN / LAN Ethernet optical port circuit from being connected at the same time. The 4G communication module is connected to the central processing unit; The 5G communication module is connected to the central processing unit; The power module has a protection circuit to prevent overcurrent and overvoltage, and a DC-to-DC circuit electrically connected to the output terminal of the protection circuit. The DC-to-DC circuit splits into two step-down circuits. The first step-down circuit supplies power to the system and the second step-down circuit supplies power to the 4G module. The circuit structure of the protection circuit is as follows: pin 2 of the power interface CN1 is connected to the positive terminal of the Zener diode D3 and pin 1 of the first coil of the inductor L1. The negative terminal of the Zener diode D3 is connected to one end of the fuse TP1. The other end of the fuse TP1 is connected to the DCIN_24 voltage. The negative terminal of the Zener diode D3 is also connected to pin 2 of the second coil of the inductor L1. Pin 4 of the first coil of the inductor L1 is grounded and connected to the negative terminal of a polarized capacitor C1. Pin 3 of the second coil of the inductor L1 outputs the VDD_24 voltage and is connected to the positive terminal of the polarized capacitor C1. The circuit structure of the DC-to-DC circuit is as follows: The DC-to-DC circuit converts the input 12~24V voltage to a 5V voltage output. The 12~24V voltage enters the voltage regulator chip U3 through the Zener diode, and then passes through the filter of the inductor L2 to output a stable 5V voltage. The first step-down circuit receives a 5V voltage from a DC-to-DC converter, which then passes through a Zener diode and enters regulators U1 and U2, ultimately outputting a 3.3V voltage to power the system. The second step-down circuit receives a 5V voltage output from a DC-to-DC converter, which is filtered by inductor L3 and then fed into a JW5357 step-down regulator U4. The voltage is then divided by resistor R6 to output a 4.0V voltage, which powers the 4G module. The power supply circuit of the power module to the central processing unit is equipped with a voltage regulator circuit. The voltage regulator circuit provides a stable voltage to the central processing unit and suppresses current fluctuations to prevent voltage fluctuations. The circuit structure of the voltage regulator circuit is as follows: a 3.3V voltage is supplied to the central processing module. The 3.3V voltage is connected to the first terminal of the inductor FB1. The second terminal of the inductor FB1 is connected to the positive terminal of a polarized capacitor C25. The negative terminal of the polarized capacitor C25 is grounded. The polarized capacitor C25 is connected in parallel with capacitors C26, C27, and C28. Through the inductor FB1 and multiple capacitors, current fluctuations are suppressed, and a stable 3.3V voltage is output to the central processing unit. The Ethernet physical layer processor is also connected to an isolation filter circuit; the isolation filter circuit includes resistor R129, capacitor C86, capacitor C87, resistor R130, capacitor C88, capacitor C89, and capacitor C96. One end of resistor R129 is connected to a 3.3V voltage, and the other end is connected to capacitor C86, resistor R130, and pin 30 (PHY_VDD3V3) of chip U12. The other end of capacitor C86 is grounded. Capacitors C87 and C86 are connected in parallel. Resistor R129... The other end of resistor R130 is connected to capacitor C88 and pin 1 of chip U12, PHY_AVDD3V3. The other end of capacitor C88 is grounded, and it is also connected in parallel with capacitor C89. A capacitor C96 is also connected at the circuit node between resistor R130 and resistor R129. The other end of capacitor C96 is grounded. The circuit node between resistor R130 and resistor R129 is also connected to pin 29 of chip U12, PHY_VDDIO3V3. This isolation filter circuit uses RC filtering to avoid voltage fluctuations.

2. The hyperconverged gateway based on multi-channel communication according to claim 1, characterized in that... The multi-channel communication-based hyperconverged gateway also includes a TF card circuit connected to the central processing unit. The TF card circuit is equipped with an electrostatic discharge (ESD) protection circuit, which consists of an ESD5341N ESD protector connected to each circuit.

3. A hyper-converged gateway based on multi-channel communication according to claim 1, characterized in that... The LAN Ethernet isolation circuit is equipped with surge and electrostatic protection circuits. The LAN Ethernet isolation circuit is isolated by dual transformers and outputs via a LAN Ethernet interface. The LAN Ethernet isolation circuit has 16 isolation channels, each of which requires isolation via a T1 / T2 transformer. The front-end circuit of each of the 16 isolation channels is equipped with surge and electrostatic discharge protection circuits, that is, each isolation channel is equipped with a BV03C type anti-static bidirectional diode. Each of the 16 isolation channels is also equipped with a P0640SC type bidirectional diode for electrostatic discharge protection. The LAN Ethernet interface has multiple ports.

4. A hyper-converged gateway based on multi-channel communication according to claim 3, characterized in that... The WAN / LAN Ethernet port circuit is equipped with an auxiliary power supply. The front-end circuit of the auxiliary power supply has a protocol adaptation processing chip, and the rear-end circuit has a power regulator chip. The interface of the WAN / LAN Ethernet port circuit is an RJ45 crystal head interface.

5. A hyper-converged gateway based on multi-channel communication according to claim 1, characterized in that... The WAN / LAN Ethernet optical port circuit adopts a single-port SFP interface structure.

6. A hyperconverged gateway based on multi-channel communication according to claim 1, characterized in that, The LAN Ethernet interface is provided in multiple ways, all of which are RJ45 interfaces.

7. A hyperconverged gateway based on multi-channel communication according to claim 1, characterized in that, The multi-channel communication-based hyper-converged gateway also includes a SIM card interface circuit, which is electrically connected to the 4G communication module and the 5G communication module respectively, and the SIM card interface circuit is equipped with an ESD protection circuit.

8. A hyperconverged gateway based on multi-channel communication according to claim 1, characterized in that, The RS485 channel unit is connected to two RS485 conversion IC circuits via an isolation IC. In the RS485 output circuit, the input terminal of chip U8 is connected to a 3.3V voltage and chip U5. Chip U8 is an isolation IC, model π162U31. The output terminal of chip U8 is divided into two paths, which are connected to chip U7 and chip U9 respectively. Chips U7 and U9 are UART to RS485 chips. The UART signal is isolated by chip U8 and then converted into RS485 output by chips U7 and U9.

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