Semiconductor device and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method and a memory system. The semiconductor device comprises semiconductor columns arranged in an array mode, gate structures and back gate structures, the gate structures and the back gate structures are located on the two opposite sides of the semiconductor columns in the first direction respectively, each gate structure comprises an upper surface and a lower surface which are opposite in the second direction, and the first direction intersects with the second direction. The second direction is the extension direction of the semiconductor column; the back gate structure comprises a top surface and a bottom surface which are opposite in the second direction; and the lower surface is flush with the bottom surface in the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and preparation, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is one of the important storage components in electronic systems. Taking DRAM as an example, a semiconductor device may include a storage unit composed of a capacitor and a transistor, wherein a plurality of storage units may be arranged in the form of a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor array (Vertical Gate Transistor, VGT). In this structure, the extension direction of the channel of the transistor is perpendicular to the substrate surface, and the source and drain of the transistor are respectively formed at both ends of the channel extension direction, and the gate structure of the transistor is formed on at least one side of the channel.

[0003] With the rapid development of semiconductor technology, how to optimize the comprehensive performance of semiconductor devices, simplify the preparation process and reduce process costs is one of the important research directions in the industry. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: semiconductor columns, gate structures and back gate structures arranged in an array, wherein the gate structure and the back gate structure are respectively located on two sides of the semiconductor column that are opposite to each other along a first direction, wherein the gate structure includes an upper surface and a lower surface that are opposite to each other in a second direction, wherein the first direction intersects with the second direction, and the second direction is an extension direction of the semiconductor column; the back gate structure includes a top surface and a bottom surface that are opposite to each other in the second direction; and the lower surface is flush with the bottom surface in the second direction.

[0006] In one embodiment of the present application, the semiconductor device includes at least one storage plane area formed with the semiconductor pillar, the storage plane area includes a first area located at the edge of the storage plane area and a second area different from the first area, wherein the lower surfaces of the plurality of gate structures located in the second area are flush in the second direction.

[0007] In one embodiment of the present application, the semiconductor device includes at least one storage plane area formed with the semiconductor pillar, the storage plane area includes a first area located at the edge of the storage plane area and a second area different from the first area, wherein the lower surfaces of the multiple back gate structures located in the second area are flush in the second direction.

[0008] In one embodiment of the present application, in the second direction, the upper surface of the gate structure and the top surface of the back gate structure are located at different heights, respectively.

[0009] In one embodiment of the present application, the back gate structure includes a conductive layer.

[0010] In one embodiment of the present application, the gate structure includes a gate adhesion layer and a gate metal layer, wherein the gate adhesion layer is located between the first sidewall of the semiconductor pillar and the gate metal layer.

[0011] In one embodiment of the present application, the gate adhesion layer and the conductive layer include conductive material layers of the same material.

[0012] In one embodiment of the present application, along the second direction, the gate structure includes an upper end and a lower end opposite to each other, wherein the thickness of each portion of the lower end in the first direction is consistent.

[0013] In one embodiment of the present application, the cross-sectional shape of the gate structure in a plane parallel to the plane formed by the first direction and the second direction is a rectangle; and / or the cross-sectional shape of the back gate structure in the plane is a rectangle.

[0014] In one embodiment of the present application, the gate structure includes a gate dielectric layer located on a first side wall of the semiconductor column; and the back gate structure includes a back gate dielectric layer located on a second side wall of the semiconductor column, wherein the first side wall and the second side wall are opposite to each other in the first direction.

[0015] In one embodiment of the present application, the gate dielectric layer and the back gate dielectric layer include insulating material layers made of the same material.

[0016] In one embodiment of the present application, the semiconductor device also includes a bit line structure and a bit line isolation structure, wherein the bit line structure extends in the first direction and contacts the plurality of semiconductor pillars; and the bit line structure and the bit line isolation structure are alternately arranged in a third direction, wherein the first direction, the second direction and the third direction intersect with each other.

[0017] In one embodiment of the present application, the bit line isolation structure includes an isolation dielectric layer and an air gap layer surrounded by the isolation dielectric layer.

[0018] On the other hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming an initial semiconductor column extending along a second direction on a first side of a substrate; forming an initial gate structure and an initial back gate structure on two opposite sides of the initial semiconductor column in the first direction, respectively, wherein the first direction and the second direction intersect with each other; removing a portion of the initial gate structure and a portion of the initial back gate structure from a second side opposite to the first side to form a gate structure and a back gate structure; and forming a sealing layer, wherein the sealing layer covers the groove formed by the removal process from the second side.

[0019] In one embodiment of the present application, the gate structure includes an upper surface and a lower surface opposite to each other in the second direction, the lower surface is equivalent to the upper surface close to the substrate; the back gate structure includes a top surface and a bottom surface opposite to each other in the second direction, the bottom surface is close to the substrate relative to the top surface; and the lower surface is flush with the bottom surface in the second direction.

[0020] In one embodiment of the present application, the substrate includes a plurality of semiconductor layers arranged at intervals in a third direction, the third direction intersecting with the first direction and the second direction, and forming the initial semiconductor column includes forming a first groove and a second groove extending in the substrate along the second direction from the first side, wherein a plurality of the first grooves and a plurality of the second grooves are alternately distributed in the first direction to divide the semiconductor layer into a plurality of the initial semiconductor columns, wherein the plurality of the first grooves have different depths along the second direction.

[0021] In one embodiment of the present application, the substrate includes a plurality of semiconductor layers arranged at intervals in a third direction, the third direction intersecting with the first direction and the second direction, and forming the initial semiconductor column includes forming a first groove and a second groove extending in the substrate along the second direction from the first side, wherein a plurality of the first grooves and a plurality of the second grooves are alternately distributed in the first direction to divide the semiconductor layer into a plurality of the initial semiconductor columns, wherein a plurality of the second grooves have different depths along the second direction.

[0022] In one embodiment of the present application, the method further includes forming a semiconductor column, wherein forming a plurality of the semiconductor columns includes: before removing a portion of the initial gate structure and a portion of the initial back gate structure, removing a portion of the initial semiconductor column from the second side to form the semiconductor column.

[0023] In one embodiment of the present application, forming the initial gate structure includes forming the initial gate structure in the first trench, wherein an initial gate dielectric layer is formed on the sidewalls and bottom of the first trench; and an initial gate adhesion layer and an initial gate metal layer are sequentially formed on the surface of the initial gate dielectric layer.

[0024] In one embodiment of the present application, forming the initial back gate structure includes forming the initial back gate structure in the second trench, wherein an initial back gate dielectric layer is formed on the sidewall and bottom of the second trench; and an initial conductive layer is used to fill the remaining space of the second trench.

[0025] In one embodiment of the present application, the initial gate structure includes an initial gate dielectric layer and an initial gate conductive layer, the initial back gate structure includes an initial back gate dielectric layer and an initial back gate conductive layer, and removing a portion of the initial gate structure and a portion of the initial back gate structure from a second side opposite to the first side includes: removing a portion of the initial semiconductor column from the second side to expose a portion of the initial gate dielectric layer and a portion of the initial back gate dielectric layer.

[0026] In one embodiment of the present application, after exposing a portion of the initial gate dielectric layer and a portion of the initial back gate dielectric layer, the method further includes: removing the exposed portion of the initial gate dielectric layer and a portion of the initial back gate dielectric layer, a portion of the initial gate conductive layer corresponding to the exposed portion of the initial gate dielectric layer, and a portion of the initial back gate conductive layer corresponding to the exposed portion of the initial back gate dielectric layer; and continuing to remove a portion of the initial gate conductive layer and a portion of the initial back gate conductive layer from the second side.

[0027] In one embodiment of the present application, a sealing layer is formed, wherein the sealing layer covers the groove formed by the removal process from the second side, including: forming an initial sealing layer from the second side, the initial sealing layer at least covering the groove formed after continuing to remove a portion of the initial gate conductive layer and the groove formed after continuing to remove a portion of the initial back gate conductive layer; and removing a portion of the initial sealing layer to form the sealing layer.

[0028] In one embodiment of the present application, removing the exposed portion of the initial gate dielectric layer and the initial back gate dielectric layer, the portion of the initial gate adhesion layer and the portion of the initial gate metal layer corresponding to the exposed portion of the initial gate dielectric layer, and the portion of the initial conductive layer corresponding to the exposed portion of the initial back gate dielectric layer comprises: using a dry etching process to remove the exposed portion of the initial gate dielectric layer and the initial back gate dielectric layer, the portion of the initial gate adhesion layer and the portion of the initial gate metal layer corresponding to the exposed portion of the initial gate dielectric layer, and the portion of the initial conductive layer corresponding to the exposed portion of the initial back gate dielectric layer in the same process.

[0029] In one embodiment of the present application, continuing to remove a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial conductive layer from the second side includes: using a wet etching process to continue to remove a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial conductive layer from the second side in the same process.

[0030] In one embodiment of the present application, after forming the gate structure and the back gate structure, the method further includes: forming an initial bit line structure covering at least the gate structure and the back gate structure from the second side; removing part of the initial bit line structure to form a bit line structure and openings alternately arranged with the bit line structure in a third direction, wherein the bit line structure extends along the first direction and connects the first ends of a plurality of the semiconductor pillars, and the third direction intersects with the first direction and the second direction; and forming a bit line isolation structure in the opening, wherein the bit line isolation structure includes an isolation dielectric layer and an air gap layer surrounded by the isolation dielectric layer.

[0031] Another aspect of the present application provides a storage system, which includes the semiconductor device provided in one aspect of the present application and a controller coupled to the semiconductor device, wherein the controller is used to store data in the semiconductor device.

[0032] According to a semiconductor device, a preparation method, and a memory system provided by at least one embodiment of the present application, the semiconductor device includes semiconductor pillars, a gate structure, and a back gate structure arranged in an array, the gate structure and the back gate structure are respectively located on two opposite sides of the semiconductor pillar in a first direction, and the lower surface of the gate structure close to the bottom end of the semiconductor pillar and the bottom surface of the back gate structure close to the bottom end of the semiconductor pillar are flush in the extension direction of the semiconductor pillar, thereby improving the structural consistency of the storage unit in the semiconductor device, which is beneficial to improving the impact of structural differences on the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0034] Figure 1 is a top view of a semiconductor device according to an exemplary embodiment of the present application;

[0035] Figure 2 yes Figure 1 A schematic cross-sectional view of the semiconductor device shown is taken along line AA';

[0036] Figure 3 yes Figure 1 A schematic cross-sectional view of the semiconductor device shown is taken along line BB';

[0037] Figure 4 is a bottom view of a semiconductor device according to an exemplary embodiment of the present application;

[0038] Figure 5 is a flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present application;

[0039] Fig. 6A A schematic top view of a structure formed after a basic structure is formed according to a preparation method in one embodiment of the present application;

[0040] Figure 6B It is a schematic top view of a structure formed after forming a first groove and a second groove according to a preparation method in one embodiment of the present application;

[0041] Figure 6C for Figure 6B A schematic cross-sectional view of the intermediate body shown along line AA';

[0042] Fig. 7A A schematic top view of a structure formed after an initial gate structure and an initial back gate structure are formed according to a preparation method in one embodiment of the present application;

[0043] Figure 7B yes Fig. 7A A schematic cross-sectional view of the intermediate body shown along line AA';

[0044] Figure 7C yes Fig. 7A A schematic cross-sectional view of the intermediate body shown along line BB';

[0045] Fig. 8A A schematic top view of a structure formed after removing part of the basic structure according to a preparation method in one embodiment of the present application;

[0046] Figure 8BIt is a cross-sectional schematic diagram of a structure formed after removing part of the basic structure according to a preparation method in one embodiment of the present application;

[0047] Figure 8C It is a cross-sectional schematic diagram of a structure formed after removing part of the basic structure according to a preparation method in one embodiment of the present application;

[0048] Fig. 9A A schematic top view of a structure formed after exposing an initial gate dielectric layer and an initial back gate dielectric layer according to a preparation method in one embodiment of the present application;

[0049] Fig. 9B A schematic cross-sectional view of a structure formed after exposing an initial gate dielectric layer and an initial back gate dielectric layer according to a preparation method in one embodiment of the present application;

[0050] Fig. 9C A schematic cross-sectional view of a structure formed after exposing an initial gate dielectric layer and an initial back gate dielectric layer according to a preparation method in one embodiment of the present application;

[0051] Fig. 10A A schematic top view of a structure formed by removing a portion of an initial gate structure and a portion of an initial back gate structure according to a preparation method in one embodiment of the present application;

[0052] Fig. 10B A schematic cross-sectional view of a structure formed after removing a portion of an initial gate structure and a portion of an initial back gate structure according to a preparation method in one embodiment of the present application;

[0053] Fig. 10C A schematic cross-sectional view of a structure formed after removing a portion of an initial gate structure and a portion of an initial back gate structure according to a preparation method in one embodiment of the present application;

[0054] Fig.11A A schematic top view of a structure formed after a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial back gate conductive layer are further removed according to a preparation method in one embodiment of the present application;

[0055] Fig. 11B A schematic cross-sectional view of a structure formed after a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial back gate conductive layer are further removed according to a preparation method in one embodiment of the present application;

[0056] Fig. 11C A schematic cross-sectional view of a structure formed after a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial back gate conductive layer are further removed according to a preparation method in one embodiment of the present application;

[0057] Fig. 12AA schematic top view of a structure formed after a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial back gate conductive layer are further removed according to a preparation method in one embodiment of the present application;

[0058] Fig. 12B A schematic cross-sectional view of a structure formed after a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial back gate conductive layer are further removed according to a preparation method in one embodiment of the present application;

[0059] Fig. 12C A schematic cross-sectional view of a structure formed after a portion of the initial gate adhesion layer, a portion of the initial gate metal layer, and a portion of the initial back gate conductive layer are further removed according to a preparation method in one embodiment of the present application;

[0060] Fig.13A A schematic top view of a structure formed after forming an isolation initial gate adhesion layer, an initial gate metal layer and an initial back gate conductive layer according to a preparation method in one embodiment of the present application;

[0061] Fig. 13B A schematic cross-sectional view of a structure formed after forming an isolation initial gate adhesion layer, an initial gate metal layer and an initial back gate conductive layer according to a preparation method in one embodiment of the present application;

[0062] Fig. 13C A schematic cross-sectional view of a structure formed after forming an isolation initial gate adhesion layer, an initial gate metal layer and an initial back gate conductive layer according to a preparation method in one embodiment of the present application;

[0063] Fig.14A A schematic top view of a structure formed after an initial bit line structure is formed according to a preparation method in one embodiment of the present application;

[0064] Fig. 14B A schematic cross-sectional view of a structure formed after an initial bit line structure is formed according to a preparation method in one embodiment of the present application;

[0065] Fig. 14C A schematic cross-sectional view of a structure formed after an initial bit line structure is formed according to a preparation method in one embodiment of the present application;

[0066] Fig.15A A schematic top view of a structure formed after a gate structure and a back gate structure are formed according to a preparation method in one embodiment of the present application;

[0067] Fig. 15B A bottom view schematically shows a structure formed after a bit line structure is formed on the back side of an intermediate body according to a preparation method in one embodiment of the present application;

[0068] Fig.16AA schematic top view of a structure formed after a basic structure is formed according to a preparation method in another embodiment of the present application;

[0069] Fig. 16B It is a schematic top view of a structure formed after forming a first groove and a second groove according to a preparation method in another embodiment of the present application;

[0070] Fig. 16C for Fig. 16B A schematic cross-sectional view of the intermediate body shown along line AA';

[0071] Fig.17A is a schematic top view of a structure formed after forming an initial gate structure and an initial back gate structure according to a preparation method in another embodiment of the present application;

[0072] Fig. 17B yes Fig.17A A schematic cross-sectional view of the intermediate body shown along line AA';

[0073] Fig. 17C yes Fig.17A A schematic cross-sectional view of the intermediate body shown along line BB';

[0074] Fig.18A It is a schematic top view of a structure formed after removing part of the basic structure according to a preparation method in another embodiment of the present application;

[0075] Fig.18B It is a cross-sectional schematic diagram of a structure formed after removing part of the basic structure according to a preparation method in another embodiment of the present application;

[0076] Fig. 18C It is a cross-sectional schematic diagram of a structure formed after removing part of the basic structure according to a preparation method in another embodiment of the present application;

[0077] Fig.19A A schematic top view of a structure formed after exposing an initial gate adhesion layer and an initial back gate conductive layer according to a preparation method in another embodiment of the present application;

[0078] Fig.19B It is a cross-sectional schematic diagram of a structure formed after exposing an initial gate adhesion layer and an initial back gate conductive layer according to a preparation method in another embodiment of the present application;

[0079] Fig.19C It is a cross-sectional schematic diagram of a structure formed after exposing an initial gate adhesion layer and an initial back gate conductive layer according to a preparation method in another embodiment of the present application;

[0080] Fig. 20AA schematic top view of a structure formed after a gate adhesion layer, a gate metal layer and a back gate conductive layer are formed according to a preparation method in another embodiment of the present application;

[0081] Fig. 20B It is a cross-sectional schematic diagram of a structure formed after a gate adhesion layer, a gate metal layer and a back gate conductive layer are formed according to a preparation method in another embodiment of the present application;

[0082] Fig. 20C It is a cross-sectional schematic diagram of a structure formed after a gate adhesion layer, a gate metal layer and a back gate conductive layer are formed according to a preparation method in another embodiment of the present application;

[0083] Fig.21A It is a schematic top view of a structure formed after an initial sealing layer is formed according to a preparation method in another embodiment of the present application;

[0084] Fig. 21B It is a cross-sectional schematic diagram of a structure formed after an initial sealing layer is formed according to a preparation method in another embodiment of the present application;

[0085] Fig. 21C It is a cross-sectional schematic diagram of a structure formed after an initial sealing layer is formed according to a preparation method in another embodiment of the present application;

[0086] Fig.22A It is a schematic top view of a structure formed after a sealing layer is formed according to a preparation method in another embodiment of the present application;

[0087] Fig. 22B It is a cross-sectional schematic diagram of a structure formed after a sealing layer is formed according to a preparation method in another embodiment of the present application;

[0088] Fig. 22C It is a cross-sectional schematic diagram of a structure formed after a sealing layer is formed according to a preparation method in another embodiment of the present application;

[0089] Fig.23A is a schematic top view of a structure formed after an initial bit line structure is formed according to a preparation method in another embodiment of the present application;

[0090] Fig. 23B is a schematic cross-sectional view of a structure formed after an initial bit line structure is formed according to a preparation method in another embodiment of the present application;

[0091] Fig.23C is a schematic cross-sectional view of a structure formed after an initial bit line structure is formed according to a preparation method in another embodiment of the present application;

[0092] Fig.24A A schematic top view of a structure formed after a gate structure and a back gate structure are formed according to a preparation method in another embodiment of the present application;

[0093] Fig. 24B A bottom view schematically shows a structure formed after a bit line structure is formed on the back side of an intermediate body according to a preparation method in another embodiment of the present application; and

[0094] Fig.25 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0095] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0096] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first end discussed in this application may also be referred to as the second end, and vice versa.

[0097] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0098] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0099] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0100] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0101] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0102] The present application will be described in detail below with reference to the accompanying drawings and in combination with implementation modes.

[0103] Some embodiments of the present application provide a semiconductor device. Figure 1 is a top view of a semiconductor device 1000 according to an exemplary embodiment of the present application. Figure 2 yes Figure 1 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line AA′. Figure 3 yes Figure 1 The semiconductor device 1000 is shown as a schematic cross-sectional view taken along line BB′.

[0104] like Figures 1 to 3 As shown, the semiconductor device 1000 includes a semiconductor column 100, a gate structure 200 and a back gate structure 300. A plurality of semiconductor columns 100 are arranged in an array, and the gate structure 200 and the back gate structure 300 are respectively located on two opposite sides of the semiconductor column 100 in the x direction, wherein the gate structure 200 includes an upper surface 202 and a lower surface 201 opposite to each other in the second direction (z direction), and the lower surface 201 is close to the first end 110 (which can be understood as the bottom end of the semiconductor column 100) of the semiconductor column 100 relative to the upper surface 202; the back gate structure 300 includes a top surface 302 and a bottom surface 301 opposite to each other in the z direction, and the bottom surface 301 is close to the first end 110 of the semiconductor column 100 relative to the top surface 302. The lower surface 201 is flush with the bottom surface 301 in the z direction, the x direction and the z direction intersect each other, and the z direction is the extension direction of the semiconductor column 100.

[0105] According to at least one embodiment of the present application, the semiconductor device includes semiconductor pillars, gate structures and back gate structures arranged in an array, the gate structure and the back gate structure are respectively located on two opposite sides of the semiconductor pillar in a first direction, and the lower surface of the gate structure close to the bottom end of the semiconductor pillar and the bottom surface of the back gate structure close to the bottom end of the semiconductor pillar are flush in the extension direction of the semiconductor pillar, thereby improving the structural consistency of the storage unit in the semiconductor device, which is beneficial to improving the impact of structural differences on the performance of the semiconductor device.

[0106] Specifically, taking DRAM as an example, the semiconductor device may include a memory cell composed of a capacitor and a transistor, and a plurality of memory cells may be arranged in the form of a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor array (Vertical Gate Transistor, VGT). In this structure, the extension direction of the channel of the transistor is perpendicular to the substrate surface, and the source and drain of the transistor may be formed at both ends of the channel extension direction, respectively, and the gate structure of the transistor may be formed on at least one side of the channel.

[0107] In one embodiment of the present application, a vertical transistor such as a vertical metal oxide semiconductor field effect transistor (MOSFET) can replace a conventional planar transistor as a transfer transistor of a memory cell to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity. In some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical transistor may include a semiconductor pillar 100 extending vertically in the z direction above a substrate (not shown). The semiconductor pillar 100 may extend above the top surface of the substrate, exposing not only the top surface of the semiconductor pillar 100, but also one or more sidewalls of the semiconductor pillar 100, such as a first sidewall 120 and a second sidewall 130.

[0108] Alternatively, the semiconductor column 100 may have a cubic shape to expose its four side walls. However, it should be understood by those skilled in the art that the semiconductor column 100 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. In other words, the cross section of the semiconductor column 100 in a plane parallel to the plane formed by the x-direction and the y-direction (hereinafter referred to as the xy plane) may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape, wherein the x-direction, the y-direction, and the z-direction intersect with each other. It should be understood that, consistent with the scope of the present application, for a semiconductor column having a circular or elliptical cross section in the above plane, the semiconductor column can still be considered to have multiple side walls, so that the gate structure contacts more than one side wall of the semiconductor column, and the back gate structure contacts one side wall of the semiconductor column. As described below with respect to the preparation process, the semiconductor column 100 can be formed by a substrate by, for example, etching or epitaxial processes, and therefore can have the same semiconductor material as the substrate.

[0109] As an option, the material of the substrate may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. For example, the substrate may be a silicon substrate. Accordingly, the semiconductor pillar 100 may include at least one of the above materials.

[0110] The vertical transistor may include a gate structure 200 in contact with one or more sidewalls of the semiconductor pillar 100. For example, the gate structure 200 may be located on one of two sidewalls of the semiconductor pillar 100 that are opposite in the x-direction. In addition, on this basis, the gate structure 200 may also be located on the remaining sidewalls of the semiconductor pillar 100 except the two sidewalls that are opposite in the x-direction, which is not limited in the present application.

[0111] In one embodiment of the present application, the gate structure 200 may include a gate dielectric 230 on one or more sidewalls of the semiconductor pillar 100. In addition, the gate structure 200 may further include a gate adhesion layer 210 on and in contact with the gate dielectric 230, and a gate metal layer 220 on and in contact with the gate adhesion layer 210. In other words, the gate adhesion layer 210 is located between the first sidewall 120 of the semiconductor pillar 100 and the gate metal layer 220. Alternatively, the gate adhesion layer 210 and the gate metal layer 220 may be referred to as a gate conductive layer of the gate structure 200.

[0112] The gate dielectric 230 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 230 may include silicon oxide. In addition, the gate adhesion layer 210 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer 220 may include any suitable conductive material, such as the gate metal layer 220 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The gate adhesion layer 210 is used to block the diffusion of metal materials in the gate metal layer 220, and is also used to improve the adhesion between the gate metal layer 220 and the gate dielectric 230.

[0113] In some embodiments, the vertical transistor may further include a source and a drain formed at two ends of the semiconductor column 100 in the z direction, respectively, which may be understood as a doped region of the semiconductor column 100, and may also be referred to as a source electrode and a drain electrode. As an option, the source and the drain may be doped with any suitable P-type dopant, and the P-type dopant may include any one or a combination of boron (B) or gallium (Ga). As another option, the source and the drain may be doped with any suitable N-type dopant, and the N-type dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb). The source and the drain may be separated by the gate structure 200 in the z direction. In other words, the gate structure 200 is formed between the source and the drain along the z direction. Thus, when the gate voltage applied to the gate structure 200 is higher than the threshold voltage of the vertical transistor, one or more channels of the vertical transistor may be formed in the semiconductor column 100 along the z direction between the source and the drain (which may be understood as the gate control capability of the gate structure).

[0114] In some embodiments, the vertical transistor is a multi-gate transistor. In other words, the gate structure 200 may contact more than one sidewall of the semiconductor pillar 100 to form more than one gate, so that more than one channel may be formed between the source and the drain in operation. For example, the gate structure 200 may be located on one of the two sidewalls of the semiconductor pillar 100 opposite to each other in the x-direction, and on this basis, also located on the remaining sidewalls of the semiconductor pillar 100 except the two sidewalls opposite to each other in the x-direction.

[0115] Unlike a planar transistor including only a single planar gate, due to the 3D structure of the semiconductor pillar 100 and the gate structure 200 surrounding the multiple sidewalls of the semiconductor pillar 100, the multi-gate vertical transistor has a larger gate control area compared to the planar transistor to achieve better channel control with a smaller subthreshold swing. In addition, for the purpose of, for example, increasing the density of transistors and memory cells, the gate structure 200 may also be in contact with only a single sidewall of the semiconductor pillar 100, for example, the gate structure 200 is in contact with one of the two sidewalls of the semiconductor pillar 100 that are opposite in the x-direction, and the present application is not limited to this.

[0116] In addition, in some embodiments of the present application, the semiconductor device 1000 may include at least one storage plane region (not shown) formed with a semiconductor pillar 100, and a plurality of semiconductor pillars 100 are arranged in an array on the storage plane region, wherein the storage plane region may include a first region (not shown) located at the edge of the storage plane region and a second region (not shown) different from the first region. Each of the plurality of gate structures 200 may be located on one of two sidewalls of a single semiconductor pillar 100 opposite in the x direction, wherein the plurality of gate structures 200 located in the first region may be used for process and electrical buffering, and thus may also be referred to as dummy gate structures; the lower surfaces 201 of the plurality of gate structures 200 located in the second region may be flush in the z direction.

[0117] like Figure 2 As shown, the lower surfaces 201 of the plurality of gate structures 200 in the second region are flush in the z direction, which can be understood as the lower surfaces 201 of the gate conductive layers of the plurality of gate structures 200 in the second region are flush in the z direction. Optionally, the gate conductive layer includes a gate adhesive layer 210 and a gate metal layer 220 .

[0118] In addition, the gate structure 200 may further include a sealing layer 106 ′ located below the gate conductive layer. Optionally, the sealing layer 106 ′ may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric.

[0119] In addition, the gate structure 200 may further include a gate filling layer 240 surrounded by the gate conductive layer. Optionally, the gate filling layer 240 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric.

[0120] As an option, the gate dielectric 230, the gate filling layer 240 and the sealing layer 106' can be made of the same material. In this case, there is no obvious boundary between the portions where the gate dielectric 230, the gate filling layer 240 and the sealing layer 106' contact each other. Therefore, the bottom surfaces of the multiple gate structures 200 located in the second area are flush in the z direction, which can also be understood as the bottom surfaces of the gate dielectric 230, the gate filling layer 240 and the sealing layer 106' of the multiple gate structures 200 located in the second area are all flush in the z direction.

[0121] The lower surfaces of the multiple gate structures are substantially flush in the z direction, so that on the side 11 close to the first end 110, the gate metal layers 220 and the gate adhesive layers 210 of different gate structures 200 are flush with each other in the z direction relative to the same reference plane, which can improve the consistency of the gate structure, enhance the gate control capability of the gate structure, and improve the switching speed of the gate structure and the reliability of the semiconductor device. It should be noted that, due to process limitations, the error range of the lower surfaces 201 of the multiple gate structures 200 relative to the same reference plane can be between -10% and 10%.

[0122] In addition, in some embodiments, by applying a reference voltage (e.g., a ground voltage) to the back gate structure 300 of the semiconductor device 1000, interference between adjacent gate structures 200 in the semiconductor device 1000 can be reduced. The back gate structure 300 may include a back gate dielectric layer 320 located on the second sidewall 130 of the semiconductor pillar 100, and a back gate conductive layer 310 on the back gate dielectric layer 320 and in contact with the back gate dielectric layer 320. Optionally, the back gate dielectric layer 320 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the back gate dielectric layer 320 may include silicon oxide. In addition, the back gate conductive layer 310 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, and the like.

[0123] In order to simplify the manufacturing process and save production costs, the back gate dielectric layer 320 can be formed in the process of forming the gate dielectric 230, and the gate dielectric 230 and the back gate dielectric layer 320 can be prepared using the same material. In other words, the gate dielectric 230 and the back gate dielectric layer 320 can include insulating material layers made of the same material.

[0124] Similarly, to simplify the manufacturing process and save production costs, the same material can be used to prepare the back gate conductive layer 310 and the gate adhesive layer 210. In other words, the gate adhesive layer 210 and the back gate conductive layer 310 can include conductive material layers of the same material.

[0125] In addition, in some embodiments of the present application, the bottom surfaces 301 of the plurality of back gate structures 300 located in the second region may be flush in the z direction. Figure 2 The fact that the lower surfaces 301 of the plurality of back-gate structures 300 located in the second region are flush in the z direction can be understood as the fact that the lower surfaces 301 of the back-gate conductive layers 310 of the plurality of back-gate structures 300 located in the second region are flush in the z direction.

[0126] In addition, the enclosed layer 106' may also be located below the back gate conductive layer 310. As an option, the back gate dielectric layer 320 and the enclosed layer 106' may be made of the same material. In this case, there is no obvious boundary between the parts where the back gate dielectric layer 320 and the enclosed layer 106' contact each other. Therefore, the lower surfaces of the multiple back gate structures 300 located in the second area are flush in the z direction, which can also be understood as the lower surfaces of the back gate dielectric layer 320 and the enclosed layer 106' of the multiple back gate structures 300 located in the second area are flush in the z direction.

[0127] In other words, on the side 11 close to the first end 110, the back gate conductive layers 310 of different back gate structures 300 are flush with each other in the z direction relative to the same reference plane, so that the output terminal (not shown) of the reference voltage can be connected to the flush surfaces of the back gate conductive layers 310 of multiple different back gate structures 300. Therefore, the consistency of the back gate structure is improved, and the stability of its connection with the reference voltage output terminal can be enhanced.

[0128] On this basis, the lower surface 201 of the gate structure 200 is flush with the bottom surface 301 of the back gate structure 300 in the z direction, which can be understood as the lower surface 201 of the gate conductive layer is flush with the lower surface 301 of the back gate conductive layer 310 in the z direction.

[0129] Optionally, when the gate dielectric 230, the back gate dielectric layer 320, the gate filling layer 240 and the sealing layer 106' are made of the same material, the lower surfaces of the gate dielectric 230, the gate filling layer 240 and the sealing layer 106' of the gate structure 200 are flush with the lower surfaces of the back gate dielectric layer 320 and the sealing layer 106' of the back gate structure 300 in the z direction.

[0130] The lower surface of the gate structure near the bottom end of the semiconductor column and the bottom surface of the back gate structure near the bottom end of the semiconductor column are flush in the extension direction of the semiconductor column, which can improve the structural consistency of the storage unit in the semiconductor device and is beneficial to improving the impact of structural differences on the performance of the semiconductor device.

[0131] In addition, in some embodiments of the present application, in the z direction, the upper surface 202 of the gate structure 200 and the top surface 302 of the back gate structure 300 are respectively located at different heights. In other words, from the side 12 away from the first end 110, the gate metal layer 220 and the gate adhesive layer 210 of different gate structures 200 are flush in the z direction and are located at different heights with the back gate conductive layer 310 of the back gate structure 300.

[0132] In addition, in some embodiments of the present application, the gate structure 200 may include an upper end 200-1 and a lower end 200-2 opposite to each other along the z direction, wherein the lower end 200-2 is closer to the first end 110 relative to the upper end 200-1, and the thickness of the lower end 200-2 in the x direction is uniform.

[0133] In addition, optionally, the cross-sectional shape of the gate structure 200 in the xy plane is a rectangle. Optionally, the cross-sectional shape of the back gate structure 300 in the xy plane is a rectangle. Optionally, the cross-sectional shapes of the gate structure 200 and the back gate structure 300 in the xy plane are both rectangles.

[0134] Specifically, the gate structure can usually be formed by forming a groove extending along the z direction from the first side of the base structure through an etching process, and then filling the above-mentioned groove. However, due to the limitations of the etching process, it is difficult to form a flat surface at the bottom of the groove, so it is necessary to fill the groove from the first side multiple times (for example, FCVD process) and etch back multiple times to construct a flat surface at the bottom of the groove; then, a gate dielectric, an initial gate adhesion layer and an initial gate metal layer are sequentially formed on the sidewall and bottom flat surface of the groove from the first side; then, a punch etch process is used to remove the initial gate adhesion layer and the initial gate metal layer at the bottom of the groove from the first side, respectively, so as to form two gate structures located on opposite sidewalls of the groove.

[0135] However, in the above process, in the step of filling the trench from the first side and etching back multiple times, the process cost is high and the control difficulty is relatively large. In addition, in the step of removing the initial gate bonding layer and the initial gate metal layer located at the bottom of the trench from the first side by punch etching, the process window is small, and it is difficult to completely disconnect the initial gate bonding layer and the initial gate metal layer at the bottom of the trench, which may cause the two gate structures to be electrically connected, affecting the electrical performance of the final product.

[0136] In addition, since the shape of the previously formed initial gate structure (eg, gate dielectric, initial gate adhesion layer and initial gate metal layer) tends to the formation state of the sidewall and bottom surface of the trench, the cross-sectional shape of the initial gate structure in the xy plane is irregular.

[0137] In at least one embodiment of the present application, a gate structure is formed by removing a portion of an initial gate structure from a back side opposite to a first side, and an uneven portion of the initial gate structure located at a bottom surface of the trench is removed, so that the cross section of the finally formed gate structure in an xy plane can form a regular rectangular shape.

[0138] Likewise, in at least one embodiment of the present application, by using the same or similar process as described above, the back gate structure 300 may also have a regular rectangular cross-section in the xy plane.

[0139] In addition, thanks to the above process, the thickness of each part of the lower end 200 - 2 of the gate structure 200 in the x direction is consistent. The improvement of the consistency of the gate structure is conducive to improving the influence of structural differences on the performance of semiconductor devices.

[0140] Figure 4 is a bottom view of a semiconductor device 1000 according to an exemplary embodiment of the present application.

[0141] like Figure 2 , Figure 3 and Figure 4 As shown, in some embodiments of the present application, the semiconductor device 1000 further includes a bit line structure 400 and a bit line isolation structure 500, wherein the bit line structure 400 extends in the x-direction and contacts the first ends 110 of the plurality of semiconductor pillars 100, so that the plurality of first ends 110 are connected to each other through the bit line structure 400. The bit line structure 400 and the bit line isolation structure 500 are alternately arranged in the y-direction.

[0142] Alternatively, the bit line structure 400 may be a composite structure, for example, including a first bit line layer 400-1 and a second bit line layer 400-2 stacked in sequence in the z direction. Optionally, the first bit line layer 400-1 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The second bit line layer 400-2 may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate semiconductor material. Optionally, the second bit line layer 400-2 is located above the first bit line layer 400-1 and contacts the first end portions 110 of the plurality of semiconductor pillars 100.

[0143] In addition, in some embodiments of the present application, the bit line isolation structure 500 may include an isolation dielectric layer 510 and an air gap layer 520 surrounded by the isolation dielectric layer 510. The air gap layer 520 surrounded by the isolation dielectric layer 510 may reduce interference between adjacent gate structures 200 in the semiconductor device 1000.

[0144] Some embodiments of the present application provide a method for manufacturing a semiconductor device. Figure 5 is a flow chart of a method 2000 for fabricating a semiconductor device according to an exemplary embodiment of the present application. Figures 6A-15B They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to an embodiment of the present application; and Figures 16A-24B They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to another embodiment of the present application.

[0145] like Figure 5As shown, the present application provides a method 2000 for preparing a semiconductor device, comprising:

[0146] S1, forming an initial semiconductor column extending along a second direction on a first side of a substrate.

[0147] S2, forming an initial gate structure and an initial back gate structure on two opposite sides of the initial semiconductor column in a first direction, respectively, wherein the first direction and the second direction intersect each other.

[0148] S3, removing a portion of the initial gate structure and a portion of the initial back gate structure from a second side opposite to the first side to form a gate structure and a back gate structure.

[0149] S4, forming a sealing layer, wherein the sealing layer covers the groove formed by the removal process from the second side.

[0150] The following will be combined Figures 5 to 15B The specific process of each step of the above-mentioned preparation method 2000 in Example 1 is described in detail.

[0151] Example 1

[0152] Step S1

[0153] Fig. 6A It is a schematic top view of a structure formed after forming a basic structure 101 according to a preparation method in one embodiment of the present application. Figure 6B It is a schematic top view of a structure formed after forming the first groove 104 and the second groove 105 according to a preparation method in one embodiment of the present application. Figure 6C for Figure 6B The intermediate body is shown in a schematic cross-sectional view taken along line AA'.

[0154] like Figures 5 to 6C As shown, step S1 of forming an initial semiconductor column extending along the second direction on the first side of the substrate may, for example, include: forming a base structure 101 on the first side 12, wherein the base structure 101 includes a semiconductor layer 103 and an isolation layer 102 alternately distributed in the y direction, and the y direction intersects with the z direction and the x direction; forming a first trench 104 and a second trench 105 extending in the base structure 101 along the z direction respectively from the first side 12, wherein a plurality of first trenches 104 and a plurality of second trenches 105 are alternately distributed in the x direction to divide the semiconductor layer 103 into a plurality of initial semiconductor columns 100'.

[0155] Specifically, in one embodiment of the present application, the material for preparing the substrate can be any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the substrate can be selected from single crystal silicon.

[0156] In one embodiment of the present application, the substrate may be, for example, a composite substrate for supporting a device structure thereon. The substrate may be formed by sequentially arranging a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0157] In one embodiment of the present application, the substrate may include a substrate sacrificial layer. Optionally, the substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0158] In addition, a part of the substrate may also form a well region formed by doping with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Furthermore, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0159] After forming the substrate, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the substrate to form a plurality of openings (not shown) spaced apart along the y direction, wherein the remaining part of the substrate is also spaced apart in the y direction to form a plurality of semiconductor layers 103. Thereafter, the plurality of openings can be filled by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form an isolation layer 102. The isolation layer 102 can be formed using any suitable dielectric material. Optionally, the isolation layer 102 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0160] After forming the base structure 101, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to form a first groove 104 and a second groove 105 extending in the base structure 101 along the z direction respectively from the first side 12, wherein a plurality of first grooves 104 and a plurality of second grooves 105 are alternately distributed in the x direction to divide the semiconductor layer 103 into a plurality of initial semiconductor pillars 100'.

[0161] Optionally, the extension lengths of the multiple first trenches 104 in the z direction may be different. Similarly, the extension lengths of the multiple second trenches 105 in the z direction may be different. As described above, the initial gate structure and the initial back gate structure will be formed in the first trench and the second trench later, so the extension lengths of the multiple initial gate structures in the z direction may also be different, and the extension lengths of the multiple initial back gate structures in the z direction may also be different. By removing part of the initial gate structure and part of the initial back gate structure from the back side opposite to the first side, a gate structure and a back gate structure having a flat surface in the z direction on the back side can be formed, thereby improving the structural consistency of the storage unit in the semiconductor device and improving the impact of structural differences on the performance of the semiconductor device. The above-mentioned allowing the extension lengths of the multiple initial back gate structures in the z direction to be different, and the extension lengths of the multiple initial back gate structures in the z direction to be different, can reduce the difficulty of the etching process and increase the process window for preparing semiconductor devices.

[0162] Step S2

[0163] Fig. 7AIt is a schematic top view of a structure formed after forming an initial gate structure 200 ′ and an initial back gate structure 300 ′ according to a manufacturing method in one embodiment of the present application. Figure 7B yes Fig. 7A The intermediate body is shown in a schematic cross-sectional view taken along line AA'. Figure 7C yes Fig. 7A The intermediate body is shown in a schematic cross-sectional view taken along line BB'.

[0164] like Figure 5-7C As shown, step S2 forms an initial gate structure and an initial back gate structure on two opposite sides of the initial semiconductor column in a first direction, respectively, wherein the first direction and the second direction intersect each other and may, for example, include: forming an initial gate structure 200' on a first side wall 120' of the initial semiconductor column 100' in the x-direction; and forming an initial back gate structure 300' on a second side wall 130' of the initial semiconductor column 100' in the x-direction.

[0165] Combination Figure 6B , Figure 6C , Figure 7B and Figure 7C In one embodiment of the present application, forming the initial gate structure 200' includes: forming the initial gate structure 200' in the first trench 104 by one or more thin film deposition processes, the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, wherein an initial gate dielectric layer 230' is formed on the sidewall and bottom of the first trench 104; and an initial gate adhesion layer 210' and an initial gate metal layer 220' are sequentially formed on the surface of the initial gate dielectric layer 230'.

[0166] Alternatively, the initial gate adhesive layer 210 ′ and the initial gate metal layer 220 ′ may be referred to as an initial gate conductive layer of the initial gate structure 200 ′.

[0167] Optionally, the initial gate dielectric layer 230' may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the initial gate dielectric layer 230' may include silicon oxide. In addition, the initial gate adhesion layer 210' may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the initial gate metal layer 220' may include any suitable conductive material, such as the gate metal layer 220 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The initial gate adhesion layer 210' is used to block the diffusion of metal materials in the initial gate metal layer 220', and is also used to improve the adhesion between the initial gate metal layer 220' and the initial gate dielectric layer 230'.

[0168] Combination Figure 6B , Figure 6C , Figure 7B and Figure 7C In one embodiment of the present application, forming an initial back gate structure 300' includes: forming an initial back gate structure 300' in the second trench 105 by one or more thin film deposition processes, the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, wherein an initial back gate dielectric layer 320' is formed on the sidewall and bottom of the second trench 105; and filling the remaining space of the second trench 105 with an initial back gate conductive layer 310'.

[0169] Optionally, the initial back gate dielectric layer 320' may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the initial back gate dielectric layer 320' may include silicon oxide. In addition, the initial back gate conductive layer 310' may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0170] In order to simplify the preparation process and save production costs, the initial back gate dielectric layer 320' can be formed in the process of forming the initial gate dielectric 230', and the initial gate dielectric 230' and the initial back gate dielectric layer 320' can be prepared by the same material. In other words, the initial gate dielectric 230' and the initial back gate dielectric layer 320' can include insulating material layers made of the same material.

[0171] Similarly, to simplify the preparation process and save production costs, the initial back gate conductive layer 310' and the initial gate adhesive layer 210' can be prepared with the same material. In other words, the initial gate adhesive layer 210' and the initial back gate conductive layer 310' can include conductive material layers of the same material.

[0172] Step S3

[0173] Fig. 8A It is a schematic top view of a structure formed after removing part of the basic structure 101 according to a preparation method in one embodiment of the present application. Figure 8B It is a cross-sectional schematic diagram of a structure formed after removing part of the basic structure 101 according to a preparation method in one embodiment of the present application. Figure 8C It is a cross-sectional schematic diagram of a structure formed after removing part of the basic structure 101 according to a preparation method in one embodiment of the present application. Fig. 9A It is a schematic top view of a structure formed after the initial gate dielectric 230 ′ and the initial back gate dielectric layer 320 ′ are exposed according to a preparation method in one embodiment of the present application. Fig. 9BIt is a cross-sectional schematic diagram of a structure formed after the initial gate dielectric 230 ′ and the initial back gate dielectric layer 320 ′ are exposed according to a preparation method in one embodiment of the present application. Fig. 9C It is a cross-sectional schematic diagram of a structure formed after the initial gate dielectric 230 ′ and the initial back gate dielectric layer 320 ′ are exposed according to a preparation method in one embodiment of the present application. Fig. 10A It is a schematic top view of a structure formed after removing a portion of the initial gate structure 200 ′ and a portion of the initial back gate structure 300 ′ according to a manufacturing method in one embodiment of the present application. Fig. 10B It is a cross-sectional schematic diagram of a structure formed after removing a portion of the initial gate structure 200 ′ and a portion of the initial back gate structure 300 ′ according to a manufacturing method in one embodiment of the present application. Fig. 10C It is a cross-sectional schematic diagram of a structure formed after removing a portion of the initial gate structure 200 ′ and a portion of the initial back gate structure 300 ′ according to a manufacturing method in one embodiment of the present application. Fig.11A It is a schematic top view of a structure formed after further removing a portion of the initial gate adhesion layer 210 ′, a portion of the initial gate metal layer 220 ′ and a portion of the initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig. 11B It is a cross-sectional schematic diagram of a structure formed after further removing a portion of the initial gate adhesion layer 210 ′, a portion of the initial gate metal layer 220 ′ and a portion of the initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig. 11C It is a cross-sectional schematic diagram of a structure formed after further removing a portion of the initial gate adhesion layer 210 ′, a portion of the initial gate metal layer 220 ′ and a portion of the initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application.

[0174] like Figure 5 , Figures 7A-11C As shown, step S3 removes part of the initial gate structure and part of the initial back gate structure from the second side opposite to the first side to form the gate structure and the back gate structure, which may for example include: removing part of the initial semiconductor pillar 100' from the second side 11 to expose part of the initial gate dielectric 230' and part of the initial back gate dielectric layer 320'; removing the exposed part of the initial gate dielectric layer 230' and part of the initial back gate dielectric layer 230', the part of the initial gate conductive layer corresponding to the exposed part of the initial gate dielectric layer 230', and the part of the initial back gate conductive layer 310' corresponding to the exposed part of the initial back gate dielectric layer 320'; and continuing to remove part of the initial gate conductive layer and part of the initial back gate conductive layer 310' from the second side.

[0175] Specifically, Figures 7A-8CAs shown, in one embodiment of the present application, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove part of the substrate from the second side 11, for example, at least remove the substrate 101' located under the isolation layer 102, and thin the substrate located under the initial semiconductor column 100'.

[0176] Afterwards, if Figures 8A-9C As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to continue to remove a portion of the initial semiconductor column 100' from the second side 11 to expose a portion of the initial gate dielectric 230' and a portion of the initial back gate dielectric layer 320', and form the semiconductor column 100.

[0177] In other words, in one embodiment of the present application, the method 1000 for preparing a semiconductor device further includes forming a semiconductor pillar 100. Optionally, forming a plurality of semiconductor pillars 100 may include removing a portion of the initial semiconductor pillar 100' from the second side 11 before removing a portion of the initial gate structure 200' and a portion of the initial back gate structure 300' to form the semiconductor pillar 100.

[0178] like Figures 9A-10C As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to remove the exposed portion of the initial gate dielectric layer 230' and the portion of the initial back gate dielectric layer 230', the initial gate conductive layer corresponding to the exposed portion of the initial gate dielectric layer 230', and the portion of the initial back gate conductive layer 310' corresponding to the exposed portion of the initial back gate dielectric layer 320' from the second side 11.

[0179] Specifically, the above process can be used to remove the exposed portion of the initial gate dielectric layer 230' and the portion of the initial back gate dielectric layer 230', the portion of the initial gate adhesion layer 210' and the portion of the initial gate metal layer 220' corresponding to the exposed portion of the initial gate dielectric layer 230', and the portion of the initial back gate conductive layer 310' corresponding to the exposed portion of the initial back gate dielectric layer 320' from the second side 11, thereby forming a first initial gate dielectric layer 230'-1, a first initial gate adhesion layer 210'-1 and a first initial gate metal layer 220'-1 having a flush surface in the z direction; and a first initial back gate dielectric layer 320'-1 and a first initial back gate conductive layer 310'-1 having a flush surface in the z direction.

[0180] Optionally, in order to reduce the process difficulty, simplify the process steps and reduce the preparation cost, a dry etching process may be used to remove the exposed part of the initial gate dielectric layer 230' and the part of the initial back gate dielectric layer 230', the part of the initial gate adhesive layer 210' and the part of the initial gate metal layer 220' corresponding to the exposed part of the initial gate dielectric layer 230', and the part of the initial back gate conductive layer 310' corresponding to the exposed part of the initial back gate dielectric layer 320' from the second side 11 in the same process. Therefore, the first initial gate dielectric layer 230'-1, the first initial gate adhesive layer 210'-1 and the first initial gate metal layer 220'-1, the first initial back gate dielectric layer 320'-1 and the first initial back gate conductive layer 310'-1 may have a flush surface in the z direction. As an option, the flush surface may be flush with the surface of the first end 110 of the semiconductor pillar 100.

[0181] It should be noted that, in the above process, the initial gate structure 200 ′ and the back gate structure 300 ′ located in the isolation layer 102 do not change.

[0182] Therefore, if Figures 10A-11C As shown, in order to remove part of the initial gate structure 200' and part of the back gate structure 300' located in the isolation layer 102, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to continue to remove part of the initial gate conductive layer and part of the initial back gate conductive layer 310' from the second side 11.

[0183] Specifically, the above process can be used to continue removing part of the initial gate adhesion layer 210 ′, part of the initial gate metal layer 220 ′ and part of the initial back gate conductive layer 310 ′ from the second side 11 , thereby forming a first groove 01 , a second groove 02 , a third groove 03 and a fourth groove 04 .

[0184] Among them, reference Figures 9A-11C In the above steps, a portion of the initial back gate conductive layer 310' between adjacent semiconductor pillars 100 is continuously removed from the second side 11 to form a first groove 01 and a back gate conductive layer 310; a portion of the initial gate adhesion layer 210' and a portion of the initial gate metal layer 220' between adjacent semiconductor pillars 100 are continuously removed from the second side 11 to form a second groove 02 and a gate adhesion layer 210 and a gate metal layer 220; a portion of the initial back gate conductive layer 310' in the isolation layer 102 is continuously removed from the second side 11 to form a third groove 03 and a back gate conductive layer 310; a portion of the initial gate adhesion layer 210' and a portion of the initial gate metal layer 220' in the isolation layer 102 is continuously removed from the second side 11 to form a fourth groove 04 and a gate adhesion layer 210 and a gate metal layer 220.

[0185] As an option, in order to reduce process difficulty, simplify process steps and reduce preparation cost, a wet etching process can be used to continue to remove part of the initial gate adhesion layer 210', part of the initial gate metal layer 220' and part of the initial back gate conductive layer 310' from the second side 11 in the same process.

[0186] Through the above steps, multiple gate adhesion layers 210, multiple gate metal layers 220 and multiple back gate conductive layers 310 can all have surfaces that are flush in the z direction, thereby improving the structural consistency of the storage unit in the semiconductor device and helping to improve the impact of structural differences on the performance of the semiconductor device.

[0187] Step S4

[0188] Fig. 12A It is a schematic top view of a structure formed after further removing a portion of the initial gate adhesion layer 210 ′, a portion of the initial gate metal layer 220 ′ and a portion of the initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig. 12B It is a cross-sectional schematic diagram of a structure formed after further removing a portion of the initial gate adhesion layer 210 ′, a portion of the initial gate metal layer 220 ′ and a portion of the initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig. 12C It is a cross-sectional schematic diagram of a structure formed after further removing a portion of the initial gate adhesion layer 210 ′, a portion of the initial gate metal layer 220 ′ and a portion of the initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig.13A It is a schematic top view of a structure formed after forming an isolation initial gate adhesion layer 210 ′, an initial gate metal layer 220 ′ and an initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig. 13B It is a cross-sectional schematic diagram of a structure formed after forming an isolation initial gate adhesion layer 210 ′, an initial gate metal layer 220 ′ and an initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig. 13C It is a cross-sectional schematic diagram of a structure formed after forming an isolation initial gate adhesion layer 210 ′, an initial gate metal layer 220 ′ and an initial back gate conductive layer 310 ′ according to a preparation method in one embodiment of the present application. Fig.14A It is a schematic top view of a structure formed after forming an initial bit line structure 400 ′ according to a manufacturing method in one embodiment of the present application. Fig. 14B It is a schematic cross-sectional view of a structure formed after forming an initial bit line structure 400 ′ according to a manufacturing method in one embodiment of the present application. Fig. 14CIt is a schematic cross-sectional view of a structure formed after forming an initial bit line structure 400 ′ according to a manufacturing method in one embodiment of the present application. Fig.15A It is a schematic top view of a structure formed after forming a gate structure 200 and a back gate structure 300 according to a preparation method in one embodiment of the present application. Fig. 15B It is a bottom view schematic diagram of a structure formed after a bit line structure 400 is formed on the back side of an intermediate body according to a manufacturing method in one embodiment of the present application.

[0189] like Figures 11A-13C As shown, step S4 forms a sealing layer, wherein the sealing layer covers the groove formed by the removal process from the second side, which may for example include: forming an initial sealing layer 106' from the second side 11, the initial sealing layer 106' at least covering the groove formed after continuing to remove a portion of the initial gate conductive layer and the groove formed after continuing to remove a portion of the initial back gate conductive layer 310'; and removing a portion of the initial sealing layer 106' to form a sealing layer 106.

[0190] like Figures 11A-12C As shown, in one embodiment of the present application, the initial sealing layer 106 is formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The initial sealing layer 106 may fill the first groove 01, the second groove 02, the third groove 03 and the fourth groove 04, and cover the first end 110 of the semiconductor pillar 100.

[0191] Alternatively, the initial sealing layer 106 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0192] Afterwards, if Figures 12A-13C As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the initial sealing layer 106 to form a sealing layer 106'.

[0193] Optionally, in the process of forming the sealing layer 106', a portion of the isolation layer 102 is removed to form a spacer layer 102' spaced apart from the semiconductor pillar 100 in the second direction. Optionally, the sealing layer 106', the spacer layer 102' and the first end 110 of the semiconductor pillar 100 are flush in the z direction.

[0194] In addition, if Figure 1-Figure 3 as well as Figures 13A-15BAs shown, in one embodiment of the present application, after forming the gate structure 200 and the back gate structure 300, the method 2000 for preparing a semiconductor device further includes: from the second side 11, forming an initial bit line structure 400' that at least covers the gate structure 200 and the back gate structure 300; removing part of the initial bit line structure 400' to form a bit line structure 400 and openings 05 alternately arranged with the bit line structure 400 in the y direction, wherein the bit line structure 400 extends along the x direction and connects the first end portions 110 of a plurality of semiconductor pillars 100; and forming a bit line isolation structure 500 in the opening 05, wherein the bit line isolation structure 500 includes an isolation dielectric layer 510 and an air gap layer 520 surrounded by the isolation dielectric layer 510.

[0195] Alternatively, if Figures 13A-14C As shown, an initial bit line structure 400' is formed on the surface of the sealing layer 106', the spacer layer 102' and the first end 110 of the semiconductor pillar 100 flush in the z direction by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The initial bit line structure 400' may be a composite structure, for example, including a first initial bit line layer 400'-1 and a second initial bit line layer 400'-2 stacked in sequence in the z direction. Optionally, the first initial bit line layer 400'-1 may include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The second initial bit line layer 400'-2 may include but is not limited to silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI) or any other appropriate semiconductor material. Optionally, the second initial bit line layer 400'-2 is located above the first initial bit line layer 400'-1 and contacts the first end portions 110 of the plurality of semiconductor pillars 100. In addition, when the material of the second initial bit line layer 400'-2 is the same as that of the semiconductor pillars 100, there is no obvious boundary between the second initial bit line layer 400'-2 and the first end portions 110 of the semiconductor pillars 100.

[0196] like Figure 14A-Figure 15B As shown, after the initial bit line structure 400' is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the initial bit line structure 400' to form the bit line structure 400 and the openings 05 alternately arranged with the bit line structure 400 in the y direction. Fig.15A and Fig. 15B As shown, the opening 05 is opposite to the spacer layer 102 ′ in the xy plane.

[0197] Afterwards, if Figure 1-Figure 3 as well as Figure 14A-Figure 15B As shown, a bit line isolation structure 500 is formed in the opening 05 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The bit line isolation structure 500 may include an isolation dielectric layer 510 and an air gap layer 520 surrounded by the isolation dielectric layer 510. The air gap layer 520 surrounded by the isolation dielectric layer 510 can reduce interference between adjacent gate structures 200 in the finally formed semiconductor device.

[0198] In addition, optionally, a covering dielectric layer 600 covering the bit line structure 400 and the bit line isolation structure 500 may be formed from the second side 11 by one or more thin film deposition processes. The covering dielectric layer 600 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the covering dielectric layer 600 may include silicon oxide.

[0199] The following will be combined Figures 16A-24B The specific process of each step of the above-mentioned preparation method 2000 in Example 2 is described in detail.

[0200] Example 2

[0201] Since the contents involved in the method 2000 for preparing a semiconductor device described in the above embodiment 1 can be fully or partially applied to the method for preparing a semiconductor device described here (embodiment 2), the contents related or similar thereto are not described in detail. However, it can be understood by those skilled in the art that the semiconductor device 1000 (such as the semiconductor device 1000) can be formed according to the method 2000 for preparing a semiconductor device described in embodiment 1. Figure 1-Figure 4 As shown in FIG. 1 , the semiconductor device 1000 can also be formed according to the method 2000 for preparing a semiconductor device described in Embodiment 2. Based on this, the method 2000 for preparing a semiconductor device described in Embodiments 1 and 2 has the same beneficial effects as the semiconductor structure 1000, and will not be described in detail here.

[0202] Step S1

[0203] Fig.16A It is a schematic top view of a structure formed after forming a basic structure 101 according to a preparation method in another embodiment of the present application. Fig. 16B It is a schematic top view of a structure formed after forming the first groove 104 and the second groove 105 according to a preparation method in another embodiment of the present application. Fig. 16C for Fig. 16BThe intermediate body is shown in a schematic cross-sectional view taken along line AA'.

[0204] like Figure 5 , FIG. 16A to FIG. 16C As shown, step S1 of forming an initial semiconductor column extending along the second direction on the first side of the substrate may, for example, include: forming a base structure 101 on the first side 12, wherein the base structure 101 includes a semiconductor layer 103 and an isolation layer 102 alternately distributed in the y direction, and the y direction intersects with the z direction and the x direction; forming a first trench 104 and a second trench 105 extending in the base structure 101 along the z direction respectively from the first side 12, wherein a plurality of first trenches 104 and a plurality of second trenches 105 are alternately distributed in the x direction to divide the semiconductor layer 103 into a plurality of initial semiconductor columns 100'.

[0205] Step S2

[0206] Fig.17A It is a schematic top view of a structure formed after forming an initial gate structure 200 ′ and an initial back gate structure 300 ′ according to a manufacturing method in another embodiment of the present application. Fig. 17B yes Fig.17A The intermediate body is shown in a schematic cross-sectional view taken along line AA'. Fig. 17C yes Fig.17A The intermediate body is shown in a schematic cross-sectional view taken along line BB'.

[0207] like Figure 5 , Figure 17A-Figure 17C As shown, step S2 forms an initial gate structure and an initial back gate structure on two opposite sides of the initial semiconductor column in a first direction, respectively, wherein the first direction and the second direction intersect each other and may, for example, include: forming an initial gate structure 200' on a first side wall 120' of the initial semiconductor column 100' in the x-direction; and forming an initial back gate structure 300' on a second side wall 130' of the initial semiconductor column 100' in the x-direction.

[0208] Step S3

[0209] Fig.18A It is a schematic top view of a structure formed after removing part of the basic structure 101 according to a preparation method in another embodiment of the present application. Fig.18B It is a schematic cross-sectional view of a structure formed after removing part of the basic structure 101 according to a preparation method in another embodiment of the present application. Fig. 18C It is a schematic cross-sectional view of a structure formed after removing part of the basic structure 101 according to a preparation method in another embodiment of the present application. Fig.19AIt is a schematic top view of a structure formed after the initial gate adhesion layer 210 ′ and the initial back gate conductive layer 310 ′ are exposed according to a preparation method in another embodiment of the present application. Fig.19B It is a schematic cross-sectional view of a structure formed after the initial gate adhesion layer 210 ′ and the initial back gate conductive layer 310 ′ are exposed according to a preparation method in another embodiment of the present application. Fig.19C It is a schematic cross-sectional view of a structure formed after the initial gate adhesion layer 210 ′ and the initial back gate conductive layer 310 ′ are exposed according to a preparation method in another embodiment of the present application. Fig. 20A It is a schematic top view of a structure formed after forming a gate adhesion layer 210, a gate metal layer 220 and a back gate conductive layer 310 according to a preparation method in another embodiment of the present application. Fig. 20B It is a schematic cross-sectional view of a structure formed after forming a gate adhesion layer 210 , a gate metal layer 220 and a back gate conductive layer 310 according to a preparation method in another embodiment of the present application. Fig. 20C It is a schematic cross-sectional view of a structure formed after forming a gate adhesion layer 210 , a gate metal layer 220 and a back gate conductive layer 310 according to a preparation method in another embodiment of the present application.

[0210] like Figure 5 , Figures 17A-20C As shown, step S3 removes part of the initial gate structure and part of the initial back gate structure from the second side opposite to the first side to form the gate structure and the back gate structure, which may for example include: removing part of the initial semiconductor pillar 100' from the second side 11 to expose part of the initial gate dielectric 230' and part of the initial back gate dielectric layer 320'; removing the exposed part of the initial gate dielectric layer 230' and part of the initial back gate dielectric layer 230', part of the initial gate adhesion layer 210' and part of the initial gate metal layer 220' corresponding to the exposed part of the initial gate dielectric layer 230', and part of the initial back gate conductive layer 310' corresponding to the exposed part of the initial back gate dielectric layer 320'; and continuing to remove part of the initial gate adhesion layer 210', part of the initial gate metal layer 220' and part of the initial back gate conductive layer 310' from the second side.

[0211] Specifically, Figures 17A-18C As shown, in one embodiment of the present application, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove part of the substrate from the second side 11, for example, at least remove the substrate 101' located under the isolation layer 102, and thin the substrate located under the initial semiconductor column 100'.

[0212] Afterwards, if Figures 18A-19CAs shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to continue to remove a portion of the initial semiconductor column 100' from the second side 11 to expose a portion of the initial gate dielectric 230' and a portion of the initial back gate dielectric layer 320' and form the semiconductor column 100.

[0213] Afterwards, the formation can continue through, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to remove the exposed portion of the initial gate dielectric 230' and the portion of the initial back gate dielectric layer 320' to expose the initial gate adhesion layer 210' (it can be understood that a portion of the initial gate conductive layer is exposed) and the initial back gate conductive layer 310'.

[0214] Optionally, the exposed portion of the initial gate dielectric 230' and the portion of the initial back gate dielectric layer 320' are removed, and the formed first initial gate dielectric 230'-1 and the first initial back gate dielectric layer 320'-1 have flush surfaces in the z direction. For example, the first initial gate dielectric 230'-1 and the first initial back gate dielectric layer 320'-1 are flush with the first end 100 of the semiconductor pillar 100 in the z direction.

[0215] like Figures 19A-20C As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to remove the exposed portion of the initial gate adhesion layer 210' and the portion of the initial gate metal layer 220', as well as the exposed portion of the initial back gate conductive layer 310' from the second side 11, thereby forming a gate dielectric layer 230, a gate adhesion layer 210 and a gate metal layer 220 having a flush surface in the z direction; and a back gate dielectric layer 320 and a back gate conductive layer 310 having a flush surface in the z direction.

[0216] Optionally, in order to reduce the process difficulty, simplify the process steps and reduce the preparation cost, a dry etching process can be used to remove the exposed portion of the initial gate dielectric layer 230' and the portion of the initial back gate dielectric layer 230', the portion of the initial gate adhesion layer 210' and the portion of the initial gate metal layer 220' corresponding to the exposed portion of the initial gate dielectric layer 230', and the portion of the initial back gate conductive layer 310' corresponding to the exposed portion of the initial back gate dielectric layer 320' from the second side 11 in the same process.

[0217] Afterwards, in order to reduce the process difficulty, simplify the process steps and reduce the preparation cost, a wet etching process can be used to continue to remove part of the initial gate adhesion layer 210', part of the initial gate metal layer 220' and part of the initial back gate conductive layer 310' from the second side 11 in the same process to form a gate structure 200 and a back gate structure 300, wherein the gate structure 200 includes a gate dielectric layer 230, a gate adhesion layer 210 and a gate metal layer 220, and the back gate structure 300 includes a back gate dielectric layer 320 and a back gate conductive layer 310.

[0218] It should be noted that in the above process, the initial gate structure 200 ′ and the back gate structure 300 ′ located in the isolation layer 102 are processed together with the initial gate structure 200 ′ and the back gate structure 300 ′ located between the plurality of semiconductor pillars 100 (or the initial semiconductor pillars 100 ′).

[0219] Through the above treatment, the gate dielectric layer 230, the gate adhesive layer 210 and the gate metal layer 220, the back gate dielectric layer 320 and the back gate conductive layer 310 may have a flush surface in the z direction. As an option, the flush surface may be flush with the surface of the first end portion 110 of the semiconductor pillar 100. In other words, the plurality of gate adhesive layers 210, the plurality of gate metal layers 220 and the plurality of back gate conductive layers 310 may all have a flush surface in the z direction, thereby improving the structural consistency of the memory cell in the semiconductor device, which is beneficial to improving the influence of the structural difference on the performance of the semiconductor device.

[0220] Step S4

[0221] Fig.21A It is a schematic top view of a structure formed after forming an initial sealing layer 106 according to a preparation method in another embodiment of the present application. Fig. 21B It is a schematic cross-sectional view of a structure formed after forming an initial sealing layer 106 according to a preparation method in another embodiment of the present application. Fig. 21C It is a schematic cross-sectional view of a structure formed after forming an initial sealing layer 106 according to a preparation method in another embodiment of the present application. Fig.22A It is a schematic top view of a structure formed after forming a sealing layer 106 ′ according to a preparation method in another embodiment of the present application. Fig. 22B It is a schematic cross-sectional view of a structure formed after forming a sealing layer 106 ′ according to a preparation method in another embodiment of the present application. Fig. 22C It is a schematic cross-sectional view of a structure formed after forming a sealing layer 106 ′ according to a preparation method in another embodiment of the present application. Fig.23A FIG. 4 is a schematic top view of a structure formed after forming an initial bit line structure 400 ′ according to a manufacturing method in another embodiment of the present application. Fig. 23BFIG. 4 is a schematic cross-sectional view of a structure formed after forming an initial bit line structure 400 ′ according to a manufacturing method in another embodiment of the present application. Fig.24A It is a schematic top view of a structure formed after forming a gate structure 200 and a back gate structure 300 according to a preparation method in another embodiment of the present application. Fig. 24B It is a bottom view schematic diagram of a structure formed after a bit line structure 400 is formed on the back side of an intermediate body according to a manufacturing method in another embodiment of the present application.

[0222] like Figures 20A-21C As shown, in one embodiment of the present application, the initial sealing layer 106 is formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The initial sealing layer 106 covers the first end 110 of the semiconductor pillar 100, the gate adhesion layer 210, the gate metal layer 220, and the exposed surface of the back gate conductive layer 310 from the second side 11.

[0223] Alternatively, the initial sealing layer 106 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0224] Combination Figures 11A-11C as well as Figure 20A-20C It should be noted that in Embodiment 1 and Embodiment 2, the groove formed after continuing to remove a portion of the initial gate conductive layer and the groove formed after continuing to remove a portion of the initial back gate conductive layer 310' are not the same.

[0225] In Embodiment 1, the initial sealing layer 106 may fill the first groove 01 , the second groove 02 , the third groove 03 , and the fourth groove 04 , and cover the first end portion 110 of the semiconductor pillar 100 . Among them, part of the initial back gate conductive layer 310' between adjacent semiconductor pillars 100 is continuously removed from the second side 11 to form a first groove 01 and a back gate conductive layer 310; part of the initial gate adhesion layer 210' and part of the initial gate metal layer 220' (which can be understood as part of the initial gate conductive layer) between adjacent semiconductor pillars 100 are continuously removed from the second side 11 to form a second groove 02 and a gate adhesion layer 210 and a gate metal layer 220 (which can be understood as forming a second groove 02 and a gate conductive layer); part of the initial back gate conductive layer 310' in the isolation layer 102 is continuously removed from the second side 11 to form a third groove 03 and a back gate conductive layer 310; part of the initial gate adhesion layer 210' and part of the initial gate metal layer 220' in the isolation layer 102 are continuously removed from the second side 11 to form a fourth groove 04 and a gate adhesion layer 210 and a gate metal layer 220.

[0226] In Embodiment 2, the initial sealing layer 106 may fill the first groove 01 and the second groove 02, and cover the first end 110 of the semiconductor pillar 100. The first groove 01 and the back-gate conductive layer 310 may be formed by continuing to remove a portion of the initial back-gate conductive layer 310' between adjacent semiconductor pillars 100 from the second side 11; or the first groove 01 and the back-gate conductive layer 310 may be formed by continuing to remove a portion of the initial back-gate conductive layer 310' in the isolation layer 102 from the second side 11.

[0227] Continuing to remove part of the initial gate adhesion layer 210' and part of the initial gate metal layer 220' (which can be understood as part of the initial gate conductive layer) between adjacent semiconductor pillars 100 from the second side 11, a second groove 02 and the gate adhesion layer 210 and the gate metal layer 220 (which can be understood as the formation of the second groove 02 and the gate conductive layer) can be formed; or, continuing to remove part of the initial gate adhesion layer 210' and part of the initial gate metal layer 220' in the isolation layer 102 from the second side 11, a second groove 02 and the gate adhesion layer 210 and the gate metal layer 220 can be formed.

[0228] Afterwards, if Figure 21A-Figure 22C As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the initial sealing layer 106 to form a sealing layer 106'.

[0229] Optionally, in the process of forming the sealing layer 106', a portion of the isolation layer 102 is removed to form a spacer layer 102' spaced apart from the semiconductor pillar 100 in the second direction. Optionally, the sealing layer 106', the spacer layer 102' and the first end 110 of the semiconductor pillar 100 are flush in the z direction.

[0230] In addition, if Figure 1-Figure 3 as well as Figure 22A-Figure 24B As shown, in one embodiment of the present application, after forming the gate structure 200 and the back gate structure 300, the method 2000 for preparing a semiconductor device further includes: from the second side 11, forming an initial bit line structure 400' that at least covers the gate structure 200 and the back gate structure 300; removing part of the initial bit line structure 400' to form a bit line structure 400 and openings 05 alternately arranged with the bit line structure 400 in the y direction, wherein the bit line structure 400 extends along the x direction and connects the first end portions 110 of a plurality of semiconductor pillars 100; and forming a bit line isolation structure 500 in the opening 05, wherein the bit line isolation structure 500 includes an isolation dielectric layer 510 and an air gap layer 520 surrounded by the isolation dielectric layer 510.

[0231] Alternatively, if Figure 22A-Figure 23CAs shown, an initial bit line structure 400' is formed on the surface of the sealing layer 106', the spacer layer 102' and the first end 110 of the semiconductor pillar 100 flush in the z direction by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The initial bit line structure 400' may be a composite structure, for example, including a first initial bit line layer 400'-1 and a second initial bit line layer 400'-2 stacked in sequence in the z direction. Optionally, the first initial bit line layer 400'-1 may include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicide, etc. The second initial bit line layer 400'-2 may include but is not limited to silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI) or any other appropriate semiconductor material. Optionally, the second initial bit line layer 400'-2 is located above the first initial bit line layer 400'-1 and contacts the first end portions 110 of the plurality of semiconductor pillars 100. In addition, when the material of the second initial bit line layer 400'-2 is the same as that of the semiconductor pillars 100, there is no obvious boundary between the second initial bit line layer 400'-2 and the first end portions 110 of the semiconductor pillars 100.

[0232] like Figure 23A-Figure 24B As shown, after the initial bit line structure 400' is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed to remove part of the initial bit line structure 400' to form the bit line structure 400 and the openings 05 alternately arranged with the bit line structure 400 in the y direction. Fig.24A and Fig. 24B As shown, the opening 05 is opposite to the spacer layer 102 ′ in the xy plane.

[0233] Afterwards, if Figure 1-Figure 3 as well as Figure 23A-Figure 24B As shown, a bit line isolation structure 500 is formed in the opening 05 by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The bit line isolation structure 500 may include an isolation dielectric layer 510 and an air gap layer 520 surrounded by the isolation dielectric layer 510. The air gap layer 520 surrounded by the isolation dielectric layer 510 can reduce interference between adjacent gate structures 200 in the finally formed semiconductor device.

[0234] In addition, optionally, a covering dielectric layer 600 covering the bit line structure 400 and the bit line isolation structure 500 may be formed from the second side 11 by one or more thin film deposition processes. The covering dielectric layer 600 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the covering dielectric layer 600 may include silicon oxide.

[0235] in addition, Fig.25 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0236] like Fig.25 As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following will be described by taking a three-dimensional semiconductor device as an example.

[0237] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0238] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0239] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0240] Although an exemplary method and structure of manufacturing a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of each layer exemplified are merely exemplary.

[0241] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

[0242] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor column, a gate structure and a back-gate structure are arranged in an array, wherein the gate structure and the back-gate structure are respectively located on two opposite sides of the semiconductor column along a first direction, Wherein, the gate structure comprises an upper surface and a lower surface opposite to each other in a second direction, wherein the first direction intersects with the second direction, and the second direction is an extension direction of the semiconductor column; The back gate structure includes a top surface and a bottom surface opposite to each other in the second direction; and The lower surface is flush with the bottom surface in the second direction.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes at least one storage plane region formed with the semiconductor pillar, the storage plane region includes a first area located at an edge of the storage plane region and a second area different from the first area, Wherein, lower surfaces of the plurality of gate structures located in the second region are flush with each other in the second direction.

3. The semiconductor device according to claim 1, wherein The semiconductor device includes at least one storage plane region formed with the semiconductor pillar, the storage plane region includes a first area located at an edge of the storage plane region and a second area different from the first area, Wherein, the bottom surfaces of the plurality of back gate structures located in the second region are flush with each other in the second direction.

4. The semiconductor device according to claim 1, wherein: In the second direction, the upper surface of the gate structure and the top surface of the back gate structure are located at different heights, respectively.

5. The semiconductor device according to claim 1, wherein The back gate structure includes a back gate conductive layer.

6. The semiconductor device according to claim 5, wherein: The gate structure includes a gate adhesion layer and a gate metal layer, wherein the gate adhesion layer is located between the first sidewall of the semiconductor pillar and the gate metal layer.

7. The semiconductor device according to claim 6, wherein: The gate adhesive layer and the back gate conductive layer include conductive material layers of the same material.

8. The semiconductor device according to any one of claims 1 to 7, wherein: Along the second direction, the gate structure includes an upper end and a lower end opposite to each other, Wherein, the thickness of each part of the lower end in the first direction is consistent.

9. The semiconductor device according to any one of claims 1 to 7, wherein: The cross-sectional shape of the gate structure in a plane parallel to a plane formed by the first direction and the second direction is a rectangle; and / or The cross-sectional shape of the back gate structure in the plane is a rectangle.

10. The semiconductor device according to any one of claims 1 to 7, wherein: The gate structure includes a gate dielectric layer located on a first sidewall of the semiconductor pillar; and The back gate structure comprises a back gate dielectric layer located on the second side wall of the semiconductor column. The first side wall and the second side wall are opposite to each other in the first direction.

11. The semiconductor device according to claim 10, wherein: The gate dielectric layer and the back gate dielectric layer include insulating material layers made of the same material.

12. The semiconductor device according to claim 1, wherein The semiconductor device further includes a bit line structure and a bit line isolation structure. Wherein, the bit line structure extends in the first direction and contacts the plurality of semiconductor pillars; and The bit line structures and the bit line isolation structures are alternately arranged in a third direction, wherein the first direction, the second direction and the third direction intersect each other.

13. The semiconductor device according to claim 12, wherein: The bit line isolation structure includes an isolation dielectric layer and an air gap layer surrounded by the isolation dielectric layer.

14. A method for preparing a semiconductor device, characterized in that: include: forming an initial semiconductor column extending along a second direction on the first side of the substrate; forming an initial gate structure and an initial back gate structure respectively on two opposite sides of the initial semiconductor column in a first direction, wherein the first direction and the second direction intersect each other; removing a portion of the initial gate structure and a portion of the initial back gate structure from a second side opposite to the first side to form a gate structure and a back gate structure; as well as A sealing layer is formed, wherein the sealing layer covers the groove formed by the removal process from the second side.

15. The method according to claim 14, wherein: The gate structure comprises an upper surface and a lower surface opposite to each other in the second direction, wherein the lower surface is closer to the substrate than the upper surface; The back gate structure includes a top surface and a bottom surface opposite to each other in the second direction, the bottom surface being closer to the substrate than the top surface; and The lower surface is flush with the bottom surface in the second direction.

16. The method according to claim 14, wherein: The substrate includes a plurality of semiconductor layers arranged at intervals in a third direction, the third direction intersecting the first direction and the second direction, and forming the initial semiconductor pillars includes forming a first trench and a second trench extending in the substrate along the second direction from the first side, wherein a plurality of the first trenches and a plurality of the second trenches are alternately distributed in the first direction to divide the semiconductor layer into a plurality of the initial semiconductor pillars, Wherein, the plurality of first grooves have different depths along the second direction.

17. The method according to claim 14 or 16, wherein: The substrate includes a plurality of semiconductor layers arranged at intervals in a third direction, the third direction intersecting the first direction and the second direction, and forming the initial semiconductor pillars includes forming a first trench and a second trench extending in the substrate along the second direction from the first side, wherein a plurality of the first trenches and a plurality of the second trenches are alternately distributed in the first direction to divide the semiconductor layer into a plurality of the initial semiconductor pillars, Wherein, a plurality of the second grooves have different depths along the second direction.

18. The method according to claim 14, wherein: The method further includes forming a semiconductor pillar, wherein forming a plurality of the semiconductor pillars includes: Before removing a portion of the initial gate structure and a portion of the initial back gate structure, a portion of the initial semiconductor column is removed from the second side to form the semiconductor column.

19. The method according to claim 16, wherein: forming the initial gate structure comprises forming the initial gate structure in the first trench, Wherein, an initial gate dielectric layer is formed on the sidewall and bottom of the first trench; and An initial gate adhesion layer and an initial gate metal layer are sequentially formed on the surface of the initial gate dielectric layer.

20. The method according to claim 19, wherein: Forming the initial back gate structure includes forming the initial back gate structure in the second trench, Wherein, an initial back gate dielectric layer is formed on the sidewall and bottom of the second trench; and The remaining space of the second trench is filled with an initial back gate conductive layer.

21. The method according to claim 14, wherein: The initial gate structure includes an initial gate dielectric layer and an initial gate conductive layer, the initial back gate structure includes an initial back gate dielectric layer and an initial back gate conductive layer, and removing part of the initial gate structure and part of the initial back gate structure from a second side opposite to the first side comprises: A portion of the initial semiconductor column is removed from the second side to expose a portion of the initial gate dielectric layer and a portion of the initial back gate dielectric layer.

22. The method according to claim 21, wherein: After exposing a portion of the initial gate dielectric layer and a portion of the initial back gate dielectric layer, the method further includes: removing the exposed portion of the initial gate dielectric layer and the initial back gate dielectric layer, the portion of the initial gate conductive layer corresponding to the exposed portion of the initial gate dielectric layer, and the portion of the initial back gate conductive layer corresponding to the exposed portion of the initial back gate dielectric layer; and A portion of the initial gate conductive layer and a portion of the initial back gate conductive layer are continuously removed from the second side.

23. The method according to claim 22, wherein: Forming a sealing layer, wherein the sealing layer covers the groove formed by the removal process from the second side comprises: forming an initial sealing layer from the second side, the initial sealing layer at least covering the groove formed after continuing to remove a portion of the initial gate conductive layer and the groove formed after continuing to remove a portion of the initial back gate conductive layer; and A portion of the initial sealing layer is removed to form the sealing layer.

24. The method according to claim 14, wherein: After forming the gate structure and the back gate structure, the method further includes: From the second side, forming an initial bit line structure covering at least the gate structure and the back gate structure; Removing a portion of the initial bit line structure to form a bit line structure and openings alternately arranged with the bit line structure in a third direction, wherein the bit line structure extends along the first direction and connects the first ends of the plurality of semiconductor pillars, and the third direction intersects the first direction and the second direction; and forming a bit line isolation structure in the opening, The bit line isolation structure includes an isolation dielectric layer and an air gap layer surrounded by the isolation dielectric layer.

25. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 13; as well as The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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