Semiconductor structure and method of manufacturing the same

Abstract

The present application relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and a word line structure. The substrate includes an array region and a peripheral region surrounding the array region. The substrate includes at least one active region isolated by a shallow trench isolation structure. The word line structure extends through the shallow trench isolation structure and the active region in a first direction, and a plurality of the word line structures extend in the first direction and are arranged in a second direction. The word line structure includes a first word line layer, a first metal oxide layer, and a second metal oxide layer. The first word line layer includes a first portion and a second portion, the first portion is located on the array region, and the second portion is located on the peripheral region, wherein a top surface of the second portion is lower than a top surface of the first portion in a direction perpendicular to the substrate. The first metal oxide layer is located on the first portion. The second metal oxide layer is located on the second portion, and a thickness of the second metal oxide layer is greater than a thickness of the first metal oxide layer. The present application can effectively improve the performance of a memory device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] A memory device typically includes an array region and a peripheral region surrounding the array region. The array region can form a memory array. The peripheral region can also contain contact plugs, which connect wordline structures to upper-layer logic circuits in the peripheral region, providing signals to the memory array.

[0003] However, the performance of existing memory devices needs to be further improved. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor structure and a preparation method thereof that can improve the performance of a memory device.

[0005] A semiconductor structure comprising:

[0006] A substrate comprising an array region and a peripheral region surrounding the array region, wherein the substrate comprises at least one active region isolated by a shallow trench isolation structure;

[0007] a word line structure passing through the shallow trench isolation structure and the active area along a first direction, wherein a plurality of the word line structures extend along the first direction and are arranged along a second direction, wherein the second direction intersects the first direction;

[0008] Furthermore, the word line structure includes:

[0009] a first word line layer comprising a first portion and a second portion, wherein the first portion is located on the array region; the second portion is located on the peripheral region, wherein an upper surface of the second portion is lower than an upper surface of the first portion in a direction perpendicular to the substrate;

[0010] a first metal oxide layer located on the first portion;

[0011] The second metal oxide layer is located on the second portion, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

[0012] In one embodiment, on a side away from the substrate, an upper surface of the second metal oxide layer is lower than an upper surface of the first portion;

[0013] The first metal oxide layer extends from the upper surface of the first portion to the sidewall of the first portion.

[0014] In one embodiment, the thickness of the second metal oxide layer gradually increases from away from the array region to closer to the array region.

[0015] In one embodiment, the word line structure further includes:

[0016] The second word line layer is located on the first metal oxide layer.

[0017] In one embodiment, the thickness of the second word line layer gradually increases from close to the peripheral region to away from the peripheral region.

[0018] In one embodiment, the semiconductor structure further comprises:

[0019] a word line trench located in the substrate and passing through the shallow trench isolation structure and the active area along a first direction, wherein a plurality of the word line trenches are spaced apart and arranged along a second direction;

[0020] a gate dielectric layer, located on the sidewalls and bottom of the word line trench; the word line structure is located on the surface of the gate dielectric layer and partially fills the word line trench;

[0021] A filling dielectric layer is provided to fill the remaining space of the word line trench.

[0022] A method for preparing a semiconductor structure comprises the following steps:

[0023] providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region;

[0024] forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates the substrate into at least one active area;

[0025] forming a plurality of word line trenches in the substrate, the word line trenches extending from the array region to the peripheral region and passing through the shallow trench isolation structure and the active region along a first direction, the plurality of word line trenches extending along the first direction and arranged along a second direction, the second direction intersecting the first direction;

[0026] forming a word line structure in the word line trench;

[0027] The word line structure includes a first word line layer, a second metal oxide layer and a first metal oxide layer; the first word line layer includes a first portion and a second portion, the first portion is located on the array area; the second portion is located on the peripheral area, wherein the upper surface of the second portion is lower than the upper surface of the first portion in a direction perpendicular to the substrate; the first metal oxide layer is located on the first portion; the second metal oxide layer is located on the second portion, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

[0028] In one embodiment, before forming a plurality of word line trenches in the substrate, the method includes:

[0029] forming a mask layer covering the shallow trench isolation structure and the active area on the substrate;

[0030] The step of forming a plurality of word line trenches in the substrate comprises:

[0031] etching the substrate based on the mask layer to form the word line trench;

[0032] Before forming a word line structure in the word line trench, the method includes:

[0033] A gate dielectric layer is formed on the sidewalls and bottom of the word line trench.

[0034] In one embodiment, forming a word line structure in the word line trench includes:

[0035] forming the first word line layer on the surface of the gate dielectric layer;

[0036] forming a first metal oxide material layer and a second word line material layer in sequence on the first word line layer;

[0037] Sequentially etching and removing the second word line material layer and the first metal oxide material layer located in the peripheral area to form the second word line layer and the first metal oxide layer in the array area;

[0038] The second metal oxide layer is formed on the first word line layer in the peripheral region.

[0039] In one embodiment, after forming the word line structure in the word line trench, the method further includes:

[0040] forming a filling dielectric layer in the remaining space of the word line trench;

[0041] A plurality of bit line structures are formed on the filling dielectric layer. The plurality of bit line structures extend along the second direction and are arranged along the first direction.

[0042] In the aforementioned semiconductor structure and fabrication method, the second metal oxide layer is thicker than the first metal oxide layer. Therefore, when etching to form contact holes, the second metal oxide layer effectively protects the first word line layer, preventing etching damage to the first word line layer, thereby effectively improving the reliability of the word line structure.

[0043] At the same time, the upper surface of the second portion of the first word line layer in the peripheral region is set lower than the upper surface of the first portion of the first word line layer in the array region. This not only provides space for the thicker second metal oxide layer, but also increases the distance between the second portion of the first word line layer and the bit line structure above the word line structure. This increases the distance between the upper surface of the second metal oxide layer and the bit line structure, thereby preventing lateral short circuits or leakage between the second metal oxide layer and the bit line structure.

[0044] Therefore, the present application can effectively improve the performance of storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a schematic top view of a partial structure of a semiconductor structure provided in one embodiment;

[0047] Figure 2a The semiconductor structure provided in one embodiment is Figure 1 Schematic diagram of the local structure cross section after the AA direction section;

[0048] Figure 2b In another embodiment, a semiconductor structure is provided along Figure 1 Schematic diagram of the local structure cross section after the AA direction section;

[0049] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0050] Figures 4 to 11 FIG. 1 is a schematic cross-sectional view of a local structure during the preparation process of a semiconductor structure provided in one embodiment, wherein Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 as well as Figure 11 In the figure, (a) is along Figure 1 Schematic diagram of the local structure section after the AA' direction section in (a) is along Figure 1 Schematic diagram of the local structure cross section after the BB' direction section.

[0051] Description of reference numerals:

[0052] 100-base; 110-substrate; 111-active area; 120-shallow trench isolation structure; 200-word line structure; 210-first word line layer; 211-first part; 212-second part; 220-first metal oxide layer; 2201-first metal oxide material layer; 230-second word line layer; 2301-second word line material layer; 240-second metal oxide layer; 300-mask layer; 400-gate dielectric layer; 500-filling dielectric layer; 600-bit line structure; 700-first contact plug; 10-word line trench; A1-array area; A2-peripheral area. DETAILED DESCRIPTION

[0053] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0055] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used solely to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below could be referred to as a second element, component, region, layer, or portion; for example, a first doping type could be referred to as a second doping type without departing from the teachings of the present invention.

[0056] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0057] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] In one embodiment, see Figure 1 as well as Figure 2a (or Figure 2b ), a semiconductor structure is provided, which includes a substrate 110 and a word line structure 200.

[0059] The substrate 110 includes an array region A1 and a peripheral region A2 surrounding the array region A1 .

[0060] The substrate 110 may have a single-layer structure or a multi-layer structure. For example, the substrate may include a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate. Therefore, the type of substrate should not limit the scope of protection of this application.

[0061] The substrate 110 includes at least one active region 111 isolated by a shallow trench isolation structure 120 .

[0062] The shallow trench isolation structure 120 may be located in the substrate and isolate the substrate 110 into a plurality of spaced-apart active regions 111 .

[0063] The word line structure 200 passes through the shallow trench isolation structure 120 and the active area 111 along a first direction.

[0064] The word line structures 200 extend along a first direction and are arranged along a second direction. The first direction intersects the second direction.

[0065] As an example, the first direction and the second direction may both intersect the extension direction of the active layer 111. The same word line structure 200 may pass through multiple active regions 111 along the first direction. Multiple word line structures 200 may pass through the same active region 111.

[0066] The word line structure 200 includes a first word line layer 210 , a first metal oxide layer 220 and a second metal oxide layer 240 .

[0067] The material of the first word line layer 210 may include a metal material or a conductive material such as metallization, such as metal tungsten.

[0068] The first word line layer 210 extends from the array area A1 to the peripheral area A2 and includes a first portion 211 and a second portion 212. The first portion 211 is located on the array area A1, and the second portion 212 is located on the peripheral area A2.

[0069] At the same time, in a direction perpendicular to the substrate, the upper surface of the second portion 212 of the first word line layer 210 is lower than the upper surface of the first portion 211 of the first word line layer 210. That is, the upper surface of the first word line layer 210 in the peripheral area A2 is lower than its upper surface in the array area A1.

[0070] The first metal oxide layer 220 is located on the first portion 211 of the first word line layer 210. The second metal oxide layer 240 is located on the second portion 212 of the first word line layer 210. That is, the first metal oxide layer 220 is located in the array area A1, and the second metal oxide layer 240 is located in the peripheral area A2.

[0071] The material of the first metal oxide layer 220 and the material of the second metal oxide layer 240 can be the same or different, and can be set according to actual needs. As an example, the material of the first metal oxide layer 220 and the material of the second metal oxide layer 240 can both be tungsten oxide.

[0072] The second metal oxide layer 240 and the first metal oxide layer 220 may jointly form a metal diffusion barrier layer, thereby preventing metal diffusion in the first word line layer 310 .

[0073] A first contact plug 700 may be formed on the second metal oxide layer 240. The first contact plug 700 may be used to transmit a signal to the word line structure 200. To form the first contact plug 700, a contact hole may be first formed by etching. Then, a conductive material may be filled into the contact hole to form the first contact plug 700.

[0074] In this embodiment, the thickness of the second metal oxide layer 240 is set to be greater than the thickness of the first metal oxide layer 220. Therefore, when etching to form contact holes, the second metal oxide layer 240 can effectively protect the first word line layer 210 and prevent etching damage to the first word line layer 210, thereby effectively improving the reliability of the word line structure 200.

[0075] At the same time, the upper surface of the second portion 212 of the first word line layer 210 in the peripheral area A2 is set lower than the upper surface of the first portion 211 of the first word line layer 210 in the array area A1. This not only provides space for the thicker second metal oxide layer 240, but also increases the distance between the second portion 212 of the first word line layer 210 and the bit line structure 600 above the word line structure 200. This increases the distance between the upper surface of the second metal oxide layer 240 and the bit line structure 600, thereby preventing lateral short circuits or leakage between the second metal oxide layer 240, the first contact plug 700, and the bit line structure 600.

[0076] In one embodiment, see Figure 2a On the side away from the substrate 110 , the upper surface of the second metal oxide layer 240 is lower than the upper surface of the first portion 211 of the first word line layer 210 .

[0077] At this time, the distance between the upper surface of the second metal oxide layer 240 and the bit line structure 600 is greater, thereby better preventing lateral short circuit or leakage between the second metal oxide layer 240 , the first contact plug 700 and the bit line structure 600 .

[0078] The first metal oxide layer 220 extends from the upper surface of the first portion 211 of the first word line layer 210 to the sidewalls of the first portion 211 .

[0079] It can be understood that the thickness of the first metal oxide layer 220 located on the upper surface of the first portion 211 of the first word line layer 210 and the first metal oxide layer (220) located on the sidewall of the first portion 211 are both less than the thickness of the second metal oxide layer (240).

[0080] By extending the first metal oxide layer 220 to the sidewall of the first portion 211 of the first word line layer 210 , the sidewall of the first word line layer 210 can be well covered by the first metal oxide layer 220 when the upper surface of the second metal oxide layer 240 is low and cannot cover the top of the sidewall of the first portion 211 .

[0081] At this time, the second metal oxide layer 220 can be connected to the first metal oxide layer 220 located on the side wall of the first part 211, so that the second metal oxide layer 240 and the first metal oxide layer 220 can completely cover the various surfaces of the first word line layer 210, thereby effectively preventing the metal in the first word line layer 210 from diffusing.

[0082] Of course, in other embodiments, the upper surface of the second metal oxide layer 240 may also be higher than the upper surface of the first portion 211 of the first word line layer 210 .

[0083] For example, the upper surface of a portion of the second metal oxide layer 240 near the array area A1 may be higher than the upper surface of the first portion 211 of the first word line layer 210, while the upper surface of another portion of the second metal oxide layer 240 away from the array area A1 may be lower than the upper surface of the first portion 211 of the first word line layer 210. Of course, the upper surface of the entire second metal oxide layer 240 may also be higher than the upper surface of the first portion 211 of the first word line layer 210, and this is not limited here.

[0084] In this case, the sidewalls of the first portion 211 can be covered by the second metal oxide layer 240. Furthermore, the first metal oxide layer 220 can be located only on the upper surface of the first portion 211 of the first word line layer 210. Furthermore, the first metal oxide layer 220 is connected to the second metal oxide layer 240, thereby effectively preventing metal diffusion in the first word line layer 210.

[0085] In one embodiment, see Figure 2b The thickness of the second metal oxide layer (240) gradually increases from a direction away from the array region (A1) to a direction close to the array region (A1).

[0086] At this point, on the one hand, the second metal oxide layer 240 is thicker near the sidewalls of the first portion 211 of the first word line layer 210, thereby ensuring effective coverage of the first word line layer 210. On the other hand, the second metal oxide layer 240 is relatively thinner away from the sidewalls of the first portion 211 of the first word line layer 210, thereby preventing the overall height of the second metal oxide layer 240 from being too high, which would increase the risk of short circuits with the bit line structure 700. Furthermore, the gradual thickness of the second metal oxide layer 240 also facilitates processing.

[0087] In one embodiment, see Figure 2a or Figure 2b The word line structure 200 further includes a second word line layer 230. The material of the second word line layer 230 may include but is not limited to polysilicon.

[0088] The second word line layer 230 is located on the first metal oxide layer 220 in the array area A1 , and thus can serve as a component of the gate of the transistor located in the array area A1 .

[0089] The work function of the second word line layer 230 may be different from the work function of the first word line layer 210 , thereby adjusting a threshold voltage of a transistor, etc.

[0090] The first metal oxide layer 220 is located between the second word line layer 230 and the first word line layer 210 , thereby effectively preventing mutual diffusion between the two.

[0091] In one embodiment, the thickness of the second word line layer 230 gradually increases from close to the peripheral area A2 to away from the peripheral area A2.

[0092] The first metal oxide layer 220 and the second metal oxide layer 240 are bonded to each other at or near the boundary between the peripheral area A2 and the array area A1. Therefore, the ability to prevent metal diffusion in the first word line layer 210 is relatively weak at the boundary between the peripheral area A2 and the array area A1.

[0093] Therefore, the thickness of the second word line layer 230 is relatively thin near the peripheral area A2, which can reduce the diffusion risk between the second word line layer 230 and the first word line layer 210. At the same time, the gradual thickness of the second word line layer 230 also facilitates processing.

[0094] In one embodiment, see Figure 11 The semiconductor structure further includes a word line trench 10 , a gate dielectric layer 400 and a filling dielectric layer 500 .

[0095] The word line trench 10 is located in the substrate 110 and passes through the shallow trench isolation structure 120 and the active area 111 along the first direction, thereby extending along the first direction.

[0096] The plurality of word line trenches 10 are arranged at intervals along the second direction. As an example, the plurality of word line trenches 10 can be arranged in parallel and at equal intervals.

[0097] The gate dielectric layer 400 is located on the sidewalls and bottom of the word line trench 10 .

[0098] The gate dielectric layer 400 may be made of a high-k dielectric layer. For example, the gate dielectric layer may be made of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0099] Of course, the material of the gate dielectric layer 400 may also include a low-k dielectric layer. For example, the material of the gate dielectric layer includes a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON).

[0100] The word line structure 200 is located on the surface of the gate dielectric layer 400 .

[0101] The material filling the dielectric layer 500 may include, but is not limited to, a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide (Al 2 O 3 ), or a silicon oxynitride layer (SiON).

[0102] The filling dielectric layer 500 fills the remaining space of the word line trench 10 , thereby insulating and isolating the word line structure 200 .

[0103] In one embodiment, see Figure 3 , provides a method for preparing a semiconductor structure, comprising the following steps:

[0104] Step S10, see Figure 4 , providing a substrate 110, the substrate 110 includes an array area A1 and a peripheral area A2 surrounding the array area A1.

[0105] The substrate 110 may have a single-layer structure or a multi-layer structure. For example, the substrate may include a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate. Therefore, the type of substrate should not limit the scope of protection of this application.

[0106] Step S20, see Figure 4 A shallow trench isolation structure 120 is formed in the substrate 110 , and the shallow trench isolation structure 120 isolates the substrate 110 into at least one active area 111 .

[0107] A shallow trench may be first formed in the substrate 110 , and then a filling insulating material is formed in the shallow trench to form the shallow trench isolation structure 120 .

[0108] The shallow trench isolation structure 120 can isolate the substrate 110 into a plurality of active regions 111 disposed at intervals.

[0109] Step S40, see Figure 4 , a plurality of word line trenches 10 are formed in the substrate 110, the word line trenches 10 extend from the array area A1 to the peripheral area A2, and pass through the shallow trench isolation structure 120 and the active area 111 along the first direction, and the plurality of word line trenches 10 extend along the first direction and are arranged along the second direction.

[0110] The shallow trench isolation structure 120 and the active area 111 may be etched simultaneously, thereby forming a plurality of word line trenches 10 in the substrate 110 after the shallow trench isolation structure 120 is formed.

[0111] The extending direction of the active region 111 may intersect both the first direction and the second direction. The same word line trench 10 may pass through multiple active regions 111 along the first direction. The same active region 111 may be passed through by multiple word line trenches 10.

[0112] It should be noted that, in this article, “plurality” can mean two or more than two.

[0113] It is also understood that the active regions 111 may be unevenly distributed along the first direction, and the active regions and the shallow trench isolation structures 120 may be made of different materials. Therefore, the depths of the word line trenches 10 at different locations along the first direction may be different (see FIG. Figure 4 (a) in the figure).

[0114] Step S60, see Figure 11 A wordline structure 200 is formed in the wordline trench 10. The wordline structure 200 includes a first wordline layer 210, a second metal oxide layer 240, and a first metal oxide layer 220. The first wordline layer 210 includes a first portion 211 and a second portion 212. The first portion 211 is located on the array area A1; the second portion 212 is located on the peripheral area A2, wherein the upper surface of the second portion 212 is lower than the upper surface of the first portion 211 in a direction perpendicular to the substrate. The first metal oxide layer 220 is located on the first portion 211; the second metal oxide layer 240 is located on the second portion 212, and the thickness of the second metal oxide layer 240 is greater than that of the first metal oxide layer 220.

[0115] The material of the first word line layer 210 may include a metal material (such as metal tungsten) or a conductive material such as metallization.

[0116] The second metal oxide layer 240 and the first metal oxide layer 220 may jointly form a metal diffusion barrier layer, thereby preventing metal diffusion in the first word line layer 310 .

[0117] The materials of the second metal oxide layer 240 and the first metal oxide layer 220 may include but are not limited to tungsten oxide.

[0118] See also Figure 2a After step S60, the following steps may also be included:

[0119] A first contact plug 700 extending to the second metal oxide layer 240 is formed.

[0120] Specifically, a contact hole may be formed by an etching process first, and then a conductive material is filled in the contact hole to form the first contact plug 700 .

[0121] In this embodiment, after forming the wordline trenches 10, when forming the wordline structure 200, the thickness of the second metal oxide layer 240 in the peripheral area A2 is greater than the thickness of the first metal oxide layer 220 in the array area A1. Therefore, when etching to form contact holes, the second metal oxide layer 240 can effectively protect the first wordline layer 210, preventing etching damage to the first wordline layer 210, thereby effectively improving the reliability of the wordline structure 200.

[0122] At the same time, when forming the wordline structure 200, the upper surface of the second portion 212 of the first wordline layer 210 in the peripheral area A2 is also lower than the upper surface of the first portion 211 of the first wordline layer 210 in the array area A1. This not only provides space for the thicker second metal oxide layer 240, but also increases the distance between the second portion 212 of the first wordline layer 210 in the peripheral area A2 and the subsequently formed bitline structure 600. This increases the distance between the surface of the second metal oxide layer 240 and the bitline structure 600, thereby preventing lateral short circuits or leakage between the second metal oxide layer 240 and the bitline structure 600.

[0123] In one embodiment, see Figure 4 Before forming a plurality of word line trenches 10 in the substrate 110 , step S40 includes:

[0124] In step S30 , a mask layer 300 is formed on the substrate 110 to cover the shallow trench isolation structure 120 and the active area 111 .

[0125] A mask material layer may be formed first, and then patterned by a photolithography process to form the mask layer 300 .

[0126] Meanwhile, step S40 includes:

[0127] In step S41 , the substrate 110 is etched based on the mask layer 300 to form word line trenches 10 .

[0128] Furthermore, before forming the word line structure 200 in the word line trench 10 , step S60 includes:

[0129] In step S50 , a gate dielectric layer 400 is formed on the sidewalls and bottom of the word line trench 10 .

[0130] As an example, see Figure 5 , a gate dielectric layer 400 may be formed on the upper surface of the mask layer 300 , the sidewalls of the word line trench 10 , and the bottom of the word line trench 10 .

[0131] In one embodiment, step S60 of forming the word line structure 200 in the word line trench 10 includes:

[0132] Step S61, see Figure 6 , a first word line layer 210 is formed on the surface of the gate dielectric layer 400 .

[0133] As an example, a first word line initialization layer with a flat upper surface can be formed on the surface of the gate dielectric layer 400. Then, the first word line initialization layer in the peripheral area A2 can be etched and thinned to form a first word line layer 210 with an upper surface of the second portion 212 lower than that of the first portion 211.

[0134] At the same time, the inclination angle of the sidewall of the first portion 211 can be adjusted by adjusting the etching process conditions.

[0135] As an example, after the first word line layer 210 is formed, the gate dielectric layer 400 located on the upper surface of the mask layer 300 may be removed.

[0136] Step S62, see Figure 7 as well as Figure 8 , a first metal oxide material layer 2201 and a second word line material layer 2301 are sequentially formed on the first word line layer 210 .

[0137] First, a first metal oxide material layer 2201 may be deposited on the surface of the first word line layer 210 , and then a second word line material layer 2301 may be deposited on the surface of the first metal oxide material layer 2201 .

[0138] Step S63, see Figure 9 The second word line material layer 2301 and the first metal oxide material layer 2201 in the peripheral area A2 are sequentially etched away to form a second word line layer 230 and a first metal oxide layer 220 in the array area A1.

[0139] As an example, a second mask layer (not shown in the figure) can be formed on the second word line material layer 2301 in the array area A1, and the second word line material layer 2301 is etched using the first metal oxide material layer 2201 as an etching stop layer to form the second word line layer 230 and the first metal oxide layer 220.

[0140] Step S64, see Figure 10 , a second metal oxide layer 240 is formed on the first word line layer 210 in the peripheral area A2.

[0141] A second metal oxide layer may be formed first and then etched to form a second metal oxide layer 240. The second metal oxide layer 240 may be connected to the first metal oxide layer 220, so that the two can jointly prevent metal diffusion in the first word line layer 210.

[0142] As an example, after etching the first metal oxide layer 2201 in step S63, the first metal oxide layer 2201 located on the sidewalls of the first portion 211 of the first word line layer 210 may remain. That is, the first metal oxide layer 220 formed after etching may extend from the upper surface of the first portion 211 to the sidewalls of the first portion 211.

[0143] At this time, the upper surface of the second metal oxide layer 240 formed in step S64 may be lower than the upper surface of the first portion 211 .

[0144] As another example, after etching the first metal oxide material layer 2201 , the first metal oxide material layer 2201 located on the sidewall of the first portion 211 of the first word line layer 210 may also be etched away, so that the first metal oxide layer 220 is only located on the upper surface of the first portion 211 .

[0145] At this time, the upper surface of the second metal oxide layer 240 formed in step S64 can be higher than the upper surface of the first portion 211 , so that the second metal oxide layer 240 can cover the sidewall of the first portion 211 of the first word line layer 210 and connect to the first metal oxide layer 220 .

[0146] In one embodiment, after forming the word line structure 200 in the word line trench 10 in step S60 , the step further includes:

[0147] Step S70, see Figure 11 , a filling dielectric layer 500 is formed in the remaining space of the word line trench 10 .

[0148] The filling dielectric layer 500 may fill the remaining space of the word line trench 10 .

[0149] Step S80, please refer to Figure 2a or Figure 2b, a plurality of bit line structures 600 are formed on the filling dielectric layer 500 , and the plurality of bit line structures 600 extend along the second direction and are arranged along the first direction.

[0150] The bit line structure 600 may be connected to the active region on one side of the word line structure 200 through a second contact plug (not shown), thereby being connected to the source region or drain region of the transistor, thereby providing a bit line signal for the memory cell.

[0151] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0152] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0153] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising an array region and a peripheral region surrounding the array region, wherein the substrate comprises at least one active region isolated by a shallow trench isolation structure; a word line structure passing through the shallow trench isolation structure and the active area along a first direction, wherein a plurality of the word line structures extend along the first direction and are arranged along a second direction, wherein the second direction intersects the first direction; Furthermore, the word line structure includes: a first word line layer comprising a first portion and a second portion, wherein the first portion is located on the array region; the second portion is located on the peripheral region, wherein an upper surface of the second portion is lower than an upper surface of the first portion in a direction perpendicular to the substrate; a first metal oxide layer located on the first portion; The second metal oxide layer is located on the second portion, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

2. The semiconductor structure according to claim 1, wherein: On a side away from the substrate, an upper surface of the second metal oxide layer is lower than an upper surface of the first portion; The first metal oxide layer extends from the upper surface of the first portion to the sidewall of the first portion.

3. The semiconductor structure according to claim 1, wherein: The thickness of the second metal oxide layer gradually increases from a direction away from the array region to a direction close to the array region.

4. The semiconductor structure according to claim 1, wherein: The word line structure further includes: The second word line layer is located on the first metal oxide layer.

5. The semiconductor structure according to claim 4, wherein: The thickness of the second word line layer gradually increases from close to the peripheral region to away from the peripheral region. The semiconductor structure according to claim 1 , wherein: The semiconductor structure further comprises: a word line trench located in the substrate and passing through the shallow trench isolation structure and the active area along a first direction, wherein a plurality of the word line trenches are spaced apart and arranged along a second direction; a gate dielectric layer, located on the sidewalls and bottom of the word line trench; the word line structure is located on the surface of the gate dielectric layer and partially fills the word line trench; A filling dielectric layer is provided to fill the remaining space of the word line trench.

7. A method for preparing a semiconductor structure, characterized in that: The steps include: providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region; forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates the substrate into at least one active area; forming a plurality of word line trenches in the substrate, the word line trenches extending from the array region to the peripheral region and passing through the shallow trench isolation structure and the active region along a first direction, the plurality of word line trenches extending along the first direction and arranged along a second direction, the second direction intersecting the first direction; forming a word line structure in the word line trench; Wherein, the word line structure includes a first word line layer, a second metal oxide layer and a first metal oxide layer; The first word line layer includes a first portion and a second portion, the first portion is located on the array area; the second portion is located on the peripheral area, wherein the upper surface of the second portion is lower than the upper surface of the first portion in a direction perpendicular to the substrate; the first metal oxide layer is located on the first portion; the second metal oxide layer is located on the second portion, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

8. The method for preparing a semiconductor structure according to claim 7, wherein: Before forming a plurality of word line trenches in the substrate, the method includes: forming a mask layer covering the shallow trench isolation structure and the active area on the substrate; The step of forming a plurality of word line trenches in the substrate comprises: etching the substrate based on the mask layer to form the word line trench; Before forming a word line structure in the word line trench, the method includes: A gate dielectric layer is formed on the sidewalls and bottom of the word line trench.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The forming of the word line structure in the word line trench includes: forming the first word line layer on the surface of the gate dielectric layer; forming a first metal oxide material layer and a second word line material layer in sequence on the first word line layer; Sequentially etching and removing the second word line material layer and the first metal oxide material layer located in the peripheral area to form a second word line layer and the first metal oxide layer in the array area; The second metal oxide layer is formed on the first word line layer in the peripheral region.

10. The method for preparing a semiconductor structure according to claim 8, wherein: After forming the word line structure in the word line trench, the method further includes: forming a filling dielectric layer in the remaining space of the word line trench; A plurality of bit line structures are formed on the filling dielectric layer. The plurality of bit line structures extend along the second direction and are arranged along the first direction.

Images