Semiconductor memory device and manufacturing method thereof

Abstract

The technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first stack structure, a plurality of first slits passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting a top of the first stack structure, a second source line layer directly contacting the first source line layer, and a second source line layer contacting the second source line layer. A second stack structure contacting the second source line layer and overlapping the first stack structure in the vertical direction, and a plurality of second slits penetrating the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0111907, filed on August 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to electronic devices, and more particularly, to semiconductor memory devices having a vertical channel structure and methods of manufacturing the same. Background Art

[0004] Semiconductor memory devices are mainly divided into volatile memory devices and nonvolatile memory devices.

[0005] The writing speed and reading speed of nonvolatile memory devices are relatively slow compared to the writing speed and reading speed of volatile memory devices, however, unlike volatile memory devices, nonvolatile memory devices can maintain stored data even when the power is disconnected. Therefore, nonvolatile memory devices are used to store data to be maintained regardless of the power supply. Examples of nonvolatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is generally classified as NOR or NAND type. Summary of the invention

[0006] One embodiment of the present disclosure provides a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the same.

[0007] According to one embodiment of the present disclosure, a semiconductor memory device includes a first stacking structure, a plurality of first slits passing through the first stacking structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting the top of the first stacking structure, a second source line layer directly contacting the first source line layer, a second stacking structure contacting the second source line layer and overlapping with the first stacking structure in the vertical direction, and a plurality of second slits passing through the second stacking structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.

[0008] According to one embodiment of the present disclosure, a semiconductor memory device includes a first memory chip structure, a second memory chip structure, and a third memory chip structure, the first memory chip structure including a first plane area and a second plane area each including a plurality of first stacked structures, the second memory chip structure being coupled to the top surface of the first memory chip structure in a vertical direction and including a third plane area and a fourth plane area each including a plurality of second stacked structures, the third memory chip structure being coupled to the bottom surface of the first memory chip structure in a vertical direction and including a first page buffer area and a second page buffer area where page buffers for controlling the operation of memory cells included in the first memory chip structure and the second memory chip structure are disposed, and a first row decoder area and a second row decoder area where row decoders for controlling the operation of the memory cells are disposed. The first memory chip structure includes a first slit that passes through the plurality of first stacked structures in a vertical direction and extends in a first horizontal direction orthogonal to the vertical direction, and the second memory chip structure includes a second slit that passes through the plurality of second stacked structures in a vertical direction and extends in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction.

[0009] According to one embodiment of the present disclosure, a semiconductor memory device includes a first memory chip structure, a second memory chip structure, and a third memory chip structure, the first memory chip structure including first to fourth stacking structures arranged in a matrix form, the second memory chip structure being coupled to the top surface of the first memory chip structure in a vertical direction and including fifth to eighth stacking structures arranged in a matrix form, the third memory chip structure being coupled to the bottom surface of the first memory chip structure in a vertical direction and including a first page buffer region and a second page buffer region in which page buffers for controlling the operation of memory cells included in the first memory chip structure and the second memory chip structure are disposed, and a first row decoder region to an eighth row decoder region in which row decoders for controlling the operation of the memory cells are disposed. The first memory chip structure includes a first slit that passes through a plurality of first stacking structures in a vertical direction and extends in a first horizontal direction orthogonal to the vertical direction, and the second memory chip structure includes a second slit that passes through a plurality of second stacking structures in a vertical direction and extends in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction.

[0010] According to one embodiment of the present disclosure, a semiconductor memory device includes a first memory chip structure, a second memory chip structure, and a third memory chip structure, the first memory chip structure including a first plane area and a second plane area each including a plurality of first stacked structures, the second memory chip structure being coupled to the top surface of the first memory chip structure in a vertical direction and including a third plane area and a fourth plane area each including a plurality of second stacked structures, the third memory chip structure being coupled to the bottom surface of the first memory chip structure in a vertical direction and including a first page buffer area to a fourth page buffer area where a page buffer for controlling the operation of memory cells included in the first memory chip structure and the second memory chip structure is disposed, and a first row decoder area to a fourth row decoder area where a row decoder for controlling the operation of the memory cells is disposed. The first memory chip structure includes a first slit that passes through the plurality of first stacked structures in a vertical direction and extends in a first horizontal direction orthogonal to the vertical direction, and the second memory chip structure includes a second slit that passes through the plurality of second stacked structures in a vertical direction and extends in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction.

[0011] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor memory may include forming a first stacking structure, and forming a lower stacking structure through the first stacking structure, including a first interlayer insulating layer and a second word line pattern alternately stacked in a vertical direction, a first cell plug having an end extending upward by passing through the lower stacking structure, a plurality of first slits extending in a first horizontal direction orthogonal to the vertical direction by passing through the lower stacking structure in the vertical direction, and a first source line layer stacked on the lower stacking structure and connected to the end of the first cell plug; and forming a second stacking structure on the first stacking structure, and forming a second source line layer directly contacting the first source line layer, an upper stacking structure including a second interlayer insulating layer and a third word line pattern alternately stacked in the vertical direction, a second cell plug extending downward by passing through the upper stacking structure and having an end contacting the second source line layer, and a plurality of second slits extending in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction by passing through the upper stacking structure in the vertical direction.

[0012] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor memory may include forming a first stacking structure on a first substrate, and forming a lower stacking structure including a first interlayer insulating layer and a second word line pattern alternately stacked in a vertical direction, a first cell plug having an end extending upward by passing through the lower stacking structure, a plurality of first slits extending in a first horizontal direction orthogonal to the vertical direction by passing through the lower stacking structure in the vertical direction, and a first source line layer stacked on the lower stacking structure and connected to the end of the first cell plug, forming a first bonding pad exposed to an upper surface in the first source line layer, forming a second stacking structure on a second substrate, and forming a first interlayer insulating layer and a second word line pattern alternately stacked in a vertical direction through the first stacking structure. A method for forming a first substrate and a second substrate layer comprising a first cell plug and a second cell plug having an upper stack structure including second interlayer insulating layers and third word line patterns alternately stacked in a vertical direction, a second cell plug having an end portion extending upward by passing through the upper stack structure, a plurality of second slits extending in a second horizontal direction orthogonal to the vertical direction and the first horizontal direction by passing through the upper stack structure in the vertical direction, and a second source line layer stacked on the upper stack structure and connected to the end portion of the first cell plug, forming a second bonding pad exposed to an upper surface in the second source line layer, and aligning a first source line layer of a first substrate and a second source line layer of a second substrate so that the first source line layer and the second source line layer face each other, and then performing a bonding process to bond the first source line layer and the second source line layer.

[0013] In one embodiment of the present disclosure, the slits passing through the stacked structure of the first memory chip structure and the slits passing through the stacked structure of the second memory chip structure are arranged to cross each other. Therefore, the warping phenomenon at the interface between the first memory chip structure and the second memory chip structure can be improved, and the source line layer of the first memory chip structure and the source line layer of the second memory chip structure can be shared by directly combining the source line layer of the first memory chip structure and the source line layer of the second memory chip structure.

[0014] These and other features and advantages of the present invention will be better understood from the following drawings and detailed description of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram showing a semiconductor memory device;

[0016] Figure 2A and Figure 2B is a schematic perspective view showing a semiconductor memory device according to an embodiment of the present disclosure;

[0017] Figure 3 is a diagram showing an embodiment according to the present disclosure Figure 2BSimplified cross-sectional schematic diagrams of a first memory chip structure, a second memory chip structure, and a fifth memory chip structure shown;

[0018] Figure 4 It is shown Figure 3 A graph of region A;

[0019] Figure 5 Another embodiment of the present disclosure is shown in FIG. Figure 2B Simplified cross-sectional schematic diagrams of a first memory chip structure, a second memory chip structure, and a fifth memory chip structure shown;

[0020] Fig. 6A , Figure 6B and Figure 6C is a diagram showing an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure according to an embodiment of the present disclosure;

[0021] Fig. 7A , Figure 7B and Figure 7C is a diagram showing an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure according to another embodiment of the present disclosure;

[0022] Fig. 8A , Figure 8B and Figure 8C is a diagram showing an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure according to yet another embodiment of the present disclosure;

[0023] 9A to 9F , Fig.10 , Fig.11 and FIG. 12A to FIG. 12D is a simplified cross-sectional schematic diagram illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure;

[0024] Fig.13A and Fig. 13B is a simplified cross-sectional schematic diagram illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure;

[0025] Fig.14 is a diagram showing a memory card system to which the semiconductor memory device of the present disclosure is applied; and

[0026] Fig.15 is a diagram showing a solid state drive (SSD) system to which the semiconductor memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0027] The specific structural or functional description of the embodiment according to the concept disclosed in this specification is only used to describe the embodiment according to the concept of the present disclosure. The embodiment according to the concept of the present disclosure can be implemented in various forms and should not be interpreted as limited to the embodiment described in this specification.

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings so as to describe them in sufficient detail to allow those having ordinary skill in the art to easily implement the present invention.

[0029] Figure 1 is a diagram showing a semiconductor memory device.

[0030] refer to Figure 1 , the semiconductor memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0031] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi, where i is a positive integer. Each of the first to i-th memory blocks BLK1 to BLKi may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly connected to the first to i-th memory blocks BLK1 to BLKi.

[0032] In the present disclosure, a memory area may indicate a memory plane or a memory block. In the present disclosure, for convenience of description, a description is given based on that a memory area is a memory block, but the present disclosure is not limited thereto.

[0033] The first to i-th memory blocks BLK1 to BLKi may be formed in a three-dimensional structure. The memory block having the three-dimensional structure may include memory cells stacked in a vertical direction on a substrate.

[0034] According to the programming method, the memory cell can store 1 bit or 2 bits or more data. For example, the method of storing 1 bit of data in one memory cell is called a single-level cell method, and the method of storing 2 bits of data in one memory cell is called a multi-level cell method. The method of storing 3 bits of data in one memory cell is called a three-level cell method, and the method of storing 4 bits of data in one memory cell is called a four-level cell method. In addition, five bits or more of data can be stored in one memory cell.

[0035] The peripheral circuit 170 may be configured to perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0036] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to an operation code OPCD received from the control circuit 180. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to a drain selection line DSL, a word line WL, a source selection line SSL, and a source line SL of a memory block selected by the row decoder 130.

[0037] The programming voltage may be a voltage applied to a selected word line in the word line WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. The precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used during a verification operation to determine whether the threshold voltage of a selected memory cell is increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0038] During a read operation of a selected memory cell, a read voltage may be applied to a selected word line. For example, the read voltage may be set to various levels according to a programming method of the selected memory cell.

[0039] The pass voltage may be a voltage applied to an unselected word line in a word line WL during a programming or reading operation, and may be used to turn on a memory cell connected to an unselected word line. In a read operation according to the present embodiment, the pass voltage may include a target pass voltage set to be the highest, and a sub-pass voltage lower than the target pass voltage. For example, before the read voltage is applied to the selected word line, the sub-pass voltage may be applied to an adjacent word line adjacent to the selected word line. When the sub-pass voltage is applied to the adjacent word line, the target pass voltage may be applied to the remaining unselected word lines. When the read voltage is applied to the selected word line, the target pass voltage may be applied to the adjacent word line.

[0040] The erase voltage may be used to erase memory cells included in a selected memory block during an erase operation, and may be applied to the source line SL.

[0041] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the i-th memory block BLKi through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0042] The page buffer group 140 may include page buffers PB1 to PBn (not shown) connected to the first to i-th memory blocks BLK1 to BLKi. Each of the page buffers (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi through a bit line BL. During a read operation, the page buffer (not shown) may sense a current or voltage of a bit line that varies according to a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and temporarily store the sensed data.

[0043] The column decoder 150 may be configured to respond to the column address CADD so that data is transmitted between the page buffer group 140 and the input / output circuit 160. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL, and an enable signal may be transmitted through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0044] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller to the control circuit 180 through the input / output line I / O, and transmit data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0045] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation of a memory block selected by the address, and output the read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation of the selected memory block.

[0046] Figure 2A and Figure 2B is a schematic perspective view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0047] refer to Figure 2A , a semiconductor memory device according to an embodiment of the present disclosure may include a plurality of memory chip structures 2100, 2200, 2300, and 2400. The first memory chip structure 2100 and the second memory chip structure 2200 may be joined in a vertical direction Z.

[0048] The first memory chip structure 2100 may include a plurality of planar regions. For example, the first memory chip structure 2100 may include a first planar region P1 and a second planar region P2. In addition, each of the first planar region P1 and the second planar region P2 may include a plurality of stacked structures. For example, the first planar region P1 may include a first stacked structure ST1 and a second stacked structure ST2, and the second planar region P2 may include a third stacked structure ST3 and a fourth stacked structure ST4. In addition, each of the first planar region P1 and the second planar region P2 may include a plurality of slits that cross the stacked structures and may pass through the stacked structures. For example, the first slit S1 may extend in a first horizontal direction X perpendicular to the vertical direction Z and may pass through the first stacked structure ST1. The second slit S2 may extend in the first horizontal direction X and may pass through the second stacked structure ST2. (See also Fig. 6A ). The third slit S3 may extend in the first horizontal direction X and may pass through the third stacked structure ST3. The fourth slit S4 may extend in the first horizontal direction X and may pass through the fourth stacked structure ST4.

[0049] exist Figure 2A , the first memory chip structure 2100 includes a first planar region P1 and a second planar region P2, but the embodiment is not limited thereto and may include one or two or more planar regions.

[0050] The second memory chip structure 2200 may overlap the first memory chip structure 2100 and bond to the first memory chip structure 2100. The second memory chip structure 2200 may include a plurality of plane regions. For example, the second memory chip structure 2200 may include a third plane region P3 and a fourth plane region P4. In addition, each of the third plane region P3 and the fourth plane region P4 may include a plurality of stacked structures. For example, the third plane region P3 may include a fifth stacked structure ST5 and a sixth stacked structure ST6, and the fourth plane region P4 may include a seventh stacked structure ST7 and an eighth stacked structure ST8. In addition, each of the third plane region P3 and the fourth plane region P4 may include a plurality of slits that cross the stacked structure and may pass through the stacked structure. For example, the fifth slit S5 may extend in a second horizontal direction Y perpendicular to the vertical direction Z and may pass through the fifth stacked structure ST5. The second horizontal direction Y may be perpendicular to the first horizontal direction X. The sixth slit S6 may extend in the second horizontal direction Y and may pass through the sixth stacked structure ST6. The seventh slit S7 may extend in the second horizontal direction Y and may pass through the seventh stacked structure ST7. The eighth slit S8 may extend in the second horizontal direction Y and may pass through the eighth stacked structure ST8 .

[0051] exist Figure 2A , the second memory chip structure 2200 includes a third planar region P3 and a fourth planar region P4, but the embodiment is not limited thereto and may include one or two or more planar regions.

[0052] The above-mentioned first planar area P1, second planar area P2, third planar area P3, and fourth planar area P4 may include a memory cell structure including a plurality of memory cells arranged three-dimensionally.

[0053] The first memory chip structure 2100 and the third memory chip structure 2300 may be coupled in the vertical direction Z. For example, the third memory chip structure 2300 may overlap below the first memory chip structure 2100 and be coupled to the first memory chip structure 2100. The third memory chip structure 2300 may include a first logic circuit region LC1. The first logic circuit region LC1 may include Figure 1 The peripheral circuit 170 in the first memory chip structure 2100 is used to drive the plurality of memory cells included in the first memory chip structure 2100.

[0054] The second memory chip structure 2200 and the fourth memory chip structure 2400 may be coupled in the vertical direction Z. For example, the fourth memory chip structure 2400 may be overlapped on the second memory chip structure 2200 and bonded to the second memory chip structure 2200. The fourth memory chip structure 2400 may include a second logic circuit region LC2. The second logic circuit region LC2 may include Figure 1 The peripheral circuit 170 in the second memory chip structure 2200 is used to drive the plurality of memory cells included in the second memory chip structure 2200.

[0055] As described above, in one embodiment of the present disclosure, the first memory chip structure 2100 and the second memory chip structure 2200 are combined in the vertical direction, the plurality of slits S1 to S4 included in the first memory chip structure 2100 extend in the first horizontal direction X, and the plurality of slits S5 to S8 included in the second memory chip structure 2200 extend in the second horizontal direction Y orthogonal to the first horizontal direction X and are arranged in the second horizontal direction Y. Such an orientation of the slits is advantageous because the directions of the tensile stress or compressive stress occurring in the first memory chip structure 2100 and the directions of the tensile stress or compressive stress occurring in the second memory chip structure 2200 are orthogonal to each other to alleviate these stresses. Therefore, the warpage phenomenon occurring between the first memory chip structure 2100 and the second memory chip structure 2200 can be improved.

[0056] refer to Figure 2B, a semiconductor memory device according to another embodiment of the present disclosure may include a plurality of memory chip structures 2100, 2200, and 2500. The first memory chip structure 2100 and the second memory chip structure 2200 may be coupled in a vertical direction Z.

[0057] Since the first memory chip structure 2100 and the second memory chip structure 2200 have the same Figure 2A The structure is similar to that of FIG. 1 , so its detailed description is omitted.

[0058] The first memory chip structure 2100 and the fifth memory chip structure 2500 may be coupled in the vertical direction Z. For example, the fifth memory chip structure 2500 may overlap below the first memory chip structure 2100 and may be coupled to the first memory chip structure 2100. The fifth memory chip structure 2500 may include a plurality of first page buffer regions PB1, a plurality of second page buffer regions PB2, a plurality of first row decoder regions XDEC1, and a plurality of second row decoder regions XDEC2. The plurality of first page buffer regions PB1 may include Figure 1 The page buffer group 140 in the first memory chip structure 2100 is used to drive a plurality of memory cells included in the first memory chip structure 2100, and a plurality of first row decoder regions XDEC1 may include Figure 1 The row decoder 130 in the first memory chip structure 2100 is used to drive the plurality of memory cells included in the first memory chip structure 2100. The plurality of second page buffer regions PB2 may include Figure 1 The page buffer group 140 in the second memory chip structure 2200 is used to drive a plurality of memory cells included in the second memory chip structure 2200, and a plurality of second row decoder regions XDEC2 may include Figure 1 The row decoder 130 is used to drive a plurality of memory cells included in the second memory chip structure 2200 .

[0059] As described above, in another embodiment of the present disclosure, a peripheral circuit for driving a plurality of memory cells included in a plurality of memory chip structures (i.e., the first memory chip structure 2100 and the second memory chip structure 2200) may be included in the fifth memory chip structure 2500. Therefore, the integration degree of the semiconductor memory device may be improved.

[0060] Figure 3 is a diagram showing an embodiment according to the present disclosure Figure 2B Simplified cross-sectional schematic diagrams of a first memory chip structure, a second memory chip structure, and a fifth memory chip structure are shown.

[0061] Figure 3 It is shown along Figure 2BFIG. 1 is a simplified cross-sectional schematic diagram of a region cut along line II′ of FIG. 1 , for describing a semiconductor memory device according to an embodiment of the present disclosure.

[0062] refer to Figure 3 , the semiconductor memory device may include a first memory chip structure 2100 , a second memory chip structure 2200 , and a fifth memory chip structure 2500 .

[0063] The first memory chip structure 2100 may include a first stacked structure ST1 , a plurality of cell plugs CP1 , a plurality of first slits S1 , and a first source line layer SL1 .

[0064] In the first stacked structure ST1, a plurality of interlayer insulating layers ILD1 and a plurality of word line patterns WP1 may be alternately stacked. Both ends of the first stacked structure ST1 may have a multi-step shape, and an end of each of the plurality of word line patterns WP1 may be exposed by the multi-step shape. The plurality of word line patterns WP1 may extend in a horizontal direction.

[0065] The first source line layer SL1 may be disposed on the first stacked structure ST1 . The first source line layer SL1 may be exposed to a top surface of the first memory chip structure 2100 .

[0066] Each of the plurality of cell plugs CP1 may extend in a vertical direction within the first stacked structure ST1 . One end portion of each of the plurality of cell plugs CP1 may directly contact the first source line layer SL1 , and may extend into the first source line layer SL1 .

[0067] The plurality of first slits S1 may be disposed between the plurality of cell plugs CP1 and may pass through the first stack structure ST1 in a vertical direction. Although not shown in the drawings, the plurality of first slits S1 may extend in the first horizontal direction X, such as Figure 2B That is, the first slit S1 may cross the first stack structure ST1 in the first horizontal direction X and may pass through the first stack structure ST1 in the vertical direction. The first slit S1 may include an insulating material. At least one cell plug CP1 may be disposed between the plurality of first slits S1.

[0068] One end of each of the plurality of cell plugs CP1 is connected to the bit line BL1 through the bit line contact BC1. The bit line BL1 may be connected to the bonding pad BP3 exposed through the bottom surface of the first memory chip structure 2100 through the bit line contact plug BLCP.

[0069] The first stacked structure ST1 , the plurality of cell plugs CP1 , the plurality of first slits S1 , and the first source line layer SL1 may be covered by an interlayer insulating layer 2101 .

[0070] The second memory chip structure 2200 may be bonded to the first memory chip structure 2100. The second memory chip structure 2200 may be configured by including a fifth stack structure ST5, a plurality of cell plugs CP2, a plurality of fifth slits (not shown), and a second source line layer SL2.

[0071] In the fifth stacked structure ST5, a plurality of interlayer insulating layers ILD2 and a plurality of word line patterns WP2 may be alternately stacked. Both ends of the fifth stacked structure ST5 may have a multi-step shape, and an end of each of the plurality of word line patterns WP2 may be exposed by the multi-step shape. The plurality of word line patterns WP2 may extend in a horizontal direction.

[0072] The second source line layer SL2 may be disposed under the fifth stacked structure ST5 , and the second source line layer SL2 may be exposed to the bottom surface of the second memory chip structure 2200 .

[0073] Each of the plurality of cell plugs CP2 may extend in the vertical direction within the fifth stacked structure ST5 . One end portion of each of the plurality of cell plugs CP2 may directly contact the second source line layer SL2 , and may extend into the second source line layer SL2 .

[0074] A plurality of fifth slits (not shown) may be disposed between the plurality of cell plugs CP2 and may pass through the fifth stacked structure ST5 in the vertical direction. Although not shown in the drawings, the plurality of fifth slits may extend in the second horizontal direction Y, such as Figure 2B That is, the fifth slit may cross the fifth stacked structure ST5 in the second horizontal direction Y, and may pass through the fifth stacked structure ST5 in the vertical direction. The fifth slit may include an insulating material.

[0075] One end portion of each of the plurality of word line patterns WP2 may be connected to a bonding pad BP2 through a word line contact WC, a word line wiring WCP, and a first word line contact plug WLCP1 .

[0076] One end of each of the cell plugs CP2 is connected to the bit line BL2 through the bit line contact BC2.

[0077] The first source line layer SL1 of the first memory chip structure 2100 and the second source line layer SL2 of the second memory chip structure 2200 may directly contact each other. Therefore, the cell plugs CP1 of the first memory chip structure 2100 and the cell plugs CP2 of the second memory chip structure 2200 may share the physically and electrically connected source line layers SL1 and SL2.

[0078] The fifth stacked structure ST5 , the plurality of cell plugs CP2 , and the second source line layer SL2 may be covered by the interlayer insulating layer 2201 .

[0079] The bit line contact plugs BLCP of the first memory chip structure 2100 may be disposed along one side direction of the first stack structure ST1. For example, the bit line contact plugs BLCP corresponding to the first stack structure ST1 may be disposed along one side direction of the first stack structure ST1. Figure 2B The memory chip 2500 may be located in a region adjacent to the third stack structure ST3 and may be disposed to overlap with the first page buffer region PB1 of the fifth memory chip structure 2500 .

[0080] In addition, first and second word line contact plugs WLCP1 and WLCP2 corresponding to the fifth stack structure ST5 of the second memory chip structure 2200 may be disposed adjacent to a region where the bit line contact plug BLCP is disposed and may be disposed to overlap the second row decoder region XDEC2 of the fifth memory chip structure 2500 .

[0081] The first memory chip structure 2100 and the second memory chip structure 2200 may be bonded to each other through a bonding process.

[0082] For example, the bonding pad BP1 of the top surface of the first memory chip structure 2100 and the bonding pad BP2 of the bottom surface of the second memory chip structure 2200 may be disposed to face each other and may be bonded to each other.

[0083] The fifth memory chip structure 2500 may be coupled to a lower portion of the first memory chip structure 2100 .

[0084] The fifth memory chip structure 2500 may be configured by including a plurality of transistors TR, and may further include a transistor for configuring Figure 1 Multiple resistors or multiple capacitors of the peripheral circuit 170.

[0085] The fifth memory chip structure 2500 may include a CMOS circuit structure including a plurality of transistors TR formed on a substrate SUB. Each of the plurality of transistors TR may be formed in an active region partitioned by an element isolation layer ISO, and may include a gate insulating layer, a gate electrode, and junctions J1 and J2. The plurality of transistors TR may be connected to a bonding pad BP4 through a line ML including a plurality of conductive patterns C1 to C3.

[0086] The plurality of transistors TR may be covered by an interlayer insulating layer 2501 .

[0087] The first memory chip structure 2100 and the fifth memory chip structure 2500 may be bonded to each other through a bonding process.

[0088] For example, the bonding pad BP3 of the bottom surface of the first memory chip structure 2100 and the bonding pad BP4 of the top surface of the fifth memory chip structure 2500 may be disposed to face each other and may be bonded to each other.

[0089] Figure 4 It is shown Figure 3 Graph of area A.

[0090] refer to Figure 4 , the cell plug CP1 may extend in a vertical direction by passing through the first stacked structure ST1 , and one end portion may extend to the first source line layer SL1 .

[0091] The cell plug CP1 may include a core insulation layer CO extending in a vertical direction, a channel layer CHL surrounding a sidewall of the core insulation layer CO and a bottom surface of the core insulation layer CO, a memory layer ML extending along an outer wall of the channel layer CH, and a cap layer CAP disposed on the core insulation layer CO and the channel layer CHL.

[0092] The channel layer CHL of the cell plug CP1 extending into the first source line layer SL1 may be exposed, and thus the first source line layer SL1 and the channel layer CHL may directly contact each other.

[0093] The memory layer ML may include a tunnel insulating layer surrounding the channel layer CHL, a data storage layer surrounding the tunnel insulating layer, and a blocking insulating layer surrounding the data storage layer.

[0094] Figure 5 Another embodiment of the present disclosure is shown in FIG. Figure 2B Simplified cross-sectional schematic diagrams of a first memory chip structure, a second memory chip structure, and a fifth memory chip structure are shown.

[0095] Figure 5 It is shown along Figure 2B 1 is a simplified cross-sectional schematic diagram of a region cut off by line JJ′ of FIG. 1 , for describing a semiconductor memory device according to another embodiment of the present disclosure.

[0096] refer to Figure 5 , the semiconductor memory device may include a first memory chip structure 2100 , a second memory chip structure 2200 , and a fifth memory chip structure 2500 .

[0097] The first memory chip structure 2100 may include a first stacked structure ST1 , a plurality of cell plugs CP1 , a plurality of first slits (not shown), and a first source line layer SL1 .

[0098] In the first stacked structure ST1, a plurality of interlayer insulating layers ILD1 and a plurality of word line patterns WP1 may be alternately stacked. Both ends of the first stacked structure ST1 may have a multi-step shape, and an end of each of the plurality of word line patterns WP1 may be exposed by the multi-step shape. The plurality of word line patterns WP1 may extend in a horizontal direction.

[0099] The first source line layer SL1 may be disposed under the first stacked structure ST1 .

[0100] Each of the plurality of cell plugs CP1 may extend in a vertical direction within the first stacked structure ST1 . One end portion of each of the plurality of cell plugs CP1 may directly contact the first source line layer SL1 , and may extend into the first source line layer SL1 .

[0101] A plurality of first slits (not shown) may be disposed between the plurality of cell plugs CP1 and may penetrate the first stack structure ST1 in a vertical direction. Although not shown in the drawings, the plurality of first slits may extend in the first horizontal direction X, such as Figure 2B That is, the first slit may cross the first stacked structure ST1 in the first horizontal direction X and may pass through the first stacked structure ST1 in the vertical direction. The first slit may include an insulating material. At least one cell plug CP1 may be disposed between the plurality of first slits.

[0102] One end of each of the plurality of cell plugs CP1 is connected to the bit line BL1 through the bit line contact BC1. The bit line BL1 may be connected to the bonding pad BP3 exposed through the bottom surface of the first memory chip structure 2100 through the bit line contact plug BLCP. In addition, the bit line BL1 may be connected to the bonding pad BP1 exposed through the top surface of the first memory chip structure 2100.

[0103] The first memory chip structure 2100 may further include a plug line (not shown) and a contact plug (not shown) passing through the first memory chip structure 2100 .

[0104] The first stacked structure ST1 , the plurality of cell plugs CP1 , the plurality of first slits, and the first source line layer SL1 may be covered by an interlayer insulating layer 2101 .

[0105] The second memory chip structure 2200 may be coupled to the first memory chip structure 2100. The second memory chip structure 2200 may be configured by including a fifth stack structure ST5, a plurality of cell plugs CP2, a plurality of fifth slits S5, and a second source line layer SL2.

[0106] In the fifth stacked structure ST5, a plurality of interlayer insulating layers ILD2 and a plurality of word line patterns WP2 may be alternately stacked. Both ends of the fifth stacked structure ST5 may have a multi-step shape, and an end of each of the plurality of word line patterns WP2 may be exposed by the multi-step shape. The plurality of word line patterns WP2 may extend in a horizontal direction.

[0107] The second source line layer SL2 may be disposed on the fifth stacked structure ST5 .

[0108] Each of the plurality of cell plugs CP2 may extend in the vertical direction within the fifth stacked structure ST5 . One end portion of each of the plurality of cell plugs CP2 may directly contact the second source line layer SL2 , and may extend into the second source line layer SL2 .

[0109] A plurality of fifth slits S5 may be disposed between the plurality of unit plugs CP2, wherein there is one fifth slit S5 between each pair of adjacent unit plugs CP2. The fifth slits S5 may each pass through the fifth stacked structure ST5 in the vertical direction. Although not shown in the figure, the plurality of fifth slits S5 may extend in the second horizontal direction Y, such as Figure 2B That is, the fifth slit S5 may cross the fifth stacked structure ST5 in the second horizontal direction Y, and may pass through the fifth stacked structure ST5 in the vertical direction. The fifth slit S5 may include an insulating material.

[0110] One end portion of each of the plurality of word line patterns WP1 may be connected to a bonding pad BP3 through a word line contact WC, a word line wiring WCP, and a first word line contact plug WLCP1 .

[0111] One end of each of the cell plugs CP2 is connected to the bit line BL2 through the bit line contact BC2. The bit line BL2 may be connected to the bonding pad BP2 exposed through the bottom surface of the second memory chip structure 2200 through the bit line contact plug PL3.

[0112] The first memory chip structure 2100 may further include bit line contact plugs PL1 and PL2 , and a contact plug CTP1 electrically connected to the bit line contact plug PL3 of the second memory chip structure 2200 .

[0113] The fifth stacked structure ST5 , the plurality of cell plugs CP2 , and the second source line layer SL2 may be covered by the interlayer insulating layer 2201 .

[0114] The first word line contact plug WLCP1 of the first memory chip structure 2100 may be disposed along one side direction of the first stack structure ST1. For example, the first word line contact plug WLCP1 corresponding to the first stack structure ST1 may be disposed Figure 2BThe bit line contact plugs PL1, PL2 and PL3 corresponding to the fifth stack structure ST5 may be disposed adjacent to the region in which the first word line contact plug WLCP1 is disposed, and may be disposed to overlap with the second page buffer region PB2 of the fifth memory chip structure 2500.

[0115] The first memory chip structure 2100 and the second memory chip structure 2200 may be bonded to each other through a bonding process.

[0116] For example, the bonding pad BP1 of the top surface of the first memory chip structure 2100 and the bonding pad BP2 of the bottom surface of the second memory chip structure 2200 may be disposed to face each other and may be bonded to each other.

[0117] The fifth memory chip structure 2500 may be coupled to a lower portion of the first memory chip structure 2100 .

[0118] The fifth memory chip structure 2500 may be configured by including a plurality of transistors TR, and may further include a transistor for configuring Figure 1 Multiple resistors or multiple capacitors of the peripheral circuit 170.

[0119] The fifth memory chip structure 2500 may include a CMOS circuit structure including a plurality of transistors TR formed on a substrate SUB. Each of the plurality of transistors TR may be formed in an active region partitioned by an element isolation layer ISO, and may include a gate insulating layer, a gate electrode, and junctions J1 and J2. The plurality of transistors TR may be connected to a bonding pad BP4 through a line ML including a plurality of conductive patterns C1 to C3.

[0120] The plurality of transistors TR may be covered by an interlayer insulating layer 2501 .

[0121] The first memory chip structure 2100 and the fifth memory chip structure 2500 may be bonded to each other through a bonding process.

[0122] For example, the bonding pad BP3 of the bottom surface of the first memory chip structure 2100 and the bonding pad BP4 of the top surface of the fifth memory chip structure 2500 may be disposed to face each other and may be bonded to each other.

[0123] Fig. 6A , Figure 6B and Figure 6C is a diagram illustrating an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure according to an embodiment of the present disclosure.

[0124] Fig. 6A is a diagram showing an overlapping area of ​​a first memory chip structure and a fifth memory chip structure.

[0125] refer to Fig. 6A , the first planar area P1 of the first memory chip structure may include a first stacked structure ST1 and a second stacked structure ST2 arranged side by side to be adjacent to each other in the first horizontal direction X. The first stacked structure ST1 and the second stacked structure ST2 may be spaced apart from each other by a certain distance. In addition, the second planar area P2 of the first memory chip structure may include a third stacked structure ST3 and a fourth stacked structure ST4 arranged side by side to be adjacent to each other in the first horizontal direction X, and the third stacked structure ST3 and the fourth stacked structure ST4 may be spaced apart from each other by a certain distance. The first stacked structures ST1 to the fourth stacked structures ST4 may be arranged in a matrix form.

[0126] The first slit S1 may extend in a first horizontal direction X perpendicular to the vertical direction Z and may pass through the first stacked structure ST1. The second slit S2 may extend in the first horizontal direction X and may pass through the second stacked structure ST2. The third slit S3 may extend in the first horizontal direction X and may pass through the third stacked structure ST3. The fourth slit S4 may extend in the first horizontal direction X and may pass through the fourth stacked structure ST4.

[0127] The first page buffer region PB1 of the fifth memory chip structure may overlap the first stack structure ST1 and the fourth stack structure ST4. For example, the first page buffer region PB1 of the fifth memory chip structure may be disposed below the first stack structure ST1 to be adjacent to the third stack structure ST3, and the first page buffer region PB1 of the fifth memory chip structure may be disposed below the fourth stack structure ST4 to be adjacent to the second stack structure ST2. The first page buffer region PB1 of the fifth memory chip structure may be a region in which a page buffer connected to a bit line of a memory cell included in the first memory chip structure is disposed.

[0128] The first row decoder region XDEC1 of the fifth memory chip structure may overlap with a region between the first stack structure ST1 and the second stack structure ST2, and the first row decoder region XDEC1 of the fifth memory chip structure may overlap with a region between the third stack structure ST3 and the fourth stack structure ST4. The first row decoder region XDEC1 of the fifth memory chip structure may be a region in which row decoders connected to word lines of memory cells included in the first memory chip structure are disposed.

[0129] A partial area that does not overlap with the first row decoder area XDEC1 in the area between the first stacking structure ST1 and the second stacking structure ST2 of the first memory chip structure can be defined as an OFC area OFC, and the OFC area OFC can be the following area: the first stacking structure ST1 and the lines connected to the bit lines connected to the cell plugs set in the first stacking structure ST1 extend to the area of ​​the lower fifth memory chip structure.

[0130] In addition, a partial area that does not overlap with the first row decoder area XDEC1 in the area between the third stacking structure ST3 and the fourth stacking structure ST4 of the first memory chip structure can be defined as an OFC area, and the OFC area OFC can be the following area: a line connected to the bit line connected to the cell plug set in the third stacking structure ST3 and the fourth stacking structure ST4 extends to the area of ​​the lower fifth memory chip structure.

[0131] Figure 6B is a diagram showing an overlapping area of ​​the second memory chip structure and the fifth memory chip structure.

[0132] refer to Figure 6B , the third plane area P3 of the second memory chip structure may include a fifth stacked structure ST5 and a sixth stacked structure ST6 arranged side by side to be adjacent to each other in the second horizontal direction Y. The fifth stacked structure ST5 and the sixth stacked structure ST6 may be spaced apart from each other by a certain distance. In addition, the fourth plane area P4 of the second memory chip structure may include a seventh stacked structure ST7 and an eighth stacked structure ST8 arranged side by side to be adjacent to each other in the second horizontal direction Y. The seventh stacked structure ST7 and the eighth stacked structure ST8 may be spaced apart from each other by a certain distance. The fifth stacked structure ST5 to the eighth stacked structure ST8 may be arranged in a matrix form.

[0133] The fifth slit S5 may extend in the second horizontal direction Y perpendicular to the vertical direction Z and may pass through the fifth stacked structure ST5. The sixth slit S6 may extend in the second horizontal direction Y and may pass through the sixth stacked structure ST6. The seventh slit S7 may extend in the second horizontal direction Y and may pass through the seventh stacked structure ST7. The eighth slit S8 may extend in the second horizontal direction Y and may pass through the eighth stacked structure ST8.

[0134] The second page buffer region PB2 of the fifth memory chip structure may overlap with the region between the fifth stack structure ST5 and the seventh stack structure ST7. Fig. 6AThe OFC region between the first stack structure ST1 and the second stack structure ST2 overlaps. In addition, the second page buffer region PB2 of the fifth memory chip structure may overlap with the region between the sixth stack structure ST6 and the eighth stack structure ST8. In addition, the second page buffer region PB2 of the fifth memory chip structure may overlap with the region between the sixth stack structure ST6 and the eighth stack structure ST8. Fig. 6A The OFC region between the third stack structure ST3 and the fourth stack structure ST4 overlaps. The second page buffer region PB2 may be a region in which page buffers connected to bit lines of memory cells included in the second memory chip structure are disposed.

[0135] The second row decoder region XDEC2 of the fifth memory chip structure may overlap with a region between the fifth stack structure ST5 and the sixth stack structure ST6 and a region between the seventh stack structure ST7 and the eighth stack structure ST8. The second row decoder region XDEC2 of the fifth memory chip structure may be a region in which row decoders of word lines connected to memory cells included in the second memory chip structure are disposed.

[0136] Figure 6C is a diagram showing an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure.

[0137] refer to Figure 6C , the first stacking structure ST1 of the first memory chip structure and the fifth stacking structure ST5 of the second memory chip structure may overlap with each other, the second stacking structure ST2 of the first memory chip structure and the seventh stacking structure ST7 of the second memory chip structure may overlap with each other, the third stacking structure ST3 of the first memory chip structure and the sixth stacking structure ST6 of the second memory chip structure may overlap with each other, and the fourth stacking structure ST4 of the first memory chip structure and the eighth stacking structure ST8 of the second memory chip structure may overlap with each other.

[0138] In addition, the extension direction of the first slit S1 and the extension direction of the fifth slit S5 can be orthogonal to each other, the extension direction of the second slit S2 and the extension direction of the seventh slit S7 can be orthogonal to each other, the extension direction of the third slit S3 and the extension direction of the sixth slit S6 can be orthogonal to each other, and the extension direction of the fourth slit S4 and the extension direction of the eighth slit S8 can be orthogonal to each other.

[0139] A region between the first and second stack structures ST1 and ST2 may overlap the first row decoder region XDEC1 and the second page buffer region PB2 of the fifth memory chip structure, and the second page buffer region PB2 of these regions may overlap the OFC region OFC of the second memory chip structure.

[0140] A region between the third and fourth stack structures ST3 and ST4 may overlap the first row decoder region XDEC1 and the second page buffer region PB2 of the fifth memory chip structure, and the second page buffer region PB2 of these regions may overlap the OFC region OFC of the second memory chip structure.

[0141] The first row decoder region XDEC1 may be disposed adjacent to the second page buffer region PB2 .

[0142] A region between the first and third stack structures ST1 and ST3 may overlap the second row decoder region XDEC2 of the fifth memory chip structure, and the first page buffer region PB1 may overlap the first and fifth stack structures ST1 and ST5 .

[0143] A region between the second stack structure ST2 and the fourth stack structure ST4 may overlap the second row decoder region XDEC2 of the fifth memory chip structure, and the first page buffer region PB1 may overlap the fourth stack structure ST4 and the eighth stack structure ST8 .

[0144] like Figure 3 As shown, a plurality of first source line layers respectively corresponding to the first to fourth stack structures ST1 to ST4 may be exposed on the top surface of the first memory chip structure.

[0145] like Figure 3 As shown, a plurality of second source line layers respectively corresponding to the fifth to eighth stack structures ST5 to ST8 may be exposed on the bottom surface of the second memory chip structure, and the plurality of first source lines and the plurality of second source lines may be in direct contact.

[0146] Fig. 7A , Figure 7B and Figure 7C is a diagram illustrating an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure according to another embodiment of the present disclosure.

[0147] Fig. 7A is a diagram showing an overlapping area of ​​a first memory chip structure and a fifth memory chip structure.

[0148] refer to Fig. 7A, the first planar area P1 of the first memory chip structure may include a first stacked structure ST1 and a second stacked structure ST2 arranged side by side to be adjacent to each other in the first horizontal direction X, and the first stacked structure ST1 and the second stacked structure ST2 may be spaced apart from each other by a certain distance. In addition, the second planar area P2 of the first memory chip structure may include a third stacked structure ST3 and a fourth stacked structure ST4 arranged side by side to be adjacent to each other in the first horizontal direction X, and the third stacked structure ST3 and the fourth stacked structure ST4 may be spaced apart from each other by a certain distance. The first stacked structures ST1 to the fourth stacked structures ST4 may be arranged in a matrix form.

[0149] The first slit S1 may extend in a first horizontal direction X perpendicular to the vertical direction Z and may pass through the first stacked structure ST1. The second slit S2 may extend in the first horizontal direction X and may pass through the second stacked structure ST2. The third slit S3 may extend in the first horizontal direction X and may pass through the third stacked structure ST3. The fourth slit S4 may extend in the first horizontal direction X and may pass through the fourth stacked structure ST4.

[0150] The first row decoder region XDEC1_1 and the second row decoder region XDEC1_2 of the fifth memory chip structure may overlap with the region between the first stack structure ST1 and the second stack structure ST2. The first row decoder region XDEC1_1 and the second row decoder region XDEC1_2 may be spaced apart by a first distance D1, and the region of the first memory chip structure overlapping with the region between the first row decoder region XDEC1_1 and the second row decoder region XDEC1_2 may be defined as an OFC region. The first row decoder region XDEC1_1 may be a region in which a row decoder connected to a word line of a memory cell formed in the first stack structure ST1 is disposed. The second row decoder region XDEC1_2 may be a region in which a row decoder connected to a word line of a memory cell formed in the second stack structure ST2 is disposed. The OFC region OFC may be a region in which a line connected to a bit line connected to a cell plug disposed in the first stack structure ST1 and the second stack structure ST2 extends to a region of the lower fifth memory chip structure.

[0151] The third row decoder region XDEC1_3 and the fourth row decoder region XDEC1_4 of the fifth memory chip structure may overlap with the region between the third stacking structure ST3 and the fourth stacking structure ST4. The third row decoder region XDEC1_3 and the fourth row decoder region XDEC1_4 may be spaced apart by a first distance D1, and the region of the first memory chip structure overlapping with the region between the third row decoder region XDEC1_3 and the fourth row decoder region XDEC1_4 may be defined as an OFC region. The third row decoder region XDEC1_3 may be a region in which a row decoder connected to a word line of a memory cell formed in the third stacking structure ST3 is disposed. The fourth row decoder region XDEC1_4 may be a region in which a row decoder connected to a word line of a memory cell formed in the fourth stacking structure ST4 is disposed. The OFC region OFC may be a region in which a line connected to a bit line connected to a cell plug disposed in the third stacking structure ST3 and the fourth stacking structure ST4 extends to a region of the lower fifth memory chip structure.

[0152] The first page buffer region PB1 of the fifth memory chip structure may overlap with a region between the first stack structure ST1 and the third stack structure ST3 and a region between the second stack structure ST2 and the fourth stack structure ST4. The first page buffer region PB1 may be spaced apart from a region overlapping each of the first to fourth stack structures ST1 to ST4 by a second distance D2. The first page buffer region PB1 of the fifth memory chip structure may be a region in which a page buffer connected to a bit line of a memory cell included in the first memory chip structure is disposed.

[0153] Figure 7B is a diagram showing an overlapping area of ​​the second memory chip structure and the fifth memory chip structure.

[0154] refer to Figure 7B , the third plane area P3 of the second memory chip structure may include a fifth stacked structure ST5 and a sixth stacked structure ST6 arranged side by side to be adjacent to each other in the second horizontal direction Y. The fifth stacked structure ST5 and the sixth stacked structure ST6 may be spaced apart from each other by a certain distance. In addition, the fourth plane area P4 of the second memory chip structure may include a seventh stacked structure ST7 and an eighth stacked structure ST8 arranged side by side to be adjacent to each other in the second horizontal direction Y, and the seventh stacked structure ST7 and the eighth stacked structure ST8 may be spaced apart from each other by a certain distance. The fifth stacked structure ST5 to the eighth stacked structure ST8 may be arranged in a matrix form.

[0155] The fifth slit S5 may extend in the second horizontal direction Y perpendicular to the vertical direction Z and may pass through the fifth stacked structure ST5. The sixth slit S6 may extend in the second horizontal direction Y and may pass through the sixth stacked structure ST6. The seventh slit S7 may extend in the second horizontal direction Y and may pass through the seventh stacked structure ST7. The eighth slit S8 may extend in the second horizontal direction Y and may pass through the eighth stacked structure ST8.

[0156] The second page buffer region PB2 of the fifth memory chip structure may overlap with a region between the fifth stack structure ST5 and the seventh stack structure ST7 and a region between the sixth stack structure ST6 and the eighth stack structure ST8. The second page buffer region PB2 may be spaced apart from a region overlapping each of the fifth to eighth stack structures ST5 to ST8 by a second distance D2. The second page buffer region PB2 may be a region in which a page buffer connected to a bit line of a memory cell included in the second memory chip structure is disposed.

[0157] The fifth row decoder region XDEC2_5 and the sixth row decoder region XDEC2_6 of the fifth memory chip structure may overlap with the region between the fifth stacked structure ST5 and the sixth stacked structure ST6. The fifth row decoder region XDEC2_5 and the sixth row decoder region XDEC2_6 may be spaced apart by a first distance D1. The fifth row decoder region XDEC2_5 may be a region in which a row decoder of a word line connected to a memory cell formed in the fifth stacked structure ST5 is disposed. The sixth row decoder region XDEC2_6 may be a region in which a row decoder of a word line connected to a memory cell formed in the sixth stacked structure ST6 is disposed.

[0158] The seventh row decoder region XDEC2_7 and the eighth row decoder region XDEC2_8 of the fifth memory chip structure may overlap with the region between the seventh stacked structure ST7 and the eighth stacked structure ST8. The seventh row decoder region XDEC2_7 and the eighth row decoder region XDEC2_8 may be spaced apart by a first distance D1. The seventh row decoder region XDEC2_7 may be a region in which a row decoder of a word line connected to a memory cell formed in the seventh stacked structure ST7 is disposed. The eighth row decoder region XDEC2_8 may be a region in which a row decoder of a word line connected to a memory cell formed in the eighth stacked structure ST8 is disposed.

[0159] Figure 7C is a diagram showing an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure.

[0160] refer to Figure 7C , the first stacking structure ST1 of the first memory chip structure and the fifth stacking structure ST5 of the second memory chip structure may overlap with each other, the second stacking structure ST2 of the first memory chip structure and the seventh stacking structure ST7 of the second memory chip structure may overlap with each other, the third stacking structure ST3 of the first memory chip structure and the sixth stacking structure ST6 of the second memory chip structure may overlap with each other, and the fourth stacking structure ST4 of the first memory chip structure and the eighth stacking structure ST8 of the second memory chip structure may overlap with each other.

[0161] In addition, the extension direction of the first slit S1 and the extension direction of the fifth slit S5 can be orthogonal to each other, the extension direction of the second slit S2 and the extension direction of the seventh slit S7 can be orthogonal to each other, the extension direction of the third slit S3 and the extension direction of the sixth slit S6 can be orthogonal to each other, and the extension direction of the fourth slit S4 and the extension direction of the eighth slit S8 can be orthogonal to each other.

[0162] The area between the first stack structure ST1 and the second stack structure ST2 may overlap with the first row decoder region XDEC1_1, the second page buffer region PB2, and the second row decoder region XDEC1_2 of the fifth memory chip structure, and the second page buffer region PB2 among these areas may overlap with the OFC region OFC of the second memory chip structure.

[0163] The area between the third stack structure ST3 and the fourth stack structure ST4 may overlap with the third row decoder area XDEC1_3, the second page buffer area PB2, and the fourth row decoder area XDEC1_4 of the fifth memory chip structure, and the second page buffer area PB2 of these areas may overlap with the OFC area OFC of the second memory chip structure.

[0164] A region between the first stack structure ST1 and the third stack structure ST3 may overlap the fifth row decoder region XDEC2_5 , the first page buffer region PB1 , and the sixth row decoder region XDEC2_6 of the fifth memory chip structure.

[0165] A region between the second stack structure ST2 and the fourth stack structure ST4 may overlap the seventh row decoder region XDEC2_7 , the first page buffer region PB1 , and the eighth row decoder region XDEC2_8 of the fifth memory chip structure.

[0166] like Figure 3 As shown, a plurality of first source line layers respectively corresponding to the first to fourth stack structures ST1 to ST4 may be exposed on the top surface of the first memory chip structure.

[0167] like Figure 3 As shown, a plurality of second source line layers respectively corresponding to the fifth to eighth stack structures ST5 to ST8 may be exposed on the bottom surface of the second memory chip structure, and the plurality of first source lines and the plurality of second source lines may be in direct contact.

[0168] Fig. 8A , Figure 8B and Figure 8C is a diagram illustrating an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure according to still another embodiment of the present disclosure.

[0169] Fig. 8A is a diagram showing an overlapping area of ​​a first memory chip structure and a fifth memory chip structure.

[0170] refer to Fig. 8A , the first planar area P1 and the second planar area P2 of the first memory chip structure may be disposed side by side to be adjacent to each other in the first horizontal direction X. Each of the first planar area P1 and the second planar area P2 may include at least one stack structure.

[0171] The first slit S11 may extend in the first horizontal direction X perpendicular to the vertical direction Z and may pass through the stack structure included in the first and second planar regions P1 and P2 .

[0172] The first row decoder region XDEC1 of the fifth memory chip structure may be set to be adjacent to one side of the first plane region P1, and the second row decoder region XDEC2 may be set to be adjacent to one side of the second plane region P2. For example, the first row decoder region XDEC1 and the second row decoder region XDEC2 of the fifth memory chip structure may be spaced a certain distance apart from each other, and the area between the first row decoder region XDEC1 and the second row decoder region XDEC2 may overlap with the first plane region P1 and the second plane region P2 of the first memory chip structure. The first row decoder region XDEC1 may be an area in which a row decoder of a word line connected to a memory cell formed in the first plane region P1 is disposed. The second row decoder region XDEC2 may be an area in which a row decoder of a word line connected to a memory cell formed in the second plane region P2 is disposed. The area of ​​the first memory chip structure overlapping with the first row decoder region XDEC1 and the second row decoder region XDEC2 may be defined as an OFC area. The OFC region OFC may be a region in which lines connected to bit lines connected to cell plugs provided in the first and second plane regions P1 and P2 extend to a region of a lower fifth memory chip structure.

[0173] The first page buffer region PB1 of the fifth memory chip structure may overlap with the first plane region P1 of the first memory chip structure, and the second page buffer region PB2 of the fifth memory chip structure may overlap with the second plane region P2 of the first memory chip structure. The first page buffer region PB1 may be a region in which a page buffer of a bit line connected to a memory cell included in the first plane region P1 is disposed. The second page buffer region PB2 may be a region in which a page buffer of a bit line connected to a memory cell included in the second plane region P2 is disposed. The first page buffer region PB1 may be disposed at one end of the second horizontal direction Y in a region overlapping with the first plane region P1, and the second page buffer region PB2 may be disposed at the other end of the second horizontal direction Y in a region overlapping with the second plane region P2.

[0174] Figure 8B is a diagram showing an overlapping area of ​​the second memory chip structure and the fifth memory chip structure.

[0175] refer to Figure 8B , the third planar area P3 and the fourth planar area P4 of the second memory chip structure may be disposed side by side to be adjacent to each other in the second horizontal direction Y. Each of the third planar area P3 and the fourth planar area P4 may include at least one stacked structure.

[0176] The second slit S12 may extend in the second horizontal direction Y perpendicular to the vertical direction Z and may pass through the stack structure included in the third and fourth planar regions P3 and P4.

[0177] The third row decoder region XDEC3 of the fifth memory chip structure may be set adjacent to one side of the third plane region P3, and the fourth row decoder region XDEC4 may be set adjacent to one side of the fourth plane region P4. For example, the third row decoder region XDEC3 and the fourth row decoder region XDEC4 of the fifth memory chip structure may be set to be spaced a certain distance apart from each other, and the area between the third row decoder region XDEC3 and the fourth row decoder region XDEC4 may overlap with the third plane region P3 and the fourth plane region P4 of the second memory chip structure. The third row decoder region XDEC3 may be the following region: the region in which the row decoder of the word line connected to the memory cell formed in the third plane region P3 is set. The fourth row decoder region XDEC4 may be the following region: the region in which the row decoder of the word line connected to the memory cell formed in the fourth plane region P4 is set. The region of the second memory chip structure overlapping with the third row decoder region XDEC3 and the fourth row decoder region XDEC4 may be defined as an OFC region. The OFC region OFC may be a region in which lines connected to bit lines connected to cell plugs provided in the third and fourth plane regions P3 and P4 extend to a region of a lower fifth memory chip structure.

[0178] The third page buffer region PB3 of the fifth memory chip structure may overlap with the third plane region P3 of the second memory chip structure, and the fourth page buffer region PB4 of the fifth memory chip structure may overlap with the fourth plane region P4 of the second memory chip structure. The third page buffer region PB3 may be a region in which a page buffer of a bit line connected to a memory cell included in the third plane region P3 is disposed. The fourth page buffer region PB4 may be a region in which a page buffer of a bit line connected to a memory cell included in the fourth plane region P4 is disposed. The third page buffer region PB3 may be disposed at one end of the first horizontal direction X in a region overlapping with the third plane region P3, and the fourth page buffer region PB4 may be disposed at the other end of the first horizontal direction X in a region overlapping with the fourth plane region P4.

[0179] Figure 8C is a diagram showing an overlapping area of ​​a first memory chip structure, a second memory chip structure, and a fifth memory chip structure.

[0180] refer to Figure 8C , Fig. 8A The first plane region P1 may be aligned with the second memory chip structure Figure 8B A portion of the third plane region P3 and Figure 8B overlaps with a portion of the fourth plane region P4, and Fig. 8AThe second plane region P2 may be aligned with the second memory chip structure Figure 8B A portion of the third plane region P3 and Figure 8B overlaps with a portion of the fourth plane area P4.

[0181] In addition, the extending direction of the first slit S11 and the extending direction of the second slit S12 may be orthogonal to each other.

[0182] Each of the first row decoder area XDEC1 to the fourth row decoder area XDEC4 of the fifth memory chip structure can overlap with an external area, which is adjacent to the area of ​​the first memory chip structure overlapping with the first plane area P1 and the second plane area P2, or is adjacent to the area of ​​the second memory chip structure overlapping with the third plane area P3 and the fourth plane area P4.

[0183] Each of the first to fourth page buffer areas PB1 to PB4 of the fifth memory chip structure may overlap with an edge area, which is an edge area of ​​an area of ​​the first memory chip structure overlapping with the first plane area P1 and the second plane area P2, or an edge area of ​​an area of ​​the second memory chip structure overlapping with the third plane area P3 and the fourth plane area P4.

[0184] 9A to 9F , Fig.10 , Fig.11 and FIG. 12A to FIG. 12D is a simplified cross-sectional schematic diagram illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0185] 9A to 9F is a simplified cross-sectional schematic diagram illustrating the formation of a first memory chip structure.

[0186] refer to Fig.9A , the first material layers 111 and the second material layers 113 may be alternately stacked layer by layer on the first substrate 101 .

[0187] The first substrate 101 may be formed of a material having an etching rate different from that of the first material layer 111 and the second material layer 113. For example, the substrate 101 may include silicon.

[0188] In one embodiment, the first material layer 111 may be used for the above reference Figure 3The second material layer 113 may be a material having an etching rate different from that of the first material layer 111. For example, the first material layer 111 may include silicon oxide, and the second material layer 113 may include silicon nitride. The following figures show an embodiment in which the first material layer 111 is formed of an insulating material and the second material layer 113 is formed of a sacrificial layer, but the present disclosure is not limited thereto. The physical properties of the first material layer 111 and the second material layer 113 may be changed differently. For example, the first material layer 111 may be a material used for the above reference Figure 3 The insulating material of the interlayer dielectric layer ILD1 described above, and the second material layer 113 may be the insulating material used in the above reference Figure 3 A conductive material of the word line pattern WP1 is described.

[0189] refer to Fig. 9B , a first mask pattern 121 including a first opening 125 may be formed on a stack structure of the first material layer 111 and the second material layer 113. Thereafter, a channel hole 115 passing through the first material layer 111 and the second material layer 113 may be formed through the first opening 125 of the first mask pattern 121. The channel hole 115 may extend to a partial depth inside the first substrate 101. The channel hole 115 may be formed in various shapes according to an etching material used to form the channel hole 115.

[0190] In one embodiment, the channel hole 115 may be formed using a first etching material. The etching speed of the first material layer 111 and the second material layer 113 relative to the first etching material may be faster than the etching speed of the first substrate 101 relative to the first etching material. As a result, the width of the end of the channel hole 115 extending into the first substrate 101 may be formed to be narrower than the width of the channel hole 115 passing through the first material layer 111 and the second material layer 113.

[0191] refer to Fig. 9C , the memory layer 137 and the channel structure 147 may be formed inside the channel hole 115. Sidewalls of the channel structure 147 and ends of the channel structure 147 extending into the first substrate 101 may be surrounded by the memory layer 137.

[0192] Forming the memory layer 137 may include sequentially stacking a blocking insulating layer 135, a data storage layer 133, and a tunnel insulating layer 131 on a surface of the channel hole 115. The memory layer 137 may be formed in a pad shape, and a central area of ​​the channel hole 115 may be defined by the memory layer 137.

[0193] Thereafter, a channel structure 147 may be formed by forming a channel layer 141 on the surface of the memory layer 137. The channel layer 141 may include a semiconductor layer used as a channel region. For example, the channel layer 141 may include undoped polysilicon.

[0194] In one embodiment, the channel layer 141 may be formed in a pad shape, and the central area of ​​the channel hole 115 may include a portion where the channel layer 141 is not filled. When the channel layer 141 is formed in a pad shape, forming the channel structure 147 may include: filling the central area of ​​the channel hole 115 with the core insulating layer 143 on the channel layer 141; defining a recessed area in a portion of the central area of ​​the channel hole 115 by etching a portion of the core insulating layer 143; and filling the recessed area with the cap layer 145. The core insulating layer 143 may include an oxide, and the cap layer 145 may include a conductive dopant. The conductive dopant may include an n-type dopant for a junction. The conductive dopant may include a counter-doped p-type dopant.

[0195] In another embodiment, the channel layer 141 may be formed to fill the central region of the channel hole 115, and the core insulating layer 143 and the cap layer 145 may be omitted. When the core insulating layer 143 and the cap layer 145 are omitted, forming the channel structure 147 may further include doping the interior of the channel layer 141 with the above-mentioned conductive dopant.

[0196] Figure 3 The cell plug CP1 may be defined by including the above-described memory layer 137 and the channel structure 147 .

[0197] refer to Fig.9D , you can remove Fig. 9C The first mask pattern 121 is shown followed by forming a first insulating layer 151 .

[0198] Subsequently, a slit 153 may be formed. The slit 153 may pass through the first insulating layer 151 and may pass through the stacked structure of the first material layer 111 and the second material layer 113. The slit 153 may correspond to Figure 3 The second slit S2 is shown. Subsequently, a horizontal space 155 may be defined by selectively removing the second material layer 113 exposed by the slit 153. The horizontal space 155 may be defined between the first material layers 111 adjacent in the vertical direction.

[0199] refer to Fig.9E , Fig.9D The horizontal space 155 shown is filled with a conductive layer 157 through the slit 153. The conductive layer 157 can be the above reference Figure 3 The word line pattern WP1 is depicted. The conductive layer 157 may fill the horizontal space 155 to surround the channel structure 147 and the memory layer 137 .

[0200] As described above, by replacing the second material layer 113 as a sacrificial layer with the conductive layer 157 as a word line pattern, a lower stacked structure ST_U may be formed on the first substrate 101. The lower stacked structure ST_U may correspond to Figure 3 The lower stacked structure ST_U may include a structure in which the first material layer 111 as an interlayer insulating layer and the conductive layer 157 as a word line pattern are alternately stacked. The lower stacked structure ST_U may be penetrated by the channel structure 147, and the channel structure 147 may extend into the first substrate 101. The memory layer 137 may extend from an area between the channel structure 147 and the lower stacked structure ST_U to an area between an end of the channel structure 147 and the first substrate 101.

[0201] Reference above Figure 3 The first stacked structure ST1, the plurality of cell plugs CP1 and the second slit S2 described above can be referred to in detail. 9A to 9E Describe the process to form.

[0202] Subsequently, a sidewall insulating layer 161 covering the sidewalls of the lower stacked structure ST_U may be formed. Thereafter, a second insulating layer 163 filling the inside of the slit 153 and extending to cover the sidewall insulating layer 161 and the first insulating layer 151 may be formed.

[0203] refer to Fig.9F , a third insulating layer 171 may be formed on the second insulating layer 163. Subsequently, a contact plug 173 may be formed through the third insulating layer 171 or through the third insulating layer 171 and the second insulating layer 163. The contact plug 173 may extend to contact the corresponding channel structure 147.

[0204] Subsequently, a first line array 175 may be formed. The first line array 175 may be a bit line connected to the contact plug 173. The first line array 175 may correspond to Figure 3 bit line BL1.

[0205] Afterwards, a first insulating structure 181 covering the first line array 175 may be formed. The first insulating structure 181 may include two or more insulating layers 181A to 181D. The first connection structures 185, 189, 191, and 193 may be buried inside the first insulating structure 181, and the first connection structures 185, 189, 191, and 193 may be electrically connected through contact plugs (not shown).

[0206] The first connection structures 185, 189, 191, and 193 may include a bonding pad 193, a surface of which is exposed to the outside of the first insulating structure 181. The bonding pad 193 may correspond to Figure 3 The binding pad BP3.

[0207] Fig.10 is a simplified cross-sectional schematic diagram showing the structure of a fifth memory chip.

[0208] refer to Fig.10 , may include forming a plurality of transistors 200 configuring a complementary metal oxide semiconductor (CMOS) circuit on a second substrate 201 .

[0209] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or a selective layer formed by a selective epitaxial growth method.

[0210] Each of the transistors 200 may be formed in an active region of the second substrate 201 partitioned by the element isolation layer 203. Each of the transistors 200 may include a gate insulating layer 207 and a gate electrode 209 stacked on an active region corresponding thereto, and junctions 205a and 205b formed in the active region on both sides of the gate electrode 209. The junctions 205a and 205b may include a conductive dopant for realizing a transistor corresponding thereto. The junctions 205a and 205b may include at least one of an n-type dopant or a p-type dopant.

[0211] After forming the plurality of transistors 200 , a second connection structure 220 connected to the transistors 200 configuring the CMOS circuit and a second insulating structure 211 covering the second connection structure 220 and the transistors 200 may be formed.

[0212] The second insulating structure 211 may include two or more insulating layers 211A to 211D. The second connection structures 220 may be buried in the second insulating structure 211. Each of the second connection structures 220 may include a plurality of conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 are not limited to the embodiments shown in the drawings, and various changes may be made.

[0213] The conductive patterns 213, 215, 217, 219, 221, and 223 included in each of the second connection structures 220 may include a bonding pad 223, a surface of which is exposed to the outside of the second insulation structure 211. The bonding pad 223 may correspond to Figure 3 The binding pad BP4.

[0214] Fig.11is a simplified cross-sectional schematic diagram showing combining the first memory chip structure and the fifth memory chip structure with each other.

[0215] refer to Fig.11 The first substrate 101 and the second substrate 201 are aligned so that the bonding pads 193 on the first substrate 101 and the bonding pads 223 on the second substrate 201 contact each other. The bonding pads 193 and the bonding pads 223 may include various metals, and may include copper, for example.

[0216] After that, the bonding pads 193 and 223 are bonded to each other. To this end, after heat is applied to both the bonding pads 193 and 223, they may be hardened. However, in addition to thermal bonding, various other processes for connecting the bonding pads 193 and 223 may also be used.

[0217] FIG. 12A to FIG. 12D is a simplified cross-sectional schematic diagram showing formation of a second memory chip structure on a first memory chip structure.

[0218] refer to Fig. 12A , you can remove Fig.11 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 may be used as an etch stop layer. Therefore, the channel structure 147 protruding from the lower stack structure ST_U may be protected by the memory layer 137.

[0219] refer to Fig. 12B , an etching process is performed to etch the exposed memory layer 137 to expose the channel structure 147 protruding from the lower stacked structure ST_U. That is, the channel layer 141 protruding from the lower stacked structure ST_U is exposed.

[0220] Afterwards, a first source line layer 231 is formed to cover the lower stacked structure ST_U and the exposed channel layer 141. The first source line layer 231 may correspond to Figure 3 The first source line layer 231 may directly contact the channel layer 141. The first source line layer 231 may be formed of a doped polysilicon layer doped with a dopant.

[0221] refer to Fig. 12C , the second source line layer 233 may be formed on the first source line layer 231. The second source line layer 233 may correspond to Figure 3 The second source line layer SL2 may be formed of a doped polysilicon layer doped with a dopant.

[0222] Thereafter, the third material layers 235 and the fourth material layers 237 may be alternately stacked layer by layer on the second source line layer 233 .

[0223] In one embodiment, the third material layer 235 may be Fig.9A The first material layer 111 is the same material as the first material layer 111, and the fourth material layer 237 can be Fig.9A The second material layer 113 is made of the same material.

[0224] refer to Fig.12D ,exist Fig. 12C A plurality of channel structures 257 and a memory layer 249 extending in the vertical direction are formed in the third material layer 235 and the fourth material layer 237, and a plurality of channel structures 257 and a memory layer 249 extending in the vertical direction are formed. Fig. 12C The slit (not shown) between the third material layer 235 and the fourth material layer 237. Fig. 12C The slits of the third material layer 235 and the fourth material layer 237 may extend in a direction horizontally orthogonal to an extension direction of the slits 153 passing through the lower stacked structure ST_U.

[0225] The method of forming the plurality of channel structures 257 and the memory layer 249 and the method of forming the slits are similar to those described above with reference to FIG. 9B to FIG. 9D The method of forming the channel structure 147, the memory layer 137, and the slits 153 is described, and thus a detailed description is omitted.

[0226] Thereafter, the exposed portion through the slit (not shown) is removed. Fig. 12C The fourth material layer 237 is formed by filling the removed space with a conductive layer to form a word line pattern 259. As described above, the word line pattern 259 may be replaced by the word line pattern 259. Fig. 12C The fourth material layer 237 as a sacrificial layer is used to form an upper stacked structure ST_T.

[0227] Afterwards, the slits may be filled with an insulating material, and additional lines may be formed on the upper stack structure ST_T. The process of forming additional lines on the upper stack structure ST_T is similar to that described above with reference to Fig.9F A method of forming the contact plug 173 and the first line array 175 is described, and thus a detailed description is omitted.

[0228] Fig.13A and Fig. 13B is a simplified cross-sectional schematic diagram illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure.

[0229] Execute the above 9A to 9F , Fig.10 and Fig.11 The illustrated process operates to form a first memory chip structure and a fifth memory chip structure, and to couple the first memory chip structure and the fifth memory chip structure to each other.

[0230] refer to Fig.13A , you can remove Fig.11 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 may be used as an etch stop layer. Therefore, the channel structure 147 protruding from the lower stack structure ST_U may be protected by the memory layer 137.

[0231] Thereafter, an etching process may be performed to etch the exposed memory layer 137, thereby exposing the channel structure 147 protruding from the lower stacked structure ST_U. That is, the channel layer 141 protruding from the lower stacked structure ST_U is exposed.

[0232] Afterwards, a first source line layer 231 is formed to cover the lower stacked structure ST_U and the exposed channel layer 141. The first source line layer 231 may correspond to Figure 3 The first source line layer 231 directly contacts the channel layer 141. The first source line layer 231 may be formed of a doped polysilicon layer doped with a dopant.

[0233] Thereafter, a bonding pad BP is formed on the first source line layer 231. The bonding pad BP may be formed in the first source line layer 231, and thus a surface may be exposed.

[0234] The first memory chip structure 2100 and the third memory chip structure 2300 may be based on 9A to 9F , Fig.10 , Fig.11 and Fig. 12A The first memory chip structure 2100 and the third memory chip structure 2300 may be bonded to each other through a bonding structure.

[0235] In addition, the second memory chip structure 2200 and the fourth memory chip structure 2400 may be configured according to 9A to 9F , Fig.10 , Fig.11 and Fig. 12A The second memory chip structure 2200 and the fourth memory chip structure 2400 may be bonded to each other through a bonding structure.

[0236] refer to Fig. 13B , align the first source line layer SL1 of the first memory chip structure 2100 and the second source line layer SL2 of the second memory chip structure 2200 to face each other, and then perform a bonding process. At this time, they can be aligned so that the horizontal extension direction of the slit of the first memory chip structure 2100 and the horizontal extension direction of the slit of the second memory chip structure 2200 are orthogonal to each other.

[0237] Thereafter, a bonding process is performed to bond the first memory chip structure 2100 and the second memory chip structure 2200 .

[0238] Fig.14 is a diagram showing a memory card system to which the semiconductor memory device of the present disclosure is applied.

[0239] refer to Fig.14 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0240] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 may be configured to control the programming, reading or erasing operations of the memory device 3200, or to control background operations. The controller 3100 is configured to provide an interface between the memory device 3200 and the host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction circuit.

[0241] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device through at least one of various communication standards or interfaces, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards or interfaces mentioned above.

[0242] The memory device 3200 may include a plurality of semiconductor memory devices, and each of the plurality of semiconductor memory devices may be configured to communicate with Figure 1 The semiconductor memory device 100 shown is identical.

[0243] The controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), and a Universal Flash Storage (UFS).

[0244] Fig.15 is a diagram showing a solid state drive (SSD) system employing the semiconductor memory device of the present disclosure.

[0245] refer to Fig.15 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001, and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of semiconductor memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0246] The controller 4210 may control the plurality of semiconductor memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of a communication standard or an interface, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0247] The plurality of semiconductor memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of semiconductor memory devices 4221 to 422n may be configured to Figure 1 The semiconductor memory device 100 shown is the same. A plurality of memory devices 4221 to 422n may communicate with the controller 4210 through corresponding channels CH1 to CHn.

[0248] The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive a power supply voltage from the host 4100 and charge the power supply voltage. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide a power supply voltage for the SSD 4200. For example, the auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard, and may provide auxiliary power to the SSD 4200.

[0249] The buffer memory 4240 operates as a buffer memory of the SSD 4200 to temporarily store data received from the host 4100 or from one of the plurality of semiconductor memory devices 4221 to 422n. The buffer memory may also temporarily store metadata (e.g., a mapping table) of the semiconductor memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0250] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for purposes of description and not for purposes of limitation. In addition, it should be noted that the present disclosure may be implemented in various ways by substitutions, changes, and modifications that fall within the scope of the following claims, as will be recognized by those skilled in the art in light of the present disclosure. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor memory device, comprising: a first stacking structure; a plurality of first slits, passing through the first stacked structure in a vertical direction and extending in a first horizontal direction, wherein the first horizontal direction is orthogonal to the vertical direction; A first source line layer formed on top of the first stacked structure; a second source line layer formed on the first source line layer; a second stacking structure, overlapping with the first stacking structure in the vertical direction; as well as A plurality of second slits pass through the second stack structure in the vertical direction and extend in a second horizontal direction, wherein the second horizontal direction is orthogonal to the vertical direction. 2 . The semiconductor memory device according to claim 1 , wherein the first horizontal direction and the second horizontal direction are orthogonal to each other.

3. The semiconductor memory device according to claim 1, further comprising: a plurality of first cell plugs extending in the vertical direction within the first stacked structure and contacting the first source line layer; as well as A plurality of second cell plugs extend in the vertical direction within the second stack structure and contact the second source line layer.

4. The semiconductor memory device according to claim 1, wherein each of the first stack structure and the second stack structure comprises: Interlayer insulating layers and word line patterns are alternately stacked in the vertical direction.

5. The semiconductor memory device according to claim 1, further comprising: The memory chip structure includes a peripheral circuit located below the first stacking structure.

6. The semiconductor memory device according to claim 1, further comprising: a lower memory chip structure, comprising a first peripheral circuit located below the first stacked structure, the first peripheral circuit being used to operate a memory cell included in the first stacked structure; as well as The upper memory chip structure includes a second peripheral circuit located on the second stack structure, and the second peripheral circuit is used to operate the memory cells included in the second stack structure.

7. A semiconductor memory device comprising: A first memory chip structure includes a first planar region and a second planar region, wherein the first planar region and the second planar region each include a plurality of first stacked structures; a second memory chip structure bonded to a top surface of the surface of the first memory chip structure in a vertical direction and including a third planar region and a fourth planar region, the third planar region and the fourth planar region each including a plurality of second stacked structures; as well as a third memory chip structure, coupled to the bottom surface of the first memory chip structure in the vertical direction, and comprising a first page buffer region and a second page buffer region and a first row decoder region and a second row decoder region, page buffers for controlling operations of memory cells included in the first memory chip structure and the second memory chip structure are arranged at the first page buffer region and the second page buffer region, and row decoders for controlling the operations of the memory cells are arranged at the first row decoder region and the second row decoder region, wherein the first memory chip structure comprises a first slit, the first slit passes through the plurality of first stacked structures in the vertical direction and extends in a first horizontal direction, the first horizontal direction being orthogonal to the vertical direction, and The second memory chip structure includes a second slit, which passes through the plurality of second stacked structures in the vertical direction and extends in a second horizontal direction, and the second horizontal direction is orthogonal to the vertical direction and the first horizontal direction.

8. The semiconductor memory device according to claim 7, wherein a plurality of first source line layers corresponding to the respective plurality of first stack structures are exposed on a top surface of the surface of the first memory chip structure, wherein a plurality of second source line layers corresponding to the plurality of second stacked structures are exposed on the bottom surface of the second memory chip structure, and The plurality of first source line layers and the plurality of second source line layers are in direct contact with each other.

9. The semiconductor memory device according to claim 7, wherein the first row decoder region where the first row decoder for controlling the memory cells included in the first memory chip structure is disposed overlaps with: a region between the plurality of first stacked structures of the first plane region, and a region between the plurality of first stacked structures of the second plane region, and The second row decoder area where the second row decoder for controlling the memory cells included in the second memory chip structure is arranged overlaps with the following items: the area between the multiple second stacked structures in the third plane area, and the area between the multiple second stacked structures in the fourth plane area.

10. The semiconductor memory device according to claim 9, wherein the first page buffer region where the first page buffer for controlling the memory unit included in the first memory chip structure is disposed overlaps with at least one first stack structure of the plurality of first stack structures, and The second page buffer area where the second page buffer for controlling the memory unit included in the second memory chip structure is set overlaps with the following items: the area between the multiple first stacked structures in the first plane area, and the area between the multiple first stacked structures in the second plane area. 11 . The semiconductor memory device according to claim 10 , wherein the first row decoder region and the second page buffer region are disposed adjacent to each other.

12. A semiconductor memory device comprising: A first memory chip structure includes a first stacking structure, a second stacking structure, a third stacking structure, and a fourth stacking structure arranged in a matrix form; a second memory chip structure, coupled to the top surface of the first memory chip structure in a vertical direction, and comprising a fifth stacking structure, a sixth stacking structure, a seventh stacking structure, and an eighth stacking structure arranged in the matrix form; as well as a third memory chip structure, coupled to the bottom surface of the first memory chip structure in the vertical direction, and including a first page buffer region and a second page buffer region in which page buffers for controlling operations of memory cells included in the first memory chip structure and the second memory chip structure are disposed, and including a first row decoder region, a second row decoder region, a third row decoder region, a fourth row decoder region, a fifth row decoder region, a sixth row decoder region, a seventh row decoder region, and an eighth row decoder region in which row decoders for controlling the operations of the memory cells are disposed, The first memory chip structure includes a first slit, the first slit passes through the first stacking structure to the fourth stacking structure in the vertical direction and extends in a first horizontal direction, the first horizontal direction is orthogonal to the vertical direction, and The second memory chip structure includes a second slit, which passes through the fifth stacking structure to the eighth stacking structure in the vertical direction and extends in a second horizontal direction, and the second horizontal direction is orthogonal to the vertical direction and the first horizontal direction.

13. The semiconductor memory device according to claim 12, wherein a plurality of first source line layers corresponding to each of the first to fourth stacked structures are exposed on a top surface of the first memory chip structure, wherein a plurality of second source line layers corresponding to each of the fifth to eighth stacked structures are exposed on a bottom surface of the second memory chip structure, and The plurality of first source line layers and the plurality of second source line layers are in direct contact with each other.

14. The semiconductor memory device according to claim 12, The first row decoder region and the second row decoder region where the row decoders corresponding to the first stacking structure and the second stacking structure are respectively arranged overlap with the region between the first stacking structure and the second stacking structure, wherein the third row decoder region and the fourth row decoder region where the row decoders corresponding to the third stacking structure and the fourth stacking structure are respectively arranged overlap with the region between the third stacking structure and the fourth stacking structure, wherein the fifth row decoder region and the sixth row decoder region where the row decoders corresponding to the fifth stacking structure and the sixth stacking structure are disposed overlap with the region between the fifth stacking structure and the sixth stacking structure, and The seventh row decoder region and the eighth row decoder region where the row decoders corresponding to the seventh stacking structure and the eighth stacking structure are respectively arranged overlap with the region between the seventh stacking structure and the eighth stacking structure.

15. The semiconductor memory device according to claim 14, wherein the first page buffer region where the first page buffer for controlling the memory unit included in the first memory chip structure is arranged is arranged between the fifth row decoder region and the sixth row decoder region or between the seventh row decoder region and the eighth row decoder region, and The second page buffer area where the second page buffer for controlling the memory unit included in the second memory chip structure is set is set between the first row decoder area and the second row decoder area or between the third row decoder area and the fourth row decoder area.

16. A semiconductor memory device comprising: A first memory chip structure includes a first planar region and a second planar region, wherein the first planar region and the second planar region each include a plurality of first stacked structures; a second memory chip structure bonded to a top surface of the surface of the first memory chip structure in a vertical direction and including a third planar region and a fourth planar region, the third planar region and the fourth planar region each including a plurality of second stacked structures; as well as a third memory chip structure, coupled to the bottom surface of the first memory chip structure in the vertical direction, and including a first page buffer region, a second page buffer region, a third page buffer region, and a fourth page buffer region in which page buffers for controlling operations of memory cells included in the first memory chip structure and the second memory chip structure are disposed, and including first to fourth row decoder regions in which row decoders for controlling the operations of the memory cells are disposed, wherein the first memory chip structure comprises a first slit, the first slit passes through the plurality of first stacked structures in the vertical direction and extends in a first horizontal direction, the first horizontal direction being orthogonal to the vertical direction, and The second memory chip structure includes a second slit, which passes through the plurality of second stacked structures in the vertical direction and extends in a second horizontal direction, and the second horizontal direction is orthogonal to the vertical direction and the first horizontal direction.

17. The semiconductor memory device according to claim 16, wherein a plurality of first source line layers corresponding to the respective plurality of first stack structures are exposed on a top surface of the surface of the first memory chip structure, wherein a plurality of second source line layers corresponding to the plurality of second stacked structures are exposed on the bottom surface of the second memory chip structure, and The plurality of first source line layers and the plurality of second source line layers are in direct contact with each other.

18. The semiconductor memory device according to claim 16, wherein the first to fourth row decoder regions overlap with an external region, the external region being adjacent to the first and second plane regions, or adjacent to the third and fourth plane regions.

19. The semiconductor memory device according to claim 16, wherein the first page buffer region in which the first page buffer for controlling the memory cells included in the first plane region is disposed is disposed to overlap with a region where the first plane region and the third plane region overlap, wherein the second page buffer region in which the second page buffer for controlling the memory cells included in the second plane region is disposed is disposed to overlap with a region where the second plane region and the fourth plane region overlap, wherein the third page buffer region in which the third page buffer for controlling the memory cells included in the third plane region is disposed is disposed to overlap with a region where the second plane region and the third plane region overlap, and The fourth page buffer region, in which a fourth page buffer for controlling the memory cells included in the fourth plane region is disposed, is disposed to overlap with a region where the first plane region and the fourth plane region overlap.

20. A method of manufacturing a semiconductor memory device, the method comprising: forming a first stacked structure, and forming a lower stacked structure including first interlayer insulating layers and second word line patterns alternately stacked in a vertical direction, a first cell plug having an end extending upward by passing through the lower stacked structure, a plurality of first slits extending in a first horizontal direction orthogonal to the vertical direction by passing through the lower stacked structure in the vertical direction, and a first source line layer stacked on the lower stacked structure and connected to the end of the first cell plug through the first stacked structure; as well as A second stacking structure is formed on the first stacking structure, and a second source line layer directly contacting the first source line layer is formed, an upper stacking structure including a second interlayer insulating layer and a third word line pattern alternately stacked in the vertical direction, a second cell plug extending downward by passing through the upper stacking structure and having an end contacting the second source line layer, and a plurality of second slits extending in a second horizontal direction by passing through the upper stacking structure in the vertical direction, wherein the second horizontal direction is orthogonal to the vertical direction and the first horizontal direction.

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