Resistive random access memory manufacturing method and resistive random access memory chip

Abstract

The invention discloses a resistive random access memory manufacturing method, a resistive random access memory chip manufactured by the resistive random access memory manufacturing method comprises a first resistive random access memory unit and a second resistive random access memory unit, a resistive random layer of the first resistive random access memory unit comprises a high-voltage material layer, and a resistive random layer of the second resistive random access memory unit is a high-dielectric constant material layer. The first resistive random access memory unit has the characteristic of long storage time due to the fact that the resistive random layer comprises the high-voltage material layer, and the second resistive random access memory unit has the characteristics of fast response and high operation speed due to the fact that the resistive random layer is the high-dielectric-constant material layer. According to the manufacturing method of the resistive random access memory, the two resistive random access memory units can be subjected to process integration through the innovative process, and the manufactured resistive random access memory chip can meet the requirements of two performances.

Description

Technical Field

[0001] The present invention relates to memory technology, and in particular to a resistive random access memory manufacturing method and a resistive random access memory chip. Background Art

[0002] Resistive random access memory (RRAM) is a forward-looking next-generation non-volatile memory based on the reversible conversion of the material's resistance between a high-resistance state and a low-resistance state under an applied electric field. It has the potential to replace the existing mainstream Flash memory at the 32nm node and below, and has become an important research direction for new types of memory.

[0003] A typical "sandwich" (MIM) structure RRAM device has a resistive switching layer material between the upper and lower electrodes that can undergo resistance transition. Under the action of an external bias, the resistance of the device will switch between high and low resistance states, thereby realizing the storage of "0" and "1". Unlike the charge storage mechanism of traditional floating gate Flash, RRAM is a non-charge storage mechanism, so it can solve the charge leakage problem caused by the thinning of the tunneling oxide layer in Flash and has better scalability.

[0004] The current typical RRAM structure design has a resistive layer between the top plate (TP) and the bottom plate (TP). The resistive layer usually uses HK (High k, high dielectric constant) materials such as HfOx, TaOx and TiOx. The characteristics of HK resistive layer RRAM are fast response and high computing speed, which can be used for artificial intelligence applications. However, the disadvantage of HK resistive layer RRAM as a memory is that its durability is relatively poor. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a resistive random access memory (RRAM) manufacturing method, wherein the manufactured resistive random access memory (RRAM) chip includes a first resistive random access memory unit having the characteristics of long storage time and a second resistive random access memory unit having the characteristics of fast response and high computing speed, thereby meeting the requirements of both performances.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a resistive random access memory, which comprises the following steps:

[0007] S1. forming a lower interlayer dielectric layer 1 on the substrate, completing the metal layer process, forming a first region lower metal layer 11 and a second region lower metal layer 12 in the lower interlayer dielectric layer 1; the upper surfaces of the first region lower metal layer 11 and the second region lower metal layer 12 are flush with the lower interlayer dielectric layer 1;

[0008] S2. A barrier layer 2 is covered on the lower interlayer dielectric layer 1, the lower metal layer 11 in the first region and the lower metal layer 12 in the second region;

[0009] S3. forming contact holes in the barrier layer 2 respectively connected to the metal layer 11 under the first region and the metal layer 12 under the second region;

[0010] S4. Depositing a bottom electrode layer 3 on the wafer, the bottom electrode layer 3 is short-connected to the lower metal layer 11 of the first region and the lower metal layer 12 of the second region through contact holes;

[0011] S5. Depositing a high voltage material layer 4 on the bottom electrode layer 3;

[0012] S6. By means of a photolithography / etching process, a high-voltage region is defined, the high-voltage region is located directly above the metal layer 11 under the first region, the high-voltage material layer 4 outside the high-voltage region is removed, and the high-voltage material layer 4 at the high-voltage region is retained;

[0013] S7. Depositing a high dielectric constant material layer 5 on the wafer;

[0014] S8. By means of a photolithography / etching process, a high dielectric constant region is defined, the high dielectric constant region is located directly above the metal layer 12 under the second region, the high dielectric constant material layer 5 outside the high voltage region and the high dielectric constant region is removed, and the high dielectric constant material layer 5 in the high voltage region and the high dielectric constant region is retained; or, the high dielectric constant material layer 5 outside the high dielectric constant region is removed, and only the high dielectric constant material layer 5 in the high dielectric constant region is retained;

[0015] S9. Depositing a top electrode layer 6 on the wafer;

[0016] S10. By photolithography / etching process, the top electrode layer 6 outside the high voltage region and the high dielectric constant region is removed, and the top electrode layer 6 in the high voltage region and the high dielectric constant region is retained;

[0017] S11 . Perform subsequent processes to form a first type of resistive memory cell whose resistive switching layer includes a high voltage material layer 4 and a second type of resistive memory cell whose resistive switching layer includes a high dielectric constant material layer 5 on the same chip.

[0018] Preferably, step S11 includes the following steps:

[0019] S111. Depositing a surface protection layer 7 on the wafer;

[0020] S112. Depositing a low dielectric constant material layer 8 on the surface protection layer 7;

[0021] S113. Planarization of the low dielectric constant material layer 8 is achieved by CMP;

[0022] S114. Form a first region upper metal layer 91 short-connected to the top electrode layer 6 at the high voltage region through the contact hole above the low dielectric constant material layer 8, and a second region upper metal layer 92 short-connected to the top electrode layer 6 at the high dielectric constant region through the contact hole.

[0023] Preferably, the high voltage material layer 4 is silicon nitride or silicon oxide.

[0024] Preferably, the thickness of the high-pressure material layer 4 is

[0025] Preferably, the high dielectric constant material layer 5 is hafnium oxide HfOx, tantalum oxide TaOx, titanium oxide TiOx or zirconium oxide ZrO2.

[0026] Preferably, the thickness of the high dielectric constant material layer 5 is

[0027] Preferably, the thickness of the high-pressure material layer 4 is

[0028] The thickness of the high dielectric constant material layer 5 is

[0029] Preferably, the surface protection layer 7 is silicon nitride or silicon oxide;

[0030] The low dielectric constant layer 8 is porous silicon oxide, silicon nitride or silicon oxynitride;

[0031] The bottom electrode layer 3 is TiN, W, Pt or Pd;

[0032] The top electrode layer 6 is TiN, Ti, Al or W;

[0033] The barrier layer 2 is nitrogen-doped silicon carbide;

[0034] The lower interlayer dielectric layer 1 is made of silicon dioxide, silicon nitride, silicon oxynitride, fluorinated silicon glass, carbon-doped silicon oxide or nitrogen-doped silicon oxide;

[0035] The first region lower metal layer 11 and the second region lower metal layer 12 are made of copper.

[0036] In order to solve the above technical problems, the present invention provides a resistive memory chip, which includes a first resistive memory unit and a second resistive memory unit;

[0037] The resistive switching layer of the first resistive switching memory cell includes a high voltage material layer 4;

[0038] The resistive switching layer of the second resistive switching memory unit is a high dielectric constant material layer 5 .

[0039] Preferably, the high voltage material layer 4 is silicon nitride or silicon oxide;

[0040] The high dielectric constant material layer 5 is hafnium oxide HfOx, tantalum oxide TaOx, titanium oxide TiOx or zirconium oxide ZrO2.

[0041] The resistive random access memory (RRAM) manufacturing method of the present invention, the resistive random access memory (RRAM) chip manufactured by the resistive random access memory (RRAM) chip includes a first resistive random access memory unit and a second resistive random access memory unit, the resistive random access layer of the first resistive random access memory unit includes a high voltage (High Voltage) material layer 4, and the resistive random access layer of the second resistive random access memory unit is a high dielectric constant (HK) material layer 5. The first resistive random access memory unit has the characteristics of long storage time because its resistive random access layer includes the high voltage (High Voltage) material layer 4, and the second resistive random access memory unit has the characteristics of fast response and high computing speed because its resistive random access layer is the high dielectric constant (HK) material layer 5. The resistive random access memory (RRAM) manufacturing method innovates the process flow, so that the two resistive random access memory (RRAM) units can be integrated in the process, and the manufactured resistive random access memory (RRAM) chip includes the first resistive random access memory unit with the characteristics of long storage time and the second resistive random access memory unit with the characteristics of fast response and high computing speed, so that the manufactured resistive random access memory (RRAM) chip can take into account the requirements of both performances. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figures 1 to 10 It is a process diagram of the resistive random access memory manufacturing method of the present invention.

[0044] Description of reference numerals:

[0045] 1 lower interlayer dielectric layer; 11 lower metal layer of the first region; 12 lower metal layer of the second region; 2 barrier layer; 3 bottom electrode metal layer; 4 high voltage material layer; 5 high dielectric constant material layer; 6 top electrode metal layer; 7 surface protection layer; 8 low dielectric constant material layer; 91 upper metal layer of the first region; 92 upper metal layer of the second region. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "front", "back" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0048] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0049] Embodiment 1

[0050] A method for manufacturing a resistive random access memory (RRAM), such as Figures 1 to 7 As shown, the following steps are included:

[0051] S1. forming a lower interlayer dielectric layer 1 on the substrate, completing a metal layer process (Mx Process), forming a first region lower metal layer 11 and a second region lower metal layer 12 in the lower interlayer dielectric layer 1; the upper surfaces of the first region lower metal layer 11 and the second region lower metal layer 12 are flush with the lower interlayer dielectric layer 1;

[0052] S2. Covering a barrier layer 2 on the lower interlayer dielectric layer 1, the lower metal layer 11 in the first region and the lower metal layer 12 in the second region, such as Figure 1 As shown;

[0053] S3. forming contact holes in the barrier layer 2 that are connected to the metal layer 11 in the first region and the metal layer 12 in the second region, respectively, such as Figure 2 As shown;

[0054] S4. Depositing a bottom plate metal layer 3 on the wafer, the bottom plate metal layer 3 is short-connected to the lower metal layer 11 of the first region and the lower metal layer 12 of the second region through contact holes;

[0055] S5. Depositing a high voltage material layer 4 on the bottom plate metal layer 3, such as Figure 3 As shown;

[0056] S6. A high voltage (HV) region is defined by a photolithography / etching (PH / ET) process. The high voltage (HV) region is located directly above the metal layer 11 under the first region. The high voltage (HV) material layer 4 outside the high voltage (HV) region is removed, and the high voltage (HV) material layer 4 in the high voltage (HV) region is retained. Figure 3 As shown;

[0057] S7. Depositing HK (High k, high dielectric constant) material layer 5 on the wafer, such as Figure 5 As shown;

[0058] S8. A high dielectric constant (HK) region is defined by a photolithography / etching (PH / ET) process, the high dielectric constant (HK) region is located directly above the metal layer 12 under the second region, the HK (High k) material layer 5 outside the high voltage (HV) region and the high dielectric constant (HK) region is removed, and the HK (High k) material layer 5 at the high voltage (HV) region and the high dielectric constant (HK) region is retained; or, the HK (High k) material layer 5 outside the high dielectric constant (HK) region is removed, and only the HK (High k) material layer 5 at the high dielectric constant (HK) region is retained, such as Figure 6 As shown;

[0059] S9. Depositing a top plate metal layer 6 on the wafer, such as Figure 7 As shown;

[0060] S10. Remove the top plate metal layer 6 outside the high voltage (HV) region and the high dielectric constant (HK) region through a photolithography / etching (PH / ET) process, and retain the top plate metal layer 6 in the high voltage (HV) region and the high dielectric constant (HK) region, such as Figure 8 As shown;

[0061] S11 . Perform subsequent processes to form a first type of resistive memory cell whose resistive switching layer includes a high voltage material layer 4 and a resistive memory cell whose resistive switching layer is a high dielectric constant (HK) material layer 5 on the same chip.

[0062] The resistive random access memory (RRAM) manufacturing method of the first embodiment, the resistive random access memory (RRAM) chip manufactured by the manufacturing method includes a first resistive random access memory unit and a second resistive random access memory unit, the resistive random access memory unit of the first resistive random access memory unit includes a high voltage (High Voltage) material layer 4, and the resistive random access memory unit of the second resistive random access memory unit is a high dielectric constant (HK) material layer 5. The first resistive random access memory unit has the characteristics of long storage time because its resistive random access memory layer includes the high voltage (High Voltage) material layer 4, and the second resistive random access memory unit has the characteristics of fast response and high computing speed because its resistive random access memory layer is the high dielectric constant (HK) material layer 5.

[0063] The resistive random access memory (RRAM) manufacturing method of the first embodiment innovates the process flow so that two resistive random access memory (RRAM) units can be process-integrated. The manufactured resistive random access memory (RRAM) chip includes both the first resistive random access memory unit with the characteristics of long storage time and the second resistive random access memory unit with the characteristics of fast response and high computing speed, so that the manufactured resistive random access memory (RRAM) can meet the requirements of both performances.

[0064] Embodiment 2

[0065] Based on the resistive random access memory (RRAM) manufacturing method of the first embodiment, step S11 includes the following steps:

[0066] S111. Depositing a surface protection layer 7 on the wafer, such as Fig. 9 As shown;

[0067] S112. Depositing a low dielectric constant (Low K) material layer 8 on the surface protection layer 7;

[0068] S113. Planarizing the low dielectric constant (Low K) material layer 8 by CMP (chemical mechanical polishing);

[0069] S114. A first region upper metal layer 91 is formed on the low dielectric constant (Low K) material layer 8 and is shorted to the top electrode (top plate) layer 6 at the high voltage (HV) region through the contact hole, and a second region upper metal layer 92 is formed on the top electrode (top plate) layer 6 at the high dielectric (HK) region through the contact hole, as shown in FIG. Fig.10 shown.

[0070] Preferably, the high voltage material layer 4 is silicon nitride or silicon oxide.

[0071] Preferably, the thickness of the high voltage material layer 4 is (For example, the thickness of the high-pressure material layer is ).

[0072] Preferably, the HK (High k, high dielectric constant) material layer 5 is hafnium oxide HfOx, tantalum oxide TaOx, titanium oxide TiOx or zirconium oxide ZrO2, etc.

[0073] Preferably, the thickness of the HK (High k, high dielectric constant) material layer 5 is (For example, the thickness of the HK material layer is ).

[0074] Preferably, the surface protection layer 7 is silicon nitride or silicon oxide.

[0075] Preferably, the low dielectric constant (Low K) layer 8 is porous silicon oxide, silicon nitride or silicon oxynitride.

[0076] Preferably, the bottom plate layer 3 is made of materials such as TiN, W, Pt or Pd;

[0077] Preferably, the top plate layer 6 is made of TiN, Ti, Al or other materials.

[0078] Preferably, the barrier layer 2 is NDC (N Doped SiC, nitrogen doped silicon carbide).

[0079] Preferably, the lower interlayer dielectric layer 1 is made of silicon dioxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), carbon-doped silicon oxide, nitrogen-doped silicon oxide, etc.

[0080] Preferably, the first region lower metal layer 11 and the second region lower metal layer 12 are copper.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a resistive random access memory, characterized in that: The following steps are involved: S1. forming a lower interlayer dielectric layer (1) on a substrate, completing a metal layer process, and forming a first-region lower metal layer (11) and a second-region lower metal layer (12) in the lower interlayer dielectric layer (1); the upper surfaces of the first-region lower metal layer (11) and the second-region lower metal layer (12) are flush with the lower interlayer dielectric layer (1); S2. Covering a barrier layer (2) on the lower interlayer dielectric layer (1), the lower metal layer (11) of the first region and the lower metal layer (12) of the second region; S3. forming contact holes in the barrier layer (2) that are connected to the metal layer (11) under the first region and the metal layer (12) under the second region respectively; S4. Depositing a bottom electrode layer (3) on the wafer, the bottom electrode layer (3) is short-connected to the lower metal layer (11) of the first region and the lower metal layer (12) of the second region through contact holes; S5. depositing a high voltage material layer (4) on the bottom electrode layer (3); S6. By means of a photolithography / etching process, a high-voltage region is defined, the high-voltage region is located directly above the metal layer (11) under the first region, the high-voltage material layer (4) outside the high-voltage region is removed, and the high-voltage material layer (4) at the high-voltage region is retained; S7. Depositing a high dielectric constant material layer (5) on the wafer; S8. By means of a photolithography / etching process, a high dielectric constant region is defined, the high dielectric constant region is located directly above the metal layer (12) under the second region, the high dielectric constant material layer (5) outside the high voltage region and the high dielectric constant region is removed, and the high dielectric constant material layer (5) in the high voltage region and the high dielectric constant region is retained; or, the high dielectric constant material layer (5) outside the high dielectric constant region is removed, and only the high dielectric constant material layer (5) in the high dielectric constant region is retained; S9. depositing a top electrode layer (6) on the wafer; S10. By means of a photolithography / etching process, the top electrode layer (6) outside the high voltage region and the high dielectric constant region is removed, and the top electrode layer (6) in the high voltage region and the high dielectric constant region is retained; S11. Perform subsequent processes to form a first type of resistive memory unit whose resistive switching layer includes a high voltage material layer (4) and a second type of resistive memory unit whose resistive switching layer is a high dielectric constant material layer (5) on the same chip.

2. The method for manufacturing a resistive random access memory according to claim 1, wherein: Step S11 includes the following steps: S111. Depositing a surface protection layer (7) on the wafer; S112. Depositing a low dielectric constant material layer (8) on the surface protection layer (7); S113. Planarizing the low dielectric constant material layer (8) by CMP; S114. A first region upper metal layer (91) is formed above the low dielectric constant material layer (8) and is short-connected to the top electrode layer (6) at the high voltage region through the contact hole, and a second region upper metal layer (92) is short-connected to the top electrode layer (6) at the high dielectric constant region through the contact hole.

3. The method for manufacturing a resistive random access memory according to claim 1, wherein: The high-voltage material layer (4) is silicon nitride or silicon oxide.

4. The method for manufacturing a resistive random access memory according to claim 1, wherein: The thickness of the high-pressure material layer (4) is 5. The method for manufacturing a resistive random access memory according to claim 1, wherein: The high dielectric constant material layer (5) is hafnium oxide HfOx, tantalum oxide TaOx, titanium oxide TiOx or zirconium oxide ZrO2.

6. The method for manufacturing a resistive random access memory according to claim 1, wherein: The thickness of the high dielectric constant material layer (5) is 7. The method for manufacturing a resistive random access memory according to claim 1, wherein: The thickness of the high-pressure material layer (4) is The thickness of the high dielectric constant material layer (5) is 8. The method for manufacturing a resistive random access memory according to claim 2, wherein: The surface protection layer (7) is silicon nitride or silicon oxide; The low dielectric constant layer (8) is porous silicon oxide, silicon nitride or silicon oxynitride; The bottom electrode layer (3) is TiN, W, Pt or Pd; The top electrode layer (6) is TiN, Ti, Al or W; The barrier layer (2) is nitrogen-doped silicon carbide; The lower interlayer dielectric layer (1) is silicon dioxide, silicon nitride, silicon oxynitride, fluorinated silicon glass, carbon-doped silicon oxide or nitrogen-doped silicon oxide; The first region lower metal layer (11) and the second region lower metal layer (12) are copper.

9. A resistive memory chip, characterized in that: It includes a first resistive memory unit and a second resistive memory unit; The resistive switching layer of the first resistive switching memory unit includes a high voltage material layer (4); The resistive switching layer of the second resistive switching memory unit is a high dielectric constant material layer (5).

10. The resistive memory chip according to claim 9, characterized in that: The high-voltage material layer (4) is silicon nitride or silicon oxide; The high dielectric constant material layer (5) is hafnium oxide HfOx, tantalum oxide TaOx, titanium oxide TiOx or zirconium oxide ZrO2.

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