Integrated circuit (IC) structure and method of forming same

Abstract

One aspect of the disclosure relates to an integrated circuit (IC) structure and a method of forming the same. The IC structure may include a first plurality of thermal vias disposed at a first pitch and a third plurality of thermal vias disposed at a second pitch, the second pitch being greater than the first pitch.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit (IC) structures and methods of forming the same. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. In order to meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance and low-power ICs. To date, these goals have been achieved to a large extent by reducing the IC size (e.g., minimum IC component size), thereby improving production efficiency and reducing related costs. However, such scaling also increases the complexity of IC manufacturing processes. Therefore, achieving continuous progress in IC devices and their performance requires similar progress in IC manufacturing processes and technologies.

[0003] As technology nodes become smaller, ICs can be stacked vertically to form so-called three-dimensional (3D) IC structures. In addition to shrinking the density of transistors in a given die, by arranging semiconductor devices in 3 dimensions (e.g., vertically stacking dies), the semiconductor devices in the structure can be placed closer to each other. This can reduce line lengths and minimize delays and resistance.

[0004] Thus, while existing IC structures having stacked ICs are generally adequate for their intended purposes, they are not completely satisfactory in every respect. Summary of the invention

[0005] Some embodiments of the present application provide an integrated circuit structure, including: a first die, the first die including: a first transistor device formed on a substrate; a first multilayer interconnect located above the substrate, wherein the first multilayer interconnect includes a plurality of metal lines and intermediate metal vias, wherein the first multilayer interconnect is electrically coupled to the first transistor device; and a first plurality of thermal vias laterally adjacent to the first multilayer interconnect; a thermal bonding layer located above the first die; and a second die located above the thermal bonding layer, the second die including: a second transistor device formed on another substrate; a second multilayer interconnect located above the another substrate, wherein the second multilayer interconnect includes a plurality of metal lines and intermediate metal vias, wherein the second multilayer interconnect is electrically coupled to the second transistor device; and a second plurality of thermal vias laterally adjacent to the second multilayer interconnect, wherein the second plurality of thermal vias is less than the first plurality of thermal vias.

[0006] Other embodiments of the present application provide an integrated circuit structure comprising: a plurality of vertically stacked dies; a thermal bonding layer extending between a first die and a second die of the plurality of vertically stacked dies, wherein the thermal bonding layer comprises a material having a thermal conductivity between approximately 10 and 500 W / m / K; and a plurality of thermal vias located on at least one of the first die or the second die, wherein the plurality of thermal vias are arranged adjacent to a high-power transistor device.

[0007] Still other embodiments of the present application provide a method for forming an integrated circuit structure, comprising: forming a first transistor device on a first die, and forming a second transistor device on a second die; forming a first plurality of thermal vias on the first die adjacent to the first transistor device, and forming a second plurality of thermal vias on the second die adjacent to the second transistor device, wherein the first plurality of thermal vias have an area larger than that of the second plurality of thermal vias; depositing a thermal bonding layer on a surface of the first die; and attaching the second die to the thermal bonding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustrative purposes only. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion. It is also emphasized that the accompanying drawings illustrate only typical embodiments of the disclosed embodiments and, therefore, should not be considered as limiting the scope, as the disclosed embodiments may be equally well adapted to other embodiments. In addition, the accompanying drawings may implicitly describe components that are not explicitly described in the detailed description.

[0009] Figure 1 A perspective view of an integrated circuit (IC) structure having multiple stacked dies with thermal vias and thermal bonding layers according to an embodiment of the present disclosure is shown.

[0010] Figure 2A A cross-sectional view of an IC structure having a first exemplary configuration of dies according to an embodiment of the present disclosure is shown.

[0011] Figure 2B A cross-sectional view of an IC structure having a first configuration of dies and another embodiment of a thermal bonding layer according to an embodiment of the disclosure is shown.

[0012] Figure 3 A cross-sectional view of an IC structure having a second exemplary configuration of dies according to an embodiment of the present disclosure is shown.

[0013] Figure 4 A cross-sectional view of an IC structure having a third exemplary configuration of dies according to an embodiment of the disclosure is shown.

[0014] Figure 5 A cross-sectional view of an IC structure having a fourth exemplary configuration of dies according to an embodiment of the disclosure is shown.

[0015] Figure 6 A cross-sectional view of an IC structure having a fifth exemplary configuration of dies according to an embodiment of the disclosure is shown.

[0016] Figure 7 A cross-sectional view of an IC structure having a sixth exemplary configuration of dies according to an embodiment of the disclosure is shown.

[0017] Figure 8 A cross-sectional view of an IC structure is shown having a seventh exemplary configuration of dies and another embodiment of a thermal bonding layer according to an embodiment of the disclosure.

[0018] Fig.9A and Fig. 9B Shown are top views of a first IC die and a second IC die each having a circuit area with electrical and thermal vias according to an embodiment of the disclosure.

[0019] Fig. 10A and Fig. 10B Shown are top views of a first IC die and a second IC die each having a circuit area with electrical and thermal vias according to an embodiment of the disclosure.

[0020] Fig.11A and Fig. 11B Shown are top views of a first IC die and a second IC die each having a circuit area with electrical and thermal vias according to an embodiment of the disclosure.

[0021] Fig.12 A flow chart of a method of forming a semiconductor structure according to an embodiment of the present disclosure is shown.

[0022] FIG. 13A to FIG. 13F The embodiment according to the present disclosure is shown Fig.12 The method deals with the formation of IC structures at intermediate manufacturing stages.

[0023] Fig.14 A flow chart of a method of providing a design of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0024] Fig.15A shows a cross-sectional view of another integrated circuit (IC) structure having multiple stacked dies with thermal vias and thermal bonding layers according to an embodiment of the present disclosure; Fig. 15B Shown for Fig.15A Parameter table of the implementation scheme of the IC structure.

[0025] Fig.16A , Fig. 16B , Fig. 16C An embodiment of a graphical representation of thermal performance of a 3D-IC structure according to aspects of an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0028] In addition, when "about", "approximately", etc. are used to describe a numerical value or a range of numerical values, as understood by a person of ordinary skill in the art, the term is intended to cover numerical values ​​within a reasonable range taking into account the variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the numerical values, the numerical value or range of numerical values ​​covers a reasonable range including the described numerical value, such as within + / -10% of the described numerical value. For example, a material layer with a thickness of "about 5nm" may include a size range from 4.25nm to 5.75nm, where the manufacturing tolerance associated with the deposited material layer known to a person of ordinary skill in the art is + / -15%. In addition, the disclosed dimensions of different components may implicitly disclose the size ratios between the different components. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0029] Embodiments of the present disclosure relate to semiconductor or integrated circuit (IC) structures provided in a stacked configuration, and in particular to the incorporation of thermal vias and thermal bonding layers to improve heat or heat distribution in the structure. As 3D integration of stacked die (or chips) continues to be implemented to realize the benefits of increased device density and scaling, it is necessary to address the heat dissipation problem from the position within the stacked die. For example, the middle die may be limited in the heat dissipation path due to their position. Embodiments of the present disclosure describe various solutions to help vertically and laterally (e.g., horizontally) dissipate heat from hot spots in one or more dies of a 3D-IC structure. In some embodiments, the solution includes determining or identifying a high-power device of the die, and positioning the thermal vias adjacent to the high-power device. In some embodiments, a thermal bonding layer is implemented to provide improved thermal conductivity. The thermal vias adjacent to the high-power device can provide a larger area than the thermal vias at other areas of the device. Therefore, certain embodiments of the embodiments of the present disclosure cause improved heat dissipation in semiconductor structures such as 3D-IC or stacked dies.

[0030] In various embodiments, the disclosed embodiments describe an IC structure (or IC chip, such as a 3D IC) including a plurality of stacked dies. The dies may be physically and / or electrically coupled, such as by through substrate vias (TSVs). The IC structure also includes a thermal bonding layer between the stacked dies. The IC structure also includes thermal vias to effectively dissipate heat and reduce hot spot temperatures, including near high-power devices such as in logic areas. The thermal bonding layer and thermal vias may allow for lateral and vertical heat dissipation, and may be implemented for hot spot areas (e.g., high-power devices) of the IC structure. The thermal bonding layer may be formed above a multi-layer interconnect (MLI) formed in a back-end-of-line (BEOL) semiconductor process; and the thermal vias may be formed to be lateral to the MLI in the BEOL process, and in some embodiments combined with the MLI in the BEOL process. A high-power device or high-power transistor may be a transistor having a high speed, and may be distinguished from other logic or memory devices such as low-power logic devices (e.g., logic devices for switching functions). High-power devices may generate hot spots, which are areas where heat accumulates.

[0031] For this aspect of the following description, the front-end of the line (FEOL) generally refers to the portion of device (die) manufacturing where functional devices such as logic and memory devices are formed. This is also referred to as the device layer of the structure in some instances. FEOL components include transistors and their components, such as source / drain components, channel regions, gate structures. Device level contacts or metal components extend to the terminals of the transistors. The back-end of the line (BEOL) in the embodiments of the present disclosure generally refers to components formed after the FEOL components and includes multi-layer interconnects (MLI). The MLI provides a plurality of metal lines (also referred to as interconnects) and intermediate vias that provide electrical connections to the FEOL components. The metal lines provide horizontal wiring, and the vias provide vertical wiring to connect metal lines at different metal layers. Any number of metal layers can be used, including, for example, an exemplary MLI can include five (5) or more metal lines stacked vertically, generally referred to as M1, M2, M3, etc. The MLI includes a dielectric or insulating material surrounding the metal lines and vias to provide appropriate direction for signals transmitted in the lines, and the dielectric can be referred to as an inter-metal dielectric (IMD), as discussed below.

[0032] Figure 1 A perspective view of a semiconductor or IC structure 100 including a substrate 102, a plurality of stacked dies 104, 106, and 108, and a heat sink 110 thereon is shown. The IC structure 100 may be referred to as a 3D-IC. Although three dies are shown, any number of dies is possible. The first die 104, the second die 106, and the third die 108 may include: logic devices, including high-power devices, such as high-power logic devices, memory devices, and / or other functions. The first die 104, the second die 106, and the third die 108 may be identical to each other, or the first die 104, the second die 106, and the third die 108 may be different in function and / or footprint.

[0033] IC structure 100 may be an IC package mounted to a printed circuit board (PCB). In other embodiments, substrate 102 may include a PCB, a semiconductor substrate, an interposer, a dielectric substrate, and / or other supporting components. In some embodiments, substrate 102 may include conductive traces connected to an upper die (such as die 104). In some embodiments, substrate 102 may include input / output terminals, such as bumps, balls, or pillars (not shown).

[0034] The first die 104 is connected or attached to the second die 106 via a thermal bonding layer 112. The second die 106 is connected or attached to the third die 108 via the thermal bonding layer 112. In some embodiments, the thermal bonding layer 112 may also be between the die 108 and the heat sink 110 (not shown). The thermal bonding layers 112 may differ from each other in composition and thickness, or in other embodiments, may be substantially the same. The thermal bonding layer 112 may include one or more materials that provide a thermal conductivity (k) in the range of about 10 to 500 watts per meter Kelvin (W / mK). In an embodiment, the thickness of the thermal bonding layer 112 is between about 1 μm and about 50 μm. Exemplary materials for the thermal bonding layer 112 include boron nitride (BN), beryllium oxide (BeO), diamond, aluminum nitride (AlN), and aluminum oxide (Al2O3).

[0035] In an embodiment, the thermal bonding layer 112 comprises AlN. In a further embodiment, the thermal bonding layer has a thermal conductivity (k) between about 20 and 200 W / mK. In a further embodiment, the thermal bonding layer has a thermal conductivity (k) of about 30 W / mK. In an embodiment, the thermal bonding layer 112 comprises diamond. In a further embodiment, the thermal bonding layer has a thermal conductivity (k) between about 200 and 500 W / mK. In an embodiment, the thermal bonding layer 112 comprises boron nitride (BN). In a further embodiment, the thermal bonding layer has a thermal conductivity k (in-plane) between about 50 and 200 W / mK and / or a thermal conductivity k (cross-plane) between about 2 and 10 W / mK. In an embodiment, the thermal bonding layer 112 comprises Al2O3. In a further embodiment, the thermal bonding layer has a thermal conductivity (k) between about 10 and 30 W / mK. In an embodiment, the thermal bonding layer 112 comprises BeO. In a further embodiment, the thermal bonding layer has a thermal conductivity (k) between about 200 and 500 W / mK.

[0036] A plurality of thermal vias 114 extend through one or more of the first die 104, the second die 106, and the third die 108. The thermal vias 114 may be provided at localized areas. In other words, in some embodiments, the thermal vias are not distributed throughout each of the dies 104, 106, 108, but are provided in defined areas thereof. In the present embodiment, the thermal vias 114 are positioned as hot spots 116 adjacent to the structure 100. In some embodiments, other areas of any of the dies 104, 106, or 108 may not include thermal vias, include few thermal views, or include smaller areas of thermal vias (e.g., a percentage area of ​​thermal vias relative to non-thermal vias, which may be measured, for example, from a top view). The hot spot 116 may be an area of ​​elevated thermal conditions (e.g., heat) such as generated by a high power semiconductor device (e.g., a high power transistor). In some embodiments, a vertex is an area (e.g., having a higher heat (W / cm2 ) 100-300 square micron area of ​​energy). Although thermal vias 114 are shown as extending through each die, thermal vias 114 may be located in the BEOL components of each die, including as discussed below. Exemplary materials for thermal vias include copper (Cu), diamond nanoparticles, AlN, boron nitride nanoparticles, and / or other suitable thermally conductive materials.

[0037] The thermal vias 114 can be electrically isolated from the conductive vias and metal lines of the structure 100. In other words, the thermal vias 114 can be floating. The conductive elements can be those metallizations of semiconductor devices (e.g., transistors) coupled to the die. In an embodiment, the thermal vias 114 are spaced apart from the electrical components (e.g., electrical vias) by a distance of about 50 nanometers (nm) to about 500 nm (e.g., as measured in the x-direction / laterally). In an embodiment, the thermal vias 114 can be about 100 nm to about 10 μm in width. (In some embodiments, the electrical components (e.g., electrical vias) are a few nanometers to a few micrometers (μm).) The thermal vias 114 are in direct contact with the thermal bonding layer 112.

[0038] Figures 2A to 8 It shows that it can be Figure 1 FIG. 1 is a cross-sectional view of a 3D-IC of an embodiment of structure 100 . Figure 2A A semiconductor structure (e.g., 3D-IC) 200 is shown having a first die 204, a second die 206, a third die 208, and an overlying substrate 210 and a component (e.g., heat sink) 212. One or more components may be omitted from the structure 200, and / or other components may be added. As described above, the semiconductor structure 200 may be Figure 1 1 and 2. The semiconductor structure 100 of FIG. 2 is an embodiment of the present invention, and the description provided above is applicable to the structure 200. In an embodiment, the first die 204 is a logic device, the second die 206 is a logic device, and the third die 208 is a logic device. Exemplary logic devices include a central processing unit (CPU), a graphics processing unit (GPU), various processors, various controllers, and / or other chips that implement operations or execute instruction groups. A memory die or chip is a die that stores and retrieves data.

[0039] Each die 204, 206, and 208 includes a semiconductor substrate 202 and a plurality of semiconductor devices 203 formed on the semiconductor substrate in a FEOL process. Such a FEOL process can form semiconductor devices 203 such as transistors on the substrate 202 to provide different functions. For example, as discussed above with respect to the logic die, these various transistors can form a central processing unit (CPU), a graphics processing unit (GPU), access transistors for memory devices, image signal processing (ISP) circuits, and / or other suitable circuits. The transistor can be a planar transistor or a multi-gate transistor. A planar device refers to a device having a gate structure with a planar surface that engages a semiconductor active region. A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and full-all-around gate (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). The GAA transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the GAA transistor can also be called a surround gate transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of the GAA transistor can be formed by nanowires, nanosheets or other nanostructures, for which reason, the GAA transistor can also be called a nanowire transistor or a nanosheet transistor. This article generally refers to transistors, and each of the configurations discussed is applicable to the embodiments of this article. As shown, the semiconductor device 203 includes a gate structure 203A and two source / drain regions 203B.

[0040] In some embodiments, the semiconductor substrate 202 includes silicon (Si). Alternatively or additionally, the substrate 202 includes: another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, the substrate 202 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some embodiments, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate can be manufactured using isolation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0041] As noted above, the semiconductor device 203 may include a transistor having a source / drain region 203B and a gate structure 203A in various configurations. The source / drain region 203B may be a doped region and / or an epitaxial growth region defining a source / drain component associated with the gate structure 203A of the semiconductor device. The source / drain region 203B may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain region 203B is n-type, it may include silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenic (As). When the source / drain region 306 is p-type, it may include silicon germanium (SiGe) doped with a p-type dopant, such as boron (B) or boron difluoride (BF2). In some embodiments, the source / drain region 203B may include multiple layers, such as layers with different dopant concentrations.

[0042] The gate structure 203A may include an interface layer, a gate dielectric layer, and a gate electrode. The interface layer of the gate structure 203A may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may be formed on the interface layer. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Optionally, the gate dielectric layer of the gate structure 203A may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods. The gate electrode layer of the gate structure 203A may include a single layer or optionally a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof.

[0043] A device level contact 220A connected to the semiconductor device 203 terminal and extending through an interlayer dielectric (ILD) 220B is formed. The ILD layer 220B can be deposited using PECVD, FCVD, spin coating or other suitable deposition techniques. In some embodiments, after forming the ILD layer 220B, the structure can be annealed to improve the integrity of the ILD layer 220B. Although not explicitly shown in the figure, it should be understood that a contact etch stop layer (CESL) can be deposited before depositing the ILD layer 220B so that the CESL is disposed between the ILD layer 220B and the transistor component. The CESL can include silicon nitride or silicon oxynitride, and can be deposited using CVD, ALD or a suitable method. The contact structure 220A extends through the ILD layer 220B to the source / drain region 203B and the gate structure 203A, and provides electrical connection to the semiconductor device 203. The contact structure 220A can be referred to as a middle-end process (MEOL) structure. As an example, the contact structure 220A may include ruthenium (Ru), cobalt (Co), nickel (Ni), tungsten (W), copper (Cu) or other metals. In some embodiments, the contact structure 220A may include a barrier layer to interface with the ILD layer 220B. Such a barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride or nickel nitride. In addition, to reduce contact resistance, a silicide component may be part of the contact structure 220A and interface with the transistor component (such as the gate structure 203A) it contacts. The contact structure 220A may be formed by: photolithography to pattern the ILD layer 220B; etching contact holes in the ILD layer 220B; and depositing a conductive material using CVD, PVD or other suitable methods. Similarly, the device level contact 220A transmits electrical signals of the semiconductor device 203 to provide the functions of the corresponding tube core.

[0044] A multi-layer interconnect (MLI) is formed over substrate 202 including a plurality of metal lines 218A and intervening metal vias 218B that provide electrical connections to semiconductor devices 203 (via device level contacts 220A). Metal lines 218A and metal vias 218B may also be referred to as electrical wires and electrical vias because they are used to transmit signals of the device. IMD layer 218C provides an insulating layer within and around the MLI. The MLI is a BEOL component, as discussed above. Although only three metallization layers are shown for ease of illustration, the MLI of semiconductor structure 200 may include any plurality of layers in the MLI, for example, the MLI may typically include about five (5) to about twenty (20) metal layers (or metallization layers including metal lines 218A). Each of the metal layers of the MLI includes a plurality of vias 218B and metal lines 218A embedded in a dielectric or insulating layer, which may also be referred to herein as an inter-metal dielectric (IMD) layer 218C. The via 218B and the metal line 218A may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), and / or other suitable materials. In an embodiment, they are formed of copper (Cu). The IMD layer 218C may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. In one embodiment, the IMD layer 218C includes silicon oxide.

[0045] Thermal vias 216 are formed laterally adjacent to the wires and electrical vias of the MLI, and also extend through the IMD layer 218C. The thermal vias 216 may be substantially similar to the reference Figure 1 The thermal vias 114 discussed. The thermal vias 216 can vertically span the entire height of the MLI component. In a further embodiment, the thermal vias 216 can be positioned above the second metal layer (M2) of the MLI. In such an embodiment, the terminal of the thermal via 216 can be connected to the IMD 218C. In some embodiments, one end is connected to the ILD 220B and the opposite end directly contacts the surface of the thermal bonding layer 112. The thermal vias 216 are not electrically connected to any of the semiconductor devices 203 (e.g., transistor devices). Instead, they serve as heat absorbing components embedded in the IMD layer 218C. Exemplary materials for the thermal vias 216 include copper (Cu), diamond nanoparticles, AlN, boron nitride nanoparticles, and / or other suitable materials.

[0046] Thermal vias 216 may be placed adjacent to those semiconductor devices 203 that generate hot spots 205, which may be areas of elevated thermal conditions (e.g., heat), such as those generated by high-power semiconductor devices (e.g., high-power transistors). In other areas of the die (204, 206, or 208) where no hot spots are generated, there may be fewer to no thermal vias 216. In some embodiments, the lateral distance between electrical metal line 218A or via 218B and thermal via 216 is between about 50 nm and about 500 nm.

[0047] As shown, a substrate 210 is formed over the top die (here die 208). In an embodiment, substrate 210 is a carrier substrate. Substrate 210 may include silicon (Si) or other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), diamond, and / or other suitable substrates. In some embodiments, substrate 210 may be omitted and / or used in manufacturing to provide structural support. A heat sink 212 may be formed at an upper portion of structure 200 (e.g., in contact with thermal bonding layer 112).

[0048] The thermal bonding layer 112 is disposed between each die (e.g., between die 204 and die 206, between die 206 and die 208) and between the upper die and the upper component (e.g., between die 208 and substrate 210). The thermal bonding layer 112 may be substantially similar to the above reference Figure 1 The thermal bonding layer 112 discussed. In an embodiment, the thermal bonding layer 112 is a single layer. For example, in a further embodiment, the thermal bonding layer 112 is a single layer of AlN. Therefore, in some embodiments, the composition of the thermal bonding layer 112 is connected to the back side of the substrate 202 of the upper tube core (e.g., tube core 206) and the upper surface of the lower tube core (e.g., tube core 204) (such as the uppermost dielectric material (e.g., IMD 218C) of the MLI structure). The thickness of the thermal bonding layer 112 can vary between 0.1 μm and 50 μm. In an embodiment, the thickness of the thermal bonding layer 112 can be about 10 μm. The thermal bonding layer 112 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), and / or other suitable processes. In some embodiments, the deposition is carried out at a temperature of less than about 400°C. (e.g. Figure 2B As discussed in , a thin bonding layer (eg, nitride or oxide) may be deposited beneath the thermal bonding layer 112 .

[0049] Through substrate vias (TSVs) 222 extend through one or more devices, for example, die 206 and die 208. TSVs 222 can provide electrical connections between the dies. TSVs 222 can include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), and / or suitable materials. In some embodiments, TSVs 222 are connected to one or more MLI structures of dies 204, 206, or 208. In some embodiments, TSVs 222 provide input / output paths for accessing the upper die in 3D-IC 200.

[0050] Still referring to structure 200, various input / output components (not shown) may be included, such as a controlled collapse chip connection (C4) layer, a package substrate, an interposer substrate, a ball grid array (BGA) structure, a printed circuit board (PCB), and / or other components. In addition, each of dies 204, 206, 208 may have different sizes (footprints) and / or functions.

[0051] Figure 2B A cross-sectional view of an IC structure 200 ′ is shown according to an embodiment of the present disclosure. Figure 2B The IC structure 200' is similar to Figure 2A The IC structure is similar to that of FIG. 1 , and similar components will not be described again for the sake of brevity. The difference is that there is a bonding layer 224 below the thermal bonding layer 112. In an embodiment, the bonding layer 224 may be an oxide material or a nitride material. In some embodiments, the bonding layer 224 may include Al2O3, SiO2, SiN, and / or other suitable materials. In a further embodiment, the thermal bonding layer 112 is AlN and is directly disposed on the bonding layer 224. Figure 2A The IC structure is the same as Figure 2B The IC structure 200' is also Figure 1 The embodiments of structure 100 are described above, and the description thereof applies equally here. The bonding layer 224 is thinner than the thermal bonding layer 112. The thickness of the thermal bonding layer 112 may vary between 0.1 μm and 50 μm; the thickness of the bonding layer 224 may be between 10% and 70% of the thermal bonding layer 112. In some embodiments, the thickness and / or material of the bonding layer and the thermal bonding layer may be determined by considering the desired effective thermal conductivity (e.g., the thermal conductivity (k) of the resulting layer stack).

[0052] Figure 3 A cross-sectional view of an IC structure 300 is shown in accordance with an embodiment of the present disclosure. Figure 3 The IC structure 300 is similar to Figure 2AThe IC structure 200 in FIG. 1 is similar to the IC structure 200 in FIG. 1 , and similar components will not be described again for the sake of brevity. Similar to as discussed above, the IC structure 300 (which may also be referred to as a 3D-IC) is Figure 1 The description of the embodiment of the structure 100 also applies here. Figure 3 Includes a first die 204, a second die 302, and a third die 304. The first die 204 may be a logic die. The first die 204 may include a high-power device 203 having a hot spot 205. A plurality of thermal vias 216 are disposed adjacent to the high-power device 203. The second die 302 may be a memory die, and may include a semiconductor device 203 to implement a memory function. In some embodiments, the semiconductor device 203 does not present a hot spot. In some embodiments, a second plurality of thermal vias 216 are disposed on the second die 302. In an embodiment, the number of the second plurality of thermal vias 216 is less than the number of the first plurality of thermal vias 216 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the second plurality of thermal vias 216 is less than the area of ​​the first plurality of thermal vias 216 (e.g., when considered from a top view or a cross-sectional view). The third die 304 may also be a memory die. The third die 304 may include a semiconductor device 203 designed to implement the purpose of the memory die. And in some embodiments, the semiconductor device 203 of the third die 304 also does not have a hot spot. A third plurality of thermal vias 216 are disposed on the third die 304. In an embodiment, the number of the third plurality of thermal vias 216 is less than the number of the first plurality of thermal vias 216 of the die 204 (e.g., for a given area of ​​the corresponding die). In an embodiment, the area of ​​the third plurality of thermal vias 216 is less than the area of ​​the first plurality of thermal vias 216 (e.g., when considered from a top view or a cross-sectional view). As shown, a single thermal bonding layer 112 is disposed between the die 204 and the die 302, and a single thermal bonding layer 112 is disposed between the die 302 and the die 304. In an embodiment, the single thermal bonding layer 112 is disposed between the die 304 and the substrate 210. In an example, the single thermal bonding layer 112 is AlN. In other embodiments, one or more bonding layers 112 are a multilayer structure, such as Figure 2B The multi-layer structure of the thermal bonding layer 112 and the bonding layer 224 is shown in FIG.

[0053] Figure 4 A cross-sectional view of an IC structure 400 is shown in accordance with an embodiment of the present disclosure. Figure 4 The IC structure 400 is similar to Figure 2A The IC structure 200 in FIG. 1 is similar to the IC structure 200 in FIG. 1 , and similar components will not be described again for the sake of brevity. Similar to as discussed above, the IC structure 400 (which may also be referred to as a 3D-IC) is Figure 1 The description of the embodiment of the structure 100 also applies here. Figure 4Includes a first die 204, a second die 402, and a third die 302. The first die 204 may be a logic die. The first die 204 may include a high-power device 203 having a hot spot 205. A first plurality of thermal vias 216 are disposed adjacent to the high-power device 203. The second die 402 may be a logic die. The second die 402 may include a semiconductor device 203 to implement a logic function. In some embodiments, the semiconductor device 203 of the second die 402 does not present a hot spot. In an embodiment, the second die 402 is a logic die including a low-power device (e.g., a low-power transistor device 203). In some embodiments, a second plurality of thermal vias 216 are disposed on the second die 402. In an embodiment, the number of the second plurality of thermal vias 216 is less than the number of the first plurality of thermal vias 216 of the first die 204 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the second plurality of thermal vias 216 is less than the area of ​​the first plurality of thermal vias 216 of the first die 204 (e.g., when considered from a top view or a cross-sectional view). The third die 302 may be a memory die. The third die 302 may include a semiconductor device 203 to implement a memory function. In some embodiments, the semiconductor device 203 of the third die 302 does not have a hot spot. In some embodiments, the third plurality of thermal vias 216 are disposed on the third die 302. In an embodiment, the number of the third plurality of thermal vias 216 of the third die 302 is less than the number of the first plurality of thermal vias 216 of the first die 204 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the third plurality of thermal vias 216 of the third die 302 is less than the area of ​​the first plurality of thermal vias 216 of the first die 204 (e.g., when considered from a top view or a cross-sectional view). As shown, a single thermal bonding layer 112 is disposed between die 204 and die 402, and a single thermal bonding layer 112 is disposed between die 402 and die 302. In an embodiment, a single thermal bonding layer 112 is disposed between die 302 and substrate 210. For example, the single thermal bonding layer 112 may include a thermally conductive material of AlN. In other embodiments, one or more bonding layers 112 are multi-layer structures, such as Figure 2B The multi-layer structure of the thermal bonding layer 112 and the bonding layer 224 is shown in FIG.

[0054] Figure 5 A cross-sectional view of an IC structure 500 is shown in accordance with an embodiment of the present disclosure. Figure 5 The IC structure 500 is similar to Figure 2A The IC structure 200 in FIG. 1 is similar to the IC structure 200 in FIG. 1 , and similar components will not be described again for the sake of brevity. Similar to as discussed above, the IC structure 500 (which may also be referred to as a 3D-IC) is Figure 1 The description of the embodiment of the structure 100 also applies here. Figure 5The present invention includes a first die 204, a second die 302, and a third die 402. The first die 204 may be a logic die. The first die 204 may include a high-power device 203 having a hot spot 205. The first plurality of thermal vias 216 are disposed adjacent to the high-power device 203. The second die 302 may be a memory die. The second die 302 may include a semiconductor device 203 to implement a memory function. In some embodiments, the semiconductor device 203 of the second die 302 does not have a hot spot. In some embodiments, the second plurality of thermal vias 216 are disposed on the second die 302. In an embodiment, the number of the second plurality of thermal vias 216 of the second die 302 is less than the number of the first plurality of thermal vias 216 of the first die 204 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the second plurality of thermal vias 216 of the die 302 is less than the area of ​​the first plurality of thermal vias 216 of the first die 204 (e.g., when considered from a top view or a cross-sectional view). The third die 402 may be a logic die. The third die 402 may include a semiconductor device 203 to implement a logic function. In some embodiments, the semiconductor device 203 of the third die 402 does not have a hot spot. In an embodiment, the third die 402 is a logic die of a low-power device (e.g., a low-power transistor device 203). In some embodiments, a third plurality of thermal vias 216 are disposed on the third die 402. In an embodiment, the number of the third plurality of thermal vias 216 of the third die 402 is less than the number of the first plurality of thermal vias 216 of the first die 204 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the third plurality of thermal vias 216 of the third die 402 is less than the area of ​​the first plurality of thermal vias 216 of the first die 204 (e.g., when considered from a top view or a cross-sectional view). As shown, a single thermal bonding layer 112 is disposed between the die 204 and the die 302, and a single thermal bonding layer 112 is disposed between the die 302 and the die 402. In an embodiment, a single thermal bonding layer 112 is disposed between the die 402 and the substrate 210. For example, the single thermal bonding layer 112 is AlN. In other embodiments, one or more bonding layers 112 are multi-layer structures, such as Figure 2B The multi-layer structure of the thermal bonding layer 112 and the bonding layer 224 is shown in FIG.

[0055] Figure 6 A cross-sectional view of an IC structure 600 is shown in accordance with an embodiment of the present disclosure. Figure 6 The IC structure 600 is similar to Figure 2A The IC structure 200 in FIG. 1 is similar to the IC structure 200 in FIG. 1 , and similar components will not be described again for the sake of brevity. Similar to as discussed above, the IC structure 600 (which may also be referred to as a 3D-IC) is Figure 1 The description of the embodiment of the structure 100 also applies here. Figure 6Includes a first die 204, a second die 402, and a third die 404. The first die 204 may be a logic die. The first die 204 may include a high-power device 203 having a hot spot 205. A first plurality of thermal vias 216 are disposed adjacent to the high-power device 203. The second die 402 may be a logic die. The second die 402 may include a semiconductor device 203 to implement a logic function. In some embodiments, the semiconductor device 203 of the second die 402 does not have a hot spot. In an embodiment, the second die 402 is a logic die of a low-power device (e.g., a low-power transistor device 203). In some embodiments, a second plurality of thermal vias 216 are disposed on the second die 402. In an embodiment, the number of the second plurality of thermal vias 216 of the second die 402 is less than the number of the first plurality of thermal vias 216 of the first die 204 (e.g., for a given region, such as a vertically aligned region). In an embodiment, the area of ​​the second plurality of thermal vias 216 of the die 402 is less than the area of ​​the first plurality of thermal vias 216 of the first die 204 (e.g., when considered from a top view or a cross-sectional view). The third die 404 may be a logic die. The third die 404 may include a semiconductor device 203 to implement a logic function. In some embodiments, the semiconductor device 203 of the second die 402 does not have a hot spot. In an embodiment, the third die 404 is a logic die of a low-power device (e.g., a low-power transistor device 203). In some embodiments, the third plurality of thermal vias 216 are disposed on the third die 404. In an embodiment, the number of the third plurality of thermal vias 216 of the third die 404 is less than the number of the first plurality of thermal vias 216 of the first die 204 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the third plurality of thermal vias 216 of the die 404 is less than the area of ​​the first plurality of thermal vias 216 of the first die 204 (e.g., when considered from a top view or a cross-sectional view). As shown, a single thermal bonding layer 112 is disposed between die 204 and die 402, and a single thermal bonding layer 112 is disposed between die 402 and die 404. In an embodiment, a single thermal bonding layer 112 is disposed between die 404 and substrate 210. For example, single thermal bonding layer 112 is AlN. In other embodiments, one or more bonding layers 112 are multi-layer structures, such as Figure 2B The multi-layer structure of the thermal bonding layer 112 and the bonding layer 224 is shown in FIG.

[0056] Figure 7 A cross-sectional view of an IC structure 700 is shown in accordance with an embodiment of the present disclosure. Figure 7 The IC structure 700 is similar to Figure 2A The IC structure 200 in FIG. 1 is similar to the IC structure 200 in FIG. 1 , and similar components will not be described again for the sake of brevity. Similar to as discussed above, the IC structure 700 (which may also be referred to as a 3D-IC) is Figure 1The description of the embodiment of the structure 100 also applies here. Figure 7 The present invention includes a first die 302, a second die 304, and a third die 204. The third die 204 may be a logic die. The third die 204 may include a high-power device 203 having a hot spot 205. A third plurality of thermal vias 216 are disposed adjacent to the high-power device 203. The second die 304 may be a memory die. The second die 304 may include a semiconductor device 203 to implement a memory function. In some embodiments, the semiconductor device 203 of the second die 304 does not have a hot spot. In some embodiments, the second plurality of thermal vias 216 are disposed on the second die 304. In an embodiment, the number of the second plurality of thermal vias 216 of the second die 304 is less than the number of the third plurality of thermal vias 216 of the third die 204 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the second plurality of thermal vias 216 of the die 304 is less than the area of ​​the third plurality of thermal vias 216 of the third die 204 (e.g., when considered from a top view or a cross-sectional view). The first die 302 may be a memory die. The first die 302 may include a semiconductor device 203 to implement a memory function. In some embodiments, the semiconductor device 203 of the first die 302 does not have a hot spot. In some embodiments, a first plurality of thermal vias 216 are disposed on the first die 302. In an embodiment, the number of the first plurality of thermal vias 216 of the first die 302 is less than the number of the third plurality of thermal vias 216 of the third die 204 (e.g., for a given area, such as a vertically aligned area). In an embodiment, the area of ​​the first plurality of thermal vias 216 of the die 302 is less than the area of ​​the third plurality of thermal vias 216 of the third die 204 (e.g., when considered from a top view or a cross-sectional view). As shown, a single thermal bonding layer 112 is disposed between the die 302 and the die 304, and a single thermal bonding layer 112 is disposed between the die 304 and the die 204. In an embodiment, the single thermal bonding layer 112 is disposed between the die 204 and the substrate 210. For example, the single thermal bonding layer 112 is AlN. In other embodiments, one or more bonding layers 112 are multi-layer structures, such as Figure 2B The multi-layer structure of the thermal bonding layer 112 and the bonding layer 224 is shown in FIG. For example, in some embodiments, between the memory die 302 and the memory die 304, a multi-layer structure of the thermal bonding layer 112 and the bonding layer 224 is provided.

[0057] Figure 8 A cross-sectional view of an IC structure 800 is shown in accordance with an embodiment of the present disclosure. Figure 8 The IC structure 800 is similar to Figure 2A800 and similar components will not be described again for the sake of brevity. The difference is that structure 800 shows a first region 802 of structure 800 and a second region 804 of structure 800. The first region 802 includes a plurality of thermal vias 216, which may be the same or different between the dies of the 3D-IC structure as IC structure 800. The second region 804 does not include thermal vias 216. In other words, thermal vias 216 are confined to the region of one or more dies that are adjacent to or vertically aligned with the transistor that generates the hot spot. Figure 2A The IC structure is the same as Figure 8 The IC structure of 800 is also Figure 1 The description of the embodiment of the structure 100 is also applicable here.

[0058] Fig.9A and Fig. 9B It shows that the embodiments discussed previously (including Figure 1 Embodiments or Figures 2A to 8 A top view of an IC chip or die in any one of the embodiments of the present invention. The corresponding top view shows that the distribution of thermal vias is non-uniform across the device area of ​​the die. In some embodiments, the thermal vias are positioned to be adjacent to a determined hot spot of the die (e.g., localized). The positioning can include: excluding thermal vias in other parts of the die; or reducing the area covered by thermal vias in other parts of the die. The hot spots and therefore the areas for thermal vias can be determined by experimental results, simulations, design rules, design data, and / or including as described below. Fig.14 The other components discussed are determined.

[0059] Fig.9A A top view of a first die or IC chip 902 is shown. The die 902 shown can be a portion of an IC chip including a circuit area in which different semiconductor components, such as the transistor components discussed above, are formed. In an embodiment, the die 902 is a logic chip. In an embodiment, the die 902 is a logic chip with high-power devices (e.g., high-power transistors). The high-power transistors can generate hot spots 910. Therefore, the high-power transistors can be located at the location of the hot spots 910 (e.g., at a device level below the via level shown).

[0060] Thermal vias 904 and electrical vias 906 are disposed on the first die 902. Thermal vias 904 may be substantially similar to thermal vias 114 and 216 discussed above. Thermal vias 904 may be located above a device level in a BEOL component. In some embodiments, thermal vias 904 are copper. In an embodiment, thermal vias 904 are isolated from electrical vias 906 by dielectrics 908, which may be substantially similar to IMD 218C discussed above. In an embodiment, thermal vias 904 are not electrically connected to semiconductor devices of die 902. Electrical vias 906 may be substantially similar to electrical vias 218B discussed above. In some embodiments, electrical vias 906 include copper. In an embodiment, electrical vias 906 are part of a multi-layer interconnect (MLI) and are coupled to metal lines. In an embodiment, electrical vias 906 are electrically connected (e.g., by MLI) to semiconductor devices of die 902. A plurality of electrical vias 906 are disposed adjacent to the hot spot 910, for example, adjacent to a high-power semiconductor device. In some embodiments, adjacent electrical vias 906 are connected to transistor terminals (eg, source / drain or gate) of the high-power semiconductor device.

[0061] In an embodiment, thermal vias 904 and electrical vias 906 are substantially the same size and shape, such as Fig.9A . In other embodiments, the thermal vias 904 and / or the electrical vias 906 are different shapes or sizes. In an embodiment, such as shown, the thermal vias 904 are substantially rectangular (e.g., square) in a top view. In an embodiment, such as shown, the electrical vias 906 are substantially rectangular (e.g., square) in a top view. However, other configurations are possible, including but not limited to those described in the following figures.

[0062] In an embodiment, die 902 is included in a semiconductor structure including a die stack (eg, a 3D-IC). Die 902 may be configured substantially similar to the above referenced Figure 1 One or more of the dies 104, 106, or 108 discussed above, and / or may be configured substantially similarly to the above referenced Figures 2A to 8 One or more of dies 204, 206, or 208 are discussed.

[0063] Fig. 9B A top view of a second die or IC chip 912 is shown. The die 912 shown may be a portion of an IC chip including a circuit area in which various semiconductor components are formed, such as the transistor components discussed above. In an embodiment, the die 912 is a logic chip without high power devices. In an embodiment, the die 912 is a memory chip.

[0064] Thermal vias 904 and electrical vias 906 are disposed on the second die 912. Thermal vias 904 may be substantially similar to thermal vias 114 and / or 216 discussed above. In some embodiments, thermal vias 904 are copper. Thermal vias 904 may be located above a device level in a BEOL component. In an embodiment, thermal vias 904 are isolated from electrical vias 906 by dielectrics 908, which may be substantially similar to IMD 218C discussed above. In an embodiment, thermal vias 904 are not electrically connected to the semiconductor device of die 912. Electrical vias 906 may be substantially similar to electrical vias 218B discussed above. In some embodiments, electrical vias 906 include copper. In an embodiment, electrical vias 906 are part of a multi-layer interconnect (MLI). In an embodiment, electrical vias 906 are electrically connected (e.g., by MLI) to the semiconductor device of die 912.

[0065] In an embodiment, thermal vias 904 and electrical vias 906 are substantially the same size and shape, such as Fig. 9B . In some embodiments, the thermal vias 904 and / or the electrical vias 906 are different shapes or sizes. In an embodiment, such as shown, the thermal vias 904 are substantially rectangular (e.g., square) in a top view. In an embodiment, such as shown, the electrical vias 906 are substantially rectangular (e.g., square) in a top view. In some embodiments, the sizes of the thermal vias 904 and the electrical components 906 are substantially similar. The thermal vias 904 of the second die 912 have a second number and a second spacing between the thermal vias 904.

[0066] In an embodiment, the number of thermal vias 904 in the second die 912 is less than the number of thermal vias 904 of the first die 902 (e.g., having the hot spot 910). In an embodiment, the spacing between the thermal vias 904 in the region of the second die 912 is greater than the spacing between the thermal vias 904 in the corresponding region of the first die 902 (e.g., having the hot spot 910). In an embodiment, the spacing between the thermal vias 904 of the second die 912 is about twice the spacing between the thermal vias 904 of the first die 902 (e.g., having the hot spot 910). In an embodiment, in another region of the first die 902 (not the region positioned around the hot spot 910), the number of thermal vias and / or the spacing of the thermal vias is about equal to the corresponding region of the second die 912.

[0067] In an embodiment, die 912 is included in a semiconductor structure (eg, a 3D-IC) including a die stack. Die 912 may be configured substantially similar to the above referenced Figure 1 One or more of the dies 104, 106, or 108 discussed above. Die 912 may be configured substantially similarly to the above referenced Figures 2A to 8One or more of the discussed dies 302, 304, 402, or 404. In an embodiment, a 3D-IC includes a die stack including Fig.9A The first die 902 and Fig. 9B In a further embodiment, the second die 912 is the next die adjacent to (eg, above or below) the die 902 in the 3D-IC.

[0068] Fig. 10A A top view of a first die or IC chip 1002 is shown. The die 1002 shown may be a portion of an IC chip including a circuit area in which different semiconductor components, such as the transistor components discussed above, are formed. In an embodiment, the die 1002 is a logic chip. In an embodiment, the die 1002 is a logic chip having high-power devices (e.g., high-power transistors). The high-power transistors may generate hot spots 910. Thus, the high-power transistors may be located at the location of the hot spots 910 (e.g., at a device level below the via level shown).

[0069] Thermal vias 904 and electrical vias 906 are disposed on the first die 1002. Thermal vias 904 may be substantially similar to thermal vias 114 and 216 discussed above. In some embodiments, thermal vias 904 are copper. In an embodiment, thermal vias 904 are isolated from electrical vias 906 by dielectrics 908, which may be substantially similar to IMD 218C discussed above. In an embodiment, thermal vias 904 are not electrically connected to semiconductor devices of die 902. Electrical vias 906 may be substantially similar to electrical vias 218B discussed above. In some embodiments, electrical vias 906 include copper. In an embodiment, electrical vias 906 are part of a multi-layer interconnect (MLI) and are coupled to metal lines. In an embodiment, electrical vias 906 are electrically connected (e.g., by MLI) to semiconductor devices of die 902. Multiple electrical vias 906 are disposed adjacent to hot spots 910, for example, adjacent to high-power semiconductor devices. In some embodiments, adjacent electrical vias 906 are connected to transistor terminals (eg, source / drain or gate) of a high-power semiconductor device.

[0070] The thermal vias 904 and the electrical vias 906 can be of different configurations (e.g., shapes) and sizes. In an embodiment, such as shown, the thermal vias 904 are substantially rectangular in a top view (e.g., a rectangle extending in the y-direction or the x-direction). In an embodiment, such as shown, the electrical vias 906 are substantially rectangular in a top view (e.g., a square). The thermal vias 904 can include larger vias and smaller vias. In some embodiments, the smaller vias are substantially the same size and shape as the electrical vias 906. In some embodiments, the larger thermal vias are 2 to 80 times larger than the electrical vias 906 of the die 1002.

[0071] In an embodiment, die 1002 is included in a semiconductor structure (eg, 3D-IC) including a die stack. Die 1002 may be configured substantially similar to the above referenced Figure 1 One or more of the dies 104, 106, or 108 discussed above. Die 1002 may be configured substantially similar to the above referenced Figures 2A to 8 One or more of dies 204, 206, or 208 are discussed.

[0072] Fig. 10B A top view of a second die or IC chip 1012 is shown. The die 1012 shown may be a portion of an IC chip including a circuit area in which various semiconductor components are formed, such as the transistor components discussed above. In an embodiment, the die 1012 is a logic chip without high power devices. In an embodiment, the die 1012 is a memory chip.

[0073] Thermal vias 904 and electrical vias 906 are disposed on the second die 1012. Thermal vias 904 may be substantially similar to thermal vias 114 and / or 216 discussed above. In some embodiments, thermal vias 904 are copper. In an embodiment, thermal vias 904 are isolated from electrical vias 906 by an isolation material 908, which may be substantially similar to IMD 218C discussed above. In an embodiment, thermal vias 904 are not electrically connected to semiconductor devices of die 912. Electrical vias 906 may be substantially similar to electrical vias 218B discussed above. In some embodiments, electrical vias 906 include copper. In an embodiment, electrical vias 906 are part of a multi-layer interconnect (MLI) and are connected to metal lines of the MLI. In an embodiment, electrical vias 906 are electrically connected (e.g., by the MLI) to semiconductor devices of die 1012.

[0074] In some embodiments, the thermal vias 904 and / or the electrical vias 906 are different shapes or sizes. In an embodiment, such as shown, the thermal vias 904 are substantially rectangular (e.g., square) in a top view. In an embodiment, such as shown, the electrical vias 906 are substantially rectangular (e.g., square) in a top view. In some embodiments, the sizes of the thermal vias 904 and the electrical components 906 are substantially similar. In an embodiment, the area of ​​the thermal vias 904 of the second die 1012 is smaller than the area of ​​the thermal vias 904 of the first die 1002 (e.g., having a hot spot 910). In an embodiment, when comparing the area around the hot spot 910 of the first die 1002, the area of ​​the thermal vias 904 of the second die 1012 is smaller than the area of ​​the thermal vias 904 of the first die 1002. For example, when stacked in a 3D-IC, region A can be vertically aligned with region B, where region A has a significantly larger area of ​​the thermal vias 904 than region B. In some embodiments, other areas of the vertically aligned first die 1002 and second die 1012 have substantially similar areas of thermal vias 904 .

[0075] In an embodiment, die 1012 is included in a semiconductor structure (eg, 3D-IC) including a die stack. Die 1012 may be configured substantially similar to the above referenced Figure 1 One or more of the dies 104, 106, or 108 discussed above. Die 1012 may be configured substantially similar to the above referenced Figures 2A to 8 One or more of the discussed dies 302, 304, 402, or 404. In an embodiment, a 3D-IC includes a die stack including Fig. 10A The first die 1002 and Fig. 10B The second die 1012 is a second die 1012. In further embodiments, the second die 1012 is the next die in the 3D-IC adjacent to (eg, above or below) the die 1002. As discussed above, the first die 1002 and the second die 1012 can be vertically aligned (eg, region B is vertically aligned with region A).

[0076] Fig.11A A top view of a first die or IC chip 1102 is shown. The die 1102 shown can be a portion of an IC chip including a circuit area in which different semiconductor components, such as the transistor components discussed above, are formed. In an embodiment, the die 1102 is a logic chip. In an embodiment, the die 1102 is a logic chip with high-power devices (e.g., high-power transistors). The high-power transistors can generate hot spots 910. Therefore, the high-power transistors can be located at the location of the hot spots 910 (e.g., at the device level below the via level shown).

[0077] Thermal vias 904 and electrical vias 906 are disposed on the first die 1102. Thermal vias 904 may be substantially similar to thermal vias 114 and / or 216 discussed above. In some embodiments, thermal vias 904 are copper. In an embodiment, thermal vias 904 are isolated from electrical vias 906 by dielectrics 908, which may be substantially similar to IMD 218C discussed above. In an embodiment, thermal vias 904 are not electrically connected to semiconductor devices of die 1102. Electrical vias 906 may be substantially similar to electrical vias 218B discussed above. In some embodiments, electrical vias 906 include copper. In an embodiment, electrical vias 906 are part of a multi-layer interconnect (MLI) and are coupled to metal lines. In an embodiment, electrical vias 906 are electrically connected (e.g., by MLI) to semiconductor devices of die 1102. Multiple electrical vias 906 are disposed adjacent to hot spots 910, for example, adjacent to high-power semiconductor devices. In some embodiments, adjacent electrical vias 906 are connected to transistor terminals (eg, source / drain or gate) of a high-power semiconductor device.

[0078] Thermal vias 904 and electrical vias 906 are of different configurations (eg, shapes) and sizes, such as Fig.11A . In an embodiment, in a first region of the die 1102, the thermal vias 904 are substantially rectangular (e.g., square) in top view. In an embodiment, such as shown, the electrical vias 906 are substantially rectangular (e.g., square) in top view. In an embodiment, in another region of the die 1102 (designated as region C), the thermal vias are elongated rings arranged in a concentric manner. Region C can be positioned around the hot spot 910.

[0079] In an embodiment, die 1102 is included in a semiconductor structure (eg, 3D-IC) including a die stack. Die 1102 may be configured substantially similar to the above referenced Figure 1 One or more of the dies 104, 106, or 108 discussed above. Die 1102 may be configured substantially similar to the above referenced Figures 2A to 8 One or more of dies 204, 206, or 208 are discussed.

[0080] Fig. 11B A top view of a second die or IC chip 1112 is shown. The die 1112 shown may be a portion of an IC chip including a circuit area in which various semiconductor components are formed, such as the transistor components discussed above. In an embodiment, the die 1112 is a logic chip without high power devices. In an embodiment, the die 1112 is a memory chip.

[0081] Thermal vias 904 and electrical vias 906 are disposed on second die 1112. Thermal vias 904 may be substantially similar to thermal vias 114 and / or 216 discussed above. In some embodiments, thermal vias 904 are copper. In an embodiment, thermal vias 904 are isolated from electrical vias 906 by isolation 908. In an embodiment, thermal vias 904 are not electrically connected to the semiconductor device of die 1112. Electrical vias 906 may be substantially similar to electrical vias 218B discussed above. In some embodiments, electrical vias 906 include copper. In an embodiment, electrical vias 906 are part of a multi-layer interconnect (MLI) and are coupled to a metal line. In an embodiment, electrical vias 906 are electrically connected (e.g., by MLI) to the semiconductor device of die 1112.

[0082] In some embodiments, thermal vias 904 and / or electrical vias 906 are of similar shape and / or size, such as Fig. 11B In an embodiment, the area of ​​the thermal via 904 of the second die 1112 is smaller than the area of ​​the thermal via 904 of the first die 1102 when comparing the area of ​​the hot spot 910 surrounding the first die 1102. For example, when stacked in a 3D-IC, region C can be vertically aligned with region D, where region C has a significantly larger area of ​​the thermal via 904 than region D. In some embodiments, other regions of the vertically aligned first die 1002 and second die 1102 have substantially similar areas of the thermal via 904.

[0083] In an embodiment, die 1112 is included in a semiconductor structure (eg, 3D-IC) including a die stack. Die 1112 may be configured substantially similar to the above referenced Figure 1 One or more of the dies 104, 106, or 108 discussed above. Die 1112 may be configured substantially similar to the above referenced Figures 2A to 8 One or more of the discussed dies 302, 304, 402, or 404. In an embodiment, a 3D-IC includes a die stack including Fig.11A The first die 1102 and Fig. 11B In a further embodiment, the second die 1112 is the next die in the 3D-IC adjacent to (eg, above or below) the die 1102. As discussed above, the first die 1102 and the second die 1112 may be vertically aligned (eg, region D is vertically aligned with region C).

[0084] It should be noted that the embodiments of the present disclosure contemplate any combination of rectangular or square through holes, rectangular strip through holes, polygonal through holes, annular through holes, and other through holes of different shapes. The thermal through hole may be elongated in the x-direction or the y-direction. In some embodiments, the annular through hole may be a continuous structure (e.g., Fig.11A), in other embodiments, the annular through hole may be discontinuous. The area of ​​the thermal via affects the heat absorption (eg, a larger area provides greater heat absorption), and therefore, the shape and size may be determined based on the desired thermal performance.

[0085] Reference now Fig.12 , a flow chart of a method 1200 of forming an IC structure including a plurality of stacked dies according to one or more aspects of an embodiment of the present disclosure is shown. The fabricated structure may be substantially similar to that discussed above, including Figure 1 An embodiment of the structure 100, or Figures 2A to 8 Those embodiments shown in . Fig.13A , Fig. 13B , Fig. 13C , Fig. 13C , Fig.13E and Fig.13F shows the formation of an intermediate stage of manufacturing according to Fig.12 The method 1200 processes an IC structure 1300 . FIG. 13A to FIG. 13F Previously described components may be shown, and for the sake of brevity, some of these components will not be described again.

[0086] The method 1200 forms a plurality of semiconductor devices (eg, transistor devices) on a substrate at block 1202. Fig.13A In an example, a plurality of semiconductor devices 203 are formed on a semiconductor substrate 202. The semiconductor device 203 includes a channel region between source / drain (S / D) regions 203B and a gate structure 203A above the channel region. The semiconductor device 203 can be formed in any configuration (e.g., planar, GAA, FinFET), and formed with suitable materials including those discussed above by suitable deposition and patterning techniques. In an embodiment, at least one of the semiconductor devices 203 is a high power device.

[0087] The method 1200 forms a device-level contact feature electrically coupled to the semiconductor device over the semiconductor device at block 1204. In an embodiment, the semiconductor device is a transistor, and the contact feature is formed to the S / D region and / or gate structure of the device. Fig. 13BIn an example of the present invention, the conductive contact feature 220A extends through the interlayer dielectric (ILD) 220B. The contact feature 220A and the ILD 220B and the semiconductor device 203 can be formed by suitable FEOL processing techniques. The FEOL processing may include: depositing one or more ILD sublayers (e.g., CESL); performing one or more patterning processes including lithography and etching to form patterned openings in the ILD sublayers; performing one or more deposition processes such as CVD, PVD, or ALD to form metal features in the patterned trenches; and / or a planarization process such as CMP. In an embodiment, the contact feature 220A includes tungsten (W).

[0088] The method 1200 forms a multi-layer interconnect (MLI) structure over the device level contact features discussed in block 1204 at block 1206. At block 1206, a plurality of thermal vias are also formed. Fig. 13B In an example, an MLI structure including metal lines 218A and metal vias 218B embedded in dielectric IMD 218C is formed. Metal lines 218A and metal vias 218B are electrically coupled to semiconductor device 203. Thermal vias 216 are formed to be laterally spaced apart from electrical metal lines 218A and vias 218B and electrically isolated from electrical metal lines 218A and vias 218B. The configuration of thermal vias 216, including their number, shape, size, and location, can be determined based on the desired thermal performance of the die. See the discussion below. Fig.14 In some embodiments, hot spots adjacent to a die provide an increased area of ​​thermal vias compared to other areas of the die. In some embodiments, an increased area or number of thermal vias is provided for one die compared to another die (e.g., another die of a 3D-IC).

[0089] In some embodiments, thermal via 216 is formed after forming metal line 218A and electrical via 218B. In some embodiments, thermal via 114 is formed by: etching through multiple IMD layers 218C in a single etching process to form deep trenches; and then depositing metal (e.g., Cu) into the deep openings. In some embodiments, thermal via 216 is formed simultaneously with forming metal line 218A and metal via 218V. In this way, thermal via 216 is formed in multiple etching and deposition steps. As discussed above, thermal via 216 has an end that connects to ILD 220B and is insulated from the electrical connection to semiconductor device 203. The patterning of thermal via 216 can be based on the following discussion. Fig.14The method 1400 of . Patterning of the thermal via 216 may include: etching openings, as discussed above; and depositing materials by CVD, PVD, or other suitable deposition. Exemplary materials for the thermal via 216 include copper (Cu), diamond nanoparticles, AlN, boron nitride nanoparticles, and / or other suitable materials.

[0090] The method 1200 proceeds to block 1208 where a planarization process is performed. The planarization process may be chemical mechanical polishing (CMP) or other suitable process. In an embodiment, the CMP process reduces the surface roughness to less than about 1 nanometer (eg, peak to valley vertical distance). Fig. 13B In the example of FIG. 2 , the planarization process provides an upper surface that includes the IMD layer 218C and the ends of the thermal vias 216. In some embodiments, conductive portions of the MLI structure (eg, metal lines 218A or metal vias 218B) are also included in the upper, planarized surface.

[0091] Method 1200 proceeds to block 1210 where a bonding layer is deposited. In some embodiments, multiple bonding layers are deposited. In some embodiments, a single bonding layer is deposited. The bonding layer may be conformally deposited. Fig. 13C The thermal bonding layer 112 may be substantially similar to the above-mentioned reference Figure 1 In an embodiment, the bonding layer is AlN. The thickness and material of the bonding layer of frame 1210 can be based on the following discussion. Fig.14 The thermal bonding layer may be deposited by PVD, CVD or other suitable deposition methods. In some embodiments, the deposition is provided at a temperature below about 400°C.

[0092] In an embodiment, the method 1200 continues to block 1212 where a carrier substrate or wafer is attached. Fig.13D In an example of method 1200, a carrier substrate 1302 is attached. Carrier substrate 1302 may be in the shape of a wafer. The carrier substrate may include silicon (Si) or other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), diamond, and / or other suitable substrates. In some embodiments of method 1200, block 1214 thins the substrate from a surface (e.g., the back side), while the carrier substrate is attached to an opposing surface. In block 1216, the carrier substrate may be removed for further processing of the surface to which it is attached. In other embodiments of method 1200, one or more of blocks 1212, 1214, and 1216 are omitted. Fig.13DAs shown in , a first die 1304 having a semiconductor device 203, a thermal via 216, and a multi-layer interconnect having metal lines 218A and vias 218B that provide electrical connections to the semiconductor device 203 and are isolated from the thermal via 216 is thus formed. A thermal bonding layer 112 is provided on the upper surface of the die 1304. In some embodiments, a bonding layer may be deposited before the thermal bonding layer 112, such as Figure 2B as shown in .

[0093] Method 1200 includes block 1218, where a stack of substrates (eg, dies) or other components (eg, heat sinks, etc.) is formed, including the dies fabricated in blocks 1202-1216. Additional dies may be fabricated using one or more of blocks 1202-1216. Fig.13E In an example, an additional die 1304 is formed over the die 1304 and the thermal bonding layer 112. Each die 1304 can have similar functions or different functions. In some embodiments, the die 1304 is a logic die (e.g., including low power and / or high power devices) or a memory die. The die 1304 is attached by the bonding layer 112, which can be substantially similar to as discussed above.

[0094] In an embodiment, through substrate vias (TSVs) 222 are formed through one or more dies 1304 to connect the dies 1304 to each other and / or to input / output terminals of the structure. In some embodiments, after attaching the one or more dies, openings extending through the dies 1304 and filled with a conductive material are etched to form TSVs 222. In some embodiments, TSVs 222 are formed in multiple etching and deposition steps specific to a given die, and then subsequently aligned when the dies 1304 are stacked. Fig.13F A thermal bonding layer 112 is shown formed over the upper die 1304 and attaching a component 212. The component 212 may be a heat sink, a carrier wafer, a substrate, another die, a package component, and / or other components.

[0095] Reference now Fig.14, a method 1400 for determining a thermal configuration of a 3D-IC is shown. The thermal configuration may include a thermal via layout and / or thermal bonding layer parameters, such as material and thickness, of an IC device. In block 1402 of method 1400, a semiconductor structure circuit design and layout of one or more dies is determined. In an embodiment, one design determined is for a first IC die or chip, such as a logic chip including one or more logic devices and their interconnections. In some embodiments, the semiconductor circuit design and layout include high-power devices, such as high-power transistors. In an embodiment, another design determined is for a second IC die or chip, such as a logic chip or a memory chip, that will be stacked with the first chip to form a 3D-IC structure. Block 1402 may include providing a layout suitable for a graphic database system (GDS) file or other layout data.

[0096] refer to Fig.15A , a 3D-IC structure 1500 is shown. The 3D-IC structure 1500 may represent a manufactured device, or may represent a module of a die used in analog technology for 3D-IC design. The structure 1500 includes: a first die 1504, including a device layer (e.g., a substrate, a semiconductor device such as a transistor) 1504A, a first interconnect layer 1504B and a second interconnect layer 1504C, and the first interconnect layer 1504B and the second interconnect layer 1504C may be a first metal layer and a second metal layer of the MLI, respectively. The structure 1500 includes: a second die 1506, including a device layer (e.g., a substrate, a semiconductor device such as a transistor) 1506A, a first interconnect layer 1506B and a second interconnect layer 1506C (e.g., a first metal layer and a second metal layer of the MLI). The structure 1500 includes a third die 1508 including a device layer (e.g., a substrate, a semiconductor device such as a transistor) 1508A, a first interconnect layer 1508B, and a second interconnect layer 1508C (e.g., a first metal layer and a second metal layer of the MLI). A bonding layer 1510 is disposed between the first die 1504 and the second die 1506, between the second die 1506 and the third die 1508, and between the third die 1508 and a heat sink 1514. In an embodiment, one or more of the first die 1504, the second die 1506, or the third die 1508 has a thickness of about 4 micrometers (μm). The die stack is disposed on the substrate 1502, and the heat sink 1514 is disposed above the stack.

[0097] Method 1400 proceeds to block 1404 where hot spots are determined—areas of increased thermal energy as discussed above. Hot spots can be determined based on the design data of block 1402. In some embodiments, hot spots are determined by simulating the design data of block 1402. In some embodiments, hot spots are identified from the design data by locating high power transistors.

[0098] refer to Fig.15A In an example, a hot spot 1512 is identified on the second or middle die 1506. In some embodiments, the hot spot 1512 is identified by simulation. In some embodiments, the hot spot 1512 is identified by evaluating design data to determine a high-speed transistor. In an embodiment, the hot spot 1512 is a 250 μm×250 μm hot spot in the second die 1506, particularly in the device layer 1504A (e.g., the logic layer) of the second die 1506. In some embodiments, the hot spot 1512 has a power of about 500 W / cm 2 of thermal energy.

[0099] In some embodiments of block 1404, in addition to identifying hot spots, the overall heating of the die of the 3D-IC structure is determined. In some embodiments, the overall heating of the second die 1506 can be greater than the overall heating of the first die 1504 and the third die 1508. In some embodiments, the overall heating of the second die 1506 can be an order of magnitude greater than the overall heating of the first die 1504 and the third die 1508. In an embodiment, the overall heating of the die can be about 0.05 W / cm 2 and 2W / cm 2 In some embodiments, the overall heating of die 1506 can be less than the overall heating of die 1504 and / or die 1508 .

[0100] In an embodiment, when determining the thermal performance of a 3D-IC and a die including a stack, the thickness (in microns) and thermal resistance of each layer of each of the dies 1504, 1506, and 1508 are determined. Example parameters are Fig. 15B , including in columns 3, 4, and 5, which show the directional thermal coefficients for each of the elements of structure 1500. In some embodiments, the values ​​in columns 3, 4, and 5 are used to simulate the performance of structure 1500.

[0101] The method 1400 proceeds to block 1406, where a thermal via layout is determined to address the heating of the structure, and in particular the identified hot spots of block 1404. In some embodiments, the thermal via layout defines the number, size, and / or placement of thermal vias. The thermal via layout can be determined such that the thermal performance of the 3D-IC is sufficient (e.g., the maximum temperature is within design limits).

[0102] refer to Fig.15A , a thermal via 1514 is shown. The thermal via 1514 can be substantially similar to the thermal vias 114, 216, and / or 904 discussed above. Fig. 15B15, which illustrates a range of thicknesses and directional thermal resistances for layers of a die including thermal vias that can be used to perform simulations related to determining the inclusion of a thermal via in a structure 1500. The composition (eg, thermal coefficient) that may include the thermal via is determined.

[0103] The method 1400 proceeds to block 1408 where thermal considerations for a bonding layer associated with the die are determined. The thermal considerations may include simulation and / or experimental results to determine the composition and / or thickness of a thermal bonding layer for a die that provides adequate thermal performance (e.g., in conjunction with an above die or a component such as a heat sink). In an embodiment, a thermal conductivity (k) of one or more thermal bonding layers is determined. In a further embodiment, a thickness of each of the one or more thermal bonding layers is determined.

[0104] refer to Fig.15A In the example of FIG. 1 , a bonding layer 1510 is shown. The bonding layer 1510 can be substantially similar to the thermal bonding layer 112 and / or the bonding layer 224 discussed above. Fig. 15B In the example of FIG. 15 , parameters for a bonding layer 1510 suitable for simulation and / or fabrication of a structure 1500 are shown to determine suitable thermal properties for the structure 1500 .

[0105] In an embodiment, a heat transfer coefficient (HTC) boundary condition is set for structure 1500 for use in simulation methods including those discussed above. In an embodiment, a heat transfer coefficient (HTC) boundary condition is provided for structure 1500. 2 / K between the top HTC (HTC top ) and a distance of about 0.5 to 1.5 mm. In an embodiment, about 650-700 W / m 2 / K bottom HTC (HTC bottom ) and a distance of about 0.5 to 1.5 mm. In an embodiment, about 150-200 W / m 2 / K between the side HTC (HTC side ). In an embodiment, substrate 1502 is approximately 0.1 to 0.3 mm in height. In an embodiment, heat sink 1514 is approximately 0.1 to 0.3 mm in height.

[0106] Fig.16A , Fig. 16B and Fig. 16C A graphical representation of a portion of a structure designed, simulated, and / or fabricated according to method 1400 is shown. Fig.16A , Fig. 16B and Fig. 16C You can use the implementation as referenced above Fig.14 , Fig.15A and Fig. 15B The parameters discussed are generated by simulation techniques. Fig.16AThe temperature profile is shown for a structure substantially similar to structure 1500 without thermal vias and with a thermal bonding layer material having a thermal conductivity of approximately 1.4 W / mK. Fig. 16B The temperature profile is shown for a structure substantially similar to structure 1500 without thermal vias and with a thermal bonding layer material having a thermal conductivity of approximately 10 W / mK. Fig. 16C The temperature profile is shown for a structure substantially similar to structure 1500, which has a thermal conductivity (k) of the through-holes of approximately 150 W / mK. via ) of about 5% (by area) of the thermal via and the thermal bonding layer material has a thermal conductivity of about 30 W / mK. As discussed above, the thermal via can be composed of copper, diamond, boron nitride, and / or other suitable materials and is positioned adjacent to the hot spot of the structure (i.e., vertically aligned with the hot spot). The thermal via can include a thermal conductivity (k) of ≥ about 100 W / m / K. The maximum temperature is from Fig.16A The simulation parameters are Fig. 16B In an embodiment, the maximum temperature is reduced from Fig.16A Embodiments to Fig. 16B The embodiment is reduced by about 10% to 15%; and in the embodiment, the maximum temperature is reduced from Fig. 16B Embodiments to Fig. 16C The embodiments are reduced by about 3% to 8%.

[0107] Although not limiting, the disclosed embodiments provide advantages for IC semiconductor structures with thermal energy distribution and dissipation. One exemplary advantage is the incorporation of thermal vias on the die of a 3D-IC structure so that the thermal vias surround hot spots (e.g., high-power devices) of the die. The thermal vias can provide a vertical path for the dissipation of thermal energy. Another exemplary advantage is the incorporation of a thermal bonding layer between the die of a 3D-IC. The thermal bonding layer can provide a horizontal path for the dissipation of thermal energy.

[0108] One aspect of an embodiment of the present disclosure relates to an integrated circuit (IC) structure including a first die and a second die. The first die includes: a first transistor device formed on a substrate; a first multi-layer interconnect (MLI) located above the substrate, wherein the first MLI includes a plurality of metal lines and intermediate metal vias, and wherein the first MLI is electrically coupled to the first transistor device; and a first plurality of thermal vias laterally adjacent to the first MLI. A thermal bonding layer is located above the first die. The second die includes: a second transistor device formed on another substrate; a second MLI located above the other substrate, wherein the second MLI includes a plurality of metal lines and intermediate metal vias and is electrically coupled to the second transistor device; and a second plurality of thermal vias laterally adjacent to the second MLI. The second plurality of thermal vias is less than the first plurality of thermal vias.

[0109] In an embodiment, the first transistor device is a high power transistor, and wherein the second transistor device is a logic transistor. In an embodiment, the thermal bonding layer is AlN. In a further embodiment, the AlN extends from the dielectric layer of the first MLI of the first die to another substrate of the second die. In another further embodiment, another bonding layer is between the thermal bonding layer and the first die. The bonding layer can be at least one of Al2O3, SiO2 or SiN. In an embodiment, a first plurality of thermal vias laterally adjacent to the first MLI are disposed in a first region of the first die, and a third plurality of thermal vias are disposed in a second region of the first die. In a further embodiment, the first plurality of thermal vias have a larger area than the third plurality of thermal vias.

[0110] In an embodiment of the IC structure, the first plurality of thermal vias are arranged at a first pitch and the third plurality of thermal vias are arranged at a second pitch, the second pitch being greater than the first pitch. In a further embodiment, the second plurality of thermal vias of the second die are arranged at the second pitch.

[0111] Another aspect of the disclosed embodiments relates to an integrated circuit (IC) structure. The IC structure includes: a plurality of vertically stacked dies; a thermal bonding layer extending between a first die and a second die of the plurality of vertically stacked dies; and a plurality of thermal vias located on at least one of the first die or the second die. The thermal bonding layer includes a material having a thermal conductivity between about 10 and 500 W / m / K. The plurality of thermal vias are disposed adjacent to a high power transistor device.

[0112] In an embodiment, the material is AlN, diamond, boron nitride, Al2O3, BeO or a combination thereof. In a further embodiment, the material extends from the uppermost dielectric layer of the first die to the surface of the substrate of the second die. In an embodiment, the thermal bonding layer further includes another material of silicon nitride or silicon oxide. In an embodiment, an end of each of the plurality of thermal vias is connected to the thermal bonding layer. In an embodiment, the total number of thermal vias of the first die is different from the total number of thermal vias of the second die. In a further example, the plurality of thermal vias are located on a first region of the first die, and the second plurality of thermal vias are located on a second region of the first die, the first region having a greater thermal via density than the second region.

[0113] Another aspect of the disclosed embodiments relates to a method for forming an integrated circuit (IC) structure. The method includes forming a first transistor device on a first die and forming a second transistor device on a second die. A first plurality of thermal vias are formed on a first die adjacent to the first transistor device, and a second plurality of thermal vias are formed on a second die adjacent to the second transistor device. The first plurality of thermal vias have a larger area than the second plurality of thermal vias. A thermal bonding layer is deposited on a surface of the first die. The second die is attached to the thermal bonding layer.

[0114] In an embodiment, depositing includes one of chemical vapor deposition (CVD) or physical vapor deposition (PVD). In a further embodiment, forming the first plurality of thermal vias is performed after forming a multi-layer interconnect (MLI) on the first die. In an implementation, the method also includes: providing design data for a circuit of the first die; identifying a hot spot on the first die; and positioning the first plurality of thermal vias adjacent to the hot spot.

[0115] The details of the methods and devices of the embodiments of the present disclosure are described in the accompanying drawings. The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those of ordinary skill in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated circuit structure, comprising: A first tube core, wherein the first tube core comprises: A first transistor device is formed on a substrate; a first multi-layer interconnect located above the substrate, wherein the first multi-layer interconnect includes a plurality of metal lines and intervening metal vias, wherein the first multi-layer interconnect is electrically coupled to the first transistor device; and a first plurality of thermal vias laterally adjacent to the first multi-layer interconnect; a thermal bonding layer located over the first die; and A second tube core is located above the thermal bonding layer, and the second tube core includes: a second transistor device formed on another substrate; a second multi-layer interconnect located above the another substrate, wherein the second multi-layer interconnect includes a plurality of metal lines and intervening metal vias, wherein the second multi-layer interconnect is electrically coupled to the second transistor device; and A second plurality of thermal vias is laterally adjacent to the second multi-layer interconnect, wherein the second plurality of thermal vias is less than the first plurality of thermal vias.

2. The integrated circuit structure according to claim 1, wherein: The first transistor device is a high power transistor, and wherein the second transistor device is a logic transistor.

3. The integrated circuit structure according to claim 1, wherein: The thermal bonding layer is AlN.

4. The integrated circuit structure according to claim 3, wherein: The AlN extends from a dielectric layer of the first multi-layer interconnect of the first die to the other substrate of the second die.

5. The integrated circuit structure according to claim 3, wherein: Another bonding layer is interposed between the thermal bonding layer and the first die.

6. The integrated circuit structure according to claim 5, wherein: The other bonding layer is at least one of Al2O3, SiO2 or SiN.

7. The integrated circuit structure according to claim 1, wherein: The first plurality of thermal vias laterally adjacent to the first multilayer interconnect are disposed in a first region of the first die, and a third plurality of thermal vias are disposed in a second region of the first die.

8. The integrated circuit structure according to claim 7, wherein: The first plurality of thermal vias have a larger area than the third plurality of thermal vias.

9. An integrated circuit structure comprising: multiple vertically stacked dies; a thermal bonding layer extending between a first die and a second die of the plurality of vertically stacked dies, wherein the thermal bonding layer comprises a material having a thermal conductivity between about 10 and 500 W / m / K; and A plurality of thermal vias are located on at least one of the first die or the second die, wherein the plurality of thermal vias are disposed adjacent to a high power transistor device.

10. A method of forming an integrated circuit structure, comprising: forming a first transistor device on a first die and forming a second transistor device on a second die; forming a first plurality of thermal vias on the first die adjacent to the first transistor device, and forming a second plurality of thermal vias on the second die adjacent to the second transistor device, wherein the first plurality of thermal vias have a larger area than the second plurality of thermal vias; depositing a thermal bonding layer on a surface of the first die; and The second die is attached to the thermal bonding layer.

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