Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors, and the method comprises the steps: providing a substrate structure which comprises a substrate, a plurality of fins disposed on the substrate at intervals, and a gate structure which stretches across the plurality of fins; forming a first mask layer with an opening on the gate structure; forming a first insulating layer on the first mask layer; forming a patterned sacrificial layer on the first insulating layer; forming a second insulating layer covering the sacrificial layer; removing the part of the second insulating layer covering other areas outside the side wall of the sacrificial layer and the sacrificial layer, and reserving the part of the second insulating layer covering the side wall of the sacrificial layer as a side wall; forming a third insulating layer surrounding the side wall; the side wall is removed to form a groove limited by the third insulating layer, and the orthographic projection of the first part of the groove on the substrate is located in the orthographic projection of the opening on the substrate and is overlapped with the orthographic projection of the gate structure on the substrate; etching is performed to remove a portion of the gate structure along the first portion of the trench, thereby cutting off the gate structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the related art, in the process of cutting off the gate structure, two masks are used to define the area of ​​the gate structure that needs to be cut off.

[0003] In order to meet the demand for further reduction of critical dimensions, more precise lithography machines are needed to define the areas where the gate structure needs to be truncated. Summary of the invention

[0004] In view of this, the present disclosure proposes the following technical solution, which can achieve the reduction of the size of the area that needs to be truncated of the gate structure by using a lower-precision lithography machine without adding a mask.

[0005] According to one aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate structure, the substrate structure comprising a substrate, a plurality of fins spaced apart on the substrate, and a gate structure spanning the plurality of fins; forming a first mask layer having an opening on the gate structure; forming a first insulating layer on the first mask layer; forming a patterned sacrificial layer on the first insulating layer; forming a second insulating layer covering the sacrificial layer; removing portions of the second insulating layer covering other areas outside the sidewalls of the sacrificial layer and the sacrificial layer, and retaining portions of the second insulating layer covering the sidewalls of the sacrificial layer as sidewalls; forming a third insulating layer surrounding the sidewalls; removing the sidewalls to form a groove defined by the third insulating layer, the orthographic projection of a first portion of the groove on the substrate being within the orthographic projection of the opening on the substrate and overlapping with the orthographic projection of the gate structure on the substrate; and performing etching to remove a portion of the gate structure along the first portion of the groove, thereby truncating the gate structure.

[0006] In some embodiments, the substrate structure includes a plurality of the gate structures, the first mask layer has a plurality of the openings, and the groove has a plurality of spaced first portions, the orthographic projections of different first portions on the substrate are located within the orthographic projections of different openings on the substrate, and overlap with the orthographic projections of different gate structures on the substrate.

[0007] In some embodiments, an orthographic projection of at least one of the first portions of the trench on the substrate overlaps with an orthographic projection of at least two of the gate structures on the substrate.

[0008] In some embodiments, an orthographic projection of at least one of the first portions of the trench on the substrate overlaps with an orthographic projection of one of the gate structures on the substrate.

[0009] In some embodiments, the orthographic projection of the second portion of the groove on the substrate is located within the orthographic projection of the first mask layer on the substrate; performing etching includes: using the first mask layer as a stop layer, and removing a portion of the first insulating layer located on the first mask layer along the second portion of the groove.

[0010] In some embodiments, performing etching includes: performing a first etching to remove a portion of the first insulating layer located on the first mask layer along the second portion of the trench, and removing another portion of the first insulating layer located on the gate structure along the first portion of the trench; and performing a second etching to remove the portion of the gate structure along the first portion of the trench, thereby cutting off the gate structure.

[0011] In some embodiments, forming a first mask layer having an opening on the gate structure includes: forming a fourth insulating layer on the gate structure; forming a first mask material layer on the fourth insulating layer; and patterning the first mask material layer to form the first mask layer.

[0012] In some embodiments, the method further includes: after cutting off the gate structure, removing the first mask layer using the fourth insulating layer as a stop layer.

[0013] In some embodiments, the fourth insulating layer is made of a material different from that of the first insulating layer.

[0014] In some embodiments, forming a third insulating layer surrounding the side wall includes: forming a third insulating material layer covering the side wall; and removing a portion of the third insulating material layer so that the upper surface of the remaining portion of the third insulating material layer is flush with the upper surface of the side wall, and the remaining portion of the third insulating material layer serves as the third insulating layer.

[0015] In some embodiments, the sacrificial layer has a thickness of 50 nanometers to 100 nanometers.

[0016] In some embodiments, the thickness of the second insulating layer is 10 nanometers to 40 nanometers.

[0017] In some embodiments, the material of the first mask layer includes metal nitride.

[0018] In some embodiments, the gate structure is a dummy gate structure.

[0019] In some embodiments, a material of the first insulating layer is different from a material of the second insulating layer.

[0020] According to another aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate structure, comprising a substrate, a plurality of fins spaced apart on the substrate, and a plurality of gate structures extending along a first direction, wherein two adjacent gate structures are spaced apart by a groove in the first direction, and each gate structure spans at least one fin; and a first mask layer having an opening, located on the plurality of gate structures, wherein an orthographic projection of a portion of the groove between the two adjacent gate structures on the substrate is located within an orthographic projection of the opening on the substrate.

[0021] In the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure, first, a first mask layer with an opening is formed on the gate structure of the substrate structure to define the area where the gate structure needs to be truncated. Then, a patterned sacrificial layer and a second insulating layer covering the sacrificial layer are sequentially formed on the first insulating layer to retain the portion of the side wall of the second insulating layer covering the sacrificial layer as a side wall. By forming a third insulating layer around the side wall and then removing the side wall, a groove defined by the third insulating layer can be formed. Finally, etching is performed to remove a portion of the gate structure overlapping with the groove below the opening along a portion of the groove above the opening. In this way, the side wall formed by the portion of the side wall of the second insulating layer covering the sacrificial layer can be used to define the minimum line width of the truncated gate structure, and the first mask layer can be used as a stop layer to protect the area where the gate structure does not need to be truncated. In this way, a photolithography machine with lower precision can be used to meet the requirements of the gate truncation process with reduced size.

[0022] Other features, aspects and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings constitute a part of this specification, and illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0024] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0025] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 2A to Figure 15 is a schematic diagram of various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0027] Fig.16Ais a top view of a semiconductor device according to some embodiments of the present disclosure;

[0028] Fig. 16B is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0029] It should be understood that the size of each part shown in the accompanying drawings is not necessarily drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0030] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0031] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.

[0033] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0034] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0035] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2A to Figure 15 is a schematic diagram of various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0036] Combine the following Figure 1 as well as Figure 2A to Figure 15 , the manufacturing method of the semiconductor device of some embodiments of the present disclosure is described.

[0037] like Figure 1 As shown, the method for manufacturing a semiconductor device includes steps S102 to S118. The semiconductor device may include, for example, a fin field effect transistor.

[0038] In step S102 , a substrate structure is provided.

[0039] Combine the following Figure 2A to Figure 2C The substrate structure of some embodiments of the present disclosure is described.

[0040] Figure 2A is a top view of a substrate structure according to some embodiments of the present disclosure. Figure 2B According to some embodiments of the present disclosure Figure 2A The schematic cross-sectional view is taken along line BB'. Figure 2C It is along Figure 2A The schematic cross-sectional view is taken along line CC'.

[0041] like Figure 2A to Figure 2C As shown, the substrate structure 10 includes a substrate 11 , a plurality of fins 12 spaced apart on the substrate 11 , and a gate structure 13 spanning across the plurality of fins 12 .

[0042] The substrate 11 may be a semiconductor substrate. The semiconductor substrate may be, for example, silicon (Si), germanium (Ge) or other element semiconductor substrates, or may be a compound semiconductor substrate such as gallium arsenide (GaAs). The material of the fin 12 may be the same as or different from that of the substrate.

[0043] The fins 12 may be formed in a variety of ways. As some implementations, a plurality of fins 12 are integrally provided with the substrate 11. For example, a substrate material may be provided and the substrate material may be etched to obtain an integrally provided substrate 11 and a plurality of fins 12. As other implementations, a plurality of fins 12 are not integrally provided with the substrate 11. For example, a fin material may be formed on the substrate 11, and then the fin material may be patterned to form non-integrated fins 12 and substrate 11. For example, the fin material may be patterned by a self-aligned double patterning (SADP) process to obtain a fin 12 of smaller size.

[0044] See also Figure 2B and 2C The gate structure 13 may include a gate 131 and a gate dielectric layer 132. The gate dielectric layer 132 may cover the sidewalls and the upper surface of the fin 12. The gate 131 is located on the gate dielectric layer 132.

[0045] In some embodiments, the gate structure 13 may be a dummy gate structure. In this case, the gate 131 may be a dummy gate, and the dummy gate may be replaced by a metal gate through a subsequent process. The dummy gate may include, for example, amorphous silicon. The material of the gate dielectric layer 132 may include silicon oxide, such as silicon oxide (SiO2).

[0046] In some embodiments, see Figure 2A The substrate structure 10 further includes a plurality of isolation regions 14 spaced apart from each other on the substrate 11. The fin 12 may protrude from between two adjacent isolation regions 14. As some implementations, see Figure 2A , the gate dielectric layer 132 also covers the upper surface of the isolation region 14 .

[0047] It should be understood that in order to make the drawings clearer, Figure 2A The spaced-apart plurality of isolation regions 14 on the substrate 11 are not shown.

[0048] In some embodiments, see Figure 2C The substrate structure 10 further includes a spacer layer SW1 covering the sidewall of the gate structure 13. The spacer layer SW1 may be a single-layer structure or a multi-layer structure. As some implementations, the material of the spacer layer SW1 may include silicon nitride, such as silicon nitride (Si3N4).

[0049] In some embodiments, the substrate structure 10 further includes a source region and a drain region located on both sides of the gate structure 13. For example, the source region and the drain region are raised source regions and drain regions to introduce stress into the channel region, thereby improving the mobility of carriers. For example, the fin 12 is etched to form a recess, and then the source region and the drain region are formed in the recess by an epitaxial process. As an example, the material of the source region and the drain region may include silicon germanium (SiGe) or silicon phosphide (SiP).

[0050] In some embodiments, Figure 2A As shown, the substrate structure 10 includes a plurality of gate structures 13. The plurality of fins 12 spanned by different gate structures 13 may be the same or different.

[0051] In order to more clearly show the other material layers formed, in the following text, mainly combined with Figure 2A and Figure 2B The other material layers formed on the basis are described.

[0052] Next, in step S104 , a first mask layer having an opening is formed on the gate structure.

[0053] As some implementations, the first mask layer may be formed according to the following process.

[0054] First, a gate structure 13 may be formed. Figure 3 The insulating layer 15 (i.e., the fourth insulating layer 15) is shown. As some implementations, the material of the fourth insulating layer 15 may include at least one of silicon nitride, silicon carbonitride, and silicon oxycarbon nitride. The silicon nitride may be, for example, silicon nitride. The silicon carbonitride may be, for example, silicon carbonitride (SiCN). The silicon oxycarbon nitride may be, for example, silicon oxycarbon nitride (SiOCN).

[0055] Then, a layer is formed on the fourth insulating layer 15. Figure 3 The first mask material layer 16' is shown. As some implementations, the material of the first mask material layer 16' may include metal nitride. The metal nitride may include but is not limited to titanium nitride (TiN), tantalum nitride (TaN), and the like.

[0056] Finally, the first mask material layer 16' may be patterned to form Figure 4A and Figure 4B The first mask layer 16 having an opening V is shown.

[0057] like Figure 4A and 4B As shown, in some embodiments, the first mask layer 16 may include a plurality of openings V.

[0058] In the above implementation, the fourth insulating layer 15 is first formed on the gate structure 13, and then the first mask material layer 16' is formed on the fourth insulating layer 15, and the first mask material layer 16' is patterned to form the first mask layer 16 having the opening V. In this way, the fourth insulating layer 15 can protect the gate structure 13 under the fourth insulating layer 15 during the process of patterning the first mask material layer 16'.

[0059] As some implementations, the first mask material layer 16 ′ may be patterned according to the following process.

[0060] like Figure 3 As shown, first, a hard mask layer 17 may be formed on the first mask material layer 16'. The hard mask layer 17 may include, for example, a carbon layer formed by a spin coating process, that is, a spin-on carbon layer.

[0061] Then, a layer may be formed on the hard mask layer 17. Figure 3 The anti-reflection layer 18 is shown. The anti-reflection layer 18 may be, for example, a silicon-containing anti-reflection layer.

[0062] Afterwards, a patterned photoresist 19 (also referred to as photoresist) may be formed on the anti-reflection layer 18 , and the patterned photoresist 19 may define a pattern of the opening V. For example, a photoresist material under the photomask may be photolithographically processed using a photomask to obtain the patterned photoresist 19 .

[0063] Then, the anti-reflection layer 18 (if present), the hard mask layer 17 and the first mask material layer 16' are etched using the photoresist 10 as a mask. After etching, the remaining portions of the anti-reflection layer 18 and the hard mask layer 17 are removed, and the remaining portion of the first mask material layer 16' is the first mask layer 16 with the opening V.

[0064] In some implementations, the anti-reflection layer 18 may not be formed, but a patterned photoresist 19 may be directly formed on the hard mask layer 17 .

[0065] Then, in step S106, a first insulating layer is formed on the first mask layer.

[0066] As some implementations, such as Figure 5 As shown, a first insulating layer 20 may be formed on the first mask layer 16 by deposition. It should be understood that the first insulating layer 20 fills the opening V. The material of the first insulating layer 20 may include silicon oxide, for example. The silicon oxide may be silicon oxide, for example.

[0067] Next, in step S108 , a patterned sacrificial layer is formed on the first insulating layer.

[0068] As some implementations, a patterned sacrificial layer may be formed on the first insulating layer according to the following process.

[0069] First, if Figure 6 As shown, a sacrificial material layer 21' may be formed on the first insulating layer 20. The material of the sacrificial material layer 21' may include amorphous silicon, for example.

[0070] Then, a hard mask layer 22 may be formed on the sacrificial material layer 21'. The hard mask layer 22 may include, for example, a carbon layer formed by a spin coating process.

[0071] Next, an anti-reflection layer 23 is formed on the hard mask layer 22. The anti-reflection layer 23 may be, for example, an anti-reflection layer containing silicon.

[0072] Afterwards, a patterned photoresist 24 is formed on the anti-reflection layer 23. For example, a photoresist material under the photomask may be photolithographically processed using a photomask to obtain the patterned photoresist 24.

[0073] Then, the anti-reflection layer 23 (if present), the hard mask layer 22 and the sacrificial material layer 21' are etched using the patterned photoresist 24 as a mask. After etching, the remaining portions of the anti-reflection layer 23 and the hard mask layer 22 are removed, and the remaining portion of the sacrificial material layer 21' is Figure 7 The sacrificial layer 21 is shown. In the SADP process, the sacrificial layer 21 may also be referred to as a core layer.

[0074] Thereafter, in step S110 , a second insulating layer covering the sacrificial layer is formed.

[0075] As some implementations, such as Figure 8 As shown, a second insulating layer 25 covering the sacrificial layer 21 can be formed by deposition. The material of the second insulating layer 25 can include silicon nitride, for example. Silicon nitride can be silicon nitride, for example.

[0076] Next, in step S112, the portion of the second insulating layer covering other areas outside the sidewall of the sacrificial layer and the sacrificial layer are removed, and the portion of the second insulating layer covering the sidewall of the sacrificial layer is retained as a sidewall.

[0077] Fig. 9 A schematic diagram is shown of the sidewall SW2 (ie, the portion of the sidewall of the sacrificial layer 21 covered by the second insulating layer 25 ) retained after step S112 is performed.

[0078] As some implementations, the second insulating layer 25 may be etched to remove the portion of the second insulating layer 25 covering other regions outside the sidewalls of the sacrificial layer 21; after etching, the sacrificial layer 21 is removed, thereby obtaining Fig. 9 Side wall SW2 is shown.

[0079] It should be understood that during the etching process of the second insulating layer 25 , a portion of the second insulating layer 25 covering the sidewall of the sacrificial layer 21 may also be partially etched.

[0080] In some embodiments, the thickness of the sacrificial layer 21 is 50 nanometers to 100 nanometers, for example, 50 nanometers to 80 nanometers. In some implementations, the thickness of the sacrificial layer 21 is 55 nanometers, 60 nanometers, 70 nanometers, 75 nanometers, or 90 nanometers.

[0081] In other embodiments, the thickness of the second insulating layer 25 is 10 nanometers to 40 nanometers, for example, 18 nanometers to 30 nanometers. In some implementations, the thickness of the second insulating layer 25 is 15 nanometers, 20 nanometers, 23 nanometers, 26 nanometers, 29 nanometers or 35 nanometers.

[0082] In some other embodiments, the thickness of the sacrificial layer 21 is 50 nm to 100 nm, and the thickness of the second insulating layer 25 is 10 nm to 40 nm. As some implementations, the thickness of the sacrificial layer 21 is 50 nm to 80 nm, and the thickness of the second insulating layer 25 is 18 nm to 30 nm.

[0083] Then, in step S114, a third insulating layer is formed around the spacer.

[0084] As some implementations, the third insulating layer surrounding the spacer may be formed according to the following process.

[0085] First, if Fig.10 As shown, a third insulating material layer 26' covering the spacer SW2 may be formed. The material of the third insulating material layer 26' may include silicon oxide, spin-on carbon, etc. The silicon oxide may be silicon oxide, for example.

[0086] Then, if Fig.11 As shown, a portion of the third insulating material layer 26 ′ may be removed so that the upper surface of the remaining portion of the third insulating material layer 26 ′ is flush with the upper surface of the spacer SW2 . In this case, the remaining portion of the third insulating material layer 26 ′ serves as the third insulating layer 26 .

[0087] In this way, a third insulating layer 26 surrounding the sidewall spacer SW2 may be formed.

[0088] As some implementations, the third insulating material layer 26 ′ may be etched back or planarized by etching or chemical mechanical polishing to expose the sidewall spacer SW2 , so that the upper surface of the remaining portion of the third insulating material layer 26 ′ is flush with the upper surface of the sidewall spacer SW2 .

[0089] It should be noted that the “flush” mentioned in this article refers to flushness within the semiconductor process deviation range.

[0090] Next, in step S116 , the spacers are removed to form trenches defined by the third insulating layer.

[0091] As some implementations, the sidewall spacer SW2 may be removed by a dry etching process or a wet etching process to form a trench T defined by the third insulating layer 26 .

[0092] Fig. 12A A top view of the trench T defined by the third insulating layer 26 is shown. Fig. 12B A cross-sectional view of a trench T defined by the third insulating layer 26 is shown.

[0093] like Fig. 12A and Fig. 12B As shown, the orthographic projection of a portion T1 of the trench T (hereinafter referred to as the first portion T1 ) on the substrate 11 is located within the orthographic projection of the opening V on the substrate 11 , and overlaps with the orthographic projection of the gate structure 13 on the substrate 11 .

[0094] In some embodiments, see Fig. 12A and 12B , the orthographic projection of another portion T2 of the trench T (hereinafter referred to as the second portion T2 ) on the substrate 11 is located outside the orthographic projection of the opening V on the substrate 11 .

[0095] In some embodiments, Fig. 12A and 12B As shown, a plurality of trenches T defined by the third insulating layer 26 may be formed. Each trench T includes a first portion T1 whose orthographic projection on the substrate 11 is located within the orthographic projection of the opening V on the substrate 11 and overlaps with the orthographic projection of the gate structure 13 on the substrate 11, and each trench T also includes a second portion T2 whose orthographic projection on the substrate 11 is located outside the orthographic projection of the opening V on the substrate 11.

[0096] Finally, in step S118 , etching is performed to remove a portion of the gate structure along the first portion T1 of the trench, thereby cutting off the gate structure.

[0097] It should be understood that the removed portion of the gate structure 13 includes a portion overlapping with the orthographic projection of the first portion T1 of the trench T on the substrate 11 .

[0098] In some embodiments, the orthographic projection of the second portion T2 of the trench T on the substrate 11 is outside the orthographic projection of the opening V on the substrate 11. In this case, during the etching process, the first mask layer 16 is used as a stop layer, and a portion of the first insulating layer 20 located on the first mask layer 16 is removed along the second portion T2 of the trench T.

[0099] In other words, the opening V of the first mask layer 16 can define the region where the gate structure 13 needs to be cut off. In the case where the trench T includes the first portion T1 and the second portion T2, the first mask layer 16 can serve as a stop layer to protect the region where the gate structure 13 does not need to be cut off during the etching process, so that only the portion where the gate structure 13 overlaps with the first portion T1 of the trench T is cut off.

[0100] As some implementations, etching may be performed according to the following process.

[0101] First, see Fig.13 A first etching may be performed to remove a portion of the first insulating layer 20 on the first mask layer 16 along the second portion T2 of the trench T, and to remove another portion of the first insulating layer 20 on the gate structure 13 along the first portion T1 of the trench T.

[0102] Then, see Fig.14 , a second etching may be performed to remove a portion of the gate structure 13 along the first portion T1 of the trench T, thereby cutting off the gate structure 13 .

[0103] In this manner, different etchants may be used to perform the first etching and the second etching to improve the efficiency of the first etching and the second etching, thereby improving the manufacturing efficiency of the semiconductor device.

[0104] As some implementations, the second etching includes a first sub-etching and a second sub-etching. The first sub-etching is used to remove a portion of the fourth insulating layer 15 along the first portion T1 of the trench T; the second sub-etching is used to remove a portion of the gate structure 13 along the first portion T1 of the trench T, thereby cutting off the gate structure 13.

[0105] In this way, different etchants can be used to perform the first sub-etching and the second sub-etching to further improve the efficiency of the second etch, thereby further improving the manufacturing efficiency of the semiconductor device.

[0106] In the manufacturing method of the semiconductor device of the embodiment of the present disclosure, first, a first mask layer with an opening is formed on the gate structure of the substrate structure to define the area where the gate structure needs to be truncated. Then, a patterned sacrificial layer and a second insulating layer covering the sacrificial layer are sequentially formed on the first insulating layer to retain the portion of the side wall of the second insulating layer covering the sacrificial layer as a side wall. By forming a third insulating layer around the side wall and then removing the side wall, a groove defined by the third insulating layer can be formed. Finally, etching is performed to remove a portion of the gate structure overlapping with the groove below the opening along a portion of the groove above the opening. In this way, the side wall formed by the portion of the side wall of the second insulating layer covering the sacrificial layer can be used to define the minimum line width of the truncated gate structure, and the first mask layer can be used as a stop layer to protect the area where the gate structure does not need to be truncated. In this way, a photolithography machine with lower precision can be used to meet the requirements of the gate truncation process with reduced size.

[0107] Fig.15 is a top view of a truncated gate structure according to some embodiments of the present disclosure.

[0108] In some embodiments, see Fig.15 The substrate structure 10 includes a plurality of gate structures 13, the first mask layer 16 has a plurality of openings V, and the trench T has a plurality of first portions T1 spaced apart from each other. The orthographic projections of different first portions T1 on the substrate 11 are located within the orthographic projections of different openings V on the substrate 11, and the orthographic projections of different first portions T1 on the substrate 11 overlap with the orthographic projections of different gate structures 13 on the substrate 11.

[0109] In this case, etching is performed to remove a portion of the plurality of gate structures 13 at one time along the plurality of first portions T1 of the trench T, so that the plurality of different gate structures 13 can be cut off at one time. In this way, the manufacturing efficiency of the semiconductor device can be improved.

[0110] In some embodiments, an orthographic projection of at least one first portion T1 of the trench T on the substrate 11 overlaps with an orthographic projection of one gate structure 13 on the substrate 11 .

[0111] In other embodiments, see Fig.15 , the orthographic projection of at least one first portion T1 of the trench T on the substrate 11 overlaps with the orthographic projections of at least two gate structures 13 on the substrate 11. In this case, etching is performed to remove a portion of each of the at least two gate structures 13 at one time along a first portion T1 of the trench T, so that more gate structures 13 can be cut off at one time. In this way, the manufacturing efficiency of the semiconductor device can be further improved.

[0112] In some other embodiments, the orthographic projection of a first portion T1 of the trench T on the substrate 11 overlaps with the orthographic projection of a gate structure 13 on the substrate 11, and the orthographic projection of another first portion T1 of the trench T on the substrate 11 overlaps with the orthographic projections of at least two gate structures 13 on the substrate 11. In this case, etching is performed to remove a portion of a gate structure 13 at one time along a first portion T1 of the trench T, and to remove a portion of each of at least two gate structures 13 at one time along another first portion T1 of the trench T, so that one gate structure 13 can be cut off at one time using one or some first portions T1, and multiple gate structures 13 can be cut off at one time using one or some first portions T2. In this way, different cutting requirements of different gate structures 13 can be met by using one trench T, so that the manufacturing efficiency of semiconductor devices can be further improved.

[0113] In some embodiments, after the gate structure 13 is cut off, the third insulating layer 26, the first insulating layer 20 and the first mask layer 16 may be removed using the fourth insulating layer 15 as a stop layer. For example, the third insulating layer 26, the first insulating layer 20 and the first mask layer 16 may be removed using a dry etching process or a wet etching process.

[0114] As some implementations, the fourth insulating layer 15 is made of different materials from the first mask layer 16. For example, the material of the fourth insulating layer 15 may include silicon nitride (e.g., silicon nitride), and the material of the first mask layer 16 may include metal nitride (e.g., titanium nitride or tantalum nitride). Since metal nitrides tend to have a high etching selectivity, when the material of the first mask layer 16 includes metal nitrides, the difficulty of manufacturing the semiconductor device can be reduced.

[0115] The manufacturing process of the semiconductor device is described above in combination with some embodiments. It is understandable that after the gate structure is cut off, other processes can be performed according to standard processes. For example, the fourth insulating layer 15 is removed, the gate 131 in the gate structure 13 is replaced by a metal gate, and a contact hole is formed.

[0116] The method for manufacturing a semiconductor device according to the embodiment of the present disclosure may be applied to, but is not limited to, 7 nanometer and below processes.

[0117] The present disclosure also provides a semiconductor device, Fig.16A and Fig. 16B Provide explanation.

[0118] Fig.16A is a top view of a semiconductor device according to some embodiments of the present disclosure; Fig. 16B According to some embodiments of the present disclosure Fig.16A The cross-sectional schematic diagram is shown along line D-D'.

[0119] like Fig.16A and 16B As shown, the semiconductor device includes a substrate structure 10. The substrate structure 10 includes a substrate 11, a plurality of fins 12 spaced apart on the substrate 11, and a plurality of gate structures 13 extending along a first direction. Each gate structure 13 spans across at least one fin 12. The plurality of gate structures are spaced apart by trenches T in the first direction.

[0120] In some embodiments, the semiconductor device may include multiple groups of gate structures 13. Each group of gate structures 13 includes multiple gate structures 13 extending along a first direction. Here, different groups of gate structures 13 are parallel to each other in a direction perpendicular to the first direction.

[0121] like Fig.16A and 16B As shown, the semiconductor device further includes a first mask layer 16 having an opening V. Here, the orthographic projection of the portion of the trench T between two gate structures 13 adjacent along the first direction on the substrate 11 is within the orthographic projection of the opening V on the substrate 11 .

[0122] The semiconductor device of the embodiment of the present disclosure can be obtained by, but is not limited to, the method for manufacturing the semiconductor device of any one of the above embodiments.

[0123] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0124] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a substrate structure, the substrate structure comprising a substrate, a plurality of fins spaced apart on the substrate, and a gate structure spanning the plurality of fins; forming a first mask layer having an opening on the gate structure; forming a first insulating layer on the first mask layer; forming a patterned sacrificial layer on the first insulating layer; forming a second insulating layer covering the sacrificial layer; Removing the portion of the second insulating layer covering other areas outside the sidewall of the sacrificial layer and the sacrificial layer, and retaining the portion of the second insulating layer covering the sidewall of the sacrificial layer as a sidewall; forming a third insulating layer surrounding the sidewall; Removing the sidewalls to form a trench defined by the third insulating layer, wherein an orthographic projection of a first portion of the trench on the substrate is located within an orthographic projection of the opening on the substrate and overlaps with an orthographic projection of the gate structure on the substrate; as well as Etching is performed to remove a portion of the gate structure along the first portion of the trench, thereby truncating the gate structure.

2. The method according to claim 1, wherein: The substrate structure includes a plurality of the gate structures, the first mask layer has a plurality of the openings, and The trench has a plurality of spaced-apart first portions, and orthographic projections of different first portions on the substrate are located within orthographic projections of different openings on the substrate and overlap with orthographic projections of different gate structures on the substrate.

3. The method according to claim 2, wherein: An orthographic projection of at least one of the first portions of the trench on the substrate overlaps with an orthographic projection of at least two of the gate structures on the substrate.

4. The method according to claim 2 or 3, wherein: An orthographic projection of at least one of the first portions of the trench on the substrate overlaps with an orthographic projection of one of the gate structures on the substrate.

5. The method according to any one of claims 1 to 3, wherein: The orthographic projection of the second portion of the trench on the substrate is located within the orthographic projection of the first mask layer on the substrate; Performing etching includes: Using the first mask layer as a stop layer, a portion of the first insulating layer located on the first mask layer is removed along the second portion of the trench.

6. The method according to claim 5, wherein: Performing etching includes: performing a first etch to remove a portion of the first insulating layer located on the first mask layer along the second portion of the trench, and to remove another portion of the first insulating layer located on the gate structure along the first portion of the trench; and A second etch is performed to remove the portion of the gate structure along the first portion of the trench, thereby interrupting the gate structure.

7. The method according to claim 1, wherein: Forming a first mask layer having an opening on the gate structure includes: forming a fourth insulating layer on the gate structure; forming a first mask material layer on the fourth insulating layer; and The first mask material layer is patterned to form the first mask layer.

8. The method according to claim 7, further comprising: After the gate structure is cut off, the first mask layer is removed using the fourth insulating layer as a stop layer.

9. The method according to claim 7, wherein: The fourth insulating layer is made of a material different from that of the first insulating layer.

10. The method according to claim 1, wherein: Forming a third insulating layer surrounding the sidewall includes: forming a third insulating material layer covering the sidewall spacer; and A portion of the third insulating material layer is removed so that an upper surface of the remaining portion of the third insulating material layer is flush with an upper surface of the sidewall, and the remaining portion of the third insulating material layer serves as the third insulating layer.

11. The method according to claim 1, wherein: The thickness of the sacrificial layer is 50 nanometers to 100 nanometers.

12. The method according to claim 1, wherein: The thickness of the second insulating layer is 10 nanometers to 40 nanometers.

13. The method according to claim 1, wherein: The material of the first mask layer includes metal nitride.

14. The method according to claim 1, wherein: The gate structure is a dummy gate structure.

15. The method according to claim 1, wherein: The material of the first insulating layer is different from the material of the second insulating layer.

16. A semiconductor device comprising: A substrate structure, comprising a substrate, a plurality of fins spaced apart on the substrate, and a plurality of gate structures extending along a first direction, wherein two adjacent gate structures are spaced apart by a trench in the first direction, and each gate structure spans over at least one fin; as well as A first mask layer having an opening is located on the plurality of gate structures, wherein an orthographic projection of a portion of the trench located between two adjacent gate structures on the substrate is located within an orthographic projection of the opening on the substrate.

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