LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the method comprises the steps: forming a first oxide layer on a substrate, the material of the first oxide layer being a silicon-rich oxide; performing nitrogen ion implantation and annealing process treatment on the first oxide layer to form a Si-N bond and an N-O bond in the first oxide layer, so that the relative dielectric constant of the first oxide layer is at least 4.2; a first nitride layer is formed on the first oxide layer, the first oxide layer and the first nitride layer form a silicide barrier layer, and the silicide barrier layer is located above a part of the gate structure of the substrate and on the substrate between the gate and the drain region; and forming a dielectric layer, which is higher than the first nitride layer, on the surface of the substrate, and forming a conductive structure at a preset position of the dielectric layer. According to the scheme of the invention, through a mode of improving the relative dielectric constant and the density of the first oxide layer, the damage of the first oxide layer is greatly reduced when the conductive structure is formed, and then the voltage endurance capability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] In recent years, LDMOS, a high-voltage power MOS with a lateral channel structure formed by double diffusion, has been widely used as a power device in power management, switch conversion, LED drive, audio amplifier and other products due to its high operating frequency, high input impedance, large current gain, high transconductance and easy integration with low-voltage devices through internal connections in planar technology.

[0003] The formation process of LDMOS devices includes a contact field plate process, and the steps of the contact field plate process include: forming a device contact hole (Contact) in the device, and the bottom of the device contact hole is directly connected to the silicide barrier (SAB) layer, and the metal in the device contact hole is used to form a metal field plate. Among them, the metal field plate is used to adjust the electric field distribution, thereby effectively reducing the peak electric field and improving the device's withstand voltage, thereby expanding the device's use scenarios.

[0004] However, in the process of forming device contact holes, the contact hole etching process easily causes over-etching of the oxide layer in the silicide barrier layer, which will cause the oxide layer of the metal field plate to become thinner, the device withstand voltage to become lower, and affect the performance of the device.

[0005] Therefore, how to avoid the problem of reduced voltage resistance of the device during the connection hole etching process has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0006] The present invention provides an LDMOS device and a preparation method thereof, which solves the technical problem of how to avoid the decrease of the withstand voltage capability of the device in the connection hole etching process.

[0007] According to a first aspect of the present invention, an embodiment of the present invention provides a method for preparing an LDMOS device, comprising:

[0008] Providing a substrate, wherein a body region and a drift region adjacent to each other are formed in the substrate, a gate structure is formed at the junction of the body region and the drift region, a source region is formed in the body region on one side of the gate structure, and a drain region is formed in the drift region on the other side of the gate structure;

[0009] forming a first oxide layer covering the gate structure and the exposed surface of the substrate, wherein the material of the first oxide layer is silicon-rich oxide;

[0010] Performing nitrogen ion implantation and annealing treatment on the first oxide layer so that the relative dielectric constant of the first oxide layer is at least 4.2;

[0011] forming a first nitride layer on the first oxide layer, wherein the first oxide layer and the first nitride layer constitute a silicide barrier layer;

[0012] Patterning the silicide blocking layer to retain a portion of the silicide blocking layer above the gate structure and the silicide blocking layer on the substrate between the gate structure and the drain region;

[0013] Forming a dielectric layer on the surface of the substrate, wherein the dielectric layer has a height higher than the first nitride layer;

[0014] A conductive structure is formed at a preset position of the dielectric layer.

[0015] Optionally, the thickness of the first oxide layer is

[0016] Optionally, the process conditions of the nitrogen ion implantation are: the implantation energy range is greater than 0 KeV and less than or equal to 70 KeV, and the ion implantation dose range is 1×10 10 ~1×10 13 cm 2 .

[0017] Optionally, the temperature range of the annealing process is 700-1300° C., and the annealing time range is 0.5-2 hours.

[0018] Optionally, the thickness of the first nitride layer is greater than and less than or equal to

[0019] Optionally, the material of the first nitride layer is silicon nitride.

[0020] Optionally, before forming the dielectric layer on the surface of the substrate, the method further includes:

[0021] A conductive contact layer is formed on the drain region, the source region and the surface of the gate structure where the silicide barrier layer is not formed.

[0022] Optionally, the conductive structure includes a metal field plate and a second contact hole, and forming the conductive structure specifically includes:

[0023] forming a patterned photoresist mask;

[0024] A first through hole and a second through hole are formed at the preset position of the dielectric layer, wherein the first through hole penetrates the dielectric layer and the first nitride layer and is connected to the surface of the first oxide layer; the second through hole penetrates the dielectric layer and is connected to the substrate corresponding to the drain region and the source region, and the top of the gate structure where the silicide blocking layer is not formed;

[0025] Conductive material is filled into the first through hole and the second through hole to form the metal field plate and the second contact hole respectively.

[0026] According to a second aspect of the present invention, an embodiment of the present invention provides an LDMOS device, including:

[0027] A substrate, wherein a body region and a drift region adjacent to each other are formed in the substrate, a gate structure is formed at the junction of the body region and the drift region, an active region is formed in the body region on one side of the gate structure, and a drain region is formed in the drift region on the other side of the gate structure;

[0028] A silicide blocking layer, located above a portion of the gate structure and on the substrate between the gate structure and the drain region, comprises:

[0029] a first oxide layer, located above a portion of the gate structure and on the substrate between the gate structure and the drain region, wherein the material of the first oxide layer is silicon-rich oxide, and the first oxide layer is treated by nitrogen ion implantation and annealing, and the relative dielectric constant of the first oxide layer is at least 4.2; and

[0030] A first nitride layer, located on the first oxide layer;

[0031] A dielectric layer, located on the surface of the substrate, and the height of the dielectric layer is higher than the first nitride layer;

[0032] A conductive structure is located at a preset position in the dielectric layer.

[0033] Optionally, the LDMOS device further includes a metal field plate and a second contact hole, wherein the metal field plate is located in the dielectric layer and connected to the first oxide layer, and the second contact hole is located in the dielectric layer and electrically connected to the source region, the drain region and the gate structure.

[0034] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0035] In the LDMOS device and preparation method thereof of the technical solution of the present invention, the method forms Si-N bonds and NO bonds in the first oxide layer by performing nitrogen ion implantation and annealing process treatment on the first oxide layer, so that the relative dielectric constant of the first oxide layer is at least 4.2; the relative dielectric constant and density of the first oxide layer are improved, thereby greatly reducing the damage to the first oxide layer when forming a conductive structure, thereby improving the voltage resistance of the semiconductor device.

[0036] Furthermore, the material of the first nitride layer is silicon nitride. Since the growth process of silicon nitride has the characteristics of low power, it produces less plasma, which is beneficial to solve the problem of introducing additional plasma in the contact field plate process and improve the mobility of the semiconductor structure, thereby helping to improve the current switching ratio performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a schematic flow chart of a method for preparing an LDMOS device provided by one embodiment of the present invention;

[0039] Figures 2 to 13 It is a schematic cross-sectional structure diagram of the preparation process of the LDMOS device in an embodiment of the present invention.

[0040] Description of reference numerals:

[0041] 10-substrate;

[0042] 101-body area;

[0043] 102-source area;

[0044] 103-Drift Zone;

[0045] 104-drain area;

[0046] 105-gate structure;

[0047] 20-silicide barrier layer;

[0048] 201- first oxide layer;

[0049] 202- first nitride layer;

[0050] 301-first mask layer;

[0051] 401- medium layer;

[0052] 402-first through hole;

[0053] 403- second through hole;

[0054] 404-metal field plate;

[0055] 405 - second contact hole;

[0056] 501 - conductive contact layer. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0060] At present, the preparation of the metal field plate of LDMOS is mainly through the growth of oxide and nitride on the substrate between the gate structure and the gate and the drain. In the device contact hole (Contact), the metal forms a metal field plate through the contact hole. When forming the conductive structure, a contact hole etching (Etch) process is used to form a conductive structure connected to the surface of the first oxide layer. However, the contact hole etching (Etch) process is prone to cause over-etching of the first oxide, resulting in thinning of the metal field plate oxide layer, thereby reducing the voltage resistance of the metal field plate, reducing the voltage resistance of the device, and affecting the performance of the device.

[0061] Specifically, in the connection hole etching process, normal contact holes (normal CT) and trench contact holes (trench CT) will be formed in the same process flow. Normal contact holes need to be etched to the metal silicide formed on the surface of the substrate, which will cause the metal silicide to be 0 to 100 angstroms. At the same time, the trench contact hole needs to be etched to the surface of the field plate oxide layer (SRO) in the silicide barrier layer (SAB) to form a metal field plate. In actual implementation, the contact hole etching process uses the high selectivity of SIN:OX (silicon nitride oxide) to control the etching of the trench contact hole to stop on the field plate oxide layer. However, due to the loss of metal silicide during the etching process of conventional contact holes, over-etching occurs, which will cause the loss of the field plate oxide layer (SRO), thereby reducing the voltage resistance of the metal field plate device.

[0062] To solve this problem, in one implementation, a silicide barrier layer (SAB) can be designed to include a stacked structure of a first oxide layer, a nitride layer, and a second oxide layer. However, this approach will not only complicate the process flow, but the additional thin film process during manufacturing will also make the overall SAB structure thicker, thereby affecting the etching rate of subsequent processes and increasing the difficulty of the etching process.

[0063] It can be seen that it is difficult for the prior art to avoid the problem of reduced voltage resistance of the device in the connection hole etching process while maintaining minimal changes in the process structure and not affecting other devices.

[0064] In order to solve the above problems, an embodiment of the present invention provides a method for preparing an LDMOS device, comprising:

[0065] Providing a substrate, wherein a body region and a drift region adjacent to each other are formed in the substrate, a gate structure is formed at the junction of the body region and the drift region, an active region is formed in the body region on one side of the gate structure, and a drain region is formed in the drift region on the other side of the gate structure;

[0066] forming a first oxide layer covering the gate structure and the exposed surface of the substrate, wherein the material of the first oxide layer is silicon-rich oxide;

[0067] Performing nitrogen ion implantation and annealing treatment on the first oxide layer so that the relative dielectric constant of the first oxide layer is at least 4.2;

[0068] forming a first nitride layer on the first oxide layer, wherein the first oxide layer and the first nitride layer constitute a silicide barrier layer;

[0069] Patterning the silicide barrier layer, retaining a portion of the silicide barrier layer above the gate structure and the silicide barrier layer on the substrate between the gate structure and the drain region; forming a dielectric layer on the surface of the substrate, wherein the height of the dielectric layer is higher than the first nitride layer;

[0070] A conductive structure is formed at a preset position of the dielectric layer.

[0071] Therefore, the preparation method provided by the present invention forms Si-N bonds and NO bonds in the first oxide layer by performing nitrogen ion implantation and annealing process on the first oxide layer, thereby improving the relative dielectric constant and density of the first oxide layer, thereby greatly reducing the damage to the first oxide layer when forming a conductive structure, thereby improving the voltage resistance of the semiconductor device.

[0072] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the technical scheme of the present invention is described in detail below with reference to the accompanying drawings.

[0073] Figure 1 A flowchart of a method for preparing an LDMOS device provided in one embodiment of the present invention;

[0074] Figures 2 to 13 It is a schematic cross-sectional structure diagram of the LDMOS device manufacturing process according to an embodiment of the present invention.

[0075] Please refer to Figure 1 , and combined with reference Figure 2-Figure 13 , a method for preparing an LDMOS device according to an embodiment of the present invention comprises:

[0076] S1: providing a substrate 10, wherein a body region 101 and a drift region 103 are formed adjacent to each other in the substrate 10, a gate structure 105 is formed at the junction of the body region 101 and the drift region 103, an active region 102 is formed in the body region 101 on one side of the gate structure 105, and a drain region 104 is formed in the drift region 103 on the other side of the gate structure 105; Figure 2 shown.

[0077] In one embodiment, a method for forming the gate structure 105, the source region 102, and the drain region 104 includes:

[0078] providing a substrate, the substrate comprising a body region and a drift region adjacent to each other;

[0079] Performing ion implantation in the drift region of the substrate;

[0080] forming the gate structure on the substrate;

[0081] Performing ion implantation on the body region of the substrate;

[0082] Ions are implanted into the source region and the drain region.

[0083] As an example, the substrate 10 may be a silicon substrate. Of course, the present invention is not limited thereto, and an SOI substrate, a ceramic substrate, etc. may also be used. Those skilled in the art may use appropriate materials according to design requirements.

[0084] S2: forming a first oxide layer 201 covering the gate structure 105 and the exposed surface of the substrate 10, wherein the material of the first oxide layer 201 is silicon-rich oxide; Figure 3 shown.

[0085] In a specific implementation manner, step S2, for example, specifically includes:

[0086] A silicon-rich oxide material is deposited on the substrate by using a chemical vapor deposition (CVD) process to form the first oxide layer.

[0087] As an example, the thickness range of the first oxide layer 201 may be Of course, the present invention is not limited to this, and the specific thickness can be set according to the process node.

[0088] Taking into account the quality of the device to be formed, the chemical vapor deposition process can specifically be a low-temperature plasma chemical vapor deposition technology (PECVD), which has a higher etching rate, a higher hydrogen content and pinholes. Moreover, since the operating temperature of PECVD is relatively low, this process can not only deposit temperature-sensitive materials, but also reduce thermal damage to the substrate 10.

[0089] Of course, the present invention is not limited to this. As long as the deposition requirements can be met, other chemical vapor deposition processes (CVD) may also be used. Other deposition process treatment methods are also within the protection scope of the present invention.

[0090] S3: Performing nitrogen ion implantation (IMP N) and annealing process on the first oxide layer 201, so that the relative dielectric constant of the first oxide layer 201 is at least 4.2; Figure 4 shown.

[0091] In order to make the relative dielectric constant of the first oxide layer 201 at least 4.2, in one embodiment, the process conditions of the nitrogen ion implantation are: the implantation energy range is greater than 0KeV and less than or equal to 70KeV, and the ion implantation dose range is 1×10 10 ~1×10 13 cm 2 ;

[0092] The temperature range of the annealing process is 700 to 1300° C., and the annealing time ranges from 0.5 to 2 hours.

[0093] It should be understood that, in actual operation, the temperature range and annealing duration of the annealing process are determined according to the energy during ion implantation and the thickness of the SRO layer, and the present invention is not limited thereto.

[0094] Taking the material of the first oxide layer 201 as SiO2 as an example, the effect of this step is further described:

[0095] Before the first oxide layer 201 is subjected to nitrogen ion implantation and annealing process, its relative dielectric constant is only 3.9. After the first oxide layer 201 is subjected to nitrogen ion implantation and annealing process, the relative dielectric constant of the first oxide layer 201 can reach a range of 4.2 to 4.7, thereby reducing the conductivity of the first oxide layer 201.

[0096] This is because, in the nitrogen ion implantation process of the embodiment of the present invention, the high-dose implantation causes the N element to be distributed not only in the outer portion of the first oxide layer 201 (which is silicon-rich oxide, SRO in this case), but also in various portions of the first oxide layer 201, so that the first oxide layer 201 has a uniform structure, thereby reducing possible stress;

[0097] Since ion implantation will introduce certain damage into the material, an annealing process is required after the ion implantation process. The annealing process will promote the formation of Si-N bonds and NO bonds between N atoms and Si atoms in the first oxide layer 201, so that the relative dielectric constant of the first oxide layer 201 reaches at least 4.2. In practical applications, the relative dielectric constant of the first oxide layer 201 can reach 4.7, which is close to silicon oxynitride (SiON). This change will reduce the leakage current in the first oxide layer 201 by several orders of magnitude, improve the voltage resistance of the metal field plate, and at the same time make the first oxide layer have a higher density and better density, thereby slowing down the etching speed of the first oxide layer, and the first oxide layer is more easily used as an etching stop layer. On the other hand, since the structure of the first oxide layer after ion implantation is similar to SiON, the etching selectivity of the first oxide layer relative to the first nitride layer is improved, so as to achieve better control of the etching process endpoint. Furthermore, the present invention can well reduce the damage caused by the contact hole etching process.

[0098] S4: forming a first nitride layer 202 on the first oxide layer 201, wherein the first oxide layer 201 and the first nitride layer 202 constitute a silicide barrier layer 20; Figure 5 shown.

[0099] In one implementation, step S4 specifically includes, for example:

[0100] A first nitride layer is formed on the first oxide layer by using a chemical vapor deposition process.

[0101] In practical applications, the thickness of the first nitride layer 202 is greater than and less than or equal to Of course, the present invention is not limited to this, and other thicknesses may be selected as needed.

[0102] Since the contact field plate process may easily cause the introduction of additional plasma into the semiconductor structure, in a preferred embodiment, the material of the first nitride layer 202 is silicon nitride.

[0103] This is because the growth process of silicon nitride has the characteristics of low power and produces less plasma, which is beneficial to solve the problem of additional plasma introduction in the contact field plate process, improve the mobility of the semiconductor structure, and thus help improve the current switching ratio performance of the semiconductor device.

[0104] In this case, step S4 specifically includes, for example:

[0105] A low pressure chemical vapor deposition (LPCVD) process is adopted to form a first nitride layer on the first oxide layer by utilizing the reaction of silane and ammonia at 900° C.

[0106] exist Figure 5 In the example, the silicide barrier layer 20 covers the surface of the substrate 10 and wraps the gate structure 105. To facilitate subsequent processes, after forming the first nitride layer 202 and before forming the dielectric layer 401, a portion of the silicide barrier layer 20 needs to be removed.

[0107] On this basis, step S5 is executed;

[0108] S5: patterning the silicide blocking layer, retaining a portion of the silicide blocking layer above the gate structure and the silicide blocking layer on the substrate between the gate structure and the drain region; in one embodiment, step S5 specifically includes:

[0109] forming a first mask layer on the first nitride layer;

[0110] Performing a first patterning on the first mask layer to form a first patterned mask layer;

[0111] Using the first patterned mask layer as a mask and the interface between the sacrificial layer and the first substrate as an etching stop layer, the first portion of the silicide blocking layer is etched to retain only the portion of the silicide blocking layer above the gate structure and the silicide blocking layer on the substrate between the gate structure and the drain region.

[0112] Subsequent combination Figure 6 to Figure 9 Provide explanation.

[0113] Please refer to Figure 6 , forming a first mask layer 301 on the first nitride layer 202;

[0114] Please refer to Figure 7 , patterning the first mask layer 301 for the first time to form a first patterned mask layer 301;

[0115] Please refer to Figure 8 , using the first patterned mask layer 301 as a mask and the interface between the sacrificial layer and the first substrate as an etching stop layer, the first portion of the silicide blocking layer 20 is etched, leaving only the portion of the silicide blocking layer 20 above the gate structure 105 and the silicide blocking layer on the substrate 10 between the gate structure 105 and the drain region 104.

[0116] Please refer to Fig. 9 , remove the first mask layer 301.

[0117] In a preferred embodiment, after forming the patterned silicide barrier layer and before forming the dielectric layer, the method further comprises:

[0118] A conductive contact layer 501 is formed on the surface of the drain region 104, the source region 102 and the gate structure 105 where the silicide barrier layer 20 is not formed; Fig.10 shown.

[0119] In a specific example, the material of the conductive contact layer is metal silicide. The metal silicide may be cobalt silicide or titanium silicide. Specifically, the metal silicide is formed on the surface of the drain region, the source region and the gate structure where no silicide barrier layer is formed. Since the preparation of the metal silicide is a conventional technical means in the art, it will not be described in detail here.

[0120] Specifically, the method for forming the conductive contact layer 501 includes:

[0121] Depositing a metal material layer on the surface of the substrate;

[0122] The metal material layer is subjected to a thermal reaction annealing (TRA) process to form the conductive contact layer.

[0123] Among them, since the gate structure 105 has a side wall 1051, the material of the side wall 1051 is silicon oxide and silicon nitride, and the material of the silicide blocking layer 20 is the first oxide layer 201 and the first nitride layer 202. It can be seen that the side wall 1051 and the silicide blocking layer 20 cannot react with the metal material layer, so that the present invention will only form a conductive contact layer 501 on the surface of the drain area 104, the source area 102 and the gate structure 105 where the silicide blocking layer 20 is not formed.

[0124] Please continue to refer to Figure 1 , executing step S6: forming a dielectric layer 401 on the surface of the substrate 10, wherein the height of the dielectric layer 401 is higher than the first nitride layer 202; Fig.11 shown.

[0125] Please continue to refer to Figure 1 , executing step S7: forming a conductive structure at a preset position of the dielectric layer 401. In one embodiment, the conductive structure includes a metal field plate and a second contact hole, and step S7 specifically includes, for example:

[0126] forming a patterned photoresist mask;

[0127] A first through hole and a second through hole are formed at the preset position of the dielectric layer, wherein the first through hole penetrates the dielectric layer and the first nitride layer and is connected to the surface of the first oxide layer; the second through hole penetrates the dielectric layer and is connected to the substrate corresponding to the drain region and the source region, and the top of the gate structure where the silicide blocking layer is not formed;

[0128] Conductive material is filled into the first through hole and the second through hole to form the metal field plate and the second contact hole respectively.

[0129] Subsequent combination Figure 12-13 Provide explanation.

[0130] Please refer to Fig.12 , forming a patterned photoresist mask; forming a first through hole 402 and a second through hole 403 at the preset position of the dielectric layer 401, wherein the first through hole 402 penetrates the dielectric layer 401 and the first nitride layer 202, and is connected to the surface of the first oxide layer 201; the second through hole 403 penetrates the dielectric layer 402, and is connected to the substrate 10 corresponding to the drain region 104 and the source region 102, and the top of the gate structure 105 where the silicide blocking layer is not formed.

[0131] Among them, Fig.12 In the example, the second through hole 403 penetrates the dielectric layer 402 and is connected to the substrate 10 corresponding to the drain region 104 and the source region 102 , and the top of the gate structure 105 where the conductive contact layer 501 is not formed.

[0132] It can be seen that the process of forming the first through hole 402 (i.e., Trench CT) will penetrate the dielectric layer 401 and the first nitride layer 202 until the interface between the first nitride layer 202 and the first oxide layer 201. In practical applications, the etching process will cause damage to the first oxide layer 201. In the embodiment of the present invention, the damage will be less than The damage to the first oxide layer 201 is much smaller than that caused by the prior art.

[0133] The etching stop layer of the process for forming the second through hole (i.e. Normal CT) is the conductive contact layer 501. The etching process is a prior art and will not be described in detail here. Since the contact hole etching process in the present invention uses a high selectivity ratio of SIN:OX (silicon nitride and oxygen) to control the process, the selectivity ratio of silicon nitride SiN to silicon oxide OX is relatively low. Therefore, during the etching process, when etching the first oxide layer 201, the etching rate of the silicide layer (i.e. substrate 10 or the conductive contact layer 501) can be ignored. Please refer to Fig.13 , a conductive material is filled into the first through hole 402 and the second through hole 403 to respectively form the metal field plate 404 and the second contact hole 405. As an example, the conductive material may be a metal material, such as titanium (Ti), titanium nitride (TiN) and / or tungsten (W), etc., and the present invention is not limited thereto, and those skilled in the art may select a suitable conductive material as needed.

[0134] Of course, the preparation process of the semiconductor device also includes other processes. The present invention only provides processes related to the structure of the silicide barrier layer 20. Other processes are prior arts, including CMP flattening process for the surface of the substrate, forming a metal interconnection layer on the substrate, etc., which will not be described in detail in the present invention.

[0135] In summary, in the preparation method of the LDMOS device provided by the present invention, Si-N bonds and NO bonds are formed in the first oxide layer by performing nitrogen ion implantation and annealing process treatment, so that the relative dielectric constant of the first oxide layer is at least 4.2; the relative dielectric constant and density of the first oxide layer are improved, thereby greatly reducing the damage to the first oxide layer when forming a conductive structure, thereby improving the voltage resistance of the semiconductor device.

[0136] Accordingly, the embodiment of the present invention further provides an LDMOS device, please continue to refer to Fig.13 ,include:

[0137] A substrate 10, wherein a body region 101 and a drift region 103 are formed adjacent to each other in the substrate 10, a gate structure 105 is formed on the substrate 10 at the junction of the body region 101 and the drift region 103, an active region 102 is formed in the body region 101 on one side of the gate structure 105, and a drain region 104 is formed in the drift region 103 on the other side of the gate structure 105;

[0138] The silicide barrier layer 20 comprises:

[0139] A first oxide layer 201 is located above a portion of the gate structure 105 and on the substrate between the gate structure 105 and the drain region 104, and is made of silicon-rich oxide. The first oxide layer 201 is treated by nitrogen ion implantation and annealing, and has a relative dielectric constant of at least 4.2; and

[0140] A first nitride layer 202, located on the first oxide layer 201;

[0141] A dielectric layer 401 is located on the surface of the substrate 10, and the height of the dielectric layer 401 is higher than the first nitride layer 202;

[0142] A conductive structure is located at a preset position in the dielectric layer 401 .

[0143] It can be seen that in the nitrogen ion implantation process of the embodiment of the present invention, the high-dose implantation causes the N element to be distributed not only in the outer portion of the first oxide layer 201 (which is silicon rich oxide, SRO in this case), but also in various portions of the first oxide layer 201, so that the first oxide layer 201 has a uniform structure, reducing possible stress;

[0144] Since ion implantation will introduce certain damage into the material, an annealing process is required after the ion implantation process. The annealing process will promote the formation of Si-N bonds and NO bonds between N atoms and Si atoms in the first oxide layer 201, so that the relative dielectric constant of the first oxide layer 201 reaches at least 4.2. In practical applications, the relative dielectric constant of the first oxide layer 201 can reach 4.7, which is close to that of silicon oxynitride (SiON). This change can reduce the leakage current in the first oxide layer 201 by several orders of magnitude, and can have a higher density and better compactness, reduce the damage caused by subsequent processes, and improve the voltage resistance of semiconductor devices.

[0145] In order to make the relative dielectric constant of the first oxide layer 201 at least 4.2, in one embodiment, the process conditions of the nitrogen ion implantation are: the implantation energy range is greater than 0KeV and less than or equal to 70KeV, and the ion implantation dose range is 1×10 10 ~1×10 13 cm 2 ;

[0146] The temperature range of the annealing process is 700 to 1300° C., and the annealing time ranges from 0.5 to 2 hours.

[0147] It should be understood that, in actual operation, the temperature range and annealing duration of the annealing process are determined according to the energy during ion implantation and the thickness of the SRO layer, and the present invention is not limited thereto.

[0148] In practical applications, the thickness of the first oxide layer 201 may range from The thickness of the first nitride layer 202 is greater than and less than or equal to Of course, the present invention is not limited to this, and the specific thickness can be set according to the process node.

[0149] In a preferred embodiment, the material of the first nitride layer 202 may be silicon nitride. This is because the growth process of silicon nitride has the characteristics of low power, and the plasma generated is small, which is conducive to solving the problem of additional plasma introduction in the contact field plate process, improving the mobility of the semiconductor structure, and thus helping to improve the current switching ratio performance of the semiconductor device.

[0150] For the conductive structure, please continue to refer to Fig.13 In one embodiment, the conductive structure includes a metal field plate 403, which is located in the dielectric layer 401 and connected to the first oxide layer 202, wherein the metal field plate 403 includes a first through hole 402 and a conductive material filled in the first through hole 402; wherein the first through hole 402 passes through the dielectric layer 401 and the first nitride layer 202 to connect to the top of the first oxide layer 201.

[0151] In practical applications, one implementation method is as follows: Fig.13 The conductive structure also includes a second contact hole 405, which is located in the dielectric layer 401 and is electrically connected to the source region 102, the drain region 104 and the gate structure 105, wherein the second contact hole 405 includes a second through hole 403 and a conductive material filled in the second through hole; wherein the second through hole 403 penetrates the dielectric layer 402 and is connected to the substrate 10 corresponding to the drain region 104 and the source region 102, and the top of the gate structure 105 where the silicide blocking layer is not formed.

[0152] In a preferred embodiment, please refer to Fig.10 , a conductive contact layer 501 is also formed on the substrate 10 outside the patterned silicide barrier layer 20;

[0153] In this case, please continue to refer to Fig.13 The second through hole 403 penetrates the dielectric layer 401 and is connected to the substrate 10 corresponding to the drain region 104 and the source region 102 , and the top of the gate structure 105 where the conductive contact layer 501 is not formed.

[0154] As an example, the conductive material may be a metal material, such as titanium (Ti), titanium nitride (TiN) and / or tungsten (W), etc. The present invention is not limited to this, and technicians in this field can select a suitable conductive material as needed.

[0155] It should be understood that the first through hole 402 and the second through hole 403 can be formed in the same process step.

[0156] In summary, in the LDMOS device provided by the present invention, the device includes a substrate, a body region and a drift region adjacent to each other are formed in the substrate, a gate structure is formed at the junction of the body region and the drift region, an active region is formed in the body region on one side of the gate structure, and a drain region is formed in the drift region on the other side of the gate structure; a silicide barrier layer, including: a first oxide layer, located on the substrate, whose material is silicon-rich oxide, the first oxide layer is treated by nitrogen ion implantation and annealing process, and its relative dielectric constant is at least 4.2; and a first nitride layer, located on the first oxide layer; a dielectric layer, located on the surface of the substrate, and the height of the dielectric layer is higher than the first nitride layer; a conductive structure, the conductive structure at least penetrates the dielectric layer and the first nitride layer, and is connected to the surface of the first oxide layer. After the first oxide layer is treated by nitrogen ion implantation and annealing process, Si-N bonds and NO bonds are formed in the first oxide layer, which improves the relative dielectric constant and density of the first oxide layer, thereby greatly reducing the damage of the first oxide layer when forming the conductive structure, thereby improving the withstand voltage capability of the semiconductor device.

[0157] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing an LDMOS device, characterized in that: include: Providing a substrate, wherein a body region and a drift region adjacent to each other are formed in the substrate, a gate structure is formed at the junction of the body region and the drift region, a source region is formed in the body region on one side of the gate structure, and a drain region is formed in the drift region on the other side of the gate structure; forming a first oxide layer covering the gate structure and the exposed surface of the substrate, wherein the material of the first oxide layer is silicon-rich oxide; Performing nitrogen ion implantation and annealing treatment on the first oxide layer so that the relative dielectric constant of the first oxide layer is at least 4.2; forming a first nitride layer on the first oxide layer, wherein the first oxide layer and the first nitride layer constitute a silicide barrier layer; Patterning the silicide blocking layer to retain a portion of the silicide blocking layer above the gate structure and the silicide blocking layer on the substrate between the gate structure and the drain region; Forming a dielectric layer on the surface of the substrate, wherein the dielectric layer has a height higher than the first nitride layer; A conductive structure is formed at a preset position of the dielectric layer.

2. The method for preparing an LDMOS device according to claim 1, wherein: The thickness of the first oxide layer is 3. The method for preparing an LDMOS device according to claim 2, wherein: The process conditions of the nitrogen ion implantation are: the implantation energy range is greater than 0 KeV and less than or equal to 70 KeV, ion implantation dose range is 1×10 10 ~1×10 13 cm 2 .

4. The method for preparing an LDMOS device according to claim 3, characterized in that: The temperature range of the annealing process is 700 to 1300° C., and the annealing time ranges from 0.5 to 2 hours.

5. The method for preparing an LDMOS device according to claim 1, wherein: The thickness of the first nitride layer is greater than and less than or equal to 6. The method for preparing an LDMOS device according to claim 5, characterized in that: The material of the first nitride layer is silicon nitride.

7. The method for preparing an LDMOS device according to claim 1, wherein: Before forming the dielectric layer on the substrate surface, the method further includes: A conductive contact layer is formed on the drain region, the source region and the surface of the gate structure where the silicide barrier layer is not formed.

8. The method for preparing an LDMOS device according to claim 1, wherein: The conductive structure includes a metal field plate and a second contact hole, and forming the conductive structure specifically includes: forming a patterned photoresist mask; A first through hole and a second through hole are formed at the preset position of the dielectric layer, wherein the first through hole penetrates the dielectric layer and the first nitride layer and is connected to the surface of the first oxide layer; the second through hole penetrates the dielectric layer and is connected to the substrate corresponding to the drain region and the source region, and the top of the gate structure where the silicide blocking layer is not formed; Conductive material is filled into the first through hole and the second through hole to form the metal field plate and the second contact hole respectively.

9. An LDMOS device, characterized in that: include: A substrate, wherein a body region and a drift region adjacent to each other are formed in the substrate, a gate structure is formed at the junction of the body region and the drift region, an active region is formed in the body region on one side of the gate structure, and a drain region is formed in the drift region on the other side of the gate structure; A silicide blocking layer, located above a portion of the gate structure and on the substrate between the gate structure and the drain region, comprises: a first oxide layer, located above a portion of the gate structure and on the substrate between the gate structure and the drain region, wherein the material of the first oxide layer is silicon-rich oxide, and the first oxide layer is treated by nitrogen ion implantation and annealing, and the relative dielectric constant of the first oxide layer is at least 4.2; and A first nitride layer, located on the first oxide layer; A dielectric layer, located on the surface of the substrate, and the height of the dielectric layer is higher than the first nitride layer; A conductive structure is located at a preset position in the dielectric layer.

10. The LDMOS device according to claim 9, characterized in that: The LDMOS device comprises a metal field plate and a second contact hole. The metal field plate is located in the dielectric layer and connected to the first oxide layer. The second contact hole is located in the dielectric layer and electrically connected to the source region, the drain region and the gate structure.

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