Stress mitigation structure for compound semiconductor layer stack

Abstract

The invention relates to a stress mitigation structure for a compound semiconductor layer stack. Structures including a compound semiconductor layer stack and methods of forming such structures are provided. The structure includes a device region on a substrate. The device region includes a first section of a layer stack having a plurality of semiconductor layers, and each semiconductor layer includes a compound semiconductor material. The structure also includes an isolation structure disposed around the section of the layer stack, and a device located in the device region. The isolation structure passes through the layer stack to the substrate.

Description

[0001] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under HQ0727790700 awarded by the Defense Microelectronics Activity. The government has certain rights in this invention. Technical Field

[0003] The present application relates generally to semiconductor device manufacturing and integrated circuits, and more particularly to structures including stacks of compound semiconductor layers and methods of forming such structures. Background Art

[0004] Compound semiconductor-based devices, such as high electron mobility transistors, can be deployed in high voltage power electronic devices. Compound semiconductors are characterized by exploitable material properties, such as carrier mobility greater than that of silicon, and a wider band gap than silicon. Compound semiconductors can include Group III elements (e.g., aluminum, gallium, and / or indium) and Group V elements (e.g., nitrogen, phosphorus, arsenic, and / or antimony) in combination with Group III elements. A common wide bandgap compound semiconductor used to construct compound semiconductor-based devices is gallium nitride. A high electron mobility transistor can include a heterojunction between crystalline compound semiconductor materials having different bandgaps, such as a heterojunction between binary gallium nitride and ternary aluminum gallium nitride. During operation, a two-dimensional electron gas is formed near the heterojunction and defines a channel of the high electron mobility transistor.

[0005] Compound semiconductor-based devices may include a stack of compound semiconductor layers grown by heteroepitaxial growth on a wafer. Stress may be managed by adjusting the compound semiconductor layers during epitaxial growth. Despite the goal of managing stress during epitaxial growth, the wafer and layer stack may still contain significant levels of post-growth stress. The contained stress may cause wafer cracking or wafer fracture during subsequent thermal and mechanical steps. Reducing the thickness of the wafer during subsequent thermal and mechanical steps may exacerbate cracking and fracture.

[0006] Improved structures comprising stacks of compound semiconductor layers and methods of forming such structures are desired. Summary of the invention

[0007] In one embodiment of the present invention, a structure includes a device region located on a substrate. The device region includes a section of a layer stack, the layer stack has a plurality of semiconductor layers, and each semiconductor layer includes a compound semiconductor material. The structure also includes an isolation structure disposed around the section of the layer stack, and a device located in the device region. The isolation structure passes through the layer stack to the substrate.

[0008] In one embodiment of the present invention, a method includes forming a device region on a substrate, wherein the device region includes a section of a layer stack, the layer stack includes a plurality of semiconductor layers, and each semiconductor layer includes a compound semiconductor material. The method also includes forming an isolation structure disposed around the section of the layer stack and forming a device in the device region. The isolation structure passes through the layer stack to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0010] Figure 1 A cross-sectional view of a structure is shown at an initial manufacturing stage of a processing method in accordance with an embodiment of the present invention.

[0011] Figure 2 Display in Figure 1 Top view of the structure at a later stage of fabrication.

[0012] Figure 2A Display the approximate Figure 2 A cross-sectional view taken along line 2A-2A.

[0013] Figure 3 Display in Figure 2 Top view of the structure at a later stage of fabrication.

[0014] Figure 3A Display the approximate Figure 3 A cross-sectional view taken along line 3A-3A.

[0015] Figure 4 Display in Figure 3 , 3A A cross-sectional view of the structure at a later stage of fabrication.

[0016] Figure 5 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0017] Figure 6 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0018] Figure 7 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0019] Figure 8 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0020] Fig. 9 A top view showing a structure according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0021] Please refer to Figure 1 According to an embodiment of the present invention, structure 10 may include substrate 12 and layer stack 14 formed on top surface 11 of substrate 12. Substrate 12 may be a bulk wafer composed of single crystal semiconductor material (e.g., single crystal silicon). In one embodiment, the single crystal semiconductor material of substrate 12 may have a diamond lattice structure with a <111> crystal orientation specified by Miller index. In one embodiment, substrate 12 may include single crystal silicon with a diamond lattice structure with a <111> crystal orientation. For substrate 12 with a <111> crystal orientation, the (111) crystal plane is parallel to the top surface of substrate 12, and the

[111] crystal orientation is perpendicular to the (111) plane. In one embodiment, substrate 12 may be composed entirely of semiconductor material with a <111> crystal orientation. Substrate 12 may be doped with a p-type dopant (e.g., boron). In alternative embodiments, substrate 12 may be a different type of substrate, such as a sapphire substrate, an engineered substrate, etc. In an alternative embodiment, substrate 12 may be a silicon-on-insulator substrate.

[0022] The layer stack 14 may include a seed layer 16, a buffer layer 18, a channel layer 20, and a donor layer 22, each layer comprising one or more compound semiconductor materials. The seed layer 16 (which provides a thin nucleation film for the growth of the buffer layer 18) may be composed of, for example, aluminum nitride. The layers 16, 18, 20, 22 may be deposited successively using an epitaxial growth process (e.g., metal organic chemical vapor deposition, vapor phase epitaxy, or molecular beam epitaxy) to form the layer stack 14. The layer stack 14 may have a thickness of, for example, about one micron to about five microns between the top surface 15 of the layer stack 14 and the top surface 11 of the substrate 12.

[0023] The layers 16, 18, 20, 22 of the layer stack 14 may each have a single crystal crystal structure, or alternatively, a substantially single crystal crystal structure with varying degrees of crystal defectivity. The buffer layer 18 may be composed of one or more binary or ternary III-V compound semiconductor materials, such as gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination of these materials. The buffer layer 18 may include a superlattice that is adjusted in terms of material composition, doping, layering, and / or layer thickness to accommodate lattice mismatch, thermal property differences, and mechanical property differences between the material of the substrate 12 and the material of the channel layer 20. The channel layer 20 (disposed above the buffer layer 18) may include, for example, gallium nitride doped with carbon or iron. The donor layer 22 (disposed above the channel layer 20) may include a ternary III-V compound semiconductor (e.g., aluminum gallium nitride) that provides a heterointerface with the buffer layer 18 having a different composition. The channel layer 20 may include a layer composed of undoped gallium nitride adjacent to the donor layer 22 , and an optional barrier layer composed of, for example, aluminum nitride may be located between the channel layer 20 and the donor layer 22 .

[0024] Please refer to Figure 2 , Figure 2A , wherein similar reference numerals denote Figure 1 24. In one embodiment, the device region 26 is formed by patterning the layer stack 14 to define the channel 24. In one embodiment, an etch mask can be formed by a lithography process over the layer stack 14, and an etching process can be used to etch and remove the unmasked section of the layer stack 14 to define the channel 24. The masked section of the layer stack 14 can determine the patterned shape of the device region 26 and the patterned shape of the channel 24. In one embodiment, the etching process can be a reactive ion etching process. The device region 26 represents an unpatterned and intact section of the layer stack 14, which is surrounded by different channels 24 on all sides.

[0025] The trench 24 enters the layer stack 14 from the top surface 15. In one embodiment, the trench 24 may extend completely through the entire thickness of the layer stack 14 from the top surface 15 to the substrate 12 so that the bottom of the trench 24 is coextensive with the substrate 12. In one embodiment, the trench 24 and the device area 26 may be surrounded on all sides by non-patterned sections of the layer stack 14 to define a patterned area surrounded by the edge 13. In one embodiment, the trench 24 may occupy at least forty percent (40%) of the patterned area including the trench 24 and the device area 26. In one embodiment, the trench 24 may occupy forty percent (40%) to ninety percent (90%) of the patterned area including the trench 24 and the device area 26. In one embodiment, the trench 24 may occupy five percent (5%) to ninety percent (90%) of the patterned area including the trench 24 and the device area 26.

[0026] The grooves 24 (adjacent the perimeter of the device area 26 and the surrounding section of the layer stack 14) define a continuous recessed space relative to the top surface 15 of the layer stack 14. The grooves 24 have an aspect ratio of width to depth that depends on their position within the patterned area. The depth D of the grooves 24 (which can be measured from the top surface 15 of the layer stack 14 to the top surface 11 of the substrate 12) can be uniform within the range of the patterned area. In one embodiment, the width of the grooves 24 can vary to provide different aspect ratios.

[0027] The groove 24 between the edge 27 of the device area 26 and the adjacent section of the layer stack 14 adjacent to the patterned area at the edge 13 can be characterized by a width W1. The groove 24 between the edge 28 of the device area 26 and the adjacent section of the layer stack 14 adjacent to the patterned area at the edge 13 can be characterized by a width W2. The groove 24 between the edge 29 of the device area 26 and the adjacent section of the layer stack 14 adjacent to the patterned area at the edge 13 can be characterized by a width W3. The groove 24 between the edge 30 of the device area 26 and the adjacent section of the layer stack 14 adjacent to the patterned area at the edge 13 can be characterized by a width W4. In one embodiment, the widths of at least two of the grooves 24 arranged around the device area 26 can be different. In one embodiment, the widths of all the grooves 24 arranged around the device area 26 can be different. For example, the width W1 can be greater than the widths W2, W3, W4, the width W2 can be less than the widths W1, W3, W4, and the width W3 can be less than the width W4. In one embodiment, the difference in aspect ratio between a pair of trenches 24 (e.g., trenches 24 having width W1 and trenches 24 having width W2) may be greater than one order of magnitude. In one embodiment, the difference in aspect ratio between a pair of trenches 24 (e.g., trenches 24 having width W1 and trenches 24 having width W2) may be greater than two orders of magnitude.

[0028] In one embodiment, trench 24 may have vertical sidewalls 21. In an alternative embodiment, trench 24 may have sloped sidewalls 21. The patterned portion of layer stack 14 constituting device region 26 abuts sidewalls 21 of trench 24. The width of trench 24 may be assessed at top surface 15 of layer stack 14. In one embodiment, the width of trench 24 may be measured as the vertical distance between device region 26 and a surrounding section of layer stack 14 at the perimeter of trench 24.

[0029] The device region 26 of the layer stack 14 may subsequently be processed to form a single device. In an alternative embodiment, the device region 26 of the layer stack 14 may subsequently be processed to form a plurality of devices.

[0030] The trenches 24 may be used to relieve stress between the substrate 12 and the layer stack 14 after epitaxial growth of the layer stack 14 on the top surface 11 of the substrate 12. The trenches 24 are formed prior to forming a device in the device region 26. This stress relief may reduce or eliminate the occurrence of wafer cracking and / or wafer breakage during subsequent thermal and mechanical processing steps used to form the device.

[0031] Please refer to Figure 3 , Figure 3A , wherein similar reference numerals denote Figure 2 , 2A 24, and in the next manufacturing stage, a liner 32 may be formed that coats the portion of the top surface 11 of the substrate 12 exposed by the trench 24, as well as the top surface 15 of the segment of the layer stack 14 that constitutes the device area 26 and the segment of the layer stack 14 that surrounds the patterned area including the device area 26 and the trench 24. In one embodiment, the liner 32 may be composed of a dielectric material (e.g., silicon nitride), which is an electrical insulator. In one embodiment, the liner 32 may be conformal, with a uniform thickness, regardless of the topography. The liner 32 (which only partially fills the trench 24) may act as a moisture barrier for the layer stack 14.

[0032] A layer 34 is formed that can fill the remaining volume inside the trench 24 that is not filled by the liner 32. The layer 34 can be deposited and polished by a chemical mechanical polishing process, with the liner 32 acting as a polishing stop layer. In one embodiment, the layer 34 can have a top surface 33 that is substantially coplanar with the top surface 15 of the layer stack 14. In one embodiment, the top surface 33 of the layer 34 can be coplanar with the liner 32 located on the top surface 15 of the segment of the layer stack 14 that constitutes the device area 26 and on the segment of the layer stack 14 that surrounds the patterned area including the device area 26.

[0033] In one embodiment, layer 34 may be composed of a different material than liner 32. In one embodiment, layer 34 may be composed of a dielectric material, such as silicon dioxide, which is an electrical insulator. In one embodiment, liner 32 may be composed of silicon nitride, and layer 34 may be composed of silicon dioxide. In one embodiment, layer 34 may be composed of a metal, such as tungsten, which is an electrical conductor and is electrically isolated from substrate 12 and layer stack 14 at sidewall 21 by liner 32. In one embodiment, liner 32 may be composed of silicon nitride, and layer 34 may be composed of tungsten. In one embodiment, layer 34 may be composed of a polycrystalline semiconductor material, such as polysilicon, which produces a trap-rich interface. In one embodiment, liner 32 may be composed of silicon nitride, and layer 34 may be composed of polysilicon.

[0034] Liner 32 and layer 34 located inside trench 24 may together provide isolation structure 45. Isolation structure 45 abuts different portions of device region 26 around its perimeter. Liner 32 and layer 34 of isolation structure 45 may include compressive stresses to compensate for tensile stresses included in layer stack 14.

[0035] The isolation structure 45 located inside the trench 24 has a plurality of width-to-height aspect ratios depending on the location around the device region 26. The height H of the isolation structure 45 (which can be measured from the top surface 15 of the layer 34 to the top surface 11 of the substrate 12) can coincide with the location inside the trench 24, and the height H can be slightly greater than the depth D of the trench 24. In one embodiment, the width of different portions of the isolation structure 45 can vary to provide different width-to-height aspect ratios. In one embodiment, the width of the different portions of the isolation structure 45 can be equal to the width of different trenches 24. The portion of the isolation structure 45 located in the trench 24 between the edge 27 of the device region 26 and the adjacent section of the layer stack 14 adjacent to the patterned region at the edge 13 can be characterized by the width W1. The portion of the isolation structure 45 located in the trench 24 between the edge 28 of the device region 26 and the adjacent section of the layer stack 14 adjacent to the patterned region at the edge 13 can be characterized by the width W2. The portion of the isolation structure 45 in the trench 24 between the edge 29 of the device region 26 and the adjacent segment of the layer stack 14 adjoining the patterned region at the edge 13 may be characterized by a width W3. The portion of the isolation structure 45 in the trench 24 between the edge 30 of the device region 26 and the adjacent segment of the layer stack 14 adjoining the patterned region at the edge 13 may be characterized by a width W4. In one embodiment, the widths of at least two of the portions of the isolation structure 45 disposed around the device region 26 may be different. In one embodiment, the widths of all portions of the isolation structure 45 disposed around the device region 26 may be different. For example, the width W1 may be greater than the widths W2, W3, W4, the width W2 may be less than the widths W1, W3, W4, and the width W3 may be less than the width W4. In one embodiment, the difference in aspect ratio between a pair of portions of the isolation structure 45 (e.g., a portion of the isolation structure 45 having the width W1 and a portion of the isolation structure 45 having the width W2) may be greater than an order of magnitude. In one embodiment, the difference in aspect ratio between a pair of portions of isolation structure 45 (e.g., a portion of isolation structure 45 having width W1 and a portion of isolation structure 45 having width W2) can be greater than two orders of magnitude. In one embodiment, the width of the portions of isolation structure 45 can be measured as the vertical distance between device region 26 and a surrounding section of layer stack 14 at the perimeter of the patterned area.

[0036] Please refer to Figure 4 , wherein similar reference numerals denote Figure 3 , Figure 3A, and in the next manufacturing stage, a device represented by a high electron mobility transistor 35 can be formed in the device region 26. The high electron mobility transistor 35 includes a gate 36, a source ohmic contact 38, and a drain ohmic contact 40, which are disposed on the top surface of the layer stack 14 in the device region 26. In one embodiment, the gate 36 may include one or more III-V group compound semiconductor materials, and may also include a capping layer composed of, for example, titanium nitride. In one embodiment, the source ohmic contact 38 and the drain ohmic contact 40 may include an ohmic metal, such as titanium, titanium nitride, aluminum, silicon, or a combination of these materials. The gate 36 is disposed in a lateral direction between the source ohmic contact 38 and the drain ohmic contact 40.

[0037] Middle-of-line processing and back-end-of-line processing are then performed, which include forming contacts, vias, and lines of an interconnect structure 55 disposed above the substrate 12 and connected to the gate 36, the source ohmic contact 38, and the drain ohmic contact 40. The electrical connection 42 includes contacts, interconnects, and vias in the metallization level of the interconnect structure 55 coupled to the source ohmic contact 38 of the high electron mobility transistor 35. The electrical connection 44 includes contacts, interconnects, and vias in the metallization level of the interconnect structure 55 coupled to the drain ohmic contact 40 of the high electron mobility transistor 35. The electrical connection 46 includes interconnects and contacts in the metallization level of the interconnect structure 55 coupled to the gate 36 of the high electron mobility transistor 35. In one embodiment, the isolation structure 45 located in the trench 24 may not contact the electrical connection located in the interconnect structure 55.

[0038] Isolation structure 45 may enhance electrical isolation during high frequency operation of HEMT 35. In an alternative embodiment, device region 26 may include a plurality of transistors, each transistor being similar or identical to HEMT 35, for which electrical isolation may be enhanced during high frequency operation.

[0039] Please refer to Figure 5And according to alternative embodiments, structure 10 may be modified so that layer 34 fills only the portion of the volume inside trench 24 that is not filled by liner 32. Isolation structure 45 may also include layers 50, 52 that fill the portion of the volume inside trench 24 that is not filled by liner 32 and layer 34. Layers 50, 52 may be formed after forming layer 34. Layer 52 may be disposed between layer 50 and layer 34. In one embodiment, layer 34 may be composed of a polycrystalline semiconductor material (e.g., polysilicon) that produces a trap-rich interface. In one embodiment, layer 34 and layer 52 may be composed of a dielectric material (e.g., silicon dioxide) that is an electrical insulator. In one embodiment, layer 34 and layer 50 may be composed of different dielectric materials.

[0040] Please refer to Figure 6 And according to an alternative embodiment, a damaged region 54 may be formed in the substrate 12 at the bottom of each trench 24. As indicated by the single arrow, the damaged region 54 may be formed by introducing high energy ions in the substrate 12 by ion implantation. A patterned implantation mask (not shown) may be formed to define selected areas (e.g., location and horizontal dimensions) on the top surface 15 of the layer stack 14 that expose the trenches 24 for implantation, thereby defining the damaged region 54. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to adjust the electrical and physical properties of the damaged region 54. In one embodiment, the implantation conditions may include the normal incidence angle of the ions. In one embodiment, the material of the damaged region 54 may be formed by implanting ions of an electrically inactive species (e.g., nitrogen or argon) into the material of the substrate 12. In one embodiment, the material of the damaged region 54 may be formed by implanting ions of an electrically active species (e.g., arsenic or phosphorus) into the material of the substrate 12. In one embodiment, the material of the damaged region 54 may have a higher resistivity than the undamaged material of the substrate 12. The process continues to form the isolation structure 45 and the high electron mobility transistor 35 .

[0041] Please refer to Figure 7 , wherein similar reference numerals denote Figure 6 , and according to an alternative embodiment, a damaged region 54 can be formed in the substrate 12 and in the layer stack 14 at the sidewall 21 of the trench 24 adjacent to the device region 26. The damaged region 54 can be formed by introducing high energy ions by ion implantation (as shown by the single arrow) in the layer stack 14 under tilted or angled implantation conditions. Alternatively, if the sidewall 21 of the trench 24 is tilted, the damaged region 54 can result. The process continues to form the isolation structure 45 and the high electron mobility transistor 35.

[0042] Please refer to Figure 8According to alternative embodiments, passive devices 56, such as capacitors or inductors, may be formed in one or more of the metallization levels of interconnect structure 55. Isolation structure 45 may be disposed between passive devices 56 and substrate 12 so that passive devices 56 are not located over portions of layer stack 14.

[0043] Please refer to Fig. 9 According to an alternative embodiment, the structure 10 may include an additional device region 60 disposed in the patterned region, and one or more high electron mobility transistors 35 may be formed in the additional device region. The structure 10 may also include a fill shape 62 disposed in the patterned region. The device region 60 and the fill shape 62 (composed of a section of the layer stack 14) may be formed similarly and simultaneously with the formation of the device region 26. In particular, the device region 60 and the fill shape 62 may be sections of the layer stack 14. Additional trenches 24 are defined in the patterned region between the device region 60 and the device region 26, between the fill shape 62 and the device region 60, between the fill shape 62 and the device region 26, and so on. In an alternative embodiment, only the device region 60 may be added to the structure 10. In an alternative embodiment, only the fill shape 62 may be added to the structure 10.

[0044] The process continues to form isolation structure 45 and high electron mobility transistor 35. Isolation structure 45 includes portions with different aspect ratios in trench 24 between different sections of layer stack 14 implemented in device region 26, device region 60, and fill shape 62.

[0045] The method described above is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is provided in a single-chip package (e.g., a plastic carrier having pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier having single-sided or double-sided interconnects or embedded interconnects). In any case, the chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product.

[0046] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0047] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0048] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intermediate feature.

[0049] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A structure, characterized in that: include: substrate; a device region located on the substrate, the device region comprising a first section of a layer stack, the layer stack comprising a plurality of semiconductor layers, and each semiconductor layer comprising a compound semiconductor material; an isolation structure disposed around the first section of the layer stack, the isolation structure passing through the layer stack to the substrate; as well as A device is located in the device area.

2. The structure according to claim 1, characterized in that The device is a high mobility field effect transistor, which includes a source ohmic contact, a drain ohmic contact, and a gate.

3. The structure according to claim 1, characterized in that The isolation structure includes a first portion having a first aspect ratio and a second portion having a second aspect ratio different from the first aspect ratio.

4. The structure according to claim 3, characterized in that The first portion and the second portion of the isolation structure are adjacent to different portions of the device region.

5. The structure according to claim 3, characterized in that The first portion and the second portion of the isolation structure have equal heights.

6. The structure according to claim 3, characterized in that The layer stack includes a first trench passing through the layer stack to the substrate and a second trench passing through the layer stack to the substrate, the first portion of the isolation structure is disposed in the first trench, and the second portion of the isolation structure is disposed in the second trench.

7. The structure according to claim 3, characterized in that The layer stack has a top surface, and the isolation structure has a top surface that is substantially coplanar with the top surface of the layer stack.

8. The structure according to claim 3, characterized in that The layer stack includes a second section and a first trench located between the first section and the second section, and the first portion of the isolation structure is disposed in the first trench.

9. The structure according to claim 8, characterized in that The layer stack includes a third section and a second trench located between the first section and the third section, and the second portion of the isolation structure is disposed in the second trench.

10. The structure according to claim 1, characterized in that The layer stack includes a trench passing through the layer stack to the substrate, the trench adjoining the device region, and the isolation structure includes a layer located in the trench.

11. The structure according to claim 10, characterized in that The layer of the isolation structure includes a dielectric material.

12. The structure according to claim 10, characterized in that The layer of the isolation structure includes a polycrystalline semiconductor material.

13. The structure according to claim 10, characterized in that The layer of the isolation structure includes metal.

14. The structure according to claim 10, characterized in that The trench has a sidewall, the device region is adjacent to the sidewall, and the isolation structure includes a dielectric liner on the device region at the sidewall of the trench.

15. The structure according to claim 1, characterized in that Also includes: an interconnect structure located on the substrate; as well as Passive devices, located in the interconnect structure, Wherein, the isolation structure is arranged between the passive device and the substrate.

16. The structure according to claim 1, characterized in that The compound semiconductor material of at least one of the plurality of semiconductor layers includes gallium nitride.

17. The structure according to claim 1, characterized in that The device area is surrounded by a plurality of trenches in the patterned area, and the plurality of trenches occupy 40% to 90% of the patterned area.

18. The structure according to claim 1, characterized in that The layer stack comprises a trench passing through the layer stack to the substrate, the trench adjoining the substrate, and further comprising: A damaged region of semiconductor material is located in the substrate adjacent to the trench.

19. The structure according to claim 1, characterized in that The layer stack comprises a trench passing through the layer stack to the substrate, the trench adjoining the first section of the layer stack, and further comprising: A damaged region of semiconductor material is located in the first section of the layer stack adjacent to the sidewalls of the trench.

20. A method, characterized in that include: forming a device region on the substrate, wherein the device region includes a section of the layer stack, the layer stack includes a plurality of semiconductor layers, and each semiconductor layer includes a compound semiconductor material; forming an isolation structure disposed around the device region of the layer stack, wherein the isolation structure passes through the layer stack to the substrate; and A device is formed in the device region.

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