Semiconductor device, forming method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a forming method thereof and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device comprises a substrate, a first fin structure and a second fin structure, wherein the first fin structure and the second fin structure are arranged on the substrate; an embedded power rail is arranged in the substrate and comprises a first area and a second area, and the projection of the first area of the embedded power rail on the substrate is located between the projections of the first fin structure and the second fin structure on the substrate. The second area of the embedded power rail is located at one end of the first area of the embedded power rail in the extending direction, and the width of the first area of the embedded power rail is smaller than that of the second area of the embedded power rail. According to the semiconductor device, the width-depth ratio of the partial region of the embedded power rail is increased, so that the stability and the reliability of the semiconductor device can be effectively improved while the voltage drop problem of the semiconductor device is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for forming the same, and an electronic device. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor devices are also continuously developing towards smaller process nodes, making semiconductor integrated circuits smaller in size, with higher circuit precision and higher circuit complexity. Currently, the density of logic semiconductor integrated circuits can be increased by reducing the height of semiconductor devices, but at the same time, the height of semiconductor devices is easily reduced, which can reduce the stability of semiconductor devices. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device and a method for forming the same, and an electronic device, which are used to reduce the loss of an electrode structure and improve the performance of the semiconductor device.

[0004] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided. The semiconductor device includes: a substrate, and a first fin structure and a second fin structure disposed on the substrate; an embedded power rail is disposed in the substrate, the embedded power rail includes a first region and a second region, a projection of the first region of the embedded power rail on the substrate is located between projections of the first fin structure and the second fin structure on the substrate, the second region of the embedded power rail is located at one end of the first region of the embedded power rail in its extension direction, and a width of the first region of the embedded power rail is smaller than a width of the second region of the embedded power rail.

[0006] In this embodiment, an embedded power rail is provided in the substrate, and the second region of the embedded power rail has an increased width compared to the first region thereof, that is, the width-to-depth ratio of a partial region of the embedded power rail is increased, thereby reducing the voltage drop problem of the semiconductor device while effectively improving the stability and reliability of the semiconductor device. Since the embedded power rail releases the surface wiring resources of the semiconductor device, more areas of the semiconductor device can be used for signal transmission lines, which can improve the application density of the semiconductor device.

[0007] In a possible implementation, the semiconductor device further includes a third fin structure, and an extension direction of the third fin structure coincides with an extension direction of the first fin structure; a projection of the first fin structure on the substrate is located on one side of a projection of the second region of the embedded power rail on the substrate, and a projection of the third fin structure on the substrate is located on the other side of a projection of the second region of the embedded power rail on the substrate.

[0008] In this embodiment, a shorter first fin structure and a third fin structure are formed after a portion of a longer fin structure is removed, and the removed portion of the fin structure provides a space with an increased width for the second region of the embedded power rail, so the width of the embedded power rail in its own second region is greater than the width of the embedded power rail 140 in its own first region. Under the condition of the same size of the semiconductor device, compared with the linear embedded power rail, the embedded power rail provided in the embodiment of the present application has an increased width in its own second region, so the embedded power rail has a larger width-to-depth ratio in the second region, which can reduce the overall resistance of the embedded power rail, so as to reduce the impact of the voltage drop problem on the semiconductor device, provide a more stable and reliable power supply for the semiconductor device, and enable the entire semiconductor device to obtain sufficient power supply voltage.

[0009] In a possible implementation, the semiconductor device further includes a dielectric layer disposed on the substrate; a portion of the embedded power rail is disposed in the substrate, and another portion of the embedded power rail is disposed in the dielectric layer. The dielectric layer is used to insulate the embedded power rail from the rest of the semiconductor device.

[0010] In a possible implementation, the semiconductor device further includes an insulating layer, which is disposed on the substrate and covers the first fin structure, the second fin structure and the third fin structure. The insulating layer is used to insulate the embedded power rail from the first fin structure and the second fin structure.

[0011] In a possible implementation manner, a pad is provided between the substrate and the embedded power rail, and the pad is used to insulate the embedded power rail from the substrate.

[0012] In a possible implementation, two ends of the first fin structure are respectively provided with a first source structure and a first drain structure; two ends of the second fin structure are respectively provided with a second source structure and a second drain structure.

[0013] In one possible embodiment, the semiconductor device also includes: a first gate structure spanning the first fin structure, the first fin structure covered by the first gate structure does not overlap with the first source structure and the first drain structure; a second gate structure spanning the second fin structure, the second fin structure covered by the second gate structure does not overlap with the second source structure and the second drain structure.

[0014] In a possible implementation, the embedded power rail is filled with a metal material, and the metal material includes a combination of one or more of the following materials: tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0015] In a second aspect, a method for forming a semiconductor device is provided. The method for forming a semiconductor device includes: forming a substrate; forming a first fin structure and a second fin structure on the substrate respectively; forming an embedded power rail on the substrate, wherein the embedded power rail includes a first region and a second region, a projection of the first region of the embedded power rail on the substrate is located between projections of the first fin structure and the second fin structure on the substrate, the second region of the embedded power rail is located at one end of the first region of the embedded power rail in its extension direction, and a width of the first region of the embedded power rail is smaller than a width of the second region of the embedded power rail.

[0016] In a possible embodiment, forming a first fin structure on a substrate includes: forming a plurality of horizontally arranged fin structures on the substrate; dividing one of the plurality of horizontally arranged fin structures to form a first fin structure and a third fin structure; wherein an extension direction of the third fin structure coincides with an extension direction of the first fin structure; a projection of the first fin structure on the substrate is located on one side of a projection of the second region of the embedded power rail on the substrate, and a projection of the third fin structure on the substrate is located on the other side of a projection of the second region of the embedded power rail on the substrate.

[0017] In a possible implementation, before forming the embedded power rail on the substrate, the formation method further includes: depositing a first insulating material on the substrate, and forming an insulating layer covering the first fin structure, the second fin structure, and the third fin structure through a patterning process.

[0018] Correspondingly, forming an embedded power rail on a substrate includes: forming a patterned photoresist layer on an insulating layer, the patterned photoresist layer covers a portion of the insulating layer, a projection of the covered insulating layer on the substrate covers a portion of the first fin structure, a portion of the second fin structure and a portion of the third fin structure, the covered first fin structure is located on a side of the first fin structure away from the second fin structure, the covered second fin structure is located on a side of the second fin structure away from the first fin structure, and the covered third fin structure is located on a side of the third fin structure away from the second fin structure; using the patterned photoresist layer and the insulating layer not covered by the patterned photoresist layer as masks, forming a groove in the substrate, the projections of the first fin structure and the second fin structure on the substrate are respectively located on both sides of the projection of the groove on the substrate; the groove has different widths in different regions in its extension direction; forming an embedded power rail in the groove; and removing the patterned photoresist layer.

[0019] In a possible implementation, the formation method further includes: removing the insulating layer; depositing a dielectric material on the substrate to form a dielectric layer, wherein a portion of the embedded power rail is disposed in the substrate, and another portion of the embedded power rail is disposed in the dielectric layer.

[0020] In one possible implementation, forming a buried power rail in the groove includes: depositing a metal material in the groove to form the buried power rail, the metal material including a combination of one or more of the following materials: tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0021] In a possible implementation, before forming the buried power rail in the groove, the forming method further includes: depositing a second insulating material in the groove to form a liner covering the sidewall and the bottom of the groove.

[0022] In a possible implementation, the forming method further includes: forming a first source structure and a first drain structure at two ends of the first fin structure respectively; and forming a second source structure and a second drain structure at two ends of the second fin structure respectively.

[0023] In a possible embodiment, the formation method also includes: forming a first gate structure spanning the first fin structure, the first fin structure covered by the first gate structure does not overlap with the first source structure and the first drain structure; forming a second gate structure spanning the second fin structure, the second fin structure covered by the second gate structure does not overlap with the second source structure and the second drain structure.

[0024] In a third aspect, an electronic device is provided. The electronic device comprises a printed circuit board and the semiconductor device provided in the first aspect; the semiconductor device is electrically connected to the printed circuit board.

[0025] Among them, the technical effects brought about by any possible implementation method of the second aspect and the third aspect can refer to the technical effects brought about by different implementation methods of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of the structure of a semiconductor device provided in another embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0030] Figure 4A schematic flow chart of a method for forming a semiconductor device provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of the structure of a semiconductor device provided in another embodiment of the present application;

[0034] Figure 8-Figure 27 A schematic diagram of the structure of a semiconductor device at various stages during the formation process provided by another embodiment of the present application;

[0035] Fig.28 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0038] Additionally, for ease of description, spatially relative terms such as "bottom," "below," "below," "above," "above," etc. may be used herein to describe the relationship of one component or feature to another component, or function as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0039] A semiconductor integrated circuit includes a plurality of transistors, capacitors and other semiconductor devices. In a semiconductor integrated circuit, these semiconductor devices are initially isolated from each other and then interconnected through an interconnection structure to form a functional circuit. Conventional interconnection structures include lateral interconnection structures, such as metal interconnection lines, and vertical interconnection structures, such as through-hole interconnection structures and contacts. However, with the increase in density and power consumption of semiconductor integrated circuits, the design of conventional interconnection structures has become more difficult due to problems such as power noise, IR drop and interconnection coupling.

[0040] In order to further improve the density of semiconductor integrated circuits, an embodiment of the present application provides a semiconductor device, see Figure 1 ,in Figure 1 The (1) is Figure 1 The semiconductor device comprises: a substrate 110, a plurality of fin structures disposed on the substrate 110, an oxide layer 112, and a buried power rail (BPR) 140, wherein the lengths of the plurality of fin structures are the same as the lengths of the substrate 110 in the first direction (eg Figure 1 The length along the y direction shown in (ii) is consistent, and along the second direction of the substrate (such as Figure 1 In the x direction shown in (ii), the x direction is perpendicular to the y direction) and is arranged horizontally in the third direction of the substrate 110 (such as Figure 1 The z direction shown in (a) in the figure is perpendicular to the xy plane) and has a certain height. Since the length of the fin structure provided in this embodiment is relatively long, in order to distinguish in the following examples, the fin structure provided in the embodiment of the present application is as follows. Figure 1 The fin structure in the embodiment is also called a long fin structure. Figure 1In (ii), the first long fin structure 120-1, the second long fin structure 130-1, the third long fin structure 120-2, the fourth long fin structure 120-3, the fifth long fin structure 130-2 and the sixth long fin structure 130-3 are shown. The first long fin structure 120-1, the second long fin structure 130-1, the third long fin structure 120-2, the fourth long fin structure 120-3, the fifth long fin structure 130-2 and the sixth long fin structure 130-3 all extend along a first direction parallel to the substrate 110. Typically, the spacing distances between adjacent long fin structures are all L1, for example, the spacing distances between the first long fin structure 120-1 and the third long fin structure 120-2, the spacing distances between the third long fin structure 120-2 and the fourth long fin structure 120-3, the spacing distances between the second long fin structure 130-1 and the fifth long fin structure 130-2, and the spacing distances between the fifth long fin structure 130-2 and the sixth long fin structure 130-3 are all L1. Since an embedded power rail 140 needs to be formed between the first long fin structure 120-1 and the second long fin structure 130-1, the spacing distance L2 between the first long fin structure 120-1 and the second long fin structure 120-2 should be greater than L1. The projections of the second long fin structure 120-1 and the second long fin structure 130-1 on the substrate 110 are respectively located on both sides of the projection of the buried power rail 140 on the substrate 110, and a portion of the buried power rail 140 is located in the substrate 110, and the other portion is located in the oxide layer 112. The top surfaces of the first long fin structure 120-1, the second long fin structure 130-1, the oxide layer 112 and the buried power rail 140 are flush, and the projection of the buried power rail 140 on the substrate 110 is in a straight line, that is, the buried power rail 140 has a uniform width in its extension direction.

[0041] In an optional embodiment, the process of forming the above-mentioned semiconductor device is as follows: first, a substrate 110 is formed, and a plurality of horizontally arranged fin structures are formed on the substrate 110 by an etching process. Next, an oxide is deposited on the substrate 110 to form an oxide layer 112 covering the substrate 110 and the plurality of fin structures. The oxide layer 112 is flattened by grinding and / or chemical mechanical polishing (CMP) until the top surfaces of the plurality of fin structures are exposed. It can be understood that the top surfaces of the plurality of fin structures refer to the surfaces of the plurality of fin structures away from the substrate 110. Then, a first groove is formed by an etching process, the first groove penetrates the oxide layer 112 and extends to the substrate 110, wherein the projections of the first long fin structure 120-1 and the second long fin structure 120-2 on the substrate 110 are respectively located on both sides of the projection of the first groove on the substrate 110, and finally, a conductive material is filled in the first groove to form an embedded power rail 140.

[0042] In this embodiment, by increasing the spacing distance between the first long fin structure 120-1 and the second long fin structure 120-2, a formation space is provided for the embedded power rail 140, so that the embedded power rail 140 can be disposed in the substrate 110 of the semiconductor device as an interconnect structure, that is, as a Vdd power terminal or a Vss power terminal in the semiconductor device to be connected to a power supply to supply power to the semiconductor device, thereby reducing the height of the semiconductor device and increasing the density of the semiconductor integrated circuit. However, when current passes through the semiconductor device, the resistance of the embedded power rail 140 itself causes a voltage drop inside the semiconductor device. This voltage drop may cause the semiconductor device to operate unstably or even fail to operate properly. Therefore, it is necessary to reduce the resistance of the embedded power rail to reduce the voltage drop (IR drop) problem of the semiconductor device.

[0043] For this purpose, an embodiment of the present application provides a semiconductor device. Refer to Figure 2 , wherein Figure 2 in (1) is Figure 2 a cross-sectional schematic view at AA' in (2). The semiconductor device includes: a substrate 110, and a first fin structure 120a and a second fin structure 130a disposed on the substrate 110; exemplarily, the spacing distance between the first fin structure 120a and the second fin structure 130a is L2, an embedded power rail 140 is disposed in the substrate 110, the embedded power rail 140 includes a first region 141a and a second region 141b, a projection of the first region 141a of the embedded power rail 140 on the substrate 110 is located between projections of the first fin structure 120a and the second fin structure 130a on the substrate 110, the second region 141b of the embedded power rail 140 is located at one end of the first region 141a of the embedded power rail 140 in its extending direction, and a width of the first region 141a of the embedded power rail 140 is smaller than a width of the second region 141b of the embedded power rail 140. Exemplarily, a projection of the embedded power rail 140 on the substrate 110 is in an "丄" shape or in a "丅" shape. That is, a projection of the first region of the embedded power rail 140 on the substrate is in a "丨" shape, and a projection of the second region of the embedded power rail 140 on the substrate is in a "一" shape. It can be understood that the embodiment of the present application does not limit the number of the second regions of the embedded power rail. For example, as Figure 3 shown, the embedded power rail includes two second regions 141b, and the two second regions 141b are respectively located at both ends of the first region 141a of the embedded power rail 140 in its extending direction, that is, a projection of the embedded power rail 140 on the substrate 110 is in an "工" shape.

[0044] In an alternative embodiment, refer to Figure 4The process of forming the semiconductor device is as follows: S10: forming a substrate. Then S20: forming a first fin structure and a second fin structure on the substrate respectively, the first fin structure and the second fin structure both extending along a first direction parallel to the substrate; then, S40: forming an embedded power rail on the substrate, the embedded power rail comprising a first region and a second region, the projection of the first region of the embedded power rail on the substrate is located between the projections of the first fin structure and the second fin structure on the substrate, the second region of the embedded power rail is located at one end of the first region of the embedded power rail in its extension direction, and the width of the first region of the embedded power rail is smaller than the width of the second region of the embedded power rail.

[0045] Considering that the straight embedded power rail reduces its own resistance, it is necessary to increase the aspect ratio, that is, it is necessary to increase the width of the embedded power rail, which will increase the size of the semiconductor device, which is not conducive to improving the device density of the semiconductor integrated circuit. Therefore, in this embodiment, by arranging the embedded power rail in the substrate, the second area of ​​the embedded power rail has an increased width compared with the first area of ​​itself, that is, the aspect ratio of a part of the embedded power rail is increased, thereby reducing the voltage drop (IR drop) problem of the semiconductor device while effectively improving the stability and reliability of the semiconductor device. Since the embedded power rail releases the surface wiring resources of the semiconductor device, more areas of the semiconductor device can be used for signal transmission lines, which can improve the application density of the semiconductor device.

[0046] It should be noted that if Figure 5 As shown, in the semiconductor device provided in this embodiment, a plurality of fin structures may be provided on a side of the first fin structure 120a away from the second fin structure 130a, for example Figure 5 The third long fin structure 120 - 2 and the fourth long fin structure 120 - 3 are shown, and a plurality of fin structures are arranged on a side of the second fin structure 130 a away from the first fin structure 120 a , for example Figure 5 The fifth long fin structure 130-2 and the sixth long fin structure 130-3 are shown. The lengths of the plurality of fin structures are the same as the lengths of the substrate 110 in the first direction (eg Figure 5 The length of the substrate is consistent in the y direction (shown in FIG. 1 ), and along the second direction of the substrate (such as Figure 5The fin structures are arranged horizontally in the x direction shown in the figure, where the x direction is perpendicular to the y direction). Generally, the spacing distance between adjacent fin structures is L1. For example, the spacing distance between the first fin structure 120a and the third long fin structure 120-2, the spacing distance between the third long fin structure 120-2 and the fourth long fin structure 120-3, the spacing distance between the second fin structure 130a and the fifth long fin structure 130-2, and the spacing distance between the fifth long fin structure 130-2 and the sixth long fin structure 130-3 may be L1. Since an embedded power rail needs to be set between the first fin structure 120a and the second fin structure 130a, the spacing distance L2 between the first fin structure 120a and the second fin structure 130a should be greater than L1.

[0047] In an alternative embodiment, see Figure 6 The semiconductor device also includes a third fin structure 120b, and the extension direction of the third fin structure 120b coincides with the extension direction of the first fin structure 120a; the projection of the first fin structure 120a on the substrate 110 is located on one side of the projection of the second region 141b of the embedded power rail 140 on the substrate 110, and the projection of the third fin structure 120b on the substrate 110 is located on the other side of the projection of the second region 141b of the embedded power rail 140 on the substrate 110.

[0048] In a specific example, the process of forming the first fin structure 120a and the third fin structure 120b is as follows: first, a first long fin structure with a longer length is formed on the substrate 110, and then, a portion of the first long fin structure is removed to divide the first long fin structure into the first fin structure 120a and the third fin structure 120b. The area where the portion of the first long fin structure is removed is located can provide a space with increased width for the subsequent formation of the embedded power rail 140. In particular, since the first fin structure 120a and the third fin structure 120b are formed by dividing the first long fin structure, the extension direction of the third fin structure 120b coincides with the extension direction of the first fin structure 120a, and the length of the first long fin structure is greater than the length of the first fin structure 120a and the length of the third fin structure 120b.

[0049] Correspondingly, the formed embedded power rail includes two first regions 141a_1 and 141a_2 and a second region, wherein the projection of one first region 141a_1 on the substrate 110 is located between the projections of the first fin structure 120a and the second fin structure 130a on the substrate 110, and the projection of the other first region 141a_2 on the substrate 110 is located between the projections of the third fin structure 120b and the second fin structure 130a on the substrate 110. The two sides of the projection of the second region of the embedded power rail on the substrate are the projections of the first fin structure and the third fin structure on the substrate respectively, and the second fin structure can be a long fin structure, so that the projection of the formed embedded power rail on the substrate is in the shape of "┤".

[0050] It should be noted that the above embodiments are only examples provided for a better understanding of the technical solutions of the embodiments of the present invention, and are not intended to be the sole limitation of the embodiments of the present application. In other optional examples, the shape of the embedded power rail 140 can also be changed by changing the positions of the first fin structure, the second fin structure, and the third fin structure. For example, the positions of the first fin structure and the third fin structure are exchanged with the second fin structure so that the projection of the corresponding embedded power rail on the substrate is in the shape of a "├".

[0051] In the embodiment of the present application, the number and length of the fin structures provided on the substrate can be changed to form embedded power rails of different shapes. For example, a first fin structure 120a, a second fin structure 130a, a third fin structure 120b and a fourth fin structure 130b with a shorter length and arranged in an array are provided on the substrate to form an embedded power rail 140 such as Figure 7 As shown in (a), the projection of the embedded power rail 140 on the substrate 110 is in the shape of a "cross". In other examples, the length of each fin structure can be changed to form, for example, Figure 7 The projections shown in (ii) to (iv) on the substrate 110 are in the shape of "earth", "stem", or "king". In another example, the number of fin structures can be changed, for example, Figure 7 On the basis of (iv) in the above, a fifth fin structure 120c, a sixth fin structure 120d, a seventh fin structure 130c and an eighth fin structure 130d are added to form Figure 7 The embedded power rail 140 shown in (V) in the figure is projected in a "F" shape on the substrate. In an optional embodiment, the semiconductor device is a fin field-effect transistor (Finfet) device as an example, and the manufacturing process of the semiconductor device in which the embedded power rail is projected in a "X" shape on the substrate and the device structure formed in the manufacturing process are specifically described.

[0052] S10: forming a substrate 110.

[0053] like Figure 8 As shown, the semiconductor device includes a substrate 110. The substrate 110 may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 110 may include other elemental semiconductor materials such as germanium. In some embodiments, the substrate 110 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 110 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0054] S20: Forming a first fin structure 120a and a second fin structure 130a on the substrate 110 respectively. In some optional embodiments, this step further includes:

[0055] S21: forming a dielectric layer 101 on the substrate 110. The dielectric layer 101 may be made of silicon oxide.

[0056] In this embodiment, if Fig. 9 As shown, the dielectric layer 101 is a buffer layer on the substrate 110. In some optional embodiments, in the subsequent process, it is necessary to remove the first hard mask layer used to form the fin structure, and the dielectric layer 101 is used as a stop layer when removing the first hard mask layer 102. In some other optional embodiments, in the subsequent process, it is not necessary to remove the first hard mask layer used to form the fin structure, then the semiconductor device may not perform the step provided in this embodiment to form the dielectric layer 101 during the formation process, and the semiconductor device can be formed only by the steps provided in the following embodiments, and the embodiments of the present application are not limited to this.

[0057] S22 : forming a first hard mask layer 102 on the substrate 110 , and forming a first photoresist layer 103 on the first hard mask layer 102 .

[0058] like Fig.10 As shown, the first photoresist layer 103 is patterned by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0059] The first hard mask layer 102 may be made of silicon oxide, silicon nitride, silicon oxynitride or other suitable materials. The dielectric layer 101 and the first hard mask layer 102 are formed by a deposition process, such as a chemical vapor deposition (CVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process or other suitable processes.

[0060] S23: After patterning the first photoresist layer 103, the first hard mask layer 102 is patterned by using the patterned first photoresist layer 103 as a mask, thereby obtaining a patterned first hard mask layer 102. The structure of the semiconductor device is as follows Fig.11As shown, the semiconductor device includes a substrate 110, and a patterned first hard mask layer 102 and a patterned first photoresist layer 103 formed on the substrate. In some optional embodiments, the dielectric layer 101 and the first hard mask layer 102 are patterned by using the patterned first photoresist layer 103 as a mask, thereby obtaining a patterned dielectric layer 101 and a patterned first hard mask layer 102. The patterned dielectric layer 101 and the patterned first hard mask layer 102 are used as masks when forming a fin structure.

[0061] S24: removing the patterned first photoresist layer 103, and performing an etching process on the substrate 110 by using the patterned first hard mask layer 102 as a mask to form a plurality of layers along the second direction (eg, Fig.12 The fin structure is horizontally arranged in the x direction shown in (ii), for example, see Fig.12 ,in Fig.12 The (1) is Fig.12 (ii) is a cross-sectional view at AA', in which the first long fin structure 120 and the second long fin structure 130 are formed along a first direction parallel to the substrate 110 (eg Fig.12 The y direction shown in (ii) in FIG. 1 extends perpendicular to the x direction), and the lengths of the first long fin structure 120 and the second long fin structure 130 are consistent with the length of the substrate 110 in the first direction.

[0062] The etching process may be a dry etching process or a wet etching process. In some embodiments, the substrate 110 is etched by a dry etching process. The dry etching process includes using a fluorine-based etchant gas, such as SF6, CxFy, NF3, or a combination thereof. The etching process may be a time-controlled process, and the etching process continues until the first long fin structure 120 and the second long fin structure 130 are aligned in the third direction (such as the direction of the substrate 110). Fig.12 In the z direction shown in (a), the z direction is perpendicular to the xy plane) to reach a predetermined height.

[0063] S25: dividing the plurality of fin structures to form a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure.

[0064] In this embodiment, if Fig.13As shown, after forming a plurality of long fin structures on the substrate, a portion of the fin structures can be removed by etching, so that the plurality of fin structures are respectively divided to form a plurality of shorter fin structures. For example, after forming a first long fin structure 120 and a second long fin structure 130 on the substrate, the first long fin structure 120 is divided into a first fin structure 120a and a third fin structure 120b, and the second long fin structure 130 is divided into a second fin structure 130a and a fourth fin structure 130b. The area where the removed fin structure is located can provide a space for increasing the width for the subsequent formation of an embedded power rail. Among them, since the first fin structure 120a and the third fin structure 120b are both formed by dividing the first long fin structure 120, and the second fin structure 130a and the fourth fin structure 130b are formed by dividing the second long fin structure 130, the extension direction of the third fin structure 120b coincides with the extension direction of the first fin structure 120a, the extension direction of the fourth fin structure 130b coincides with the extension direction of the second fin structure 130a, and the length of the first long fin structure 120 is greater than the length of the first fin structure 120a and the length of the third fin structure 120b; the length of the second long fin structure 130 is greater than the length of the second fin structure 130a and the length of the fourth fin structure 130b. It should be noted that the number of fin structures can be adjusted according to actual applications and is not limited to Fig.13 According to the number of fin structures shown in FIG. 1 , a plurality of long fin structures with a longer length can be formed on the substrate, and the long fin structures can be divided to form shorter fin structures to form a fin structure array on the substrate.

[0065] S30 : depositing a first insulating material on the substrate 110 to form an insulating layer 150 covering the first fin structure 120 a , the second fin structure 130 a , the third fin structure 120 b , and the fourth fin structure 130 b .

[0066] In some embodiments, the first insulating material may be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or other low dielectric constant (low-k) insulating materials. The first insulating material may be deposited by a chemical vapor deposition (CVD) process, a spin-on glass process, or other applicable processes, and then an insulating layer 150 covering the first fin structure 120a, the second fin structure 130a, the third fin structure 120b, and the fourth fin structure 130b is formed by a patterning process, see Fig.14 ,in Fig.14 The (1) is Fig.14 In the cross-sectional diagram at AA' in (b), the insulating layer 150 covering the first fin structure 120a has an inverted U shape. Similarly, the insulating layers 150 covering the second fin structure 130a, the third fin structure 120b and the fourth fin structure 130b also have an inverted U shape.

[0067] S40: forming an embedded power rail 140 on the substrate 110. This step further includes:

[0068] S41 : forming a patterned second photoresist layer 160 on the insulating layer 150 , wherein the second photoresist layer 160 covers a portion of the insulating layer 150 .

[0069] In this embodiment, if Fig.15 As shown, Fig.15 The (1) is Fig.15 In (ii) the cross-sectional schematic diagram at AA', the patterned second photoresist layer 160 covers part of the insulating layer 150, and the projection of the covered insulating layer 150 on the substrate 110 covers part of the first fin structure 120a, part of the second fin structure 130a, part of the third fin structure 120b and part of the fourth fin structure 130b, the covered first fin structure 120a is located on the side of the first fin structure 120a away from the second fin structure 130a, and the covered second fin structure 130a is located on the side of the second fin structure 130a away from the first fin structure 120a; the covered third fin structure 120b is located on the side of the third fin structure 120b away from the fourth fin structure 130b, and the covered fourth fin structure 130b is located on the side of the fourth fin structure 130b away from the third fin structure 120b.

[0070] S42: Using the second photoresist layer 160 and the insulating layer 150 not covered by the photoresist layer 160 as masks, a first groove 115 is formed in the substrate 110.

[0071] In this embodiment, if Fig.16 As shown, Fig.16 The (1) is Fig.16 In the cross-sectional schematic diagram at AA' in (ii), the second photoresist layer 160 and the insulating layer 150 not covered by the photoresist layer 160 are used as masks, that is, the second photoresist layer 160 and the exposed insulating layer 150 are used as masks, and a first groove 115 is formed in the substrate through an etching process, the first groove 115 includes a first area 116a and a second area 116b, the first area 116a of the first groove 115 is located between the projections of the first fin structure 120a and the second fin structure 130a on the substrate 110; the projection of the first fin structure 120a on the substrate 110 is located on one side of the projection of the second area 116b of the first groove 115 on the substrate 110, and the projection of the third fin structure 120b on the substrate 110 is located on the other side of the projection of the second area 116b of the first groove 115 on the substrate 110.

[0072] It is understandable that the embodiments of the present application do not limit the number of the first region 116a and the second region 116b of the first groove 115. For example, the first groove 115 includes two second regions 116b, that is, the projection of the buried first groove 115 on the substrate 110 is in the shape of "工". Or, the first groove 115 includes two first regions 116a, that is, the projection of the first groove 115 on the substrate 110 is in the shape of "十". In other examples, the first groove 115 may further include a plurality of first regions 116a and a plurality of second regions 116b to form a first groove 115 whose projection on the substrate 110 is in the shape of "干", "土", "王" or "丰".

[0073] In a specific example, taking the projection of the first groove 115 on the substrate 110 as an example in the shape of "十", the first groove 115 includes two first regions 116a_1 and 116a_2 and a second region 116b. The projection of the first region 116a of the first groove 115 on the substrate 110 is in the shape of "|", and the projection of one of the first regions 116a_1 of the first groove 115 on the substrate 110 is located between the projection of the first fin structure 120a on the substrate 110 and the projection of the second fin structure 130a on the substrate 110. The projection of the other first region 116a_2 of the first groove 115 on the substrate 110 is located between the projection of the third fin structure 120b on the substrate 110 and the projection of the fourth fin structure 130b on the substrate 110. The projection of the second region 116b of the first groove 115 on the substrate 110 is in the shape of "一". The second region 116b of the first groove 115 can be regarded as being located at the lower end of the first region 116a_1 of the first groove 115 in the extending direction of the first region 116a, or it can be regarded that the second region 116b of the first groove 115 is located at the upper end of the first region 116a_2 in the extending direction of the first region 116a. Since the partial fin structures removed when forming the first fin structure 120a, the second fin structure 130a, the third fin structure 120b, and the fourth fin structure 130b provide a space with an increased width for the second region 116b of the first groove 115 on the substrate 110, the width of the second region 116b of the first groove 115 is greater than the width of the first region 116a of the first groove 115.

[0074] S43: Deposit a second insulating material in the first groove 115 to form a liner 117 covering the sidewalls and the bottom of the first groove 115. Refer to Fig.17 , and the liner 117 is used to insulate the subsequent formed embedded power rail 140 from the substrate 110.

[0075] S44: Form an embedded power rail 140 in the first groove 115.

[0076] In this embodiment, since different regions of the first groove 115 in its extending direction have different widths, the embedded power rail 140 formed in the first groove 115 also has different widths in its extending direction. For example, see Fig.18 ,in, Fig.18 The (1) is Fig.18 (ii) is a cross-sectional view at AA' in FIG. The projection of the embedded power rail 140 on the substrate is in the shape of a "+", wherein the embedded power rail 140 includes a first region 141a and a second region 141b, the projection of the first region 141a of the embedded power rail 140 on the substrate 110 is in the shape of a "|", and the projection of the first region 141a of the embedded power rail 140 on the substrate 110 is located between the projection of the first fin structure 120a on the substrate 110 and the projection of the second fin structure 130a on the substrate 110, and the embedded The projection of the second region 141b of the power rail 140 on the substrate 110 is in an "I" shape, and the projections of the first fin structure 120a and the second fin structure 130a on the substrate 110 are located on one side of the projection of the second region of the buried power rail 140 on the substrate 110 perpendicular to the extension direction, and the projections of the third fin structure 120b and the fourth fin structure 130b on the substrate 110 are located on the other side of the projection of the second region of the buried power rail 140 on the substrate 110 perpendicular to the extension direction.

[0077] Since the part of the fin structure removed when forming the first fin structure 120a, the second fin structure 130a, the third fin structure 120b, and the fourth fin structure 130b provides a space with an increased width on the substrate 110 for the second region 141b of the buried power rail 140, the width L4 of the buried power rail 140 in its own second region 141 is greater than the width L3 of the buried power rail 140 in its own first region. Under the condition of the same size of the semiconductor device, compared with the straight buried power rail, the buried power rail provided in the embodiment of the present application has an increased width in its own second region, so the buried power rail has a larger width-to-depth ratio in the second region, which can reduce the overall resistance of the buried power rail, so as to reduce the impact of the voltage drop (IR drop) problem on the semiconductor device, provide a more stable and reliable power supply for the semiconductor device, and enable the entire semiconductor device to obtain sufficient power supply voltage.

[0078] In a specific example, a metal material is deposited in the first groove 115 to form a buried power rail 140, and the formed buried power rail 140 is in contact with the liner 117 and the insulating layer 150, respectively. The deposited metal material may include a combination of one or more of the following materials: tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum. The buried power rail may be formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD) or plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD).

[0079] It is understandable that those skilled in the art can control the amount of deposited metal material to control the height of the buried power rail. In an optional example, the top surface of the buried power rail is higher than the top surface of the substrate. Or in another optional example, the top surface of the buried power rail 140 is flush with the top surfaces of the first fin structure 120a and the second fin structure 130a.

[0080] S45: removing the second photoresist layer 160. For example, the second photoresist layer 160 may be dissolved by a stripping solution to remove the second photoresist layer 160, or the second photoresist layer 160 may be stripped by a stripping device.

[0081] S51: removing the insulating layer 150. Optional, see Fig.19 When removing the insulating layer 150, the first hard mask layer 102 formed on top of the first fin structure 120a, the second fin structure 130a, the third fin structure 120b and the fourth fin structure 130b can serve as a stop layer, so that the insulating layer 150 is removed only by an etching process without destroying the shapes of the first fin structure 120a, the second fin structure 130a, the third fin structure 120b and the fourth fin structure 130b.

[0082] S52 : depositing a dielectric material on the substrate 110 to form a dielectric layer 165 , wherein a portion of the embedded power rail 140 is disposed in the substrate 110 , and another portion of the embedded power rail 140 is disposed in the dielectric layer 165 .

[0083] like Fig.19 and Fig. 20As shown, after the insulating layer 150 is removed, there is a gap between the buried power rail 140 and the first fin structure 120a and the second fin structure 130a, so it is necessary to deposit a dielectric material on the substrate to form a dielectric layer 165. The dielectric layer 165 fills the gaps between the buried power rail 140 and the first fin structure 120a, the second fin structure 130a, the third fin structure 120b and the fourth fin structure 130b, and covers the exposed surface of the buried power rail 140 to insulate the buried power rail 140, that is, a part of the buried power rail 140 is set in the substrate 110, and the other part of the buried power rail 140 is set in the dielectric layer 165.

[0084] In another optional embodiment, the insulating layer 150 may be retained, and the formed dielectric layer 165 only covers the exposed top surface of the buried power rail 140 , thereby insulating the buried power rail 140 .

[0085] S61 : forming a first dummy gate dielectric layer 171 and a first dummy gate electrode layer 172 across the first fin structure.

[0086] In some optional embodiments, such as Fig.21 As shown, a first dummy gate dielectric layer 171 and a first dummy gate electrode layer 172 are formed on the dielectric layer 165 across the first fin structure. The first dummy gate dielectric layer 171 is made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high k), or a combination thereof. The first dummy gate dielectric layer 171 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0087] In some optional embodiments, the first dummy gate electrode layer 172 is made of a conductive or non-conductive material. In some embodiments, the first dummy gate electrode layer 172 is made of polysilicon. The first dummy gate electrode layer 172 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0088] S62: forming a second hard mask layer 175 on the first dummy gate electrode layer. Patterning the second hard mask layer 175 to form a patterned second hard mask layer 175. The patterned second hard mask layer is used to protect underlying layers from being etched during subsequent processes.

[0089] S63 : removing a portion of the first dummy gate dielectric layer 171 and a portion of the first dummy gate electrode layer 172 to form a first dummy gate structure 170 a .

[0090] like Fig. 22 As shown, the first dummy gate structure 170a includes a portion of the first dummy gate dielectric layer 171 and a portion of the first dummy gate electrode layer 172 positioned below the patterned second hard mask layer 175. For example, the first end dummy gate dielectric layer 171 and the first dummy gate electrode layer 172 not blocked by the second hard mask layer 175 are removed by an etching process such as a wet etching process or a dry etching process.

[0091] It should be noted that the second pseudo gate structure 179a spanning the second fin structure 130a, the third pseudo gate structure 170b spanning the third fin structure 120b, and the fourth pseudo gate structure 179b spanning the fourth fin structure 130b can be formed with reference to the above-mentioned process of forming the first pseudo gate structure 170a. Similarly, the second pseudo gate structure 179a includes a second pseudo gate dielectric layer 176 and a second pseudo gate electrode layer 177 spanning the second fin structure, the third pseudo gate structure 170b includes a third pseudo gate dielectric layer and a third pseudo gate electrode layer spanning the third fin structure 120b, and the fourth pseudo gate structure 179b includes a fourth pseudo gate dielectric layer and a fourth pseudo gate electrode layer spanning the fourth fin structure 130b. The second dummy gate structure 179a, the third dummy gate structure 170b and the fourth dummy gate structure 179b can be formed in the same step as the first dummy gate structure 170a, or can be formed in different steps. After the first dummy gate structure 170a, the second dummy gate structure 179a, the third dummy gate structure 170b and the fourth dummy gate structure 179b are formed, the second hard mask layer 175 should be removed, which will not be described in detail in the embodiments of the present application.

[0092] S71 : forming a second groove 121 in the first fin structure 120 a .

[0093] like Fig.23 As shown, a second groove 121 is formed at both ends of the first fin structure 120a. Exemplarily, the second groove 121 has a bottom surface and a sidewall, wherein the bottom surface of the second groove 121 is flush with or lower than the top surface of the embedded power rail 140. It can be understood that the etching width of the second groove 121 in the horizontal direction can be adjusted according to actual applications, so that the etching profile of the second groove 121 can be controlled.

[0094] S72 : forming a first source structure 125 a and a first drain structure 126 a in the second groove 121 in the first fin structure 120 a , respectively.

[0095] In some embodiments, Fig.24As shown, the first source structure 125a and the first drain structure 126a formed at both ends of the first fin structure 120a are strained electrode structures. In some embodiments, the first source structure 125a and the first drain structure 126a include a combination of one or more of the following materials: silicon germanium (SiGe), germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP). Optionally, when the semiconductor device is an N-type FET (NFET) device, the first source structure 125a and the first drain structure 126a may include epitaxially grown silicon (Si). Optionally, when the semiconductor device is a P-type FET (PFET) device, the first source structure and the first drain structure may include epitaxially grown silicon germanium (SiGe).

[0096] In some optional embodiments, the first source structure 125a and the first drain structure 126a are formed by growing a strained material in the second groove 121 by an epitaxy (EPI) process. In addition, the lattice constant of the strained material may be different from the lattice constant of the substrate. The epitaxy process may include a selective epitaxial growth (SEG) process, a CVD deposition technique (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy or other suitable EPI processes.

[0097] It should be noted that the second groove 121 can be formed in the second fin structure 130a, the third fin structure 120b and the fourth fin structure 130b with reference to the above-mentioned process of forming the first source structure 125a and the first drain structure 126a, thereby forming a second source structure 135a and a second drain structure 136a arranged at both ends of the second fin structure 130a, a third source structure 125b and a third drain structure 126b arranged at both ends of the third fin structure, and a fourth source structure 135b and a fourth drain structure 136b arranged at both ends of the fourth fin structure 130b. The second source structure 135a, the second drain structure 136a, the third source structure 125b, the third drain structure 126b, the fourth source structure 135b and the fourth drain structure 136b can be formed in the same step as the first source structure 125a and the first drain structure 126a, or in different steps, which will not be repeated in the embodiments of the present application.

[0098] S81: forming an interlayer dielectric layer (ILD) 180 on the substrate.

[0099] like Fig.25 As shown, the interlayer dielectric layer 180 can be a multilayer structure made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials and / or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicate glass (FSG), carbon-doped silicon oxide, fluorinated amorphous carbon, polyparaxylene, bibenzocyclobutene (BCB) or polyimide. The interlayer dielectric layer can be formed by flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other applicable processes.

[0100] Then, according to some optional embodiments, a polishing process is performed on the interlayer dielectric layer 180. In some optional embodiments, the interlayer dielectric layer 180 is planarized by a chemical mechanical polishing (CMP) process until the top surfaces of the plurality of dummy gate structures are exposed.

[0101] S82 : removing the first dummy gate structure 170 a to form a trench 181 surrounded by the interlayer dielectric layer 180 .

[0102] like Fig.26 As shown, the first dummy gate structure 170a is removed by performing a first etching process and a second etching process. For example, the first dummy gate electrode layer 172 is removed by the first etching process, and the first dummy gate dielectric layer 171 is removed by the second etching process. In some embodiments, the first etching process is a dry etching process, and the second etching process is a wet etching process. In some embodiments, the dry etching process includes using an etching gas such as carbon tetrafluoride (CF 4 ), argon (Ar), nitrogen trifluoride (NF 3 ), chlorine (Cl 2 ), helium (He), hydrogen bromide (HBr), oxygen (O 2 ), nitrogen (N 2 ), fluoromethane (CH 3 F), methane (CH 4 ), difluoromethane (CH 2 F 2 ) or a combination thereof.

[0103] S83: Filling the first gate dielectric layer 191 and the first gate electrode layer 192 in the trench 181, thereby forming a first gate structure 190 including the first gate dielectric layer 191 and the first gate electrode layer 192, as shown in FIG. Fig. 27 As shown, the first gate structure 190 crosses the first fin structure 120 a .

[0104] In some optional embodiments, the first gate dielectric layer 191 is made of silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), a dielectric material with a low dielectric constant (low k), or a combination thereof. In some embodiments, the first gate dielectric layer 191 is made of an extremely low k (ELK) dielectric material having a dielectric constant (k) of less than about 2.5. In some embodiments, the ELK dielectric material includes carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE) (Teflon) or carbon oxide silicon polymer (SiOC). In some embodiments, the ELK dielectric material includes an existing dielectric material in a porous form, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK or porous silicon oxide (SiO2). In some embodiments, the first gate dielectric layer 191 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process or by a spin coating process.

[0105] In some optional embodiments, the first gate electrode layer 192 is made of a gate metal material. The gate metal material may include an N work function metal or a P work function metal. The N work function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or a combination thereof. The P work function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru) or a combination thereof.

[0106] It should be noted that the second gate structure 195 spanning the second fin structure 130a, the third gate structure spanning the third fin structure 120b, and the fourth gate structure spanning the fourth fin structure 130b can be formed by referring to the above-mentioned process of forming the first gate structure 190. Similarly, the second gate structure 195 includes a second gate dielectric layer 196 and a second gate electrode layer 197 spanning the second fin structure 130a, the third gate structure includes a third gate dielectric layer and a third gate electrode layer spanning the third fin structure 120b, and the fourth gate structure includes a fourth gate dielectric layer and a fourth gate electrode layer spanning the fourth fin structure 130b. The second gate structure 195, the third gate structure and the fourth gate structure may be formed in the same step as the first gate structure 190, or may be formed in different steps. In some other optional examples, the semiconductor device may also be provided with only two gate structures, i.e., a first gate structure spanning the first fin structure and the second fin structure is provided in the semiconductor device, and a second gate structure spanning the third fin structure and the fourth fin structure is provided. The first gate structure includes a second gate dielectric layer and a second gate electrode layer spanning the first fin structure 120a and the second fin structure 130a, and the second gate structure includes a second gate dielectric layer and a second gate electrode layer spanning the third fin structure 120b and the fourth fin structure 130b. The specific formation process may refer to the above-mentioned process of forming the first gate structure spanning the first fin structure, and the embodiments of the present application will not be repeated here.

[0107] In the above embodiments, each of the first gate dielectric layer, the first gate electrode layer, and the dielectric layer is a single layer, which is for illustration purposes only and is not to be construed as limiting the present invention. In some embodiments, at least one of these described components may be a multilayer structure as required.

[0108] In the above-mentioned embodiment, a "gate last" process is implemented to form the semiconductor device. However, it is also possible to form another type of semiconductor device by using a process similar to that provided in the embodiment of the present application, applying another process such as a "gate first" process, for example, a gate-all-around field-effect transistor (GAAFET) can also be formed according to a formation method similar to that provided in the embodiment of the present application.

[0109] It should be noted that the above embodiments are only specific examples for better understanding the technical methods of the embodiments of the present application, and are not intended to be the sole limitation of the embodiments of the present application. The order of semiconductor devices can also be appropriately adjusted according to the manufacturing method provided in the embodiments of the present application, or increased or decreased according to actual conditions, or combined with other manufacturing process flows of semiconductor devices to produce another type of semiconductor device.

[0110] The present application embodiment provides another electronic device. Fig.28 As shown, the electronic device may include the semiconductor device 100 and the printed circuit board (PCB) 200 provided in the above embodiment. The electronic device may include a CMOS image sensor, a NAND flash memory, a high bandwidth memory, a mobile phone, a tablet computer (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device and other electronic products. The embodiments of the present application do not impose any special restrictions on the specific form of the above electronic device.

[0111] Another embodiment of the present application also provides a non-transitory computer-readable storage medium for use with a computer, the computer having software for creating and manufacturing the above-mentioned semiconductor device, and one or more computer-readable data structures are stored on the computer-readable storage medium, and the one or more computer-readable data structures have control data for manufacturing the semiconductor device provided in any one of the diagrams provided above, such as photoresist layer data.

[0112] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The invention comprises: a substrate, and a first fin structure and a second fin structure arranged on the substrate; An embedded power rail is provided in the substrate, the embedded power rail includes a first region and a second region, a projection of the first region of the embedded power rail on the substrate is located between projections of the first fin structure and the second fin structure on the substrate, the second region of the embedded power rail is located at one end of the first region of the embedded power rail in an extension direction thereof, and a width of the first region of the embedded power rail is smaller than a width of the second region of the embedded power rail.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a third fin structure, and an extension direction of the third fin structure coincides with an extension direction of the first fin structure; The projection of the first fin structure on the substrate is located on one side of the projection of the second region of the buried power rail on the substrate, and the projection of the third fin structure on the substrate is located on the other side of the projection of the second region of the buried power rail on the substrate.

3. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor device further comprises a dielectric layer disposed on the substrate; A portion of the buried power rail is disposed in the substrate, and another portion of the buried power rail is disposed in the dielectric layer.

4. The semiconductor device according to claim 2, characterized in that The semiconductor device further includes an insulating layer disposed on the substrate and covering the first fin structure, the second fin structure and the third fin structure.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: A pad is disposed between the substrate and the buried power rail.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: A first source structure and a first drain structure are respectively disposed at two ends of the first fin structure; A second source structure and a second drain structure are respectively disposed at two ends of the second fin structure.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises: A first gate structure spanning the first fin structure, wherein the first fin structure covered by the first gate structure does not overlap with the first source structure and the first drain structure; A second gate structure straddles the second fin structure, and the second fin structure covered by the second gate structure does not overlap with the second source structure and the second drain structure.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that: The buried power rail is filled with a metal material, and the metal material includes a combination of one or more of the following materials: tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

9. A method for forming a semiconductor device, characterized in that: include: forming a substrate; forming a first fin structure and a second fin structure on the substrate respectively; An embedded power rail is formed on the substrate, the embedded power rail comprising a first region and a second region, a projection of the first region of the embedded power rail on the substrate is located between projections of the first fin structure and the second fin structure on the substrate, the second region of the embedded power rail is located at one end of the first region of the embedded power rail in an extension direction thereof, and a width of the first region of the embedded power rail is smaller than a width of the second region of the embedded power rail.

10. The method according to claim 9, characterized in that Forming a first fin structure on the substrate includes: forming a plurality of horizontally arranged fin structures on the substrate; One of the multiple horizontally arranged fin structures is divided to form the first fin structure and the third fin structure; wherein an extension direction of the third fin structure coincides with an extension direction of the first fin structure, a projection of the first fin structure on the substrate is located on one side of a projection of the second region of the embedded power rail on the substrate, and a projection of the third fin structure on the substrate is located on the other side of a projection of the second region of the embedded power rail on the substrate.

11. The method according to claim 9 or 10, characterized in that: Before forming the buried power rail on the substrate, the forming method further comprises: Depositing a first insulating material on the substrate, and forming an insulating layer covering the first fin structure, the second fin structure, and the third fin structure through a patterning process; Accordingly, forming a buried power rail on the substrate comprises: Forming a patterned photoresist layer on the insulating layer, wherein the patterned photoresist layer covers a portion of the insulating layer, a projection of the covered insulating layer on the substrate covers a portion of the first fin structure, a portion of the second fin structure, and a portion of the third fin structure, the covered first fin structure is located on a side of the first fin structure away from the second fin structure, the covered second fin structure is located on a side of the second fin structure away from the first fin structure, and the covered third fin structure is located on a side of the third fin structure away from the second fin structure; Using the patterned photoresist layer and the insulating layer not covered by the patterned photoresist layer as masks, a groove is formed in the substrate, and the projections of the first fin structure and the second fin structure on the substrate are respectively located on both sides of the projection of the groove on the substrate; forming a buried power rail in the recess; The patterned photoresist layer is removed.

12. The method according to claim 11, characterized in that The forming method further comprises: removing the insulating layer; A dielectric material is deposited on the substrate to form a dielectric layer, a portion of the embedded power rail is disposed in the substrate, and another portion of the embedded power rail is disposed in the dielectric layer.

13. The method according to claim 11, characterized in that Forming a buried power rail in the recess includes: A metal material is deposited in the groove to form the buried power rail, the metal material comprising a combination of one or more of the following materials: tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

14. The method according to claim 11, characterized in that Before forming the buried power rail in the groove, the forming method further comprises: A second insulating material is deposited in the groove to form a liner covering the sidewall and bottom of the groove.

15. The method according to any one of claims 9 to 14, characterized in that: The forming method further comprises: forming a first source structure and a first drain structure at two ends of the first fin structure respectively; A second source structure and a second drain structure are respectively formed at two ends of the second fin structure.

16. The method according to claim 15, characterized in that The forming method further comprises: forming a first gate structure spanning the first fin structure, wherein the first fin structure covered by the first gate structure does not overlap with the first source structure and the first drain structure; A second gate structure is formed across the second fin structure, and the second fin structure covered by the second gate structure does not overlap with the second source structure and the second drain structure.

17. An electronic device, characterized in that: The invention comprises a printed circuit board and the semiconductor device according to any one of claims 1 to 8; the semiconductor device and the printed circuit board are electrically connected.

Images