Source / drain dielectric structures and methods of making same

Abstract

The invention relates to a source / drain dielectric structure and a method of manufacturing the same. The present disclosure describes a semiconductor device having a source / drain dielectric. The semiconductor device includes: a channel structure on a substrate; a dielectric structure on the substrate and adjacent to the channel structure; and an epitaxial structure on a top surface of the dielectric structure. The epitaxial structure is in contact with the channel structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly to source / drain dielectric structures and methods of manufacturing the same. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling down increases the complexity of semiconductor manufacturing processes and increases the difficulty of process control in semiconductor devices. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a channel structure on a substrate; a gate structure surrounding the channel structure; an internal spacer adjacent to the gate structure and ends of the channel structure; a dielectric structure on the substrate and adjacent to the channel structure, wherein the dielectric structure is in contact with the internal spacer; and an epitaxial structure on a top surface of the dielectric structure, wherein the epitaxial structure is in contact with the channel structure.

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first channel structure and a second channel structure stacked on a fin structure; a dielectric structure on the fin structure and between the first channel structure and the second channel structure, wherein the dielectric structure extends into the fin structure and the dielectric structure is below the first channel structure and the second channel structure; and a source / drain (S / D) structure on a top surface of the dielectric structure, wherein the S / D structure is in contact with the first channel structure and the second channel structure.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a channel structure stacked on a fin structure on a substrate; forming a gate structure on the channel structure; forming a recess adjacent to the channel structure and the gate structure in the fin structure; depositing a dielectric material in the recess to form a dielectric structure on the fin structure; and growing an epitaxial structure on a top surface of the dielectric structure, wherein the epitaxial structure is in contact with the channel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures.

[0007] Figure 1 An isometric view of a semiconductor device having a source / drain dielectric structure is shown in accordance with some embodiments.

[0008] Figure 2A and Figure 2B A cross-sectional view of a semiconductor device having a source / drain dielectric structure according to some embodiments is shown.

[0009] Figure 3A and Figure 3B A cross-sectional view of a semiconductor device having another source / drain dielectric structure is shown in accordance with some embodiments.

[0010] Figure 4 is a flow chart of a method for fabricating a semiconductor device having a source / drain dielectric structure according to some embodiments.

[0011] FIG. 5A to FIG. 17 Cross-sectional views of a semiconductor device having a source / drain dielectric structure at various stages of its fabrication are shown in accordance with some embodiments.

[0012] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature and the second feature are formed in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures relative to another (some) elements or features. These spatially relative terms are also intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0015] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0016] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the specification is interpreted by persons skilled in the relevant art(s) based on the teachings herein.

[0017] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0018] With the increase in demand for lower power consumption, higher performance and smaller semiconductor devices, the size of semiconductor devices is constantly being scaled down. The continuous scaling down of device size and the growing demand for device performance may require various process and material improvements, which may have multiple challenges. For example, nanostructured transistors can provide improved device performance with channels configured with stacked nanosheets / nanowires. Nanostructured transistors may include finFETs, gate all-around field effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanobelt transistors, and transistors of other similar structures. Shallow trench isolation (STI) regions may be formed between stacked nanosheets / nanowires for isolation. However, the substrate parasitic channel under the stacked nanosheets / nanowires may introduce leakage current and reduce device performance. In addition, STI oxide slag removal in the epitaxial growth of the source / drain (S / D) structure during the cleaning process may cause gate collapse defects and yield losses.

[0019] Various embodiments in the present disclosure provide methods for forming S / D dielectric structures in semiconductor devices (e.g., nanostructure transistors) and / or other semiconductor devices in integrated circuits (ICs). In some embodiments, a channel structure stacked on a fin structure may be formed on a substrate. An S / D dielectric structure may be formed, the S / D dielectric structure being on the fin structure and adjacent to the channel structure. An epitaxial structure may be formed on the top surface of the S / D dielectric structure. The epitaxial structure may contact the channel structure. In some embodiments, the S / D dielectric structure may extend into the fin structure, and the top surface of the S / D dielectric structure may be below the bottom surface of the channel structure. In some embodiments, an STI region may be formed on the substrate between the channel structure and the adjacent channel structure. An S / D dielectric structure may be formed on the STI region. In some embodiments, a gate structure surrounding the channel structure may be formed, a gate spacer may be formed on the sidewall of the gate structure, and a spacer dielectric structure may be formed on the gate spacer. In some embodiments, the S / D dielectric structure and the spacer dielectric structure may include the same dielectric material. In some embodiments, the S / D dielectric structure may include a first S / D dielectric layer having a first dielectric material and a second S / D dielectric layer having a second dielectric material, the second dielectric material being different from the first dielectric material. In some embodiments, the S / D dielectric structure on the fin structure may reduce leakage current and improve device performance. The S / D dielectric structure on the STI region may reduce STI oxide drossing, reduce gate collapse defects, and improve process yield.

[0020] Figure 1 An isometric view of a semiconductor device 100 having an S / D dielectric structure is shown in accordance with some embodiments. Figure 2A and Figure 2B 1 and 2 show the semiconductor device 100 having an S / D dielectric structure according to some embodiments. Figure 1 Partial cross-sectional views along lines AA and BB are shown. Figure 3A and Figure 3B 1 and 2 show the semiconductor device 100 having another S / D dielectric structure according to some embodiments. Figure 1 A partial cross-sectional view of line AA and line BB is shown.

[0021] In some embodiments, the semiconductor device 100 may include transistors 102A to 102C, such as Figure 1As shown. In some embodiments, transistors 102A to 102C may include nanostructure transistors. Nanostructure transistors may include finFETs, GAA FETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. Nanostructure transistors may provide channels in stacked nanosheet / nanowire configurations. In some embodiments, transistors 102A to 102C may be n-type field effect transistors (NFETs). In some embodiments, transistors 102A to 102C may be p-type field effect transistors (PFETs). In some embodiments, any of transistors 102A to 102C may be an NFET or a PFET. Although Figure 1 Three transistors are shown, but semiconductor device 100 can have any number of transistors. In addition, semiconductor device 100 can be incorporated into an IC by using other structural components (e.g., conductive vias, wires, dielectric layers, passivation layers, and interconnects, which are not shown for simplicity). Unless otherwise noted, the discussion of elements of transistors 102A to 102C with the same annotations applies to each other. In addition, the same reference numerals generally represent the same, functionally similar, and / or structurally similar elements.

[0022] refer to Figures 1 to 3B , a semiconductor device 100 having transistors 102A to 102C may be formed on a substrate 104, and the semiconductor device 100 may be isolated by a shallow trench isolation (STI) region 106. Each of the transistors 102A to 102C may include a fin structure 108, a sidewall spacer 109, a gate dielectric layer 124, a gate structure 112, a gate spacer 114, an inner spacer 121, an S / D dielectric structure 111, an S / D structure 110, an etch stop layer (ESL) 116, and an interlayer dielectric (ILD) layer 118. In some embodiments, as Figure 2A and Figure 3A As shown, transistors 102A- 102C may have nanostructures 122 - 1 , 122 - 2 , and 122 - 3 (collectively “nanostructures 122 ”) on fin structure 108 .

[0023] refer to Figures 1 to 3B, the substrate 104 may include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a silicon wafer). In some embodiments, the substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. In addition, the substrate 104 may be doped, depending on the design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0024] STI regions 106 can provide electrical isolation between transistors 102A to 102C, electrical isolation from adjacent transistors (not shown) on substrate 104, and / or adjacent active and passive components (not shown) integrated with substrate 104 or deposited on substrate 104. STI regions 106 can be made of dielectric materials. In some embodiments, STI regions 106 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In some embodiments, STI regions 106 can include a multi-layer structure.

[0025] refer to Figures 1 to 3B , nanostructures 122 and fin structures 108 may be formed on patterned portions of substrate 104. Embodiments of the nanostructures and fin structures disclosed herein may be patterned by any suitable method. For example, the nanostructures and fin structures may be patterned using one or more photolithography processes, including double patterning processes or multi-patterning processes. Double patterning processes or multi-patterning processes may combine photolithography processes and self-alignment processes to form, for example, patterns having a spacing smaller than that obtainable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers may be formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructures and fin structures.

[0026] like Figures 1 to 3BAs shown, the nanostructure 122 and the fin structure 108 may extend along the X-axis of the transistors 102A to 102C. In some embodiments, the nanostructure 122 and the fin structure 108 may be disposed on the substrate 104. The nanostructure 122 may include a stack of nanostructures 122-1, 122-2, and 122-3, which may be in the form of nanosheets, nanowires, or nanoribbons. Each nanostructure 122 may serve as a channel structure and form a channel region below the gate structure 112 of the transistors 102A to 102C. In some embodiments, the nanostructure 122 and the fin structure 108 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon germanium. The semiconductor material of the nanostructure 122 and the fin structure 108 may be undoped or may be in-situ doped during the process of forming the nanostructure 122 and the fin structure 108. In some embodiments, as Figure 2A and Figure 3A As shown, the nanostructure 122 below the gate structure 112 may form a channel region of the semiconductor device 100 and represent a current-carrying channel structure of the semiconductor device 100. Figure 2A and Figure 3A , three layers of nanostructures 122 are shown, but transistors 102A to 102C can have any number of nanostructures 122. In some embodiments, nanostructures 122 can have a thickness in the range of about 3 nm to about 8 nm along the Z axis. In some embodiments, the spacing between adjacent nanostructures 122 can be in the range of about 5 nm to about 12 nm along the Z axis.

[0027] refer to Figures 1 to 3B , a gate dielectric layer 124 may be formed on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer 123 and a high-k dielectric layer 125. In some embodiments, the gate dielectric layer 124 may not include an interface layer and include a high-k dielectric layer 125 in direct contact with the nanostructure 122. In some embodiments, the interface layer 123 may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer 123 may have a thickness ranging from about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer 125 may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0028] In some embodiments, Figures 1 to 3BAs shown, a gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and a metal filler. The one or more work function metal layers may include a work function metal to tune the threshold voltage (V t ). In some embodiments, the gate structures 112 of the NFET and PFET devices may have substantially the same work function metal. In some embodiments, the gate structures 112 of the NFET and PFET devices may have different work function metals. In some embodiments, as Figure 2A and Figure 3A As shown, each nanostructure 122 may be surrounded by a gate structure 112, for which reason the gate structure 112 may be referred to as a "gate all around (GAA) structure", and the transistors 102A to 102C may also be referred to as "GAA FETs 102A to 102C". The one or more work function metal layers may surround the nanostructure 122, and may include work function metal to tune the V of the transistors 102A to 102C. t In some embodiments, transistors 102A to 102C may include any number of work function metal layers for V t Tuning (e.g., ultra-low V t , Low V t , and standard V t ).

[0029] In some embodiments, the NFETs 102A to 102C may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium silicon nitride, or other suitable work function metals. In some embodiments, the PFETs 102A to 102C may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbon nitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a metal layer stack. The metal layer stack may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0030] refer to Figures 1 to 3BAccording to some embodiments, a gate spacer 114 may be disposed on a sidewall of the gate structure 112, and the gate spacer 114 is in contact with the gate dielectric layer 124. A sidewall spacer 109 may be disposed on a sidewall of the fin structure 108. An internal spacer 121 may be disposed adjacent to an end of the nanostructure 122 and between the S / D structure 110 and the gate structure 112. The gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, aluminum oxide, a low-k material, and a combination of the foregoing. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include different insulating materials. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the inner spacer 121 may include a single layer or a stack of insulating layers. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the inner spacer 121 may have a low-k material having a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8).

[0031] In some embodiments, an S / D dielectric structure 111 may be disposed on the fin structure 108 and on the STI region 106. In some embodiments, the S / D dielectric structure 111 may include aluminum oxide (AlO x ), Silicon Carbide (SiC x ), silicon nitride (SiN x ), Silicon Carbonitride (SiC x N 1-x ), silicon oxycarbonitride (SiO y C x N 1-x-y ), low-k materials, and combinations of the foregoing. In some embodiments, AlO x x in can be in the range of from about 0.8 to about 1.5. In some embodiments, SiC x x in can be in the range of from about 0.8 to about 1. In some embodiments, SiN x x in can be in the range of from about 0.8 to about 1.33. In some embodiments, SiC x N 1-x The x in may be in the range of from about 0.5 to about 1. In some embodiments, SiO y C x N 1-x-y x in the range from about 0.1 to about 0.3, and SiO y C x N 1-x-yWhere y may be in a range from about 0.1 to about 0.3. In some embodiments, the S / D dielectric structure 111 on the fin structure 108 may reduce leakage current and improve device performance. In some embodiments, the S / D dielectric structure 111 on the STI region 106 may reduce STI oxide drossing adjacent to the gate structure 112, reduce gate collapse defects, and improve process yield.

[0032] In some embodiments, the S / D dielectric structure 111 may have a thickness 111t in the range from about 3 nm to about 7 nm along the Z-axis. If the thickness 111t is less than about 3 nm, the S / D dielectric structure 111 may not reduce leakage current in the semiconductor device 100 and may not improve device performance. If the thickness 111t is greater than about 7 nm, the S / D dielectric structure 111 may contact the nanostructure 122, which may result in a reduction in device current between the nanostructure 122 and the S / D structure 110 and a reduction in device performance.

[0033] In some embodiments, Figures 1 to 3B As shown, the S / D dielectric structure 111 may extend into the fin structure 108 and the STI region 106. The top surface of the S / D dielectric structure 111 may be above the top surface of the fin structure 108 and the STI region 106. In some embodiments, the top surface of the S / D dielectric structure 111 may be below the bottom surface of the bottom nanostructure 122-1 to avoid contact between the S / D dielectric structure 111 and the nanostructure 122. If the S / D dielectric structure 111 contacts the nanostructure 122, the device current between the nanostructure 122 and the S / D structure 110 may be reduced, and the device performance may be reduced.

[0034] In some embodiments, Figure 3A and Figure 3B As shown, the S / D dielectric structure 111 may include a first dielectric layer 111-1 and a second dielectric layer 111-2. The first dielectric layer 111-1 may include a first dielectric material disposed on the fin structure 108 and the STI region 106. The second dielectric layer 111-2 may include a second dielectric material disposed on the first dielectric layer 111-1. In some embodiments, each of the first dielectric material and the second dielectric material may include AlO. x 、SiC x 、SiN x 、SiC x N 1-x 、SiO y C x N 1-x-y, low-k material, or a combination of the foregoing. In some embodiments, the first dielectric material may be different from the second dielectric material. In some embodiments, the first dielectric layer 111-1 and the second dielectric layer 111-2 may reduce the parasitic capacitance of the semiconductor device 100 and further improve the device performance.

[0035] In some embodiments, Figure 2A and Figure 3A As shown, the semiconductor device may further include a spacer dielectric structure 115 on the sidewalls of the gate structure 112 and above the gate spacer 114. In some embodiments, the spacer dielectric structure 115 and the S / D dielectric structure 111 may be formed in the same process. In some embodiments, the spacer dielectric structure 115 may include the same dielectric material as the S / D dielectric structure 111. In some embodiments, the spacer dielectric structure 115 may have a height along the Z-axis in a range from about 1 nm to about 5 nm.

[0036] refer to Figures 1 to 3B , an S / D structure 110 may be disposed on the top surface of the S / D dielectric structure 111. The S / D structure 110 may be used as an S / D region of the transistors 102A to 102C. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, a cone, a rhombus, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material (e.g., silicon germanium) that is different from the material of the substrate 104, and stress may be applied to the channel region under the gate structure 112. Since the lattice constant of such an epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is strained to increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenide phosphide.

[0037] In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped using n-type dopants (e.g., phosphorus and arsenic) during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors may be used, such as phosphine, arsine, and other n-type doping precursors. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped using p-type dopants (e.g., boron, indium, and gallium) during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors may be used, such as diborane (B2H6), boron trifluoride (BF3), and other p-type doping precursors.

[0038] In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. In some embodiments, each of the one or more epitaxial layers may include Si and may differ from one another based on, for example, doping concentration and / or epitaxial growth process conditions. In some embodiments, each of the one or more epitaxial layers may include silicon germanium and may differ from one another based on, for example, doping concentration, epitaxial growth process conditions, and / or a relative concentration of germanium relative to silicon.

[0039] refer to Figures 1 to 3B , an ESL 116 may be disposed on the S / D structure 110, on the S / D dielectric structure 111 over the STI region 106, and on the sidewalls of the gate spacer 114 and the sidewall spacer 109. The ESL 116 may be configured to protect the S / D structure 110, the S / D dielectric structure 111, and the gate structure 112 during subsequent formation of an S / D contact structure on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination of the foregoing.

[0040] An ILD layer 118 may be disposed on the ESL 116 over the S / D structures 110 and the STI regions 106. In some embodiments, the ILD layer 118 may include a dielectric material deposited using a deposition method suitable for flowable dielectric materials. For example, flowable silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may include silicon oxide.

[0041] In some embodiments, FIG. 2A to FIG. 2B as well as FIG. 3A to FIG. 3BAs shown, the semiconductor device 100 may further include a protection layer 120 on the ILD layer 118. In some embodiments, the protection layer 120 may include a dielectric material, such as silicon nitride. In some embodiments, the protection layer 120 may protect the ILD layer 118 from etching damage in a subsequent sheet formation process. In some embodiments, the top surfaces of the gate structure 112, the spacer dielectric structure 115, and the protection layer 120 may be coplanar.

[0042] In some embodiments, the semiconductor device 100 may further include an S / D contact structure, a gate contact structure, metal lines, metal vias, interconnects, and additional ILD layers, which are not described in detail for clarity.

[0043] Figure 4 is a flow chart of a method 400 for manufacturing a semiconductor device 100 having an S / D dielectric structure according to some embodiments. The method 400 may not be limited to nanostructured transistor devices and may be applied to other devices that benefit from S / D dielectric structures. Additional manufacturing operations may be performed between various operations of the method 400 and may be omitted, which is merely for clarity and ease of description. Additional processes may be provided before, during and / or after the method 400; one or more of these additional processes are briefly described herein. In addition, not all operations may be required to perform the disclosure provided herein. In addition, some operations may be performed simultaneously or in conjunction with Figure 4 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0044] For the purpose of illustration, reference will be made to the manufacture of FIG. 5A to FIG. 17 An example manufacturing process of the semiconductor device 100 is described as follows. Figure 4 The operation shown. Figure 5A , Figures 6 to 8 , Fig.9A , Figures 10 to 16A as well as Fig.17 The semiconductor device 100 according to some embodiments is shown in various stages of its manufacture. Figure 1 A partial cross-sectional view along line AA is shown. Figure 5B , Fig. 9B 16B and 16B show the semiconductor device 100 at various stages of its manufacture according to some embodiments. Figure 1 The above describes a partial cross-sectional view of the line BB. Figures 1 to 3B The same annotation as the element in FIG. 5A to FIG. 17 Components in .

[0045] refer to Figure 4The method 400 begins with operation 410 and a process of forming a channel structure stacked on a fin structure on a substrate. Figure 5A and Figure 5B As shown, nanostructure 122 and nanostructures 522-1, 522-2, and 522-3 (collectively referred to as "nanostructure 522") stacked on fin structure 108 may be formed on substrate 104. In some embodiments, nanostructures 122 and 522 may be stacked in an alternating configuration. In some embodiments, nanostructures 122 and 522 may be epitaxially grown on substrate 104 and subsequently patterned to form nanostructures 122 and 522 stacked on fin structure 108. In some embodiments, nanostructures 122 and 522 may be in the form of nanosheets, nanowires, or nanobelts. In some embodiments, nanostructures 122 and 522 may include semiconductor materials similar to or different from substrate 104. In some embodiments, fin structure 108 may include the same semiconductor material as substrate 104. In some embodiments, nanostructures 122 and 522 may include different semiconductor materials. For example, nanostructure 122 may include silicon, and nanostructure 522 may include silicon germanium having an atomic percentage of germanium from about 10% to about 40%.

[0046] The embodiments of the fin structure 108 and the nanostructures 122 and 522 disclosed herein may be patterned by any suitable method. For example, the fin structure and the nanostructure may be patterned using one or more photolithography processes (including a double patterning process or a multi-patterning process). The double patterning process or the multi-patterning process may combine a photolithography process and a self-alignment process to form, for example, a pattern having a pitch smaller than that obtainable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process may be used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure and the nanostructure.

[0047] like Figure 5A and Figure 5BAs shown, after forming the nanostructure 122, an STI region 106 may be formed between adjacent stacks of the nanostructures 122 and 522, a sacrificial gate structure 512 may be formed on the nanostructure 122 and the STI region 106, a gate spacer 114 may be formed on the sacrificial gate structure 512, and the nanostructures 122 and 522 and the STI region 106 may be recessed. For the sake of clarity, these processes are not described in detail. In some embodiments, after recessing the nanostructures 122 and 522, an opening 511 may be formed in the nanostructures 122 and 522 and the STI region 106 between adjacent sacrificial gate structures 512. In some embodiments, the opening 511 may extend into the fin structure 108 and the STI region 106. In some embodiments, the opening 511 may have a recess depth 511r in the fin structure 108 and the STI region 106 along the Z axis in the range from about 2 nm to about 5 nm. The recess depth 511r may ensure that the bottom nanostructure 522 on the fin structure 108 is completely removed.

[0048] In some embodiments, the inner spacer 121 may be formed after the opening 511 is formed, such as Figures 6 to 8 As shown. In some embodiments, forming the internal spacer 121 may include laterally recessing the nanostructure 522, depositing a spacer layer 721, and trimming the spacer layer 721. In some embodiments, the nanostructure 522 may be laterally etched to form a recess 621 between the ends of the nanostructure 122. The spacer layer 721 may be conformally deposited in the recess 621 and on the gate spacer 114 and the nanostructure 122. In some embodiments, the spacer layer 721 may completely fill the recess 621. In some embodiments, the spacer layer 721 may be directionally etched to trim the spacer layer 721 on the gate spacer 114 and the nanostructure 122. After the directional etching process, the remaining spacer layer 721 in the recess 621 may form the internal spacer 121.

[0049] refer to Figure 4 In operation 420, a dielectric structure is formed on the fin structure and adjacent to the channel structure. Fig.9A As shown, an S / D dielectric structure 111 may be formed on the fin structure 108 and adjacent to the nanostructure 122. In some embodiments, as shown in FIG. Fig. 9B As shown, an S / D dielectric structure 111 may also be formed on the STI region 106 between adjacent sacrificial gate structures 512. In some embodiments, as Fig.9A and Fig. 9BAs shown, a spacer dielectric structure 115 may be formed on the sacrificial gate structure 512. In some embodiments, a dielectric material may be directionally deposited on the top surfaces of the fin structure 108, the STI region 106, and the gate spacer 114 to form the S / D dielectric structure 111 and the spacer dielectric structure 115. In some embodiments, the dielectric material may not be deposited on the sidewall surfaces of the gate spacer 114.

[0050] In some embodiments, the dielectric material may be deposited by plasma enhanced atomic layer deposition (PEALD) with a bias function. PEALD may be operated at a pressure of about 1 torr to about 5 torr, with a precursor feed time of from about 0.01 s to about 0.2 s, a purge time of from about 0.5 s to about 1.5 s, and a plasma treatment time of from about 0.1 s to about 0.3 s. In some embodiments, the precursor feed time of the PEALD process in the diffusion mode may be less than the precursor feed time of the ALD process in the reaction mode (which may be from about 0.2 s to about 3 s). In some embodiments, the precursor treatment time of the PEALD process in the diffusion mode may be less than the precursor treatment time of the ALD process in the reaction mode (which may be from about 0.3 s to about 2 s). In some embodiments, the bias function and parameter range of the PEALD process may facilitate directional deposition of dielectric material on the top surfaces of the fin structure 108, the STI region 106, and the gate spacer 114 without sidewall surface growth. In some embodiments, the dielectric material may be deposited by physical vapor deposition (PVD) at a temperature from about 350° C. to about 450° C. at a pressure from about 0.1 mTorr to about 10 mTorr. The DC plasma power of the PVD process may be in a range from about 1 kW to about 3 kW, and the processing time may be in a range from about 2 s to about 20 s. These parameter ranges for the PVD process may facilitate directional deposition of the dielectric material on the top surfaces of the fin structure 108, the STI region 106, and the gate spacer 114 without sidewall surface growth.

[0051] In some embodiments, the S / D dielectric structure 111 and the spacer dielectric structure 115 may include the same dielectric material, such as AlO. x 、SiC x 、SiN x 、SiC x N 1-x 、SiO y C x N 1-x-y , low-k materials, and combinations of the foregoing. In some embodiments, AlO x x in can be in the range of from about 0.8 to about 1.5. In some embodiments, SiC xx in can be in the range of from about 0.8 to about 1. In some embodiments, SiN x x in can be in the range of from about 0.8 to about 1.33. In some embodiments, SiC x N 1-x The x in may be in the range of from about 0.5 to about 1. In some embodiments, SiO y C x N 1-x-y x in the range from about 0.1 to about 0.3, and SiO y C x N 1-x-y Where y can be in a range from about 0.1 to about 0.3. In some embodiments, the S / D dielectric structure 111 on the fin structure 108 can reduce leakage current and improve device performance. In some embodiments, the S / D dielectric structure 111 on the STI region 106 can reduce STI oxide slag adjacent to the gate structure 112, reduce gate collapse defects, and improve process yield. In some embodiments, the S / D dielectric structure 111, the spacer dielectric structure 115, the gate spacer 114, and the internal spacer 121 can include the same dielectric material. In some embodiments, the S / D dielectric structure 111 and the spacer dielectric structure 115 can include a different dielectric material than the gate spacer 114 and / or the internal spacer 121.

[0052] In some embodiments, the S / D dielectric structure 111 may have a thickness 111t in the range from about 3 nm to about 7 nm along the Z-axis. If the thickness 111t is less than about 3 nm, the S / D dielectric structure 111 may not reduce leakage current in the semiconductor device 100 and may not improve device performance. If the thickness 111t is greater than about 7 nm, the S / D dielectric structure 111 may contact the nanostructure 122, which may result in a reduction in device current between the nanostructure 122 and the S / D structure 110 and a reduction in device performance.

[0053] In some embodiments, Fig.9A and Fig. 9B As shown, the S / D dielectric structure 111 may extend into the fin structure 108 and the STI region 106. The top surface of the S / D dielectric structure 111 may be above the top surface of the fin structure 108 and the STI region 106. In some embodiments, the top surface of the S / D dielectric structure 111 may be below the bottom surface of the bottom nanostructure 122 to avoid contact between the S / D dielectric structure 111 and the nanostructure 122. If the S / D dielectric structure 111 contacts the nanostructure 122, the device current between the nanostructure 122 and the subsequently formed S / D structure 110 may be reduced, and the device performance may be reduced.

[0054] refer to Figure 4 In operation 430, an epitaxial structure is grown on the top surface of the dielectric structure and in contact with the channel structure. Fig.10 As shown, an S / D structure 110 may be grown on the top surface of the S / D dielectric structure 111 and in contact with the nanostructure 122. In some embodiments, the S / D structure 110 may be epitaxially grown on the top surface of the S / D dielectric structure 111 and the end of the nanostructure 122. The S / D structure 110 may be used as an S / D region of the transistors 102A to 102C. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, a cone, a rhombus, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material (e.g., silicon germanium) different from the material of the substrate 104, and stress may be applied to the channel region under the gate structure 112. In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped using an n-type dopant (e.g., phosphorus and arsenic) during the epitaxial growth process. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or a III-V material (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped with a p-type dopant (e.g., boron, indium, and gallium) during the epitaxial growth process. In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition.

[0055] In some embodiments, the ESL 116 and the ILD layer 118 may be deposited after forming the S / D structure 110, such as Fig.11 The ESL 116 may be conformally deposited on the S / D structure 110, on the S / D dielectric structure 111 on the STI region 106, and on the sidewalls of the gate spacer 114. In some embodiments, an ILD layer 118 may be deposited on the ESL 116 over the S / D structure 110 and the STI region 106 using a deposition method suitable for flowable dielectric materials.

[0056] In some embodiments, a protective layer 120 may be formed after depositing the ESL 116 and the ILD layer 118. Fig.12 In some embodiments, a dielectric material (eg, silicon nitride) may be deposited on the ILD layer 118 and over the sacrificial gate structure 512, followed by a chemical mechanical polishing (CMP) process. In some embodiments, the protective layer 120 may protect the ILD layer 118 from etching damage in a subsequent sheet formation process.

[0057] In some embodiments, the sacrificial gate structure 512 may be replaced with the metal gate structure 112 after forming the protection layer 120, such as Figures 13 to 15 Replacing the sacrificial gate structure 512 may include removing the sacrificial gate structure 512, removing the nanostructure 522, and depositing the metal gate structure 112. In some embodiments, Fig.13 As shown, the first etching process can remove the sacrificial gate structure 512. In some embodiments, as shown in FIG. Fig.14 As shown, the second etching process can remove the nanostructure 522. In some embodiments, as Fig.15 As shown, an interface layer 123 and a high-k dielectric layer 125 may be formed on the sidewalls of the nanostructure 122 and the gate spacer 114. A gate structure 112 may be deposited on the nanostructure 122. In some embodiments, after depositing the gate structure 112, a CMP process may planarize the top surfaces of the gate structure 112, the spacer dielectric structure 115, and the protection layer 120, as shown in FIG. Figure 2A and Figure 2B In some embodiments, after the CMP process, the spacer dielectric structure 115 may remain on the gate spacer 114, as shown in FIG. Figure 2A shown.

[0058] In some embodiments, in operation 420, a dielectric structure including two dielectric layers may be formed on the fin structure. Fig.16A and Fig. 16B As shown, the first dielectric layer 111-1 may include a first dielectric material directionally deposited on the fin structure 108, the STI region 106, and the gate spacer 114. The second dielectric layer 111-2 may include a second dielectric material directionally deposited on the first dielectric layer 111-1. In some embodiments, the first dielectric material and the second dielectric material may be deposited by the same deposition method as described above for the S / D dielectric structure 111, such as a PEALD process and a PVD process. In some embodiments, each of the first dielectric material and the second dielectric material may include AlO x 、SiC x 、SiN x 、SiC x N 1-x 、SiO y C x N 1-x-y, low-k material, or a combination of the foregoing. In some embodiments, the first dielectric material can be different from the second dielectric material. In some embodiments, the first dielectric layer 111-1 and the second dielectric layer 111-2 on the fin structure 108 can reduce leakage current and improve device performance. In some embodiments, the first dielectric layer 111-1 and the second dielectric layer 111-2 on the STI region 106 can reduce STI oxide drossing adjacent to the gate structure 112, reduce gate collapse defects, and improve process yield.

[0059] In some embodiments, after depositing the first dielectric layer 111-1 and the second dielectric layer 111-2, an S / D structure 110 may be formed on the second dielectric layer 111-2. Fig.17 As shown. In some embodiments, the S / D structure 110 may be epitaxially grown on the second dielectric layer 111-2 as described above in operation 430. In some embodiments, after forming the S / D structure 110, the ESL 116 and the ILD layer 118 may be deposited, the protection layer 120 may be formed, and the gate structure 112 may be formed, which are described in detail above. After forming the gate structure 112, a CMP process may planarize the top surfaces of the gate structure 112, the spacer dielectric structure 115, and the protection layer 120, as described above. Figure 3A and Figure 3B In some embodiments, the first dielectric layer 111 - 1 and the second dielectric layer 111 - 2 can reduce the parasitic capacitance of the semiconductor device 100 and further improve the device performance.

[0060] Various embodiments in the present disclosure provide example methods for forming an S / D dielectric structure 111 in a semiconductor device 100. In some embodiments, a nanostructure 122 stacked on a fin structure 108 may be formed on a substrate 104. An S / D dielectric structure 111 may be formed on the fin structure 108 and adjacent to the nanostructure 122. An S / D structure 110 may be formed on a top surface of the S / D dielectric structure 111. The S / D structure 110 may be in contact with the nanostructure 122. In some embodiments, the S / D dielectric structure 111 may extend into the fin structure 108, and a top surface of the S / D dielectric structure 111 may be below a bottom surface of the nanostructure 122. In some embodiments, an STI region 106 may be formed on the substrate 104 between the nanostructures 122. The S / D dielectric structure 111 may be formed on the STI region 106. In some embodiments, the gate structure 112 may be formed to wrap around the nanostructure 122, a gate spacer 114 may be formed on a sidewall of the gate structure 112, and a spacer dielectric structure 115 may be formed on the gate spacer 114. In some embodiments, the S / D dielectric structure 111 and the spacer dielectric structure 115 may include the same dielectric material. In some embodiments, the S / D dielectric structure 111 may include a first S / D dielectric layer 111-1 having a first dielectric material and a second S / D dielectric layer 111-2 having a second dielectric material, the second dielectric material being different from the first dielectric material. In some embodiments, the S / D dielectric structure 111 on the fin structure 108 may reduce leakage current and improve device performance. The S / D dielectric structure 111 on the STI region 106 may reduce STI oxide drossing, reduce gate collapse defects, and improve process yield.

[0061] In some embodiments, the semiconductor structure includes: a channel structure on a substrate; a gate structure surrounding the channel structure; an internal spacer adjacent to the gate structure and ends of the channel structure; a dielectric structure on the substrate and adjacent to the channel structure; and an epitaxial structure on a top surface of the dielectric structure. The dielectric structure contacts the internal spacer. The epitaxial structure contacts the channel structure.

[0062] In some embodiments, a semiconductor device includes: a first channel structure and a second channel structure on a fin structure; a dielectric structure on the fin structure and between the first channel structure and the second channel structure; and a source / drain (S / D) structure on a top surface of the dielectric structure. The dielectric structure extends into the fin structure. The S / D structure contacts the first channel structure and the second channel structure, and the dielectric structure is below the first channel structure and the second channel structure.

[0063] In some embodiments, a method includes: forming a channel structure stacked on a fin structure on a substrate; forming a gate structure on the channel structure; forming a recess adjacent to the channel structure and the gate structure in the fin structure; depositing a dielectric material in the recess to form a dielectric structure on the fin structure; and growing an epitaxial structure on a top surface of the dielectric structure. The epitaxial structure contacts the channel structure.

[0064] It should be understood that the detailed description section (rather than the abstract section of the present disclosure) is intended to be used to interpret the claims. The abstract section of the present disclosure may set forth one or more embodiments, rather than all possible embodiments of the present disclosure contemplated by the inventor(s), and is therefore not intended to limit the appended claims in any way.

[0065] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0066] Example 1 is a semiconductor structure comprising: a channel structure on a substrate; a gate structure surrounding the channel structure; an internal spacer adjacent to the gate structure and ends of the channel structure; a dielectric structure on the substrate and adjacent to the channel structure, wherein the dielectric structure is in contact with the internal spacer; and an epitaxial structure on a top surface of the dielectric structure, wherein the epitaxial structure is in contact with the channel structure.

[0067] Example 2 is the semiconductor structure of Example 1, wherein a top surface of the dielectric structure is below a bottom surface of the channel structure.

[0068] Example 3 is the semiconductor structure of Example 1, wherein the thickness of the dielectric structure is in a range from about 3 nm to about 7 nm.

[0069] Example 4 is the semiconductor structure described in Example 1, further comprising: a gate spacer on the sidewall of the gate structure; and an additional dielectric structure on the sidewall of the gate structure and above the gate spacer, wherein the dielectric structure and the additional dielectric structure comprise the same dielectric material.

[0070] Example 5 is the semiconductor structure of Example 4, wherein the dielectric structure and the additional dielectric structure include the same dielectric material.

[0071] Example 6 is the semiconductor structure described in Example 4, further comprising: an interlayer dielectric (ILD) layer on the epitaxial structure and a protective layer on the ILD layer, wherein top surfaces of the protective layer and the additional dielectric structure are coplanar.

[0072] Example 7 is the semiconductor structure of Example 4, wherein top surfaces of the gate structure and the additional dielectric structure are coplanar.

[0073] Example 8 is the semiconductor structure of Example 1, wherein the dielectric structure comprises aluminum oxide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxycarbonitride, or a low-k dielectric material.

[0074] Example 9 is the semiconductor structure of Example 1, wherein the dielectric structure includes a first dielectric layer having a first dielectric material and a second dielectric layer having a second dielectric material, the second dielectric material being different from the first dielectric material.

[0075] Example 10 is a semiconductor device comprising: a first channel structure and a second channel structure stacked on a fin structure; a dielectric structure on the fin structure and between the first channel structure and the second channel structure, wherein the dielectric structure extends into the fin structure and the dielectric structure is below the first channel structure and the second channel structure; and a source / drain (S / D) structure on a top surface of the dielectric structure, wherein the S / D structure is in contact with the first channel structure and the second channel structure.

[0076] Example 11 is the semiconductor device of Example 10, wherein a top surface of the dielectric structure is below bottom surfaces of the first channel structure and the second channel structure.

[0077] Example 12 is the semiconductor device of Example 10, wherein the thickness of the dielectric structure is in a range from about 3 nm to about 7 nm.

[0078] Example 13 is the semiconductor device described in Example 10, further comprising: a gate structure surrounding the first channel structure; a gate spacer on a sidewall of the gate structure; and an additional dielectric structure on the sidewall of the gate structure and above the gate spacer.

[0079] Example 14 is the semiconductor device of Example 13, wherein the dielectric structure and the additional dielectric structure include the same dielectric material.

[0080] Example 15 is the semiconductor device of Example 13, further comprising: an interlayer dielectric (ILD) layer on the epitaxial structure and a protection layer on the ILD layer, wherein top surfaces of the protection layer and the additional dielectric structure are coplanar.

[0081] Example 16 is the semiconductor device of Example 10, wherein the dielectric structure includes a first dielectric layer having a first dielectric material and a second dielectric layer having a second dielectric material, the second dielectric material being different from the first dielectric material.

[0082] Example 17 is a method for forming a semiconductor structure, comprising: forming a channel structure stacked on a fin structure on a substrate; forming a gate structure on the channel structure; forming a recess adjacent to the channel structure and the gate structure in the fin structure; depositing a dielectric material in the recess to form a dielectric structure on the fin structure; and growing an epitaxial structure on a top surface of the dielectric structure, wherein the epitaxial structure is in contact with the channel structure.

[0083] Example 18 is the method of Example 17, wherein depositing the dielectric material comprises: directionally depositing the dielectric material on the gate structure and the fin structure.

[0084] Example 19 is the method described in Example 17, further comprising: forming a gate spacer on the sidewall of the gate structure; depositing the dielectric material on the gate spacer; and removing a portion of the dielectric material to form an additional dielectric structure on the gate spacer.

[0085] Example 20 is the method described in Example 19, further comprising: forming an interlayer dielectric (ILD) layer on the epitaxial structure; forming a protective layer on the ILD layer; and planarizing top surfaces of the protective layer, the additional dielectric structure, and the gate structure.

Claims

1. A semiconductor structure comprising: Channel structure, on substrate; A gate structure surrounding the channel structure; an internal spacer adjacent to ends of the gate structure and the channel structure; a dielectric structure on the substrate and adjacent to the channel structure, wherein the dielectric structure contacts the inner spacer; and An epitaxial structure is on a top surface of the dielectric structure, wherein the epitaxial structure is in contact with the channel structure.

2. The semiconductor structure according to claim 1, wherein: A top surface of the dielectric structure is below a bottom surface of the trench structure.

3. The semiconductor structure according to claim 1, wherein: The thickness of the dielectric structure is in the range of 3 nm to 7 nm.

4. The semiconductor structure according to claim 1, further comprising: a gate spacer on a sidewall of the gate structure; as well as An additional dielectric structure is on the sidewalls of the gate structure and above the gate spacers, wherein the dielectric structure and the additional dielectric structure include the same dielectric material.

5. The semiconductor structure according to claim 4, wherein: The dielectric structure and the additional dielectric structure include the same dielectric material.

6. The semiconductor structure according to claim 4, further comprising: An interlayer dielectric ILD layer is formed on the epitaxial structure and a protection layer is formed on the ILD layer, wherein top surfaces of the protection layer and the additional dielectric structure are coplanar.

7. The semiconductor structure according to claim 4, wherein: Top surfaces of the gate structure and the additional dielectric structure are coplanar.

8. The semiconductor structure according to claim 1, wherein: The dielectric structure includes aluminum oxide, silicon carbide, silicon carbonitride, silicon nitride, silicon oxycarbonitride, or a low-k dielectric material.

9. A semiconductor device comprising: A first channel structure and a second channel structure are stacked on the fin structure; a dielectric structure on the fin structure and between the first channel structure and the second channel structure, wherein the dielectric structure extends into the fin structure and the dielectric structure is below the first channel structure and the second channel structure; and A source / drain S / D structure is on a top surface of the dielectric structure, wherein the S / D structure is in contact with the first channel structure and the second channel structure.

10. A method of forming a semiconductor structure, comprising: forming a channel structure stacked on the fin structure on the substrate; forming a gate structure on the channel structure; forming a recess in the fin structure adjacent to the channel structure and the gate structure; depositing a dielectric material in the recess to form a dielectric structure on the fin structure; as well as An epitaxial structure is grown on a top surface of the dielectric structure, wherein the epitaxial structure is in contact with the channel structure.

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