Semiconductor device having self-aligned gate and field

Abstract

The invention relates to a semiconductor device with a self-aligned gate and a field plate and a manufacturing method thereof. An embodiment of a semiconductor device includes a semiconductor substrate and one or more lower dielectric layers on a surface of the substrate. Source, drain, gate and field plate openings formed in a self-aligned manner extend through the lower dielectric layer to the substrate. A conformal dielectric layer is disposed over the lower dielectric layer and into the gate and field plate openings. The conformal dielectric layer includes a first portion on a sidewall of the gate opening, a second portion on a sidewall of the field plate opening, and a third portion on the substrate at a bottom range region of the field plate opening. A gate spacer is formed on the first portion of the conformal dielectric layer. A gate electrode in the gate opening contacts the gate spacer and the semiconductor substrate. A field plate in the field plate opening contacts the second and third portions of the conformal dielectric layer.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to semiconductor devices and methods for fabricating such devices. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic components and systems. For example, high power, high frequency transistors are used in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly suitable for these RF power applications and power electronics applications due to its excellent electronic and thermal properties. Specifically, the high electron velocity and high breakdown field strength of GaN make devices made from this material ideal for RF power amplifiers and high power switching applications.

[0003] A GaN heterojunction field effect transistor (HFET) includes ohmic source and drain electrodes at opposite ends of a channel, with a gate electrode positioned over the channel between the source and drain electrodes. Additionally, some GaN HFETs include a source-connected field plate to enhance transistor performance and reliability.

[0004] Characteristics of GaN HFETs that affect performance include gate resistance and gate-drain capacitance. Generally, for any given GaN HFET design, it is desirable that the gate resistance and gate-drain capacitance be as low as possible in order to achieve relatively high gain and good linearity.

[0005] One way to reduce gate-drain capacitance is to reduce the space (distance) between the field plate and the GaN surface by reducing the dielectric layer separating the gate and the field plate. However, using conventional manufacturing methods, there is a limit to how small such a spacing can be without having an electrical short between the gate metal and the field plate. Therefore, there is a need for semiconductor devices (e.g., GaN HFETs) with smaller gate-to-field plate spacings and methods of manufacturing the same. Summary of the invention

[0006] According to a first aspect of the present invention, there is provided a semiconductor device, comprising:

[0007] a semiconductor substrate comprising an upper surface and a channel;

[0008] one or more lower dielectric layers disposed on the upper surface of the semiconductor substrate, wherein a source opening, a drain opening, a gate opening, and a field plate opening extend through the one or more lower dielectric layers to the semiconductor substrate, wherein the gate opening is between the source opening and the drain opening, and the field plate opening is between the gate opening and the drain opening;

[0009] a conformal dielectric layer disposed over the one or more lower dielectric layers and into at least the gate opening and the field plate opening, wherein the conformal dielectric layer includes a first portion formed on a sidewall of the gate opening, a second portion formed on a sidewall of the field plate opening, and a third portion formed on the semiconductor substrate at a bottom extent region of the field plate opening;

[0010] a gate spacer disposed on the first portion of the conformal dielectric layer;

[0011] a gate electrode disposed in the gate opening, contacting the gate spacer and the semiconductor substrate; and

[0012] A field plate is disposed in the field plate opening in contact with the second and third portions of the conformal dielectric layer.

[0013] In one or more embodiments, the conformal dielectric layer further includes a fourth portion formed on the semiconductor substrate at a bottom range region of the gate opening, wherein the gate electrode extends through the opening in the fourth portion to contact the semiconductor substrate, and wherein the gate spacer is formed on both the first and fourth portions of the conformal dielectric layer.

[0014] In one or more embodiments, the conformal dielectric layer is formed of a dielectric material selected from aluminum oxide and aluminum nitride.

[0015] In one or more embodiments, the conformal dielectric layer has a thickness in a range of 50 angstroms to 200 angstroms.

[0016] In one or more embodiments, the gate spacer is formed of silicon nitride.

[0017] In one or more embodiments, the gate electrode has a T-shaped cross-section having a stem portion extending through the one or more lower dielectric layers to contact the semiconductor substrate, and first and second protrusion regions extending above the gate spacer and the one or more lower dielectric layers.

[0018] In one or more embodiments, the field plate is recessed below an upper surface of the one or more lower dielectric layers.

[0019] In one or more embodiments, the conformal dielectric layer further includes a fifth portion formed on a sidewall of the source opening, and a sixth portion formed on a sidewall of the drain opening.

[0020] In one or more embodiments, the conformal dielectric layer further includes a seventh portion formed above the upper surface of the one or more lower dielectric layers, wherein the seventh portion extends from one of the fifth portions formed on the sidewalls of the source opening toward one of the first portions formed on the sidewalls of the gate opening; and

[0021] The conformal dielectric layer further includes an eighth portion formed above the upper surface of the one or more lower dielectric layers, wherein the eighth portion extends from one of the sixth portions formed on the sidewalls of the drain opening toward one of the second portions formed on the sidewalls of the field plate opening.

[0022] In one or more embodiments, the semiconductor device further comprises:

[0023] a source electrode disposed in the source opening;

[0024] one or more upper dielectric layers disposed over the one or more lower dielectric layers and over the gate electrode; and

[0025] A conductive connection extends over the one or more upper dielectric layers and over the gate electrode to electrically connect the field plate to the source electrode.

[0026] In one or more embodiments, the field plate and the conductive connection are formed from the same metal layer.

[0027] According to a second aspect of the present invention, there is provided a method for forming a semiconductor device, the method comprising:

[0028] forming one or more lower dielectric layers over an upper surface of the semiconductor substrate including the channel;

[0029] using a patterned photoresist mask to simultaneously form a plurality of openings through the one or more lower dielectric layers, wherein the plurality of openings include gate openings and field plate openings;

[0030] depositing a conformal dielectric layer into the plurality of openings, wherein the conformal dielectric layer includes a first portion formed on sidewalls of the gate openings, a second portion formed on sidewalls of the field plate openings, and a third portion formed on the semiconductor substrate at a bottom extent of the field plate openings;

[0031] forming a gate spacer on the first portion of the conformal dielectric layer in the gate opening;

[0032] forming a gate electrode in the gate opening in contact with the dielectric gate spacer; and

[0033] A field plate is formed in the field plate opening in contact with the second and third portions of the conformal dielectric layer.

[0034] In one or more embodiments, the conformal dielectric layer further includes a fourth portion formed on the semiconductor substrate at a bottom extent of the gate opening, wherein the gate electrode extends through the opening in the fourth portion to contact the semiconductor substrate; and

[0035] Forming the gate spacers includes forming the dielectric gate spacers on the first and fourth portions of the conformal dielectric layer.

[0036] In one or more embodiments, depositing the conformal dielectric layer includes performing atomic layer deposition to deposit the conformal dielectric layer on horizontal and vertical surfaces of the one or more underlying dielectric layers.

[0037] In one or more embodiments, the thickness of the conformal dielectric layer is in the range of 50 angstroms to 200 angstroms; and

[0038] The conformal dielectric layer is formed of a dielectric material selected from aluminum oxide and aluminum nitride.

[0039] In one or more embodiments, the gate spacer is formed of silicon nitride.

[0040] In one or more embodiments, forming the multiple openings also includes using the one patterned photoresist mask to form a source opening and a drain opening through the one or more lower dielectric layers while forming the gate opening and the field plate opening, wherein the gate opening is between the source opening and the drain opening, and the field plate opening is between the gate opening and the drain opening.

[0041] In one or more embodiments, the method further comprises:

[0042] removing portions of the conformal dielectric layer at bottom extents of the source opening and the drain opening; and

[0043] After removing portions of the conformal dielectric layer at the bottom extents of the source opening and the drain opening, a source electrode is formed in the source opening, and a drain electrode is formed in the drain opening.

[0044] In one or more embodiments, the method further comprises:

[0045] forming a source electrode in the source opening;

[0046] forming one or more upper dielectric layers over the one or more lower dielectric layers; and

[0047] A conductive connection is formed extending over the one or more upper dielectric layers and over the gate electrode to electrically connect the field plate to the source electrode.

[0048] In one or more embodiments, forming the field plate and forming the conductive connection are performed simultaneously by depositing a conductive layer.

[0049] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] A more complete understanding of the subject matter may be derived by referring to the detailed description and claims considered in conjunction with the following drawings, wherein like reference numerals refer to like elements throughout the various figures.

[0051] Figure 1 is a cross-sectional side view of an exemplary transistor according to an embodiment;

[0052] Figure 2 According to an embodiment, a Figure 1 A process flow chart of a method for producing a transistor;

[0053] Figure 3 , 4 5 and 5 are diagrams showing various manufacturing stages according to one or more embodiments. Figure 1 a cross-sectional side view of a partially formed version of a transistor;

[0054] Fig. 6A , 6B , 6C and 6D are diagrams showing various subsequent manufacturing stages according to one or more embodiments. Figure 1 a cross-sectional side view of a partially formed version of a transistor;

[0055] Fig. 7A , 7B , 7C and 7D are diagrams showing Figures 6A-6D An alternative embodiment of the manufacturing stages shown in Figure 1 a cross-sectional side view of a partially formed version of a transistor; and

[0056] Figure 8 , 9 , 10, 11, 12 and 13 are diagrams showing various subsequent manufacturing stages according to one or more embodiments. Figure 1 A cross-sectional side view of a partially formed version of a transistor. DETAILED DESCRIPTION

[0057] Embodiments of the subject matter of the invention described herein include semiconductor devices and methods for manufacturing the same. More specifically, embodiments of semiconductor devices (e.g., transistor devices) are described herein, the semiconductor devices comprising a semiconductor substrate having an upper surface and a channel, and one or more lower dielectric layers disposed on the upper surface of the semiconductor substrate. The source opening, drain opening, gate opening, and field plate opening formed simultaneously extend through the lower dielectric layer to the semiconductor substrate. According to one or more embodiments, a single patterned photoresist mask is used to form the source opening, drain opening, gate opening, and field plate opening. A conformal dielectric layer is disposed above the lower dielectric layer and at least into the gate opening and the field plate opening. The conformal dielectric layer includes a first portion formed on the sidewall of the gate opening, a second portion formed on the sidewall of the field plate opening, and a third portion formed on the semiconductor substrate at the bottom range of the field plate opening. A gate spacer is disposed on the first portion of the conformal dielectric layer. A gate electrode is disposed in the gate opening, in contact with the gate spacer and the semiconductor substrate. A field plate is disposed in the field plate opening in contact with the second and third portions of the conformal dielectric layer.

[0058] The semiconductor device described below (eg, Figure 1 Various embodiments and methods of manufacturing the device 100 may therefore have several advantages over conventional devices and methods of manufacturing. For example, as will be described in detail below, a photolithography process (e.g., Figure 4 The manufacturing stage 400 is used to define a source opening, a drain opening, a gate opening, and a field plate opening through the passivation layer (eg, Figure 4 440, 445, 450, 460 through layer 130). Thus, the source contact, drain contact, gate, and field plate (e.g., Figure 1 Elements 140, 145, 150, 160) can all be formed in a self-aligned manner. Essentially, a single photolithography process eliminates distance variations that would otherwise occur due to light misalignment using conventional methods. This also allows for extremely small gate to field plate spacings (e.g., Figure 1 Size 165).

[0059] Additionally, embodiments of the fabrication method include utilizing a thin conformal dielectric layer (e.g., Figure 5 The portion of layer 132) provides gate and field plate openings (eg, Figure 5 These portions of the conformal dielectric layer are used to line the openings 450, 460 during subsequent processing steps (e.g., Fig. 6A annealing the source and drain contacts during processing step 610 of the embodiment of the present invention) to protect the semiconductor surfaces within the gate and field plate openings. In addition, during certain processing steps (e.g., Fig.6D , 7BWhen forming the gate spacer 151), the portions of the conformal dielectric layer within the gate and field plate openings act as an etch stop layer. Figure 1 Once formed, the spacer 151 has an underlying portion of a conformal dielectric layer. This gate spacer configuration enables a gate having a very short gate length (e.g., Figure 1 The development of transistors with a size of 155) that are capable of operating at increasingly higher frequencies.

[0060] Furthermore, various embodiments include semiconductor device configurations wherein a field plate (e.g., Figure 1 The field plate 160 of the embodiment of the present invention is recessed below the surface of the lower dielectric layer (e.g., below the surface of the passivation layer 130) while still being isolated from the surface of the semiconductor substrate by the conformal dielectric layer. This recessed configuration of the field plate produces a lower gate-drain capacitance when compared to a transistor design that does not include a recessed field plate. All of these various features can result in improved high frequency gain and linearity.

[0061] Although the following description is about gallium nitride (GaN) heterojunction field effect transistor (HFET) devices (e.g., Figure 1 Examples of various embodiments are described with reference to the device 100 of FIG. 1 , but it should be noted that the various embodiments may be utilized in other types of transistors, transistors having semiconductor substrates that do not include GaN (i.e., non-GaN-based transistors), and other types of non-transistor semiconductor devices that include features that benefit from reduced gate-to-field plate spacing. Thus, the various embodiments described herein are not limited to GaN HFET devices, but include transistors other than HFET transistors, non-GaN-based transistors, and semiconductor devices other than transistors.

[0062] Figure 1 is a cross-sectional side view of an exemplary GaN HFET device 100 according to one or more embodiments. The GaN HFET device 100 includes a semiconductor substrate 110, one or more isolation regions 120, an active region 125, a first dielectric layer 130, a second dielectric layer 132, a third dielectric layer 136, a source electrode 140 (i.e., a "first current-carrying electrode"), a drain electrode 145 (i.e., a "second current-carrying electrode"), a gate electrode 150 (i.e., a "control electrode"), and a field plate 160. Various additional patterned conductive layers and dielectric layers (not shown) may be formed over the dielectric layer 136 to provide interconnects with bonding pads and other circuit elements.

[0063] Semiconductor substrate 110 may include main substrate 102, buffer layer 104 disposed on or over main substrate 102, channel layer 106 disposed on or over buffer layer 104, barrier layer 108 disposed on or over channel layer 106, and optional capping layer 109 disposed on or over channel layer 106. Channel 107 is generated in the form of two-dimensional electron gas (2-DEG) within channel layer 106 near the interface between channel layer 106 and barrier layer 108.

[0064] In one or more embodiments, the main substrate 102 may include silicon carbide (SiC). In other embodiments, the main substrate 102 may include other materials, such as sapphire, silicon (Si), GaN, aluminum nitride (AlN), diamond, polycrystalline SiC, silicon on insulator, gallium arsenide (GaAs), indium phosphide (InP), and other basic insulating or high resistivity materials. A nucleation layer (not shown) may be formed on the upper surface of the main substrate 102 between the buffer layer 104 and the main substrate 102. In an embodiment, the nucleation layer may include AlN.

[0065] Without departing from the scope of the present subject matter, it should be understood that the selection of materials and the arrangement of layers forming the semiconductor substrate 110 are exemplary. It should be understood that the inclusion of the main substrate 102, the buffer layer 104, the channel layer 106, the barrier layer 108, and the capping layer 109 in the semiconductor substrate 110 is exemplary, and the functions and operations of the various layers can be combined and can vary depending on the materials used in any specific embodiment. For example, in some embodiments, the capping layer 109 can be omitted. In other embodiments using N-polar materials, the channel layer 106 can be disposed on or above the barrier layer 108 to form a 2-DEG and a channel 107 directly below the capping layer 109 and the gate electrode 150. And other embodiments may include a semiconductor layer formed of materials including GaAs, gallium oxide (Ga2O3), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), and aluminum indium arsenide (AlInAs) to form the semiconductor substrate 110.

[0066] According to an embodiment, a high-resistivity region 122 may be formed in the semiconductor substrate 110 to define an isolation region 120 and an active region 125 above and along an upper surface 103 of the main substrate 102 .

[0067] In various embodiments, multiple dielectric layers 130, 132, 136 may be formed on or above active region 125 and isolation region 120. Dielectric layer 130 may be referred to herein as a "passivation layer" or a "lower dielectric layer". In essence, dielectric layer 130 (or passivation layer 130 or lower dielectric layer 130) may be formed from a single dielectric material layer or from multiple dielectric material layers. Dielectric layer 132 may be referred to herein as a "conformal dielectric layer", where "conformal dielectric layer" as used herein means a dielectric layer deposited on or above the vertical, horizontal, and intermediate angled surfaces of the bottom layer (e.g., on the surface of layer 130). A "conformal dielectric layer" may have a considerable thickness on the vertical, horizontal, and intermediate angled surfaces on which it is deposited. Finally, dielectric layer 136 may be referred to herein as an "upper dielectric layer". Similar to layer 130, dielectric layer 136 may be formed from a single dielectric material layer or from multiple dielectric material layers.

[0068] In various embodiments, the source electrode 140 and the drain electrode 145 are formed above and contact the source region 142 and the drain region 147 in the active region 125 of the semiconductor substrate 110. The source electrode 140 and the drain electrode 145 may be formed in source openings and drain openings (e.g., Figure 4 440, 445). More specifically, the source electrode 140 and the drain electrode 145 contact the semiconductor substrate 110 through the bottom of the source opening and the drain opening mentioned above. For example, in one or more embodiments, the bottom range of the source electrode 140 and the drain electrode 145 may be formed above the capping layer 109 and contact the capping layer 109. In other embodiments (not shown), one or both of the source electrode 140 and the drain electrode 145 may be recessed through the capping layer 109 and partially extend through the barrier layer 108, or one or both of the source electrode 140 and the drain electrode 145 may be completely recessed through the barrier layer 108 and contact the channel layer 104.

[0069] The source electrode 140 and the drain electrode 145 may be formed from portions of a first conductive layer, which may include one or more sub-layers of conductive material. When annealed, the first (lowermost) conductive layer enables ohmic contacts to be formed between the channel 107 and the source region 142 and the drain region 147 described below. Thus, alternatively, the first conductive layer may be referred to as an "ohmic layer" or "ohmic stack."

[0070] The source region 142 and the drain region 147 correspond to portions of the semiconductor substrate 110 that are respectively located below the source electrode 140 and the drain electrode 145. In some embodiments, the source region 142 and the drain region 147 may be non-intentionally doped (NID) regions of the semiconductor substrate 110. In other embodiments, ion implantation or diffusion processes may be used to produce intentionally doped source region 142 and drain region 147.

[0071] In an embodiment, gate electrode 150 is formed on or over semiconductor substrate 110 in active region 125 and between source electrode 140 and drain electrode 145. According to one or more embodiments, gate electrode 150 may have a T-shaped cross section, such as Figure 1 In such embodiments, the gate electrode 150 includes a gate opening (eg, Figure 4 The conductive "rod" (eg, Fig.10 The gate electrode 150 further includes a first and a second conductive protrusion region (eg, Fig. 9 Regions 955, 956), the first and second conductive protrusion regions extending over a portion of the lower dielectric layer 130.

[0072] According to one or more embodiments, a portion of the conformal dielectric layer 132 is located at the gate opening (eg, Figure 4 The gate electrode 150 is formed on portions of the sidewalls and bottom extents of the gate opening 450, and the dielectric gate spacer 151 is formed on those portions of the dielectric layer 134. Therefore, the stem portion of the gate electrode 150 is spaced apart from the sidewalls of the dielectric layer 130 exposed by the gate opening by the dielectric gate spacer 151 and the portions of the dielectric layer 134 on those sidewalls of the layer 130. In addition, the protruding region of the gate electrode 150 extends from the stem portion above the dielectric gate spacer 151 to contact the upper surface of the dielectric layer 130.

[0073] The configuration of the gate electrode 150 within the gate opening, the dielectric gate spacer 151, and over portions of the dielectric layers 132 and 130 enables the device 100 to be designed with an extremely short gate length (i.e., dimension 155, corresponding to the cross-sectional dimension of the portion of the gate that contacts the substrate 110), compared to some conventional devices that lack these features. For example, embodiments of the present subject matter can be used to produce devices having a gate length of less than 0.5 microns, or even less than 0.25 microns.

[0074] Many other embodiments of the gate structure may be implemented without departing from the scope of the inventive subject matter. Figure 1The exemplary embodiment of FIG. 1 depicts the gate electrode 150 as having a symmetrical T-shaped cross-section (ie, having a vertical stem and symmetrical first and second protruding regions). In other embodiments, the gate electrode 150 may have an asymmetrical T-shaped cross-section.

[0075] The gate electrode 150 is electrically coupled to the channel 107 through the capping layer 109 (if included) and the barrier layer 108. In other embodiments (not shown), the gate electrode 150 may be recessed through the capping layer 109 and partially extend into the barrier layer 108, thereby enhancing the electrical coupling of the gate electrode 150 to the channel 107. In other embodiments (not shown), the capping layer 109 may be omitted, and the gate electrode 150 may directly contact the barrier layer 108. In other embodiments (not shown), the gate electrode 150 may be disposed over a gate dielectric layer formed between the gate electrode 150 and the semiconductor substrate 110 to form a metal-insulator-semiconductor field effect transistor (MISFET) device. In either case, the change in potential applied to the gate electrode 150 can shift the quasi-Fermi level of the barrier layer 108 relative to the quasi-Fermi level of the channel layer 106 , thereby adjusting the electron concentration in the channel 107 within the semiconductor substrate 110 below the gate electrode 150 .

[0076] The conductive field plate 160 is located in a field plate opening (eg, Figure 4 The field plate 160 is positioned adjacent to the gate electrode 150 and between the gate electrode 150 and the drain electrode 145.

[0077] According to one or more embodiments, the sidewalls and bottom extents of the field plate opening are lined with portions of the conformal dielectric layer 132, and the field plate 160 is formed from a conductive layer (e.g., Fig.12 The conductive field plate 160 is formed on a portion of the layer 1210 of the lower dielectric layer 130. Therefore, the conductive field plate 160 is separated from the upper surface 109 of the semiconductor substrate 110. In addition, the bottom area of ​​the field plate 160 is recessed into the upper surface of the lower dielectric layer 130 (ie, positioned below the upper surface).

[0078] Field plate 160 is electrically coupled to source electrode 140 via field plate to source connection 180. During operation of device 100, field plate 160 may serve to increase capacitive coupling with channel 107, reduce electric fields at gate-drain edges, and reduce associated gate-drain capacitance between gate electrode 150 and drain electrode 145.

[0079] The relative arrangement of the gate electrode 150 and the field plate 160 can be characterized by a gate to field plate spacing (eg, dimension 165). As will be described in detail later, the openings for the lower gate electrode 150 and the field plate 160 (eg, Figure 4 The openings 450, 460) are formed using a single patterned photoresist mask (e.g., Figure 4 The two features 150, 160 are "self-aligned" and can achieve a reduction in the spacing 165 (distance) between the gate electrode 150 and the field plate 160 (i.e., the field plate to gate spacing) compared to the spacing that can be achieved using conventional gate and field plate structures and methods of forming the same. In some embodiments, the gate to field plate spacing 165 can be between about 0.2 microns and about 0.5 microns, but the gate to field plate distance can also be shorter or longer.

[0080] The first metal-insulator-semiconductor region 167 can be generated by the field plate 160, the portion of the underlying dielectric layer 132, and the semiconductor substrate 110. In an embodiment, the first metal-insulator-semiconductor region 167 can function as part of an active device. The first metal-insulator-semiconductor region 167 has a first threshold voltage that depends on the characteristics of the lower dielectric layer 132 and the amount of charge in the channel 107. In an embodiment, the first threshold voltage can be between about -5 volts and about -15 volts. In other embodiments, the first threshold voltage can be between about -4 volts and about -50 volts.

[0081] Upper dielectric layer 136 is disposed on or over lower dielectric layer 130 and conformal dielectric layer 132, source and drain electrodes 140 and 145, gate electrode 150, and field plate 160. Source metallization 185, drain metallization 186, and field plate to source connection 180 mentioned above are formed by conductive layers (e.g., Fig.12 A layer 1210 of the upper dielectric layer 136 is formed on or above the upper dielectric layer 136. According to an embodiment, this conductive layer extends to the source, drain and field plate openings (e.g., Fig.11 , 12 The openings 1140 , 1145 , 1160 of the transistor are formed to contact the source electrode 140 and the drain electrode 145 and to form the field plate 160 and the field plate to source connection 180 .

[0082] In some embodiments, the field plate to source connection 180 includes conductive straps 188, which are relatively narrow conductors spaced along the transistor fingers that extend periodically over the gate electrode 150 to electrically connect the field plate 160 to the source electrode 140. In other embodiments, another metal layer (e.g., an interconnect layer) may be used to achieve the connection between the field plate 160 and the source electrode 140. In still other embodiments, the field plate to source connection 180 may include a solid continuous conductive structure between the field plate 160 and the source electrode 140, rather than including conductive straps 188.

[0083] In an embodiment, the GaN HFET device 100 can be configured as a transistor finger, wherein the source electrode 140, the drain electrode 145, the gate electrode 150, and the field plate 160 can be configured as elongated parallel elements. For example, in such a transistor finger, the length of the gate electrode 150 (i.e., dimension 155) is significantly smaller than the "width" (i.e., the dimension perpendicular to the gate length) of the gate electrode. In some embodiments, the gate length can be between about 0.2 microns and about 2 microns, but the gate length can also be shorter or longer. In some embodiments, the gate width can be between about 4 microns and about 1000 microns, or longer.

[0084] Reference Figure 2 , Figure 2 Flowchart 200 depicts a method for manufacturing a semiconductor device (e.g., Figure 1 An embodiment of a method of manufacturing a GaN HFET device 100). Figure 2 It should be noted that the method for generating Figure 1 A cross-sectional side view of a semiconductor device 100 at a series of fabrication stages Figure 3-13 Check it out together.

[0085] exist Figure 2 In block 202, and as Figure 3 1 , the method may begin by forming or providing a semiconductor substrate 110. In an embodiment, stage 300 may include providing a main substrate 102, and forming a number of semiconductor layers 104, 106, 108, and 109 (described in detail below) on or over the main substrate 102. The semiconductor layers 104, 106, 108, and 109 may be grown using one of metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a combination of these techniques, but alternatively, other suitable techniques may be used.

[0086] As mentioned above, according to one or more embodiments, the main substrate 102 may include silicon carbide (SiC). In other embodiments, the main substrate 102 may include other materials, such as sapphire, silicon (Si), GaN, aluminum nitride (AlN), diamond, polycrystalline SiC, silicon on insulator, gallium arsenide (GaAs), indium phosphide (InP), and other basic insulating or high resistivity materials.

[0087] A nucleation layer (not shown) may be formed on the upper surface of the main substrate 102 between the buffer layer 104 and the main substrate 102. In an embodiment, the nucleation layer may include AlN.

[0088] Buffer layer 104 may include a plurality of III-N semiconductor layers formed on or above main substrate 102. Each of the semiconductor layers of buffer layer 104 may include an epitaxially grown III-nitride epitaxial layer. For example, the III-nitride epitaxial layer constituting buffer layer 104 may be a nitrogen (N) face or gallium (Ga) face material. For example, buffer layer 104 may include a material composed of Al with an aluminum mole fraction of X. X Ga 1-X N represents at least one AlGaN mixed crystal layer of a composition of , and X can take a value between 0 and 1. The total thickness of the buffer layer 104 and all its layers can be between about 200 angstroms and about 100,000 angstroms, but other thicknesses can also be used. The limiting X value of 0 results in pure GaN, while a value of 1 results in pure aluminum nitride (AlN). Some embodiments may include a buffer layer 104 disposed on or above a host substrate and a nucleation layer (not shown).

[0089] The buffer layer 104 may include additional Al X Ga 1-X N layer. Additional Al X Ga 1-X The thickness of the N layer may be between about 200 angstroms and about 50,000 angstroms, although other thicknesses may be used. X Ga 1-X The N layer can be configured as GaN (X=0), where Al X Ga 1-X N is not intentionally doped (NID). Additional Al X Ga 1-X The N layer may also be configured as one or more GaN layers, wherein the one or more GaN layers are intentionally doped with dopants, which may include iron (Fe), chromium (Cr), carbon (C), or other suitable dopants that make the buffer layer 104 substantially insulating or highly resistive. The dopant concentration may be between about -10 16 cm -3 with 10 19 cm -3but other higher or lower concentrations may be used. Additional Al X Ga 1-X The N layer can be configured to have X = 0.01 to 0.10, where Al X Ga 1-X N is NID, or, where Al X Ga 1-X N is intentionally doped with Fe, Cr, C or other suitable dopant species. In other embodiments (not shown), the additional layers may be configured as a superlattice, where the additional layers include a series of alternating NID layers or doped Al X Ga 1-X N layers, wherein the value of X is between 0 and 1. In other embodiments, the buffer layer 104 may further include a Y Ga 1-Y N, wherein the indium mole fraction Y can take a value between 0 and 1. The thickness of the InGaN layer can be between about 50 angstroms and about 2000 angstroms, although other thicknesses can also be used.

[0090] In other embodiments, the semiconductor layer of the buffer layer 104 may not be grown epitaxially. In other embodiments, the semiconductor layer of the buffer layer 104 may include Si, GaAs, InP or other suitable materials.

[0091] In an embodiment, channel layer 106 may be formed on or over buffer layer 104. Channel layer 106 may include one or more III-N semiconductor layers. Channel layer 106 may include Al X Ga 1-X N layers, where X takes a value between 0 and 1. In an embodiment, the channel layer 106 is configured as GaN (X=0), but other X values ​​may be used without departing from the scope of the present subject matter. The thickness of the channel layer 106 may be between about 50 angstroms and about 10,000 angstroms, but other thicknesses may also be used. The channel layer 106 may be NID, or may include Si, germanium (Ge), C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 10 15 cm -3 With about 10 19 cm -3 In other embodiments, the channel layer 106 may include NID or doped In Y Ga 1-Y N, where the indium mole fraction Y can take a value between 0 and 1.

[0092] In an embodiment, barrier layer 108 may be formed on or above channel layer 106. Barrier layer 108 may include one or more III-N semiconductor layers. In some embodiments, barrier layer 108 has a larger band gap and a larger spontaneous polarization than channel layer 106, and when barrier layer 108 is in direct contact with channel layer 106, channel 107 is generated in the form of a two-dimensional electron gas (2-DEG) within channel layer 106 near the interface between channel layer 106 and barrier layer 108. In addition, strain between barrier layer 108 and channel layer 106 may generate additional piezoelectric charge and cause the formation of 2-DEG and channel 107. Barrier layer 108 may include at least one NID Al X Ga 1-X N layers, where X takes a value between 0 and 1. In some embodiments, X may take a value between 0.1 and 0.35, although other values ​​of X may also be used. The thickness of barrier layer 108 may be between about 50 angstroms and about 1000 angstroms, although other thicknesses may also be used. Barrier layer 108 may be NID, or may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 10 16 cm -3 with 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0093] In embodiments, according to embodiments, an additional AlN interlayer barrier layer (not shown) may be formed between the channel layer 106 and the barrier layer 108. The AlN interlayer barrier layer may increase channel charge and improve electron confinement of the resulting 2-DEG while also increasing charge mobility.

[0094] In other embodiments, the barrier layer 108 may include a Y Al 1-Y N, wherein the indium mole fraction Y may take a value between about 0.1 and about 0.2, although other values ​​of Y may also be used. In the case of an InAlN barrier layer, the thickness of barrier layer 108 may be between about 30 angstroms and about 1000 angstroms, although other thicknesses may also be used. In the case of using InAlN to form barrier layer 108, InAlN may be NID, or may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 10 16 cm -3 With about 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0095] In one or more embodiments, the capping layer 109 may be formed on or above the barrier layer 108. The capping layer 109 may present a stable surface for the semiconductor substrate 110 and may protect the surface of the semiconductor substrate 110 from chemical and environmental exposure due to wafer processing. The capping layer 109 may include one or more III-N semiconductor layers. In an embodiment, the capping layer 109 is GaN. The thickness of the capping layer 109 may be between about 5 angstroms and about 100 angstroms, but other thicknesses may also be used. The capping layer 109 may be NID, or may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be between about 10 16 cm -3 with 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0096] In some embodiments, intentionally doped source and drain regions 142 and 147 may be formed through the upper surface 103 of the semiconductor substrate 110 during or later in stage 300. For example, an implantation mask (not shown) may be formed on the upper surface 103 of the semiconductor substrate 110, and openings may be formed in the mask to expose areas of the upper surface 103 where the source and drain regions 142 and 147 are to be formed. An ion implantation process may then be performed to implant dopant species into the exposed areas, thereby producing doped source and drain regions 142 and 147. In various embodiments, Si, Ge, O, or another suitable n-type dopant may be implanted into the semiconductor substrate 110 through the implantation mask. According to an embodiment, the dopant species may be activated by annealing the semiconductor substrate 110 using an activation annealing process. Alternatively, in other embodiments, the source and drain regions 142 and 147 may be NID regions of the semiconductor substrate 110.

[0097] In some embodiments, high-resistivity regions 122 may be formed through upper surface 103 of semiconductor substrate 110 during stage 300 or later. For example, high-resistivity regions 122 may be formed by dispensing and patterning a photoresist layer on or over upper surface 103 of semiconductor substrate 110 and then defining openings in the photoresist layer in desired locations of high-resistivity regions 122. As used herein, the term "photoresist mask" refers to the patterned photoresist layer. Using ion implantation, dopant species (e.g., one or more of oxygen, nitrogen, boron, arsenic, helium, and / or argon) may be driven into semiconductor substrate 110 to produce high-resistivity regions 122. In embodiments, the energy and dose of the implant may be configured to produce a sufficient amount of damage in the crystal structure of semiconductor substrate 110 such that the semiconductor substrate is substantially high-resistivity or semi-insulating within high-resistivity regions 122. In other embodiments (not shown), forming the high-resistivity region 122 may include first etching some or all semiconductor layers in the semiconductor substrate 110, followed by ion implantation to enhance the resistivity in the remaining semiconductor layers and / or the main substrate 102. The photoresist mask is removed before proceeding to the next manufacturing stage.

[0098] exist Figure 2 In block 204, and also as in Figure 3 As depicted in manufacturing stage 300 of , the method may continue by forming a lower dielectric layer 130 (e.g., a surface passivation layer) on or over upper surface 103 of semiconductor substrate 110. Lower dielectric layer 130 may include one or more dielectric layers, and thus layer 130 may be referred to as "one or more lower dielectric layers." The dielectric layer may be formed using one or more processes selected from the following: low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, physical vapor deposition (PVD), MBE, chemical vapor deposition (CVD) (including plasma enhanced (PE) CVD, MOCVD, catalytic CVD, hot filament (HW) CVD, inductively coupled plasma (ICP) CVD, and electron cyclotron resonance (ECR) CVD), combinations of these techniques, or other suitable dielectric deposition techniques.

[0099] The lower dielectric layer 130 may be formed of one or more suitable dielectric materials, including silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (AlO2 or Al2O3), aluminum nitride (AlN), and hafnium oxide (HfO2), although other substantially insulating materials may also be used. The lower dielectric layer 130 may have a thickness between 200 angstroms and 1000 angstroms. In other embodiments, the lower dielectric layer 130 may have a thickness between 50 angstroms and 10,000 angstroms, although other thicknesses may also be used.

[0100] exist Figure 2In block 206, and as Figure 4 As depicted in manufacturing stage 400 of FIG. 1 , the method may continue to form source openings 440, drain openings 445, gate openings 450, and field plate openings 460 through lower dielectric layer 130. According to one or more embodiments, source openings 440, drain openings 445, gate openings 450, and field plate openings 460 are simultaneously produced using a single patterned photoresist mask. This ensures that the source and drain contacts 140, 145, gate electrodes 150, and field plates 160 to be formed are "self-aligned" with each other, which ensures consistent performance of each device regardless of process variations and enables devices to have shorter gate-to-field plate spacings 165 ( Figure 1 ).

[0101] To form source openings 440, drain openings 445, gate openings 450, and field plate openings 460, a photoresist layer 410 is deposited on or over lower dielectric layer 130, and photoresist layer 410 is patterned to form photoresist openings 460 over source and drain regions 142, 147 and over the final locations of gate electrodes 150 and field plates 160. These openings 460 expose the upper surface of lower dielectric layer 130. Source openings 440, drain openings 445, gate openings 450, and field plate openings 460 through lower dielectric layer 130 may then be produced by etching through lower dielectric layer 130 in the areas exposed by photoresist openings 460 while stopping at upper surface 103 of base substrate 110.

[0102] Etching the lower dielectric layer 130 preferably includes performing an anisotropic etching process, which produces openings 440, 445, 450, 460 defined by substantially vertical sidewalls 441, 446, 451, 461 (of the layer 130) and substantially horizontal bottom extents 442, 447, 452, 462 (exposing the substrate 110). For example, the etching process may include one or more dry etching processes, such as reactive ion etching (RIE), ICP etching, ECR etching, or another suitable dry etching process. According to one or more embodiments, suitable dry etching techniques may use one or more of sulfur hexafluoride (SF6), carbon hexafluoride (C2F6), carbon tetrafluoride (CF4), trifluoromethane (CHF3), or other chemicals. The photoresist mask 410 may be removed after forming the source opening 440, the drain opening 445, the gate opening 450, and the field plate opening 460.

[0103] exist Figure 2 In block 208, and as in Figure 5As depicted in manufacturing stage 500 of FIG. 1 , the method may continue by depositing a conformal dielectric layer 132 on or over the upper surface of dielectric layer 130, sidewalls 441, 446, 451, 461, and bottom extent regions 442, 447, 452, 462 of source openings 440, drain openings 445, gate openings 450, and field plate openings 460 (i.e., the sidewalls of layer 130 within openings 440, 445, 450, 460 and the exposed portions of substrate 110). Conformal dielectric layer 132 is desirably deposited using a deposition technique that produces a very conformal deposited layer (i.e., a layer having substantially the same thickness on vertical, horizontal, and intermediate angled surfaces). As will be described in more detail later, this makes conformal dielectric layer 132 suitable for use during some processes (e.g., during Figure 6B 140 and drain contacts 145 of the substrate 110) and during certain etching processes (e.g., during annealing of the source contacts 140 and drain contacts 145 of the substrate 110). Fig.6D , 7B The conformal dielectric layer 132 may be deposited as an etch stop layer during the manufacturing stages 630, 720 of FIG. 1 . For example, in accordance with one or more embodiments, the conformal dielectric layer 132 may be deposited using atomic layer deposition (ALD) or another suitable conformal deposition technique such as plasma enhanced chemical vapor deposition (PECVD).

[0104] The conformal dielectric layer 132 has a first portion formed on the sidewall 451 of the gate opening 450, a second portion formed on the sidewall 461 of the field plate opening 460, and a third portion formed on the semiconductor substrate 110 at the bottom extent 462 of the field plate opening 460. In addition, the conformal dielectric layer 132 has a fourth portion formed on the semiconductor substrate 110 at the bottom extent 452 of the gate opening 450. In addition, the conformal dielectric layer 132 includes a fifth portion formed on the sidewall 441 of the source opening 440, and a sixth portion formed on the sidewall 446 of the drain opening 445. Further, the conformal dielectric layer 132 also includes a seventh portion formed above the upper surface of the lower dielectric layer 130, the seventh portion extending from one of the fifth portions formed on the sidewall 441 of the source opening 440 to one of the first portions formed on the sidewall 451 of the gate opening 450. Finally, the conformal dielectric layer 132 further includes an eighth portion formed above the upper surface of the lower dielectric layer 130 , which extends from the other of the first portions formed on the sidewalls 451 of the gate opening 450 to one of the second portions formed on the sidewalls 461 of the field plate opening 460 .

[0105] Conformal dielectric layer 132 may be formed of one or more suitable dielectric materials. For example, suitable materials for conformal dielectric layer 132 include one or more materials selected from aluminum oxide (AlO2 or Al2O3) and aluminum nitride (AlN), although other substantially insulating materials may also be used. Conformal dielectric layer 132 is preferably relatively thin. For example, layer 132 may have a thickness between 50 angstroms and 400 angstroms (e.g., about 100 angstroms). In other embodiments, conformal dielectric layer 132 may have a thickness greater than or less than the ranges given above.

[0106] At this point, drain and source contacts 140, 145 are formed within drain and source openings 440, 445, respectively. In addition, gate spacers 151 are formed. Various different process sequences may be used to form drain and source contacts 140, 145 and gate spacers 151. Blocks 210, 212, and 214 (corresponding to Figures 6A-6D The manufacturing stages 600, 610, 620, 630) are used to describe the first process sequence for forming these features 140, 145, 151. Boxes 210', 212' and 214' (corresponding to Fig. 7A , 7B , 7C and 7D) to describe the second process sequence for forming these features 140, 145, 151.

[0107] The first process sequence (blocks 210, 212, and 214) will now be described. According to one or more first embodiments, Figure 2 In block 210, and as in Fig. 6A As depicted in fabrication stage 600 of , a first process sequence includes removing portions of conformal dielectric layer 132 at bottom extents 442 , 447 of source and drain openings 440 , 445 to re-expose the upper surface of semiconductor substrate 110 within those openings 440 , 445 prior to ohmic contact formation.

[0108] To remove portions of conformal dielectric layer 132 at bottom extents 442, 447 of source opening 440 and drain opening 445, photoresist layer 610 is deposited on or over conformal dielectric layer 132, and photoresist layer 610 is patterned to form photoresist openings 620 over source region 142 and drain region 147. As shown in FIG6, vertical sidewalls 621 of photoresist opening 620 may be coplanar with vertical sidewalls of portions of conformal dielectric layer 132 located on sidewalls 441, 446 of source opening 440 and drain opening 445. This arrangement provides protection for those portions of conformal dielectric layer 132 on sidewalls 441, 446 during subsequent etching processes while exposing portions of conformal dielectric layer 132 at bottom extents 442, 447 of source opening 440 and drain opening 445.

[0109] The portions of the conformal dielectric layer 132 at the bottom extents 442, 447 of the source and drain openings 440, 445 may then be removed by etching through the portions of the layer 132 exposed by the photoresist openings 620 while stopping at or slightly below the upper surface 103 of the base substrate 110. A relatively small recess in the upper surface 103 of the base substrate 110 may be acceptable or desirable for the ohmic contacts to be formed.

[0110] Etching the exposed portion of the conformal dielectric layer 132 may include using one or more wet and / or dry etching processes and chemicals. For example, in some embodiments, the etching process may include wet etching using hydrofluoric acid (HF) or buffered oxide etching (BOE). In other embodiments, the etching process may include chlorine plasma etching. Alternatively, other suitable etching processes and chemicals may be used. In essence, the etching process causes complete removal of portions of the conformal dielectric layer 132 at the bottom range regions 442, 447 of the source opening 440 and the drain opening 445, as shown in FIG6. In some embodiments, portions of the conformal dielectric layer 132 on the sidewalls 441, 446 may remain substantially intact, while in other embodiments, some or all of those portions of the conformal dielectric layer 132 may be removed by the etching process. After the etching process is completed, the photoresist layer 610 is removed.

[0111] Next, a first process sequence includes forming drain and source contacts 140, 145 and annealing (block 212), followed by forming gate spacers 151 (block 214). Figure 2 In block 212, and as Figure 6BAs depicted in manufacturing stage 610 of , forming the source contact 140 and the drain contact 145 first includes depositing constituent layers of the ohmic stack on the surface of the conformal dielectric layer 132 and into the source opening 440 and the drain opening 445, and then patterning the ohmic stack to remove all of the ohmic stack except for the portion of the ohmic stack deposited into the source opening 440 and the drain opening 445.

[0112] Alternatively, forming the source contact 140 and the drain contact 145 may be performed using a lift-off process, wherein a photoresist layer (not shown) is applied on the surface of the conformal dielectric layer 132, and the photoresist is patterned to expose the source opening 440 and the drain opening 445. Next, constituent layers of the ohmic stack are deposited over the remaining photoresist mask and into the source opening 440 and the drain opening 445, and then the photoresist mask is removed, thereby removing the portion of the ohmic stack deposited on the photoresist mask.

[0113] In various embodiments, the constituent layers of the ohmic stack may be deposited by sputtering, evaporation, PVD, PECVD, or other suitable deposition techniques. In one or more embodiments, the ohmic stack may contain one or more conductive layers, the conductive layers comprising titanium (Ti), Al, titanium nitride (TiN), gold (Au), molybdenum (Mo), nickel (Ni), Si, Ge, platinum (Pt), tantalum (Ta), and / or other suitable materials. In other embodiments, the conductive layers of the ohmic stack may include titanium tungsten (TiW), titanium aluminum (TiAl), or titanium tungsten nitride (TiWN). In one or more specific embodiments, the ohmic stack may include a stack deposited into the source opening 440 and the drain opening 445, the stack comprising a Ti layer on the surface 103 of the substrate 110, Al on or above the Ti layer, and a TiN layer on or above the Ti layer. For example, the thickness of the Ti layer may be between about 10 angstroms and about 200 angstroms, the thickness of the Al layer may be between about 100 angstroms and about 1500 angstroms, and the thickness of the TiN layer may be between about 200 angstroms and about 2000 angstroms, although other thicknesses may alternatively be used. In other embodiments, other metals may replace the constituent layers of the ohmic stack or otherwise be placed below or on top of the constituent layers (e.g., Mo or Pt may replace TiN, or Ta may be used in addition to, above or below Ti, or in place of Ti).

[0114] After depositing the constituent layers of the ohmic stack, an annealing process may be performed to alloy the ohmic stack, thereby creating ohmic contacts to the source region 142 and the drain region 147 of the semiconductor substrate 110 (i.e., to the 2-DEG of the channel 107). It should be noted here that the conformal dielectric layer 132, which has been deposited on the upper surface 103 of the substrate 110 at the bottom extent of the gate opening 450 and the field plate opening 460, serves to protect the surface of the substrate 110 within the openings 450, 460 during the annealing process. Otherwise, without these protective portions of the conformal dielectric layer 132 within the gate opening 450 and the field plate opening 460, the high temperature of the annealing process may result in contamination of the channel 107. Therefore, the conformal dielectric layer 132 has the beneficial effect of enabling the source contact 140 and the drain contact 145 to be annealed at very high temperatures without contaminating the channel 107 at this stage of manufacturing.

[0115] In an embodiment, the annealing step may be achieved by rapid thermal annealing. For example, the ohmic stack may be alloyed at a temperature between about 400 degrees Celsius and about 700 degrees Celsius for about 15 seconds to about 60 seconds. In other embodiments, the ohmic stack may be annealed between about 300 degrees Celsius and about 900 degrees Celsius for between about 10 seconds and about 600 seconds, although other higher or lower temperatures and / or times may be used.

[0116] To complete the formation of the source contact 140 and the drain contact 145, the annealed ohmic stack is then patterned to form the source electrode 140 and the drain electrode 145. More specifically, a photoresist layer (not shown) may be deposited over the ohmic stack, and the photoresist layer is patterned to form photoresist openings over portions of the ohmic stack outside of the desired locations of the source electrode 140 and the drain electrode 145. In other words, the photoresist layer is patterned to protect portions of the ohmic stack within the source opening 440 and the drain opening 445. The portions of the ohmic stack exposed by the openings in the photoresist layer are then removed by etching through the ohmic stack while stopping at the upper surface of the lower dielectric layer 130. Etching the ohmic stack preferably includes performing a well-controlled dry etching process, such as RIE, ICP etching, ECR etching, or other suitable dry etching process. In alternative embodiments, a suitable wet chemical etching process may be performed. The etching process facilitates the formation of the source electrode 140 and the drain electrode 145 .

[0117] exist Figure 2 In block 214, and as Figure 6C and 6D As depicted in manufacturing stages 620 and 630 of , the method may continue with forming gate spacers 151 (and subsequently removing field plate spacers 161). According to one or more embodiments, as Figure 6C140 and drain contacts 145. As shown in manufacturing stage 620, this includes first blanket depositing dielectric spacer layer 134 (i.e., a dielectric layer suitable for forming spacer 151) on or over conformal dielectric layer 132 and source and drain electrodes 140, 145. Dielectric spacer layer 134 is desirably deposited using a low temperature deposition technique (e.g., about 300 degrees Celsius) that can be performed in the presence of exposed metal (i.e., exposed surfaces of source and drain contacts 140, 145). For example, according to one or more embodiments, dielectric spacer layer 134 can be deposited using PVD, PECVD, or another suitable deposition technique. Other deposition techniques (e.g., LPCVD) that should not be used in the presence of exposed metal should be avoided.

[0118] The dielectric spacer layer 134 may be formed of one or more suitable dielectric materials. The dielectric material selected for the dielectric spacer layer 134 is different from the dielectric material selected for the conformal dielectric layer 132 so that the layer 132 can be etched in a subsequent process (i.e., Fig.6D The dielectric spacer layer 134 may serve as an etch stop layer during the manufacturing stage 630 of the process. For example, suitable materials for the dielectric spacer layer 134 include SiN and / or one or more other suitable materials.

[0119] Reference Fig.6D At manufacturing stage 630, after depositing the dielectric spacer layer 134, an etching process is then performed on the dielectric spacer layer 134 to form the gate spacer 151, and in some embodiments, the field plate spacer 161. According to one or more embodiments, the etching process includes an anisotropic etching process that removes material of the dielectric spacer layer 134 in a substantially vertical direction. The etching process is highly selective to the dielectric material of the conformal dielectric layer 132 (i.e., the process does not significantly remove material of the layer 132), and thus the etching process stops when the dielectric spacer layer 134 has been completely removed from all horizontal surfaces of the conformal dielectric layer 132 while remaining on the vertical surfaces of the conformal dielectric layer 132 within the gate opening 450 and the field plate opening 460. This results in the formation of the gate spacer 151 and the field plate spacer 161. For example, the etching process may include one or more dry etching processes, such as reactive ion etching (RIE), ICP etching, ECR etching, or another suitable dry etching process. According to one or more embodiments, suitable dry etching techniques may use one or more of sulfur hexafluoride (SF6), carbon hexafluoride (C2F6), carbon tetrafluoride (CF4), trifluoromethane (CHF3), or other chemicals. It may be noted here that the inclusion of the gate spacer 151 enables the device design to have a shorter gate length (i.e., Figure 1 Size 155).

[0120] As previously mentioned, a second and different process sequence may be used to form the source and drain contacts 140, 145 and the gate spacers 151. More specifically, blocks 210', 212', and 214' may alternatively be used to form these features 140, 145, 151. The primary difference between the two process sequences is that the first process sequence (corresponding to blocks 210, 212, and 214) may utilize a low temperature material deposition process (e.g., PVD, PECVD) to deposit the dielectric spacer layer 134, whereas the second process sequence described below (corresponding to blocks 210', 212', and 214') may utilize a high temperature material deposition process (e.g., LPCVD).

[0121] Turning now to blocks 210', 212' and 214', and in accordance with one or more second embodiments, the second process sequence includes first forming gate spacers 151 (block 210'), preparing source openings 440 and drain openings 445 for ohmic contact formation (block 212'), and subsequently forming drain and source contacts 140, 145 and annealing (block 214'). Figure 2 In the frame 210', and as Fig. 7A and 7B As depicted in manufacturing stages 700 and 720 of , the method may continue with forming gate spacer 151 (and subsequently removed field plate spacer 161, source spacer 742, and drain spacer 747). According to one or more embodiments, as Fig. 7A 150 and manufacturing stage 700, which includes first blanket depositing dielectric spacer layer 134 (i.e., a dielectric layer suitable for forming spacer 151) on or over conformal dielectric layer 132. Dielectric spacer layer 134 desirably may be deposited using a high temperature deposition technique (e.g., about 700 degrees Celsius to 800 degrees Celsius) because source contact 140 and drain contact 145 have not yet been formed (i.e., there is no exposed metal during this process). For example, according to one or more embodiments, dielectric spacer layer 134 may be deposited using LPCVD or another suitable high temperature deposition technique.

[0122] Likewise, the dielectric spacer layer 134 may be formed of one or more suitable dielectric materials. For example, suitable materials for the dielectric spacer layer 134 include SiN and / or one or more other suitable materials. The dielectric spacer layer 134 may have a thickness between 200 angstroms and 2000 angstroms. In other embodiments, the dielectric spacer layer 134 may have a thickness between 50 angstroms and 10,000 angstroms, although other thicknesses may also be used.

[0123] Reference Figure 7BAt the manufacturing stage 720, after the dielectric spacer layer 134 is deposited, an etching process is then performed on the dielectric spacer layer 134 to form the gate spacer 151. In some embodiments, this also results in the formation of the field plate spacer 161, the source spacer 742, and the drain spacer 747. According to one or more embodiments, the etching process includes an anisotropic etching process that removes material of the dielectric spacer layer 134 in a substantially vertical direction. The etching process stops when the dielectric spacer layer 134 has been completely removed from all horizontal surfaces of the conformal dielectric layer 132 while remaining on the vertical surfaces of the conformal dielectric layer 132 within the source opening 440, the drain opening 445, the gate opening 450, and the field plate opening 460. This results in the formation of the gate spacer 151 and the field plate spacer 161, as well as the source spacer 742 and the drain spacer 747. For example, the etching process may include one or more dry etching processes, such as RIE, ICP etching, ECR etching, or another suitable dry etching process. According to one or more embodiments, suitable dry etching techniques may use one or more of sulfur hexafluoride (SF6), carbon hexafluoride (C2F6), carbon tetrafluoride (CF4), trifluoromethane (CHF3), or other chemicals. Also, it may be noted here that the inclusion of the gate spacer 151 enables a device design with a shorter gate length (i.e., Figure 1 Size 155).

[0124] Reference Figure 7C At fabrication stage 730, source and drain spacers 742 and 747 and portions of conformal dielectric layer 132 within source and drain openings 440 and 445 are removed. To remove these features, a photoresist layer 710 is deposited on or over conformal dielectric layer 132, source and drain spacers 742, 747, gate spacers 151 and field plate spacers 161, and exposed portions of conformal dielectric layer 132 within source and drain openings 440 and 445. Photoresist layer 710 is then patterned to form photoresist openings 735 over source and drain openings 440 and 445, while leaving gate and field plate openings 450 and 460 intact in order to protect gate and field plate spacers 151 and 161 from subsequent etching processes. Figure 7C , the vertical sidewalls of the photoresist openings 735 can be coplanar with the vertical interior sidewalls of the portions of the conformal dielectric layer 132 that are located on the sidewalls of the source openings 440 and the drain openings 445. This arrangement provides protection for those portions of the conformal dielectric layer 132 on those sidewalls while exposing the source and drain spacers 742, 747 and the portions of the conformal dielectric layer 132 within the source and drain openings 440, 440 during a subsequent etching process.

[0125] The source spacer 742 and the drain spacer 747 and the portion of the conformal dielectric layer 132 within the source opening 440 and the drain opening 440 can then be removed using an etching process. Etching these features preferably includes performing an anisotropic etching process, but an isotropic etching process can also be used together with a suitable etchant. For example, the etching process may include one or more dry etching processes, such as RIE, ICP etching, ECR etching, or another suitable dry etching process. According to one or more embodiments, suitable dry etching techniques can use one or more of sulfur hexafluoride (SF6), hexafluoride (C2F6), carbon tetrafluoride (CF4), trifluoromethane (CHF3), or other chemicals. The photoresist mask 710 can be removed after removing the source spacer 742 and the drain spacer 747 and the portion of the conformal dielectric layer 132 within the source opening 440 and the drain opening 440. Alternatively, the photoresist mask 710 may be used during a stripping process that is subsequently performed to form the source and drain contacts 140 and 145 .

[0126] exist Figure 2 In block 214', and as Fig.7D735 in the photoresist mask 710, the method may continue with forming the source contact 140 and the drain contact 145 and annealing. Forming the source contact 140 and the drain contact 145 may be performed using a lift-off process, wherein constituent layers of the ohmic stack are deposited into the openings 735 in the photoresist mask 710, followed by removing the photoresist mask 710, thereby removing the portion of the ohmic stack deposited on the photoresist mask 710. Alternatively, if the photoresist mask 710 was previously removed, forming the source and drain contacts 145 may include depositing constituent layers of the ohmic stack over the surface of the conformal dielectric layer 132 and into the source openings 440 and the drain openings 445, followed by patterning the ohmic stack to remove all but the portion of the ohmic stack deposited into the source openings 440 and the drain openings 445. In various embodiments, the constituent layers of the ohmic stack may be deposited by sputtering, evaporation, PVD, PECVD, or other suitable deposition techniques. In one or more embodiments, the ohmic stack may contain one or more conductive layers, the conductive layers comprising titanium (Ti), Al, titanium nitride (TiN), gold (Au), molybdenum (Mo), nickel (Ni), Si, Ge, platinum (Pt), tantalum (Ta), and / or other suitable materials. In other embodiments, the conductive layers of the ohmic stack may include titanium tungsten (TiW), titanium aluminum (TiAl), or titanium tungsten nitride (TiWN). In one or more specific embodiments, the ohmic stack may include a stack deposited into the source opening 440 and the drain opening 445, the stack comprising a Ti layer on the surface 103 of the substrate 110, Al on or above the Ti layer, and a TiN layer on or above the Ti layer. For example, the thickness of the Ti layer may be between about 10 angstroms and about 200 angstroms, the thickness of the Al layer may be between about 100 angstroms and about 1500 angstroms, and the thickness of the TiN layer may be between about 200 angstroms and about 2000 angstroms, although other thicknesses may alternatively be used. In other embodiments, other metals may replace the constituent layers of the ohmic stack or otherwise be placed below or on top of the constituent layers (e.g., Mo or Pt may replace TiN, or Ta may be used in addition to, above or below Ti, or in place of Ti).

[0127] After depositing the constituent layers of the ohmic stack, an annealing process may be performed to alloy the ohmic stack, thereby creating ohmic contacts to the source region 142 and the drain region 147 of the semiconductor substrate 110 (i.e., to the 2-DEG of the channel 107). It should be noted here that the conformal dielectric layer 132, which has been deposited on the upper surface 103 of the substrate 110 at the bottom extent of the gate opening 450 and the field plate opening 460, serves to protect the surface of the substrate 110 within the openings 450, 460 during the annealing process. Otherwise, without these protective portions of the conformal dielectric layer 132 within the gate opening 450 and the field plate opening 460, the high temperature of the annealing process may result in contamination of the channel 107. Likewise, the conformal dielectric layer 132 has the beneficial effect of enabling the source contact 140 and the drain contact 145 to be annealed at very high temperatures without contaminating the channel 107 at this stage of manufacturing.

[0128] In an embodiment, the annealing step may be achieved by rapid thermal annealing. For example, the ohmic stack may be alloyed at a temperature between about 400 degrees Celsius and about 700 degrees Celsius for about 15 seconds to about 60 seconds. In other embodiments, the ohmic stack may be annealed between about 300 degrees Celsius and about 900 degrees Celsius for between about 10 seconds and about 600 seconds, although other higher or lower temperatures and / or times may be used.

[0129] To complete the formation of the source contact 140 and the drain contact 145, the annealed ohmic stack is then patterned to form the source electrode 140 and the drain electrode 145. More specifically, a photoresist layer (not shown) may be deposited over the ohmic stack, and the photoresist layer is patterned to form photoresist openings over portions of the ohmic stack outside of the desired locations of the source electrode 140 and the drain electrode 145. In other words, the photoresist layer is patterned to protect portions of the ohmic stack within the source opening 440 and the drain opening 445. The portions of the ohmic stack exposed by the openings in the photoresist layer are then removed by etching through the ohmic stack while stopping at the upper surface of the lower dielectric layer 130. Etching the ohmic stack preferably includes performing a well-controlled dry etching process, such as RIE, ICP etching, ECR etching, or other suitable dry etching process. In alternative embodiments, a suitable wet chemical etching process may be performed. The etching process facilitates the formation of the source electrode 140 and the drain electrode 145 .

[0130] Regardless of whether the first process sequence is used ( Figures 6A-6D ) or the second process sequence ( Figures 7A-7D ) to form drain and source contacts 140, 145 and gate spacers 151, the method Figure 2 Continue in block 216 of Figure 8As depicted in manufacturing stage 800 of , a portion of conformal dielectric layer 132 between gate spacers 151 at bottom extent region 452 of gate opening 450 is removed to re-expose the upper surface of semiconductor substrate 110 within the opening 450 prior to forming gate 150. To remove the portion of conformal dielectric layer 132 at bottom extent region 452 of gate opening 450, a photoresist layer 810 is deposited on or over conformal dielectric layer 132, and the photoresist layer 810 is patterned to form a photoresist opening 820 over gate opening 450. According to one or more embodiments, opening 820 in photoresist layer 810 extends a short distance over passivation layer 130 on either side of gate opening 450.

[0131] The portion of the conformal dielectric layer 132 at the bottom extent region 452 of the gate opening 450 may then be removed by etching through the portion of the layer 132 exposed by the photoresist opening 820 while stopping at or slightly below the upper surface 103 of the base substrate 110. Etching the exposed portion of the conformal dielectric layer 132 may include using one or more wet and / or dry etching processes and chemistries that have low selectivity to the material of the conformal dielectric layer 132 (i.e., processes and / or chemistries designed to etch the layer 132), but have high selectivity to the material of the gate spacer 151 (i.e., processes and / or chemistries that do not significantly etch the gate spacer 151). It may be noted here that during the etching process, the portion of the conformal dielectric layer 132 exposed by the opening 820 at the upper portion of the gate spacer 151 (i.e., the portion of the layer 132 overlying the upper surface of the passivation layer 130) is also etched away.

[0132] For example, in some embodiments, the etching process may include wet etching using HF or BOE. In other embodiments, the etching process may include chlorine plasma etching. Alternatively, other suitable etching processes and chemistries may be used. In essence, the etching process results in complete removal of a portion of the conformal dielectric layer 132 at the bottom area 452 of the gate opening 450, such as Figure 8 In addition, the etching process removes portions of the conformal dielectric layer 132 at upper portions of the gate spacers 151, thus exposing the upper surface of the passivation layer 130 on either side of the gate opening 450. According to an embodiment, the photoresist layer 810 is not removed after the etching process, but remains and is used to form the gate electrode 150.

[0133] exist Figure 2 In block 218, and as Fig. 9As depicted in manufacturing stage 900 of the present invention, the method may continue with forming a gate electrode 150. According to one or more embodiments, the gate electrode 150 may be formed using a lift-off process. More specifically, as Fig. 9 , a conductive gate metal layer 950 is deposited on the patterned photoresist layer 810. In addition, the gate metal layer 950 is deposited through the photoresist openings 820 onto the passivation layer 130, the gate spacers 151, and the exposed portions of the upper surface 103 of the substrate 110 (between the gate spacers 151). The portions of the gate metal layer 950 deposited within the photoresist openings 820 form the gate electrode 150. In one or more embodiments, the various layers of the gate metal layer 950 may be deposited by evaporation, sputtering, PVD, or other suitable deposition techniques.

[0134] According to various embodiments, the gate metal layer 950 may include a metal stack of one or more Schottky contact material layers combined with one or more low stress conductive material layers. For example, the first layer in the multi-stack for forming the gate electrode 150 may include Ti, Ni, Pt, Cu, palladium (Pd), Cr, W, iridium (Ir), polysilicon or other suitable materials. The thickness of the first layer may be between about 30 and about 2,000 angstroms, but other thickness values ​​may also be used. According to an embodiment, one or more layers acting as a conductive layer may be deposited on or above the first layer to form the gate electrode 150. The conductive layer may include Au, Ag, Al, Cu, Ti or other basic conductive materials. The thickness of the conductive layer may be between about 50 and about 20,000 angstroms, but other thickness values ​​may also be used. Optionally, one or more barrier metal layers may be placed between the first layer and the conductive layer, wherein the barrier metal layer may include a material that acts as a barrier between a portion of the first layer contacting the semiconductor substrate 110 and the conductive layer, such as Ni, Pt, Cu, Pd, Cr, W, Ir or other substantially refractive materials. The barrier metal layer may have a thickness between about 50 and about 10,000 angstroms, although other thickness values ​​may also be used.

[0135] It should be appreciated that other methods may be used to form the gate electrode 150 without departing from the scope of the present subject matter. For example, in other embodiments, the gate metal layer 950 may be disposed within the gate opening 450 over a gate dielectric layer (not shown) such as SiO2, HfO2, Al2O3, or the like.

[0136] After the gate metal layer 950 is deposited, a stripping process is then performed to remove the photoresist layer 810 and the portion of the gate metal layer 950 deposited on the photoresist layer 810, while leaving intact the portion of the gate metal layer 950 deposited into the photoresist opening 820. According to an alternative embodiment, rather than performing a stripping process, the photoresist layer 810 may be removed, the gate metal layer 950 may be deposited over the surface of the device and into the gate opening 450, and the gate metal layer 950 may be patterned to remove all material except for forming the gate electrode 150.

[0137] Either process produces a gate electrode 150 having a stem portion 953 that extends into the gate opening 450, thereby contacting the gate spacer 151, the sidewalls of the conformal dielectric layer 132 at the bottom of the gate opening 450, and the upper surface 103 of the semiconductor substrate 110. The gate electrode 150 also has a first overhang or protruding segment 955 and a second overhang or protruding segment 956 that overlie and / or contact the upper surfaces of the dielectric layers 130 and 132 on both sides of the gate opening 450. The first segment 955 extends from the stem portion 953 toward the drain electrode 145, and the second segment 956 extends from the stem portion 953 toward the source electrode 140.

[0138] The portion of the stem 953 that contacts the upper surface 103 of the substrate 110 defines a gate channel. As previously mentioned, the gate channel can be characterized by a gate length 155 where the stem 953 of the gate electrode 150 contacts the semiconductor substrate 110 (i.e., where the gate electrode 150 is electrically coupled to the channel 107). In various embodiments, the gate length 155 can be less than 0.25 microns, less than 0.5 microns, between about 0.1 microns and about 1 micron, or up to about 5 microns.

[0139] exist Figure 2 In block 220, and as Fig.10 As depicted in manufacturing stage 1000 of , the method may continue to form an upper dielectric layer 136 over the final location of the source and drain contacts 140, 145, the gate electrode 150, and the field plate 160 to be formed. In one or more embodiments, the upper dielectric layer 136 may include one or more layers of SiN, Al2O3, SiO2, HfO2, indium tin oxide (ITO), diamond, polycrystalline diamond, AlN, boron nitride (BN), SiC, or a combination of these or other insulating materials. The total thickness of the layers used to form the upper dielectric layer 136 may be between about 100 angstroms and about 10,000 angstroms, but other thickness values ​​may also be used. The upper dielectric layer 136 may be deposited using LPCVD, ALD, sputtering, PVD, CVD (including PECVD, MOCVD, catalytic CVD, HWCVD, ICPCVD, and ECR CVD), a combination of these techniques, or other suitable dielectric deposition techniques.

[0140] exist Figure 2 In block 222, and as Fig.11 As depicted in manufacturing stage 1100 of the method, the method may continue to form source contact openings 1140, drain contact openings 1145, and field plate contact openings 1160 through upper dielectric layer 136. To accomplish this, a photoresist layer 1110 may be formed over upper dielectric layer 136. After dispensing, photoresist layer 1110 is patterned to form resist openings 1120 over source electrode 140, drain electrode 145, and field plate opening 460, respectively.

[0141] These openings 1120 expose the upper surface of the upper dielectric layer 136. Source contact openings 1140, drain contact openings 1145, gate contact openings, and field plate contact openings 1160 through the upper dielectric layer 136 can then be created by etching through the upper dielectric layer 136 in the areas exposed by the photoresist openings 1120 while stopping at the source and drain contacts 140, 145 and the upper surface of the conformal dielectric layer 132. Additionally, the etching process (or additional etching processes) can be performed to remove the field plate spacers 161.

[0142] Etching the lower dielectric layer 130 and the field plate spacer 161 preferably includes performing one or more anisotropic etching processes that are highly selective to the material of the conformal dielectric layer 132. For example, the etching process may include one or more dry etching processes, such as RIE, ICP etching, ECR etching, or another suitable dry etching process. According to one or more embodiments, suitable dry etching techniques may use one or more of sulfur hexafluoride (SF6), carbon hexafluoride (C2F6), carbon tetrafluoride (CF4), trifluoromethane (CHF3), or other chemicals. In alternative embodiments, alternatively, a suitable wet chemical etching process may be performed. The photoresist mask 1110 may be removed after forming the source contact opening 1140, the drain contact opening 1145, and the field plate contact opening 1160.

[0143] At this point, source metallization 185 and drain metallization 186, field plate 160, and field plate to source connection 180 are formed. Various different process sequences may be used to accomplish these processes. Blocks 224 and 226 (corresponding to Fig.12 , 13 The manufacturing stages 1200, 1300) are used to describe the first process sequence. Block 224' is then used to describe the second process sequence.

[0144] Beginning first with blocks 224 and 226 and in accordance with one or more first embodiments, a first process sequence includes first blanket depositing an interconnect metal layer (block 224) and then patterning the layer to define source and drain metallizations 185, 186 and field plate to source connection 180 (block 226).

[0145] exist Figure 2 In block 224, and as Fig.12 1, the method involves blanket depositing an interconnect metal layer 1210 on or over the upper dielectric layer 136 and into the source contact opening 1140, the drain contact opening 1145, the gate contact opening, and the field plate contact opening 1160. It may be noted here that the portion of the interconnect metal layer 1210 deposited at the lower extent of the field plate opening 1160 corresponds to the field plate 160 of the device. As previously mentioned, the relative arrangement of the gate electrode 150 and the field plate 160 may be characterized by a gate to field plate spacing (e.g., dimension 165). In some embodiments, the gate to field plate spacing 165 may be between about 0.2 microns and about 0.5 microns, but the field plate to gate distance may also be shorter or longer.

[0146] In one or more embodiments, the interconnect metal layer 1210 may be deposited by sputtering, evaporation, PVD or other suitable deposition techniques. In one or more embodiments, the interconnect metal layer 1310 may contain one or more materials selected from the following: Ti, Al, TiN, TiW, TiAl and / or TiWN, Au, Mo, Ni, Si, Ge, Pt, Ta, Cu, Au, Ag and / or other suitable materials.

[0147] exist Figure 2 In block 226, and as Fig.13 As depicted in manufacturing stage 1300 of , the method may continue patterning the interconnect metal layer 1210 to form a source metallization 185 , a drain metallization 186 , and a conductive connection 180 between the field plate 160 and the source metallization 185 (ie, between the field plate 160 and the source region 142 ).

[0148] This process may include forming and patterning a photoresist layer 1310 over the interconnect metal layer 1210. More specifically, after dispensing, the photoresist layer 1310 is patterned to form resist openings 1320 over portions of the interconnect metal layer 1210 outside of the desired locations of the source and drain metallizations 185, 186, and the conductive connections 180. In other words, the photoresist layer 1310 is patterned to protect portions of the interconnect metal layer 1210 over the source and drain electrodes 140, 145, over the field plates 160, and between the field plates 160 and the source electrode 140.

[0149] The portions of the interconnect metal layer 1210 exposed by the openings 1320 in the photoresist layer 1310 are then removed by etching through those portions of the interconnect metal layer 1210 while stopping at the upper surface of the upper dielectric layer 136. Etching the interconnect metal layer 1210 preferably includes performing a dry etching process, such as RIE, ICP etching, ECR etching, or other suitable dry etching process. For example, according to an embodiment, a suitable dry etching technique may use one or more of SF6, C2F6, CF4, CHF3, or other chemicals similar to BCl3 / Cl2. In an alternative embodiment, a suitable wet chemical etching process may be performed.

[0150] The etching process results in the formation of source metallization 185 and drain metallization 186 and conductive connection 180 between field plate 160 and source metallization 185. As previously mentioned, in some embodiments, field plate source connection 180 includes conductive straps 188 that include relatively narrow conductors spaced along the transistor fingers that extend periodically over gate electrode 150 to electrically couple multiple connection points along field plate 160 to source electrode 140. In other embodiments, field plate source connection 180 may include a solid, continuous conductive structure between field plate 160 and source electrode 140, rather than conductive straps 188. Patterned photoresist layer 1310 is removed, thereby producing Figure 1 The semiconductor device 100 depicted in FIG.

[0151] Moving now to box 224', and in accordance with one or more alternative embodiments, the process of forming source and drain metallizations, field plates, and field plate-to-source connections may alternatively use a stripping process. Similar to the process described in conjunction with forming gate electrode 150, the stripping process for forming source and drain metallizations 185, 186, field plates 160, and field plate-to-source connections 180 may include depositing a photoresist layer and patterning the photoresist layer to include openings in which source and drain metallizations 185, 186, and field plates 160 are to be formed. The process may continue with depositing an interconnect metal layer (e.g., layer 1210) onto an upper surface of the photoresist layer and into the openings in the photoresist layer. A stripping process may then be performed to remove the photoresist layer and portions of the interconnect metal layer deposited on the photoresist layer, while leaving portions of the interconnect metal layer deposited into the photoresist openings intact.

[0152] Regardless of which process sequence is used to form the drain and source metallizations 185, 186, the field plate 160, and the field plate to source connection 180, the method Figure 2Fabrication of device 100 continues in block 228 of the device 100. This may include forming additional dielectric and conductive layers (e.g., M1, M2, etc.) over the partially formed device to provide selective electrical connections between various features of device 100 (e.g., input / output bond pads, other transistor fingers, etc.). Figure 2 The method may then end.

[0153] An embodiment of a semiconductor device includes a semiconductor substrate having an upper surface and a channel, and one or more lower dielectric layers disposed on the upper surface of the semiconductor substrate. A source opening, a drain opening, a gate opening, and a field plate opening extend through the lower dielectric layer to the semiconductor substrate. A conformal dielectric layer is disposed above the lower dielectric layer and at least into the gate opening and the field plate opening. The conformal dielectric layer includes a first portion formed on the sidewall of the gate opening, a second portion formed on the sidewall of the field plate opening, and a third portion formed on the semiconductor substrate at the bottom range of the field plate opening. A gate spacer is disposed on the first portion of the conformal dielectric layer. A gate electrode is disposed in the gate opening, in contact with the gate spacer and the semiconductor substrate. A field plate is disposed in the field plate opening, in contact with the second and third portions of the conformal dielectric layer.

[0154] An embodiment of a method for forming a semiconductor device includes forming one or more lower dielectric layers above an upper surface of a semiconductor substrate including a channel. The method further includes using a patterned photoresist mask to simultaneously form multiple openings through the one or more lower dielectric layers, wherein the multiple openings include gate openings and field plate openings. A conformal dielectric layer is deposited into the multiple openings. The conformal dielectric layer includes a first portion formed on the sidewalls of the gate opening, a second portion formed on the sidewalls of the field plate opening, and a third portion formed on the semiconductor substrate at a bottom range of the field plate opening. A gate spacer is formed on the first portion of the conformal dielectric layer in the gate opening. A gate electrode is formed in the gate opening in contact with the dielectric gate spacer. A field plate is formed in the field plate opening in contact with the second and third portions of the conformal dielectric layer.

[0155] Although at least one exemplary embodiment has been presented in the foregoing specific embodiments, it should be understood that there are a large number of variations. It should also be understood that the exemplary embodiment or multiple exemplary embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. In fact, the foregoing specific embodiments will provide a convenient guide for implementing the described embodiment or embodiments to those skilled in the art. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, and the scope defined by the claims includes known equivalents and foreseeable equivalents at the time of filing this patent application.

[0156] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference purposes only, and therefore these terms are not intended to be limiting, and unless the context clearly indicates otherwise, the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order.

[0157] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly connected to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly connected to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, while the schematic diagrams shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate comprising an upper surface and a channel; one or more lower dielectric layers disposed on the upper surface of the semiconductor substrate, wherein a source opening, a drain opening, a gate opening, and a field plate opening extend through the one or more lower dielectric layers to the semiconductor substrate, wherein the gate opening is between the source opening and the drain opening, and the field plate opening is between the gate opening and the drain opening; a conformal dielectric layer disposed over the one or more lower dielectric layers and into at least the gate opening and the field plate opening, wherein the conformal dielectric layer includes a first portion formed on a sidewall of the gate opening, a second portion formed on a sidewall of the field plate opening, and a third portion formed on the semiconductor substrate at a bottom extent region of the field plate opening; a gate spacer disposed on the first portion of the conformal dielectric layer; a gate electrode disposed in the gate opening and contacting the gate spacer and the semiconductor substrate; as well as A field plate is disposed in the field plate opening in contact with the second and third portions of the conformal dielectric layer.

2. The semiconductor device according to claim 1, wherein: The conformal dielectric layer further includes a fourth portion formed on the semiconductor substrate at a bottom extent of the gate opening, wherein the gate electrode extends through the opening in the fourth portion to contact the semiconductor substrate, and wherein the gate spacer is formed on both the first and fourth portions of the conformal dielectric layer.

3. The semiconductor device according to claim 1, wherein: The conformal dielectric layer is formed of a dielectric material selected from aluminum oxide and aluminum nitride.

4. The semiconductor device according to claim 1, wherein: The gate spacers are formed of silicon nitride.

5. The semiconductor device according to claim 4, wherein: The gate electrode has a T-shaped cross-section having a stem portion extending through the one or more lower dielectric layers to contact the semiconductor substrate, and first and second protruding regions extending over the gate spacer and the one or more lower dielectric layers.

6. The semiconductor device according to claim 1, wherein: The field plate is recessed below an upper surface of the one or more lower dielectric layers.

7. The semiconductor device according to claim 1, wherein: The conformal dielectric layer additionally includes a fifth portion formed on a sidewall of the source opening, and a sixth portion formed on a sidewall of the drain opening.

8. The semiconductor device according to claim 7, wherein: the conformal dielectric layer additionally comprising a seventh portion formed over an upper surface of the one or more lower dielectric layers, wherein the seventh portion extends from one of the fifth portions formed on the sidewalls of the source opening toward one of the first portions formed on the sidewalls of the gate opening; and The conformal dielectric layer further includes an eighth portion formed above the upper surface of the one or more lower dielectric layers, wherein the eighth portion extends from one of the sixth portions formed on the sidewalls of the drain opening toward one of the second portions formed on the sidewalls of the field plate opening.

9. The semiconductor device according to claim 1, wherein: Also includes: a source electrode disposed in the source opening; one or more upper dielectric layers disposed over the one or more lower dielectric layers and over the gate electrode; as well as A conductive connection extends over the one or more upper dielectric layers and over the gate electrode to electrically connect the field plate to the source electrode.

10. A method for forming a semiconductor device, characterized in that: The method comprises: forming one or more lower dielectric layers over an upper surface of the semiconductor substrate including the channel; using a patterned photoresist mask to simultaneously form a plurality of openings through the one or more lower dielectric layers, wherein the plurality of openings include gate openings and field plate openings; depositing a conformal dielectric layer into the plurality of openings, wherein the conformal dielectric layer includes a first portion formed on sidewalls of the gate openings, a second portion formed on sidewalls of the field plate openings, and a third portion formed on the semiconductor substrate at a bottom extent of the field plate openings; forming a gate spacer on the first portion of the conformal dielectric layer in the gate opening; forming a gate electrode in the gate opening in contact with the dielectric gate spacer; and A field plate is formed in the field plate opening in contact with the second and third portions of the conformal dielectric layer.

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