Semiconductor device, manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device, a preparation method, a power module, a power conversion circuit and a vehicle. The device includes a first wafer structure and a second wafer structure, the first wafer structure includes a first surface and a second surface arranged opposite to each other, the second wafer structure includes a third surface and a fourth surface arranged opposite to each other, and the second surface and the third surface are bonded; the first wafer structure includes a first region arranged on the first surface and a well region arranged on a side of the first region away from the first surface, the first surface is provided with a first groove extending from the first surface to the first wafer structure, the second wafer structure includes a second region arranged on the third surface, and the orthographic projection of the second region on the fourth surface at least partially overlaps with the orthographic projection of the first groove on the fourth surface; the gate is located in the first groove; the drain is located on the fourth surface; and the source is located on the first surface. The present invention reduces the specific on-resistance of the semiconductor device and improves the pressure resistance of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of semiconductor devices, and in particular, to a semiconductor device, a preparation method, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] The power device may be a silicon carbide (SiC) power device. Compared with silicon (Si) material, silicon carbide material has unique performance advantages. It can have higher doping at a thinner epitaxial thickness and lower intrinsic carrier concentration. It has excellent voltage resistance and thermal conductivity. Therefore, silicon carbide devices are more suitable for current and future power electronics applications than traditional silicon devices.

[0003] However, the process of SiC devices is not yet mature, and the pressure resistance needs to be improved. At present, in order to achieve strong pressure resistance, a trench-type device structure design is usually adopted. Trench-type devices usually use ion implantation to form part of their structure, but the implantation depth of ions in the device is small, which will limit the pressure resistance of the device. If the number of trenches increases or the depth is too deep, the device will have a higher specific on-resistance and a greater process difficulty.

[0004] Existing SiC devices have the problem of poor pressure resistance, which has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] Embodiments of the present invention provide a semiconductor device, a preparation method, a power module, a power conversion circuit and a vehicle to solve the problem that SiC devices have poor pressure resistance.

[0006] In order to achieve the above technical problems, the present invention adopts the following technical solutions:

[0007] An embodiment of the present invention provides a semiconductor device, including:

[0008] A semiconductor body, the semiconductor body comprising a first wafer structure and a second wafer structure, the first wafer structure comprising a first surface and a second surface arranged opposite to each other, the second wafer structure comprising a third surface and a fourth surface arranged opposite to each other, the second surface and the third surface being bonded to each other;

[0009] The first wafer structure further includes a well region and a first region, the first region is arranged on the first surface, the well region is arranged on a side of the first region away from the first surface, the first surface is further provided with a first groove, and the first groove extends from the first surface to the first wafer structure; the first region is of the first conductivity type, and the well region is of the second conductivity type;

[0010] The second wafer structure further includes a second region, the second region is disposed on the third surface, the second region is of the second conductivity type, and an orthographic projection of the second region on the fourth surface at least partially overlaps with an orthographic projection of the first groove on the fourth surface;

[0011] A gate is located in the first trench;

[0012] a drain electrode, located on the fourth surface;

[0013] The source is located on the first surface.

[0014] Optionally, the first wafer structure includes:

[0015] A first epitaxial layer, the first epitaxial layer and the first region have the same conductivity type;

[0016] The first trench penetrates the first region, the well region and a portion of the first epitaxial layer.

[0017] Optionally, the first wafer structure further includes a first insulating layer;

[0018] The first insulating layer is arranged inside the first trench, and the gate is arranged on a side of the first insulating layer away from the inner wall of the first trench.

[0019] Optionally, the first wafer structure further includes:

[0020] The third region is arranged on the first surface, the third region runs through the first region and part of the well region, and the third region is of the second conductivity type; the ion concentration of the third region is greater than the ion concentration of the well region.

[0021] Optionally, the second wafer structure further includes:

[0022] A substrate, disposed on the fourth surface;

[0023] A second epitaxial layer is arranged on a side of the substrate away from the fourth surface, the conductivity type of the second epitaxial layer is the same as the conductivity type of the substrate, and the substrate is of the first conductivity type; the second region extends into the second epitaxial layer;

[0024] The ion concentration of the first epitaxial layer is greater than or equal to the ion concentration of the second epitaxial layer.

[0025] Optionally, the second wafer structure further includes:

[0026] A second groove, the second groove is arranged on the third surface of the second wafer structure; the second groove penetrates a portion of the second epitaxial layer;

[0027] The second region is located on the sidewall and bottom of the second trench;

[0028] The planarization layer is disposed in the second groove, and a side of the planarization layer away from the substrate is flush with the third surface.

[0029] According to another aspect of an embodiment of the present application, this embodiment provides a method for preparing a semiconductor device, comprising:

[0030] A semiconductor body is provided; the semiconductor body comprises a first wafer structure and a second wafer structure, the first wafer structure comprises a first surface and a second surface which are arranged opposite to each other, the second wafer structure comprises a third surface and a fourth surface which are arranged opposite to each other, and the second surface and the third surface are bonded to each other; the first wafer structure further comprises a well region and a first area, the first area is arranged on the first surface, the well region is arranged on a side of the first area away from the first surface, the first surface is further provided with a first groove, and the first groove extends from the first surface to the first wafer structure; the first area is of a first conductivity type, and the well region is of a second conductivity type; the second wafer structure further comprises a second area, the second area is arranged on the third surface, the second area is of a second conductivity type, and an orthographic projection of the second area on the fourth surface at least partially overlaps with an orthographic projection of the first groove on the fourth surface;

[0031] A gate is formed on a first surface of the semiconductor body; the gate is located in a first trench and extends from the first surface into the semiconductor body;

[0032] forming a drain on the fourth surface of the semiconductor body;

[0033] A source is formed on the first surface of the semiconductor body.

[0034] Optionally, a semiconductor body is provided, comprising:

[0035] A first wafer structure is provided; the first wafer structure comprises a first surface and a second surface which are arranged opposite to each other, the first wafer structure further comprises a well region and a first area, the first area is arranged on the first surface, the well region is arranged on a side of the first area away from the first surface, the first surface is further provided with a first groove, the first groove extends from the first surface to the first wafer structure; the first area is of a first conductivity type, and the well region is of a second conductivity type;

[0036] Providing a second wafer structure; the second wafer structure includes a third surface and a fourth surface that are arranged opposite to each other, and the second wafer structure also includes a second region, the second region is arranged on the third surface, and the second region is of a second conductivity type;

[0037] The second surface of the first wafer structure and the third surface of the second wafer structure are bonded; an orthographic projection of the second region on the fourth surface at least partially overlaps with an orthographic projection of the first groove on the fourth surface.

[0038] Optionally, a first wafer structure is provided, including:

[0039] forming a first epitaxial layer on one side of the substrate; the first epitaxial layer has the same conductivity type as the first region;

[0040] forming a well region on a side of the first epitaxial layer away from the substrate;

[0041] forming a first region on a side of the well region away from the substrate; the ion concentration of the first region is greater than the ion concentration of the first epitaxial layer;

[0042] Remove the base plate.

[0043] Optionally, providing a first wafer structure further includes:

[0044] A third region is formed on the first surface of the first wafer structure; the third region runs through the first region and a portion of the well region, the third region is of the second conductivity type, and the ion concentration of the third region is greater than the ion concentration of the well region.

[0045] Optionally, after forming the first epitaxial layer on one side of the substrate, the method further includes:

[0046] A first groove is formed on the first surface of the first wafer structure; the first groove extends from the first surface to the inside of the first wafer structure; the first groove penetrates the first region, the well region and a portion of the first epitaxial layer;

[0047] forming a first insulating layer inside the first trench;

[0048] Forming a gate on a first surface of a semiconductor body comprises:

[0049] A gate is formed on a side of the first insulating layer away from the inner wall of the first trench.

[0050] Optionally, a second wafer structure is provided, comprising:

[0051] forming a second epitaxial layer on one side of the substrate; the second epitaxial layer has the same conductivity type as the substrate; and the substrate is of the first conductivity type;

[0052] A second region extending from a surface of the second epitaxial layer away from the substrate into the second epitaxial layer is formed, and the second region is of a second conductivity type; and an ion concentration of the first epitaxial layer is greater than or equal to an ion concentration of the second epitaxial layer.

[0053] Optionally, a second wafer structure is provided, comprising:

[0054] forming a second epitaxial layer on one side of the substrate;

[0055] A second trench is formed on a side of the second epitaxial layer away from the substrate; the second trench penetrates a portion of the second epitaxial layer;

[0056] forming the second region on the sidewall and the bottom of the second trench; the second region is of the second conductivity type;

[0057] A planarization layer is formed in the second trench; a side of the planarization layer away from the substrate is flush with the third surface.

[0058] According to a third aspect of the embodiments of the present application, this embodiment provides a power module, comprising a substrate and at least one semiconductor device provided in any item of the first aspect, wherein the substrate is used to carry the semiconductor device.

[0059] According to a fourth aspect of the embodiments of the present application, the embodiments provide a power conversion circuit, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0060] The power conversion circuit includes a circuit board and at least one semiconductor device according to any item of the first aspect, wherein the semiconductor device is electrically connected to the circuit board.

[0061] According to the fifth aspect of the embodiment of the present application, this embodiment provides a vehicle, including a load and the power conversion circuit proposed in the fourth aspect, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0062] The semiconductor body of the semiconductor device provided by the embodiment of the present invention includes a first wafer structure and a second wafer structure. The first surface of the first wafer structure is provided with a well region and a first region, and the third surface of the second wafer structure is provided with a second region. The first region and the well region are used to form a conductive channel. The second region provided on the third surface of the second semiconductor can increase the depth and width of the depletion region, thereby improving the pressure resistance of the semiconductor device. Since the orthographic projection of the second region on the fourth surface overlaps at least partially with the orthographic projection of the first groove on the fourth surface, the second region is provided along the thickness direction of the semiconductor device, which reduces the size of the second region occupied in the width direction of the semiconductor device, thereby improving the specific on-resistance of the semiconductor device. This arrangement facilitates the simultaneous manufacture of the first wafer structure and the second wafer structure, greatly shortens the production cycle of the semiconductor device, and reduces the difficulty of the manufacturing process of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0064] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0065] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0066] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0067] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0068] Figure 5 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0069] Figure 6-Figure 11 is a schematic diagram of an intermediate structure of a first wafer structure of a semiconductor device provided by an embodiment of the present invention;

[0070] Figure 12-13 is a schematic diagram of an intermediate structure of a second wafer structure of a semiconductor device provided by an embodiment of the present invention;

[0071] Fig.14 yes Figure 5 A detailed flow chart included in S110;

[0072] Fig.15 yes Fig.14 A detailed flow chart included in S111;

[0073] Fig.16 yes Fig.14 A detailed flow chart included in S111;

[0074] Fig.17 yes Fig.14 A detailed flow chart included in S112;

[0075] Fig.18 yes Fig.14 A detailed flow chart included in S112;

[0076] Fig.19 It is a schematic diagram of an intermediate structure of a second wafer structure of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0077] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0078] Based on the above technical problems, this embodiment proposes the following solutions:

[0079] An embodiment of the present invention provides a semiconductor device. Figure 1 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention. Figure 1 The semiconductor device provided by the embodiment of the present invention includes a semiconductor body 10, the semiconductor body 10 includes a first wafer structure 20 and a second wafer structure 30, the first wafer structure 20 includes a first surface M1 and a second surface M2 arranged opposite to each other, the second wafer structure 30 includes a third surface M3 and a fourth surface M4 arranged opposite to each other, the second surface M2 and the third surface M3 are bonded to each other; the first wafer structure 20 also includes a well region 21 and a first region 22, the first region 22 is arranged on the first surface M1, the well region 21 is arranged on a side of the first region 22 away from the first surface M1, and the first surface M The first wafer structure 20 is also provided with a first trench 23, which extends from the first surface M1 to the first wafer structure 20; the first region 22 is of the first conductivity type, and the well region 21 is of the second conductivity type; the second wafer structure 30 further includes a second region 31, which is provided on the third surface M3, is of the second conductivity type, and the orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first trench 23 on the fourth surface M4; the gate 40 is located in the first trench 23; the drain 50 is located on the fourth surface M4; and the source 60 is located on the first surface M1.

[0080] Specifically, the semiconductor device provided in this embodiment may be a silicon carbide trench metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). Figure 1 , the first wafer structure 20 may include a well region 21 and a first region 22. The first region 22 is of the first conductivity type, and the well region 21 is of the second conductivity type. The well region 21 and the first region 22 are used to form a conductive channel of a semiconductor device. The well region 21 may be formed by epitaxial growth or by ion implantation. The first region 22 may be formed by ion implantation or epitaxial growth. By adjusting the size of the well region 21 and the first region 22, the channel length may be controlled, the on-resistance of the device may be reduced, and the stability of the threshold voltage of the device may be improved.

[0081] A first groove 23 can be formed by etching the first surface M1 of the first wafer structure 20. The first groove 23 extends from the first surface M1 to the inside of the first wafer structure 20. The gate 40 is arranged in the first groove 23. The gate 40 extends from the first surface M1 to the inside of the semiconductor body 10. This arrangement can make the semiconductor device have a greater channel mobility. The conductive channel is set as a vertical channel, which can eliminate the junction field-effect transistor (JFET) region and make the on-resistance of the semiconductor device lower. The density of the vertical gate is large, which can reduce the cell spacing and increase the current density.

[0082] The source electrode 60 may be a metal conductive layer. For example, the metal conductive layer may be titanium (Ti), nickel (Ni), or silver (Ag).

[0083] The second region 31 is set on the third surface M3 of the second wafer structure 30. The second region 31 is of the second conductivity type. After the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded to each other, the second region 31 set on the third surface M3 is located inside the semiconductor body 10, so that the second region 31 can be located at a very deep depth inside the semiconductor body 10. Due to the deep depth of the second region 31, the pressure resistance of the semiconductor body 10 is effectively improved. Since the second region 31 is in the second wafer structure 30, the second region 31 does not need to be grooved, or does not need to be grooved very deep, thereby reducing the difficulty of the manufacturing process of the deep groove.

[0084] By arranging the second region 31 in the second wafer structure 30, the orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first groove 23 on the fourth surface M4. This arrangement avoids wasting the area of ​​the second region 31 in the width direction of the semiconductor body 10, thereby better improving the specific on-resistance of the semiconductor device.

[0085] In addition, the first wafer structure 20 and the second wafer structure 30 can be manufactured simultaneously, which greatly shortens the production cycle of semiconductor devices.

[0086] The fourth surface M4 of the second wafer structure 30 is provided with a drain 50 . The drain 50 may be a metal conductive layer. Exemplarily, the metal conductive layer may be titanium (Ti), nickel (Ni) or silver (Ag). The drain 50 is located on the fourth surface M4 of the second wafer structure 30 .

[0087] The semiconductor body 10 of the semiconductor device provided in this embodiment includes a first wafer structure 20 and a second wafer structure 30. The first surface M1 of the first wafer structure 20 is provided with a well region 21 and a first region 22, and the third surface M3 of the second wafer structure 30 is provided with a second region 31. The first region 22 and the well region 21 are used to form a conductive channel. The second region 31 arranged on the third surface M3 of the second semiconductor can increase the depth and width of the depletion region, thereby improving the pressure resistance of the semiconductor device. Since the orthographic projection of the second region 31 on the fourth surface M4 overlaps at least partially with the orthographic projection of the first groove 23 on the fourth surface M4, the second region 31 is arranged along the thickness direction of the semiconductor device, which reduces the size of the second region 31 in the width direction of the semiconductor device, thereby improving the specific on-resistance of the semiconductor device. This arrangement facilitates the simultaneous production of the first wafer structure 20 and the second wafer structure 30, greatly shortens the production cycle of the semiconductor device, improves production efficiency, and reduces the difficulty of the manufacturing process of the semiconductor device.

[0088] Optional, Figure 2 FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 2 The first wafer structure 20 includes: a first epitaxial layer 24, the first epitaxial layer 24 and the first region 22 have the same conductivity type; a first trench 23 penetrates the first region 22, the well region 21 and part of the first epitaxial layer 24; the ion concentration of the first region 22 is greater than the ion concentration of the first epitaxial layer 24; the ion concentration of the second region 31 is greater than the ion concentration of the well region 21.

[0089] Specifically, the first epitaxial layer 24 may be formed by epitaxial growth. The material of the first epitaxial layer 24 may be silicon carbide. Figure 2 If the semiconductor device is an N-type device, the first epitaxial layer 24 may be an N-epitaxial layer, for example, an N-silicon carbide epitaxial layer. The first region 22 is an N+ region, and the second region 31 is a P+ region. If the semiconductor device is a P-type device, the first epitaxial layer 24 may be a P-epitaxial layer, for example, a P-silicon carbide epitaxial layer. The first region 22 is a P+ region, and the second region 31 is an N+ region.

[0090] The material of the well region 21 may be silicon carbide. During the growth of silicon carbide, silicon and carbon are provided. The well region 21 is formed on the side of the first epitaxial layer 24 away from the second surface M2 by using silane and propane as reaction gas sources and boron or aluminum as doping elements. If the semiconductor device is an N-type power device, the well region 21 may be a P-type well region 21.

[0091] Optionally, based on the above embodiments, continue to refer to Figure 2The first wafer structure 20 further includes a first insulating layer 41 ; the first insulating layer 41 is disposed inside the first trench 23 , and the gate 40 is disposed on a side of the first insulating layer 41 away from an inner wall of the first trench 23 .

[0092] Specifically, the first insulating layer 41 may be a gate oxide layer. The gate oxide layer may be a high dielectric constant (K) material. The gate 40 may be a polysilicon layer. Figure 2 , a first groove 23 can be etched on the first surface M1 of the first wafer structure 20. The first groove 23 extends from the first surface M1 to the inside of the first wafer structure 20. The gate 40 extends from the first surface M1 to the inside of the first wafer structure 20, which can make the semiconductor device have a greater channel mobility, and the conductive channel is a vertical channel, which can eliminate the junction field effect transistor region and make the on-resistance of the semiconductor device lower. In addition, the density of the vertical gate 40 is large, which can reduce the cell spacing of the semiconductor device and increase the current density.

[0093] Optional, Figure 3 FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 3 The first wafer structure 20 also includes: a third region 25, the third region 25 is arranged on the first surface M1, the third region 25 runs through the first region 22 and a portion of the well region 21, and the third region 25 is of the second conductivity type; the ion concentration of the third region 25 is greater than the ion concentration of the well region 21.

[0094] Specifically, a third region 25 is provided on the first surface M1 of the first wafer structure 20. Exemplarily, if the semiconductor device is an N-type power device, the second region 31 is a P+ region, and the well region 21 is a P-well. If the semiconductor device is a P-type power device, the second region 31 is an N+ region, and the well region 21 is an N-well.

[0095] Optionally, based on the above embodiments, continue to refer to Figure 3 The second wafer structure 30 may also include: a substrate 32, arranged on the fourth surface M4; a second epitaxial layer 33, arranged on the side of the substrate 32 away from the fourth surface M4, the conductivity type of the second epitaxial layer 33 is the same as the conductivity type of the substrate 32, and the substrate 32 is the first conductivity type; the second region 31 extends into the second epitaxial layer 33; the ion concentration of the first epitaxial layer 24 is greater than or equal to the ion concentration of the second epitaxial layer 33.

[0096] Specifically, the second wafer structure 30 may include a substrate 32, a second epitaxial layer 33 and a second region 31. The substrate 32 may be a silicon substrate or a silicon carbide substrate. Figure 4If the semiconductor device is an N-type device, the substrate 32 is an N+ substrate, for example, an N+ silicon carbide substrate. The second epitaxial layer 33 is an N-epitaxial layer, for example, an N-silicon carbide epitaxial layer. If the semiconductor device is a P-type device, the substrate 32 is a P+ substrate, and the second epitaxial layer 33 is a P-epitaxial layer. The second epitaxial layer 33 is formed on one side of the substrate 32.

[0097] Optional, Figure 4 FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 4 The second wafer structure 30 may also include: a second groove 34, the second groove 34 is arranged on the third surface M3 of the second wafer structure 30; the second groove 34 penetrates a portion of the second epitaxial layer 33; the second region 31 is located on the sidewall and bottom of the second groove 34; a planarization layer 35 is arranged in the second groove 34, and the side of the planarization layer 35 away from the substrate 32 is flush with the third surface M3.

[0098] Specifically, the second region 31 is formed on the sidewall and bottom of the second trench 34. The second region 31 is of the second conductivity type. The second region 31 can be formed on the sidewall and bottom of the second trench 34 by an ion implantation process. If the semiconductor device is an N-type power device, the second region 31 is a P+ type region, and the cavity pressure is The energy of P+ type ion implantation is 10Kev~800Kev, and the ion implantation dose is about .

[0099] A planarization layer 35 is formed inside the second trench 34. The planarization layer 35 may be formed by atomic layer deposition (ALD) or the like. The planarization layer 35 fills the second trench 34. The material of the planarization layer 35 may include a non-conductive material. It may include an organic material or an inorganic material. The planarization layer 35 is flush with the third surface M3, so as to facilitate bonding the third surface M3 and the second surface M2 to each other and improve the reliability of the semiconductor device.

[0100] Optional, Figure 5 FIG. 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 1 and Figure 5 , the method for preparing a semiconductor device provided in this embodiment includes:

[0101] S110, providing a semiconductor body 10; the semiconductor body 10 includes a first wafer structure 20 and a second wafer structure 30, the first wafer structure 20 includes a first surface M1 and a second surface M2 arranged opposite to each other, the second wafer structure 30 includes a third surface M3 and a fourth surface M4 arranged opposite to each other, and the second surface M2 and the third surface M3 are bonded to each other; the first wafer structure 20 also includes a well region 21 and a first area 22, the first area 22 is arranged on the first surface M1, the well region 21 is arranged on a side of the first area 22 away from the first surface M1, and the first surface M1 is also provided with a first groove 23, and the first groove 23 extends from the first surface M1 to the first wafer structure 20; the first area 22 is of the first conductivity type, and the well region 21 is of the second conductivity type; the second wafer structure 30 also includes a second area 31, the second area 31 is arranged on the third surface M3, the second area 31 is of the second conductivity type, and the orthographic projection of the second area 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first groove 23 on the fourth surface M4.

[0102] Specifically, Figure 6-Figure 11 It is a schematic diagram of an intermediate structure of a first wafer structure of a semiconductor device provided by an embodiment of the present invention. Figure 12-13 1 is a schematic diagram of an intermediate structure of a second wafer structure of a semiconductor device provided by an embodiment of the present invention. Figure 1 , Figure 5 , Figures 6 to 13 Providing the semiconductor body 10 may include providing a first wafer structure 20 and providing a second wafer structure 30 .

[0103] The first wafer structure 20 may be formed first, and then the second wafer structure 30 may be formed. Alternatively, the second wafer structure 30 may be formed first, and then the first wafer structure 20 may be formed. Alternatively, the first wafer structure 20 and the second wafer structure 30 may be formed simultaneously. The second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded to form the semiconductor body 10.

[0104] It should be noted that the production cycle of semiconductor devices is greatly shortened by manufacturing the first wafer structure 20 and the second wafer structure 30 simultaneously.

[0105] S120 , forming a gate 40 on the first surface M1 of the semiconductor body 10 ; the gate 40 is located in the first trench 23 and extends from the first surface M1 into the semiconductor body 10 .

[0106] Specifically, the first insulating layer 41 may be a gate oxide layer. The gate oxide layer may be a high dielectric constant (K) material. The gate 40 may be a polysilicon layer. A first trench 23 may be formed by etching the first surface M1 of the first wafer structure 20. The first trench 23 extends from the first surface M1 to the inside of the first wafer structure 20. The gate 40 extends from the first surface M1 to the inside of the first wafer structure 20, which may enable the semiconductor device to have a greater channel mobility. The conductive channel is a vertical channel, which may eliminate the junction field effect transistor region and make the on-resistance of the semiconductor device lower. The vertical gate 40 has a high density, which may reduce the cell spacing of the semiconductor device and increase the current density.

[0107] S130 , forming a drain 50 on the fourth surface M4 of the semiconductor body 10 .

[0108] Specifically, the drain 50 can be formed on the fourth surface M4 of the second wafer structure 30 by sputtering or the like. The drain 50 is a metal conductive layer. Exemplarily, the metal conductive layer can be titanium (Ti), nickel (Ni) or silver (Ag), etc. The fourth surface M4 of the second wafer structure 30 can be thinned first, and then the drain 50 can be formed by sputtering or the like.

[0109] S140 , forming a source 60 on the first surface M1 of the semiconductor body 10 .

[0110] Specifically, the source electrode 60 can be formed on the first surface M1 of the first wafer structure 20 by sputtering or the like. The source electrode 60 is a metal conductive layer. Exemplarily, the metal conductive layer can be titanium (Ti), nickel (Ni) or silver (Ag), etc. The source electrode 60 is located on the first surface M1.

[0111] It should be noted that, continue to refer to Fig.10 and Fig.11 Before forming the source 60 on the first surface M1 of the semiconductor body 10 , an interlayer insulating layer 61 may be formed on a side of the gate 40 away from the second surface.

[0112] The semiconductor body 10 of the semiconductor device provided in this embodiment includes a first wafer structure 20 and a second wafer structure 30. The first surface M1 of the first wafer structure 20 is provided with a well region 21 and a first region 22, and the third surface M3 of the second wafer structure 30 is provided with a second region 31. The first region 22 and the well region 21 are used to form a conductive channel. The second region 31 arranged on the third surface M3 of the second semiconductor can increase the depth and width of the depletion region, thereby improving the pressure resistance of the semiconductor device. Since the orthographic projection of the second region 31 on the fourth surface M4 overlaps at least partially with the orthographic projection of the first groove 23 on the fourth surface M4, the second region 31 is arranged along the thickness direction of the semiconductor device, which reduces the size of the second region 31 in the width direction of the semiconductor device, thereby improving the specific on-resistance of the semiconductor device. This arrangement facilitates the simultaneous production of the first wafer structure 20 and the second wafer structure 30, greatly shortens the production cycle of the semiconductor device, and reduces the difficulty of the manufacturing process of the semiconductor device.

[0113] Optional, Fig.14 yes Figure 5 A detailed flow chart of S110 included in the above embodiments. Figures 3 to 5 and Fig.14 , S110, providing a semiconductor body 10, including:

[0114] S111. Provide a first wafer structure 20; the first wafer structure 20 includes a first surface M1 and a second surface M2 that are arranged opposite to each other, the first wafer structure 20 also includes a well region 21 and a first region 22, the first region 22 is arranged on the first surface M1, the well region 21 is arranged on a side of the first region 22 away from the first surface M1, the first surface M1 is also provided with a first groove 23, the first groove 23 extends from the first surface M1 to the first wafer structure 20; the first region 22 is of the first conductivity type, and the well region 21 is of the second conductivity type.

[0115] Specifically, a well region 21 and a first region 22 are formed on the first surface M1 of the first wafer structure 20. The well region 21 and the first region 22 can be formed by epitaxial growth or by ion implantation, which is not limited here. A first groove 23 is formed on the first surface M1 of the first wafer structure 20. The first groove 23 extends from the first surface M1 to the first wafer structure 20.

[0116] S112, providing a second wafer structure 30; the second wafer structure 30 includes a third surface M3 and a fourth surface M4 that are arranged opposite to each other, and the second wafer structure 30 also includes a second region 31, the second region 31 is arranged on the third surface M3, and the second region 31 is of the second conductivity type.

[0117] Specifically, a second region 31 is formed on the third surface M3 of the second wafer structure 30. The second region 31 may be formed by epitaxial growth or by ion implantation. The second region 31 is of the second conductivity type.

[0118] S113, bonding the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30; the orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first groove 23 on the fourth surface M4; the ion concentration of the second region 31 is greater than the ion concentration of the well region 21.

[0119] Specific, combined Figure 1 and Fig.14 , the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 can be bonded to each other by bonding adhesive. After the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded to each other, the second region 31 disposed on the third surface M3 is located inside the semiconductor body 10, so that the second region 31 can be located at a very deep depth inside the semiconductor body 10. Due to the deep depth of the second region 31, the pressure resistance of the semiconductor body 10 is effectively improved, and the difficulty of the manufacturing process of the deep groove is reduced.

[0120] After the second surface M2 of the first wafer structure 20 and the third surface M3 of the second wafer structure 30 are bonded to each other, the orthographic projection of the second region 31 on the fourth surface M4 at least partially overlaps with the orthographic projection of the first groove 23 on the fourth surface M4, thereby preventing the second region 31 from occupying the dimension in the width direction of the semiconductor body 10, thereby better improving the on-resistance of the semiconductor device.

[0121] Optional, Fig.15 yes Fig.14 A detailed flow chart included in S111. Based on the above embodiments, combined with Figures 3 to 5 , Fig.14 and Fig.15 , S111, providing a first wafer structure 20, including:

[0122] S1111 , forming a first epitaxial layer 24 on one side of the substrate 26 ; the first epitaxial layer 24 and the first region 22 have the same conductivity type.

[0123] Specifically, a substrate 26 is provided, and a first epitaxial layer 24 can be formed by epitaxial growth on one side of the substrate 26. The material of the first epitaxial layer 24 can be silicon carbide. The substrate 26 can be a silicon substrate or a silicon carbide substrate.

[0124] S1112 , forming a well region 21 on a side of the first epitaxial layer 24 away from the substrate 26 .

[0125] Specifically, a well region 21 can be formed on a side of the first epitaxial layer 24 away from the substrate 26. Forming the well region 21 by epitaxial growth can reduce damage caused by ion implantation, and can accurately control the film thickness and ion concentration of the well region 21, which can ensure the stability of the ion concentration and facilitate the control of the channel length.

[0126] S1113 , forming a first region 22 on a side of the well region 21 away from the substrate 26 ; the ion concentration of the first region 22 is greater than the ion concentration of the first epitaxial layer 24 .

[0127] Specifically, a first region 22 may be formed on the side of the well region 21 away from the substrate 26. The first region 22 is located on the first surface M1 of the first wafer structure 20. Forming the first region 22 by epitaxial growth can reduce the damage caused by ion implantation, and can accurately control the film thickness and ion concentration of the well region 21 and the first region 22, which can ensure the stability of the ion concentration, and can also control the channel length, reduce the on-resistance of the semiconductor device, and improve the stability of the threshold voltage of the semiconductor device. The well region 21 and the first region 22 are used to form a conductive channel.

[0128] S1114 , remove the substrate 26 .

[0129] Specifically, by removing the substrate 26 , the first epitaxial layer 24 can be used as the second surface M2 of the first wafer structure 20 . This configuration facilitates bonding the surface of the first epitaxial layer 24 away from the first region 22 to the second wafer structure 30 .

[0130] As another optional implementation, an embodiment of the present invention provides a method for preparing a semiconductor device based on the above embodiment, and the preparation method also includes S1111-S1114 and S111-S113 as well as a specific process for forming the well region 21, the first region 22 and the second region 31.

[0131] The difference from the preparation method of the above embodiment is that:

[0132] Continue to combine Figures 9 to 11 , Fig.15 , Optionally, S111, providing a first wafer structure, further comprising:

[0133] A third region 25 is formed on the first surface M1 of the first wafer structure 20 ; the third region 25 penetrates the first region 22 and a portion of the well region 21 , is of the second conductivity type, and has an ion concentration greater than that of the well region 21 .

[0134] Specifically, the third region 25 can be formed on the first surface M1 of the first wafer structure 20 by an ion implantation process. Exemplarily, if the semiconductor device is an N-type power device, the third region 25 is a P+ region, and the well region 21 is a P-well. If the semiconductor device is a P-type power device, the third region 25 is an N+ region, and the well region 21 is an N-well.

[0135] Optional, Fig.16 yes Fig.14 A detailed flow chart included in S111. Based on the above embodiments, combined with Figures 3 to 5 , Fig.14 and Fig.16 On the basis of the above embodiments, S111, providing a first wafer structure 20, may include:

[0136] S121 , forming a first trench 23 on the first surface M1 of the first wafer structure 20 ; the first trench 23 extends from the first surface M1 to the inside of the first wafer structure 20 ; the first trench 23 penetrates the first region 22 , the well region 21 and a portion of the first epitaxial layer 24 .

[0137] Specifically, the first trench 23 is formed on the first surface M1 of the first wafer structure 20 by an etching process.

[0138] S122 , forming a first insulating layer 41 inside the first trench 23 .

[0139] Specifically, the first insulating layer 41 is deposited inside the first trench 23 by atomic layer deposition (ALD) or the like, and the first insulating layer 41 inside the first trench 23 may be a gate oxide layer. The gate oxide layer may be a high-K material, which may improve the electron mobility at the interface of the gate 40 and reduce the on-resistance of the semiconductor device.

[0140] Optionally, based on the above embodiments, Figure 5 and Fig. 9 S120 , forming a gate 40 on the first surface M1 of the semiconductor body 10 may include: forming the gate 40 on a side of the first insulating layer 41 away from the inner wall of the first trench 23 .

[0141] Specifically, the gate 40 is deposited by low pressure chemical vapor deposition (LPCVD) or the like, and the material of the gate 40 may be polysilicon.

[0142] Optional, Fig.17 yes Fig.14 A detailed flow chart included in S112. Figures 3 to 5 , Figure 12 to Figure 14 ,and Fig.17 , S112, providing a second wafer structure 30, including:

[0143] S1121, forming a second epitaxial layer 33 on one side of the substrate 32; the second epitaxial layer 33 and the substrate 32 have the same conductivity type; the substrate 32 is of the first conductivity type.

[0144] Specifically, a substrate 32 is provided. The substrate 32 may be a silicon substrate 32 or a silicon carbide substrate 32. A second epitaxial layer 33 is formed on one side of the substrate 32. The material of the second epitaxial layer 33 may be silicon carbide.

[0145] S1122, forming a second region 31 extending from the surface of the second epitaxial layer 33 away from the substrate 32 to the second epitaxial layer 33; the second region 31 is of the second conductivity type; the ion concentration of the first epitaxial layer 24 is greater than or equal to the ion concentration of the second epitaxial layer 33.

[0146] Specifically, the second region 31 is formed on the side of the second epitaxial layer 33 away from the substrate 32. Exemplarily, if the material of the second region 31 is silicon carbide, silicon and carbon elements are provided during the growth of silicon carbide, silane and propane are used as reaction gas sources, and boron or aluminum is used as a doping element to form the second region 31 on the side of the second epitaxial layer 33 away from the substrate 32. If the semiconductor device is an N-type power device, the second region 31 may be a P+ type region.

[0147] The ion concentration of the first epitaxial layer 24 can be set to be different from the ion concentration of the second epitaxial layer 33 as required. For example, the ion concentration of the first epitaxial layer 24 can be set to be greater than or equal to the ion concentration of the second epitaxial layer 33. This arrangement facilitates adjusting the leakage size and the on-resistance size of the semiconductor device as required.

[0148] Fig.18 yes Fig.14 A detailed flow chart included in S112. Fig.19 FIG. 1 is a schematic diagram of an intermediate structure of a second wafer structure of another semiconductor device provided by an embodiment of the present invention. Figure 4 , Fig.18 and Fig.19 , which is different from the preparation methods of the above embodiments in that: Optionally, S112, providing a second wafer structure, including:

[0149] S11201, forming a second epitaxial layer 33 on one side of the substrate 32; the second epitaxial layer 33 and the substrate 32 have the same conductivity type; the substrate 32 is of the first conductivity type.

[0150] S11202 , forming a second trench 34 on a side of the second epitaxial layer 33 away from the substrate 32 ; the first trench 23 partially penetrates the second epitaxial layer 33 .

[0151] Specifically, the second trench 34 can be formed by etching. The second trench 34 is formed by etching on a side of the second epitaxial layer 33 away from the substrate 32 .

[0152] S11203 , forming a second region 31 on the sidewall and bottom of the second trench 34 ; the second region 31 is of the second conductivity type.

[0153] Specifically, the second region 31 can be formed by ion implantation on the third surface M3 of the second epitaxial layer 33, the side and bottom of the second trench 34. Exemplarily, if the semiconductor device is an N-type power device, the second region 31 is a P+ region, and the well region 21 is a P-well. If the semiconductor device is a P-type power device, the second region 31 is an N+ region, and the well region 21 is an N-well.

[0154] S11204 , forming a planarization layer 35 in the second trench 34 ; a side of the planarization layer 35 away from the substrate 32 is flush with the third surface M3 .

[0155] Specifically, a planarization layer 35 may be deposited inside the second trench 34 by atomic layer deposition (ALD) or the like. The planarization layer 35 inside the second trench 34 may be a non-conductive material layer, for example, an oxide layer. The side of the planarization layer 35 away from the substrate 32 is flush with the third surface M3, so that the second epitaxial layer 33, the second region 31, and the planarization layer 35 together form the third surface M3 of the second wafer structure 30.

[0156] Based on the above embodiments, this embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device proposed in any of the above embodiments, and the substrate is used to carry the semiconductor device. The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0157] Based on the above embodiments, the present embodiment provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device proposed in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board. The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0158] Based on the above embodiments, the present embodiment provides a vehicle, including a load and a power conversion circuit proposed in any of the above embodiments, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. The vehicle provided by the technical solution of the embodiment of the present invention includes the power conversion circuit proposed in any of the above embodiments, which has the same beneficial effects as the semiconductor device described in any of the embodiments of the present invention, and will not be repeated here.

[0159] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body comprising a first wafer structure and a second wafer structure, the first wafer structure comprising a first surface and a second surface arranged opposite to each other, the second wafer structure comprising a third surface and a fourth surface arranged opposite to each other, the second surface and the third surface being bonded to each other; The first wafer structure further includes a well region and a first region, the first region is arranged on the first surface, the well region is arranged on a side of the first region away from the first surface, the first surface is further provided with a first groove, and the first groove extends from the first surface to the first wafer structure; the first region is of the first conductivity type, and the well region is of the second conductivity type; The second wafer structure further includes a second region, the second region is disposed on the third surface, the second region is of the second conductivity type, and an orthographic projection of the second region on the fourth surface at least partially overlaps with an orthographic projection of the first groove on the fourth surface; The ion concentration of the second region is greater than the ion concentration of the well region; A gate, located in the first trench; A drain electrode, located on the fourth surface; The source is located on the first surface.

2. The semiconductor device according to claim 1, wherein: The first wafer structure comprises: a first epitaxial layer, the first epitaxial layer having the same conductivity type as the first region; The first trench penetrates the first region, the well region and a portion of the first epitaxial layer; the ion concentration of the first region is greater than the ion concentration of the first epitaxial layer.

3. The semiconductor device according to claim 1, wherein: The first wafer structure also includes a first insulating layer; The first insulating layer is disposed inside the first trench, and the gate is disposed on a side of the first insulating layer away from an inner wall of the first trench.

4. The semiconductor device according to claim 1, wherein: The first wafer structure further includes: The third region is arranged on the first surface, the third region runs through the first region and part of the well region, and the third region is of the second conductivity type; the ion concentration of the third region is greater than the ion concentration of the well region.

5. The semiconductor device according to claim 2, wherein: The second wafer structure further includes: A substrate, disposed on the fourth surface; a second epitaxial layer, arranged on a side of the substrate away from the fourth surface, the conductivity type of the second epitaxial layer being the same as the conductivity type of the substrate, the substrate being of the first conductivity type; the second region extending into the second epitaxial layer; The ion concentration of the first epitaxial layer is greater than or equal to the ion concentration of the second epitaxial layer.

6. The semiconductor device according to claim 5, characterized in that The second wafer structure further includes: a second groove, wherein the second groove is disposed on the third surface of the second wafer structure; The second trench penetrates a portion of the second epitaxial layer; The second region is located on the sidewall and bottom of the second trench; A planarization layer is disposed in the second groove, and a side of the planarization layer away from the substrate is flush with the third surface.

7. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided; the semiconductor body comprises a first wafer structure and a second wafer structure, the first wafer structure comprises a first surface and a second surface arranged oppositely, the second wafer structure comprises a third surface and a fourth surface arranged oppositely, the second surface and the third surface are bonded to each other; the first wafer structure further comprises a well region and a first area, the first area is arranged on the first surface, the well region is arranged on a side of the first area away from the first surface, the first surface is further provided with a first groove, the first groove extends from the first surface to the first wafer structure; the first area is of a first conductivity type, and the well region is of a second conductivity type; the second wafer structure further comprises a second area, the second area is arranged on the third surface, the second area is of the second conductivity type, and the orthographic projection of the second area on the fourth surface at least partially overlaps with the orthographic projection of the first groove on the fourth surface; the ion concentration of the second area is greater than the ion concentration of the well region; A gate is formed on the first surface of the semiconductor body; the gate is located in the first trench and extends from the first surface into the semiconductor body; forming a drain on the fourth surface of the semiconductor body; A source is formed on the first surface of the semiconductor body.

8. The method according to claim 7, characterized in that The semiconductor body is provided, comprising: A first wafer structure is provided; the first wafer structure comprises a first surface and a second surface which are arranged opposite to each other, the first wafer structure further comprises a well region and a first area, the first area is arranged on the first surface, the well region is arranged on a side of the first area away from the first surface, the first surface is further provided with a first groove, the first groove extends from the first surface to the first wafer structure; the first area is of a first conductivity type, and the well region is of a second conductivity type; Providing a second wafer structure; the second wafer structure comprises a third surface and a fourth surface which are arranged opposite to each other, the second wafer structure further comprises a second region, the second region is arranged on the third surface, and the second region is of the second conductivity type; The second surface of the first wafer structure and the third surface of the second wafer structure are bonded; an orthographic projection of the second region on the fourth surface at least partially overlaps with an orthographic projection of the first groove on the fourth surface.

9. The method according to claim 8, characterized in that The providing of a first wafer structure comprises: forming a first epitaxial layer on one side of the substrate; the first epitaxial layer has the same conductivity type as the first region; forming a well region on a side of the first epitaxial layer away from the substrate; forming a first region on a side of the well region away from the substrate; the ion concentration of the first region is greater than the ion concentration of the first epitaxial layer; The substrate is removed.

10. The method according to claim 9, characterized in that The providing of the first wafer structure further includes: A third region is formed on the first surface of the first wafer structure; the third region runs through the first region and a portion of the well region, the third region is of the second conductivity type, and the ion concentration of the third region is greater than the ion concentration of the well region.

11. The method according to claim 9, characterized in that After forming the first epitaxial layer on one side of the substrate, the method further includes: forming a first groove on the first surface of the first wafer structure; the first groove extends from the first surface to the inside of the first wafer structure; the first groove penetrates the first region, the well region and a portion of the first epitaxial layer; forming a first insulating layer inside the first trench; The forming of a gate on the first surface of the semiconductor body comprises: A gate is formed on a side of the first insulating layer away from an inner wall of the first trench.

12. The method according to claim 9, characterized in that The providing of the second wafer structure comprises: forming a second epitaxial layer on one side of the substrate; the second epitaxial layer has the same conductivity type as the substrate; the substrate is of the first conductivity type; A second region extending from a surface of the second epitaxial layer away from the substrate into the second epitaxial layer is formed, wherein the second region is of the second conductivity type; and an ion concentration of the first epitaxial layer is greater than or equal to an ion concentration of the second epitaxial layer.

13. The method according to claim 9, characterized in that The providing of the second wafer structure comprises: forming a second epitaxial layer on one side of the substrate; A second trench is formed on a side of the second epitaxial layer away from the substrate; the second trench penetrates a portion of the second epitaxial layer; The second region is formed on the sidewall and bottom of the second trench; the second region is of the second conductivity type; A planarization layer is formed in the second trench; a side of the planarization layer away from the substrate is flush with the third surface.

14. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to any one of claims 1 to 6, wherein the substrate is used for carrying the semiconductor device.

15. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.

16. A vehicle, characterized in that: It includes a load and the power conversion circuit as described in claim 15, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

Images