A semiconductor junction terminal structure and manufacturing method thereof

Abstract

The present invention discloses a semiconductor junction terminal structure and a manufacturing method thereof, belonging to a semiconductor device, a semiconductor junction terminal structure, including a substrate and an epitaxial layer region on the substrate, the epitaxial layer region including a terminal region, the terminal region including a P-JTE working region and a P+JTE working region, the P+JTE working region is within the P-JTE working region, the concentration of the P+JTE working region and the P-JTE working region differ by more than two orders of magnitude, the junction depth of the P+JTE working region changes with the change of the depth of the field limiting ring inside the field limiting ring group of the terminal region, the field limiting ring group of the terminal region is located inside the P-JTE region and the depth of the field limiting ring group of the terminal region is greater than the depth of the P+JTE region. In the present invention, the P+JTE region can alleviate the main junction electric field, the P-JTE region can alleviate the electric field strength of the P+JTE region and the P-JTE region itself, and due to the existence of the P+JTE, its P-JTE is not affected by the surface charge, which expands the process window of its P-JTE, and the difference in junction depth can improve the device reliability.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices and relates to a semiconductor junction terminal structure and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC) is one of the representatives of the third generation of semiconductor materials. It is a compound formed by the elements C and Si. Compared with traditional semiconductor material silicon, it has obvious advantages such as high critical breakdown electric field and high electron mobility. It is an excellent semiconductor material for manufacturing high-voltage, high-temperature, and radiation-resistant power semiconductor devices.

[0003] When the device is in the blocking state, the device mainly bears the voltage through the depletion region formed by the PN junction under reverse bias. When the internal electric field of the device reaches a certain level, it will be broken down. The electric field is often concentrated at the edge and corner of the PN junction. Because of the curvature effect, the electric field at the spherical junction and the cylindrical junction is often much stronger than the electric field strength of the planar junction. This makes the corner position more sensitive and easier to break down than the middle position, resulting in a decrease in the device's withstand voltage.

[0004] In order to solve the problem of low device reliability and withstand voltage caused by electric field concentration, terminal technology is introduced. Most of the terminal technologies reduce the electric field concentration of the main junction by expanding the depletion region of the main junction, and part of the electric field of the main junction is borne by the terminal structure. The part of the JTE terminal structure close to the main junction adopts high doping to reduce the main junction electric field, and the subsequent part adopts low concentration doping to reduce its own electric field strength, so as to alleviate the main junction electric field. However, the JTE structure has very high process requirements, because the surface charge will seriously affect its performance and cannot be mass-produced. And its electric field will also produce spikes at the main junction and the end of the terminal. FLR is equivalent to placing a small main junction near the main junction to share the voltage and electric field strength of the large main junction. When the number of rings of the FLR structure is too large, it is easy to fall into saturation, and its internal electric field is uneven, which requires high terminal area and low terminal efficiency. Other terminals also have the problem that the main junction electric field they share is not evenly distributed in the terminal area, and if the electric field cannot be evenly distributed inside the terminal, it will cause the device to break down prematurely at the terminal uneven electric field, and the reliability will be reduced. Therefore, it is necessary to develop a highly reliable terminal structure with uniform internal electric field. Summary of the invention

[0005] The purpose of the present invention is to provide a semiconductor junction terminal structure and a method for manufacturing the same, which solves the current problem of lacking a high-reliability terminal structure with uniform internal electric field.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A semiconductor junction terminal structure includes a substrate and an epitaxial layer region on the substrate, the epitaxial layer region includes a terminal region, the terminal region includes a P-JTE working region and a P+JTE working region, the P+JTE working region is within the P-JTE working region, the concentration of the P+JTE working region differs from that of the P-JTE working region by more than two orders of magnitude, the junction depth of the P+JTE working region changes with the depth of a field limiting ring inside a field limiting ring group in the terminal region, the field limiting ring group in the terminal region is located inside the P-JTE working region and the depth of the field limiting ring group in the terminal region is greater than the depth of the P+JTE working region.

[0008] In the present invention, the P+JTE working area can alleviate the main junction electric field, and the P-JTE working area can alleviate the electric field strength of the P+JTE working area and the P-JTE working area itself. In addition, due to the existence of the P+JTE, the P-JTE is not affected by the surface charge, thereby expanding the process window of the P-JTE, and batch production can be carried out in terms of process. The difference in junction depth can assist the field limiting ring to evenly distribute the internal electric field and improve the reliability of the device.

[0009] Since the length of the P+JTE working area is too long, the electric field shared by the P+JTE working area will have an electric field peak at the tail of the P+JTE working area, resulting in uneven electric field inside the terminal. The field limiting ring group can evenly distribute the electric field shared by the P+JTE working area in the entire P+JTE area, so that the entire P+JTE working area bears the electric field shared by the main junction, rather than the latter half bearing it alone, eliminating its electric field peak and averaging the electric field inside the entire terminal.

[0010] The purpose of the field limiting ring group inside the P-JTE working area is to alleviate the electric field concentration effect inside the P+JTE working area and averagely differentiate the electric field stress inside it.

[0011] Furthermore, the epitaxial layer region also includes a cell region and an equipotential ring, and the equipotential ring is connected to the terminal region and the cell region.

[0012] The cell region is the core functional region of semiconductor devices (such as power semiconductor devices such as VDMOS). It occupies the largest area in the device and undertakes the key task of realizing transistor characteristics. The equipotential ring is connected to the cell region to form a protective barrier. Under high voltage conditions, the equipotential ring can share part of the voltage, reduce the direct impact on the cell region, and protect the cell region from damage. The equipotential ring is a commonly used terminal structure in semiconductor devices. In semiconductor devices, due to the existence of edge effects, the electric field at the edge of the device is often concentrated. The equipotential ring effectively alleviates the problem of electric field concentration by setting a region with the same doping type as the cell region but deeper at the edge of the device, thereby improving the voltage resistance of the device.

[0013] Furthermore, the number of field limiting ring groups in the terminal region is greater than 2, and the average junction depth of the field limiting ring groups gradually becomes shallower, the first group of field limiting ring groups has the deepest average junction depth, and the last group of field limiting ring groups has the shallowest average junction depth;

[0014] The number of field limiting rings within each group of field limiting rings is greater than 3, and the field limiting ring knot depth within each group of field limiting rings changes from deep to shallow and then to deep. The knot depth of the last field limiting ring in each group of field limiting rings is shallower than the knot depth of the first field limiting ring in the group, the middle field limiting ring has the shallowest depth, and the first field limiting ring has the deepest depth.

[0015] The shallower average junction depth of the field limiting ring group can evenly distribute the voltage of the main junction to each field limiting ring group, and the voltage distributed to each field limiting ring group is further evenly distributed by different field limiting rings in the field limiting ring group, so that the electric field distribution inside the terminal becomes very even;

[0016] Furthermore, the terminal area also includes a termination field limiting ring group, which is located outside the P-JTE working area. The termination field limiting ring group includes multiple termination deep field limiting rings, and the depths of the multiple termination deep field limiting rings gradually decrease.

[0017] When the device is subjected to voltage, the terminal structure shares the main junction electric field, and the electric field is conducted backward along with the terminal structure. The field limiting ring structure inside it can make it evenly distributed in the terminal. However, once the terminal structure is too short, or the main junction electric field is raised too high, an electric field spike will be formed at the tail of the P-JTE working area. This electric field spike will greatly affect the reliability of the device, causing the device to break down prematurely and thus reduce the withstand voltage. Adding a termination field limiting ring group at the tail of the P-JTE working area will alleviate the electric field peak at the tail of the P-JTE working area and eliminate the electric field spike. The gradually shallower junction depth can further evenly distribute the electric field peak, thereby improving the withstand voltage and reliability of the device.

[0018] Furthermore, the lower right corner of the field limiting ring inside each field limiting ring group is a beveled angle.

[0019] The junction width of the field limiting rings inside the field limiting ring group is not uniform. Specifically, the lower right corner of the field limiting ring is a bevel angle, which is achieved through ion implantation of oxide layers of different thicknesses in the process. When the field limiting ring is subjected to voltage, its electric field concentration point is often located at the right sharp corner, and the breakdown point is also often located at the right sharp corner. Therefore, etching the right corner into a bevel angle can effectively alleviate the electric field concentration, distribute the electric field within the entire junction depth, and reduce the influence of the curvature effect on it, further uniformizing the electric field distribution.

[0020] Furthermore, the lower right corner of each terminating deep field limiting ring is a bevel angle, and the bevel angle of the terminating deep field limiting ring follows the field limiting ring inside the P-JTE working area.

[0021] Furthermore, the terminal region further includes a cut-off ring, and the cut-off ring is located at the end of the terminal region.

[0022] The cut-off ring plays an important role in the terminal area of ​​semiconductor devices, such as increasing the breakdown voltage, protecting the internal part of the device, reducing leakage current, preventing the formation of surface channels, and optimizing the terminal structure. These functions jointly improve the performance and reliability of semiconductor devices, allowing the devices to operate stably in various complex environments.

[0023] The method for manufacturing a semiconductor junction terminal structure comprises the following steps: performing P injection into an epitaxial layer, and then performing high-temperature annealing to diffuse P, wherein the P is P-type doping, i.e., adding a trivalent element into a semiconductor material to make it have P-type conductivity; the carriers in the P-type semiconductor are mainly holes, which are trivalent, forming a P-JTE working area, and then performing oxidation, applying photoresist, step-etching the oxide layer after photolithography, and performing injection into a P+JTE working area after removing the photoresist, and then removing the oxide layer, reoxidizing an oxide layer, applying glue, photolithography, opening holes, further etching the step oxide layer, and then performing ion injection, injecting a termination field limiting ring group together in this step, and performing high-temperature annealing together with the P+JTE working area after the injection is completed to form a terminal structure, wherein the step oxide layer can form a concentration gradient at the right corner position of the field limiting ring during high-temperature annealing, and a chamfer angle is formed after annealing.

[0024] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0025] 1. In a semiconductor junction terminal structure, the P+JTE working area can relieve the main junction electric field, and the P-JTE working area can relieve the electric field strength of the P+JTE working area and the P-JTE working area itself. Due to the existence of the P+JTE, the P-JTE is not affected by the surface charge, thus expanding the process window of the P-JTE, and batch production is possible in terms of process. The difference in junction depth can assist the field limiting ring to evenly distribute the internal electric field and improve the device reliability.

[0026] 2. In the present invention, when the field limiting ring is subjected to voltage, its electric field concentration point is often located at the right sharp corner position, and the breakdown point is also often located at the right sharp corner position, so etching the right corner into a chamfered angle can effectively alleviate the electric field concentration, make the electric field distributed within the entire junction depth range, and reduce the influence of the curvature effect on it, further uniform electric field distribution;

[0027] 3. The present invention adds a termination field limiting ring group at the tail of the P-JTE working area to alleviate the electric field peak at the tail of the P-JTE working area and eliminate its electric field spike, and the gradually shallower junction depth can further evenly distribute the electric field peak, thereby improving the withstand voltage and reliability of the device;

[0028] 4. The method for manufacturing a semiconductor junction terminal structure of the present invention forms the terminal structure by three ion implantations, which only requires adding a few more ion implantations to the traditional process, without the assistance of special processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative work, among which:

[0030] Figure 1 The cross-sectional view of etching the stepped oxide layer at the terminal portion of the device of the present invention

[0031] Figure 2 The cross-sectional view of etching the field limiting ring stepped oxide layer at the terminal portion of the device of the present invention

[0032] Figure 3 This is a cross-sectional view of the terminal of the device of the present invention

[0033] Figure 4 This is a cross-sectional view of the terminal of the second implementation mode of the present invention

[0034] Figure 5 This is a cross-sectional view of the terminal of the third implementation mode of the present invention

[0035] Figure 6 This is a cross-sectional view of the terminal of the fourth implementation mode of the present invention

[0036] Markings in the figure: 100-substrate, 101-epitaxial layer region, 201-equipotential ring, 300-termination deep field limiting ring, 301-P+JTE working region, 302-P-JTE working region, 303-cut-off ring, 400-deep field limiting ring, 401-first deeper field limiting ring, 402-shallow field limiting ring, 403-second deeper field limiting ring, 500-oxide layer, 001-cell region, 002-terminal region, 003-first field limiting ring group, 004-second field limiting ring group, 005-third field limiting ring group, 006-termination field limiting ring group. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0039] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0040] The features and performance of the present invention are further described in detail below in conjunction with the embodiments. Example 1

[0041] A preferred embodiment of the present invention provides an implementation method of a semiconductor junction terminal structure. The present invention provides a semiconductor junction terminal structure and a manufacturing method thereof. A semiconductor junction terminal structure includes a cell region 001, a terminal region 002, a substrate 100, an epitaxial layer region 101, a P-JTE working region 302 whose depth varies with a field limiting ring group, a P+JTE working region 301, a deep field limiting ring 400, a first deeper field limiting ring 401, a shallow field limiting ring 402, a second deeper field limiting ring 403, a termination deep field limiting ring 300, an equipotential ring 201 connected to the terminal region 002 cell region 001, and a first field limiting ring group 003 composed of multiple field limiting rings, a second field limiting ring group 004, a third field limiting ring group 005, a termination field limiting ring group 006, and a cut-off ring 303 at the end of the terminal.

[0042] The P+JTE working area 301 is within the P-JTE working area 302, and is specifically located below the contact surface above the epitaxial layer; the junction depth of the P+JTE working area 301 is not uniform, and its depth changes with the change of the depth of the field limiting ring inside the field limiting ring group. The multiple field limiting rings form a field limiting ring group, the number of field limiting ring groups is greater than 2, and the group average junction depth of the field limiting ring group should gradually become shallower, the average junction depth of the first field limiting ring group is the deepest, and the average junction depth of the field limiting ring group of the last group is the shallowest. One of the implementation methods of the present application is that the junction depth of the field limiting ring inside each field limiting ring group should change from deep to shallow and then to deep, and the junction depth of the last field limiting ring in each field limiting ring group should be shallower than the junction depth of the first field limiting ring in the field limiting ring group. The field limiting ring group should be located inside the P-JTE working area, and its depth should exceed the P+JTE working area. The junction widths of the field limiting rings within the field limiting ring group are not uniform. Specifically, the lower right corner of the field limiting ring is a bevel angle, which is achieved through ion implantation of oxide layers of different thicknesses in the process.

[0043] like Figure 1-6 As shown, the number of field limiting ring groups is greater than 2, for example, including a first field limiting ring group 003 consisting of multiple field limiting rings, a second field limiting ring group 004, and a third field limiting ring group 005.

[0044] like Figure 1 As shown, the P+JTE working area can be formed by etching oxide layers of different thicknesses in a stepped manner, then performing ion implantation, and finally performing high temperature annealing.

[0045] like Figure 2 As shown, 500 is an oxide layer. Through dry etching, a step is etched out, and then ions are implanted on its surface. The oxide layer will form a concentration gradient distribution at the right corner of the field limiting ring, and a bevel angle can be formed after high-temperature annealing. The P+JTE working area is annealed at high temperature together with the field limiting ring. The longer the annealing time, the smoother the edge and the better the electric field sharing effect.

[0046] The junction depth of the P+JTE structure of the present invention follows the deep and shallow field limiting rings, covering the surface layer of the P-JTE structure, so as to increase the process window of the P-JTE and assist the field limiting rings in sharing the electric field. The deep and shallow field limiting ring structure is located in the P+JTE structure, and the tail of the field limiting ring structure is injected with different photoresist thicknesses to achieve tail chamfering to avoid the problem of electric field concentration, so that the electric field of a single field limiting ring is smoother. The depth of the deep and shallow field limiting rings changes from large to small and then to large again to make it more uniform so that the shallower field limiting rings can share the electric field left by the deeper field limiting rings, so that the overall electric field distribution of the terminal is more uniform. Thereby reducing the electric field intensity and electric field stress at the main junction, the structure can achieve terminal electric field distribution and its smoothness and uniformity through multiple equal distribution of electric fields, greatly improving the reliability of the device, expanding its process window, increasing the breakdown voltage, and avoiding the terminal area from being broken down.

[0047] The ion implantation sequence in this embodiment is to first implant the P-JTE working area, then anneal once; then etch out the oxide layer step required for implanting P+JTE and then implant the P+JTE working area, remove the oxide layer and re-oxidize, and then etch out the step oxide layer required for implanting the field limiting ring and then implant it inside. The termination field limiting ring and the cut-off ring are also ion implanted at this time; the P+JTE working area and the field limiting ring group area are annealed together. At this time, the formation Figure 3 Terminal area 002 is shown. Example 2

[0048] Based on Example 1, different from Example 1, this embodiment provides a second implementation method of a semiconductor junction terminal structure: Figure 4 As shown, it is the second implementation method of the terminal. When the number of steps is small, the concentration gradient will increase. After annealing, the smoothness of the bevel angle is not enough and it will evolve into a field limiting ring of the lower right corner step type. This type of field limiting ring can also achieve the electric field concentrated on the right side of the field limiting ring. The field limiting ring is evenly distributed on the surface of the entire field limiting ring, reducing the electric field peak of a single ring and increasing the reliability between the rings. The number of steps is not specified, and the number is at least greater than 2. When there are too many steps, it will evolve into a smooth bevel angle. The depth change also follows the above method. The process steps of this embodiment are not changed, and the ion implantation sequence is not changed. Example 3

[0049] Based on Example 1, different from Example 1, this embodiment provides a third implementation method of a semiconductor junction terminal structure: Figure 5 As shown in FIG. 1 , the third implementation of the terminal is that the depth of the field limiting rings in the field limiting ring group in the terminal can be gradually reduced until the depth of the first field limiting ring of the next field limiting ring group increases, and the depth of the field limiting rings in the group also gradually decreases, and the average depth of the subsequent field limiting ring group is lower than the average depth of the previous field limiting ring group. Figure 5 The depths of the deep field limiting ring 400, the first deeper field limiting ring 401, the shallow field limiting ring 402, and the second deeper field limiting ring 403 shown are gradually reduced, so as to share the electric field of the first field limiting ring in the field limiting ring group as much as possible, and the electric field in the entire terminal is shared by multiple field limiting ring groups. Example 4

[0050] Based on Example 1, different from Example 1, this embodiment provides a fourth implementation method of a semiconductor junction terminal structure: Figure 6 As shown, it is the fourth implementation of the terminal. The field limiting ring group in the terminal is two field limiting rings, one deep and one shallow. The two field limiting rings form a group, and the average depth of each group of field limiting rings is gradually reduced.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions and improvements made by any technician familiar with the field within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A semiconductor junction termination structure, characterized in that: The invention comprises a substrate (100) and an epitaxial layer region (101) on the substrate (100); the epitaxial layer region (101) comprises a terminal region (002); the terminal region (002) comprises a P-JTE working region (302) and a P+JTE working region (301); the P+JTE working region (301) is within the P-JTE working region (302); the concentration of the P+JTE working region (301) differs from that of the P-JTE working region (302) by more than two orders of magnitude; the junction depth of the P+JTE working region (301) changes with the depth of the field limiting ring inside the field limiting ring group of the terminal region (002); the field limiting ring group of the terminal region (002) is located inside the P-JTE working region (302) and the depth of the field limiting ring group of the terminal region (002) is greater than the depth of the P+JTE working region (301).

2. A semiconductor junction termination structure according to claim 1, characterized in that: The epitaxial layer region (101) further comprises a cell region (001) and an equipotential ring (201), wherein the equipotential ring (201) is connected to the terminal region (002) and the cell region (001).

3. A semiconductor junction termination structure according to claim 1, characterized in that: The number of field limiting ring groups in the terminal region (002) is greater than 2, and the average junction depths of the field limiting ring groups gradually become shallower, the first group of field limiting ring groups has the deepest average junction depth, and the last group of field limiting ring groups has the shallowest average junction depth; The number of field limiting rings within each group of field limiting rings is greater than 3, and the field limiting ring knot depth within each group of field limiting rings changes from deep to shallow and then to deep. The knot depth of the last field limiting ring in each group of field limiting rings is shallower than the knot depth of the first field limiting ring in the group, the middle field limiting ring has the shallowest depth, and the first field limiting ring has the deepest depth.

4. A semiconductor junction termination structure according to claim 1, characterized in that: The terminal area (002) further comprises a termination field limiting ring group (006), the termination field limiting ring group (006) being located outside the P-JTE working area (302), and the termination field limiting ring group (006) comprising a plurality of termination deep field limiting rings (300) inside, the depths of the plurality of termination deep field limiting rings (300) gradually decreasing.

5. A semiconductor junction termination structure according to claim 3, characterized in that: The lower right corner of the field limiting ring inside each group of field limiting rings is shown as a bevel angle.

6. A semiconductor junction termination structure according to claim 4, characterized in that: The lower right corner of each terminating deep field limiting ring (300) is shown as a beveled corner.

7. A semiconductor junction termination structure according to claim 1, characterized in that: The terminal region (002) further includes a cut-off ring (303), and the cut-off ring (303) is located at the end of the terminal region (002).

8. A method for manufacturing a semiconductor junction terminal structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: P is injected into the epitaxial layer, and then high-temperature annealing is performed to diffuse P. The P is P-type doping, that is, a trivalent element is added to the semiconductor material to make it have P-type conductivity; the carriers in the P-type semiconductor are mainly holes, and these holes are trivalent, forming a P-JTE working area, and then oxidation is performed, photoresist is applied, and the oxide layer is step-etched after photolithography. After removing the photoresist, the P+JTE working area is injected, and then the oxide layer is removed, a layer of oxide layer is re-oxidized, the glue is applied, the photolithography is performed, holes are opened, and the step oxide layer is further etched, and then ions are implanted. The termination field limiting ring group is injected together in this step. After the injection is completed, it is annealed at high temperature together with the P+JTE working area to form a terminal structure. During the high-temperature annealing, the step oxide layer can form a concentration gradient at the right corner of the field limiting ring, and a bevel angle is formed after annealing.

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