Transistor, array substrate, display device and preparation method of array substrate

Abstract

The invention discloses a transistor, an array substrate, a display device and a preparation method of the array substrate, the transistor comprises an active layer and a grid electrode, and one of the active layer and the grid electrode is arranged around the other one. According to the transistor, one of the active layer and the grid electrode is arranged around the other one, so that the active layer and the grid electrode have a relatively sufficient opposite area, the outer surface of the grid electrode can be relatively sufficiently opposite to the active layer, the field effect of the grid electrode can be relatively sufficiently utilized, the current output capability of the transistor per unit area can be improved, and the power consumption of the transistor can be reduced. Therefore, the transistor can output large current, and the working performance of the transistor is improved.

Description

Technical Field

[0001] The present application belongs to the field of transistor technology, and in particular, relates to a transistor, an array substrate, a display device, and a method for manufacturing the array substrate. Background Art

[0002] Transistors are single components based on semiconductor materials. Transistors have multiple functions such as detection, rectification, amplification, switching, voltage regulation, and signal modulation. Transistors can be used for a variety of digital and analog functions. Transistors are widely used in various electrical appliances. For example, transistors can be used in display panels based on technologies such as organic light emitting diodes (OLED) and light emitting diodes (LED).

[0003] However, the performance of current transistors needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a transistor, an array substrate, a display device and a method for manufacturing the array substrate, aiming to increase the output current of the transistor.

[0005] An embodiment of a first aspect of the present application provides a transistor, comprising an active layer and a gate, wherein one of the active layer and the gate is arranged around the other.

[0006] According to an implementation of the first aspect of the present application, at least one of the active layer and the gate is multiple in number, and at least part of the active layer and at least part of the gate are alternately arranged around each other.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, there are multiple active layers, and active layers are arranged on the inner and outer sides of at least part of the gate, wherein the active layer located on the inner side of the gate is surrounded by the gate, and the active layer located on the outer side of the gate is arranged around the gate.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, in the active layers located on the inner and outer sides of the gate, the active layer on one side includes a P-type active layer, and the active layer on the other side includes an N-type active layer; or, the active layers located on the inner and outer sides of the gate both include a P-type active layer; or, the active layers located on the inner and outer sides of the gate both include an N-type active layer.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, there are multiple gates, and gates are arranged on the inner and outer sides of at least part of the active layer, wherein the gate located on the inner side of the active layer is surrounded by the active layer, and the gate located on the outer side of the active layer is arranged around the active layer.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, there are multiple active layers and multiple gates, at least part of the gates are arranged around the active layers, and / or at least part of the active layers are arranged around the gates.

[0011] According to any of the aforementioned implementations of the first aspect of the present application, the active layers and the gates are arranged alternately and surround each other.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, active layers are provided on the inner and outer sides of at least part of the gate, and among the active layers located on the inner and outer sides of the gate, the active layer on one side includes a P-type active layer, and the active layer on the other side includes an N-type active layer; or, the active layers located on the inner and outer sides of the gate both include a P-type active layer; or, the active layers located on the inner and outer sides of the gate both include an N-type active layer.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the active layer and the gate are extended and formed along a preset direction. Among the adjacent active layers and gates, one is an outer layer and the other is an inner layer. The outer layer is arranged around the inner layer and is tubular.

[0014] According to any of the aforementioned implementations of the first aspect of the present application, the transistor further includes a source and a drain disposed at two ends of the active layer in a preset direction.

[0015] According to any of the aforementioned embodiments of the first aspect of the present application, an extension dimension of the outer layer in a preset direction is smaller than an extension dimension of the inner layer in the preset direction.

[0016] According to any of the aforementioned embodiments of the first aspect of the present application, the transistor further includes an insulating layer arranged between the gate and the active layer.

[0017] According to any of the aforementioned embodiments of the first aspect of the present application, the insulating layer is disposed around at least a portion of the active layer, and / or the insulating layer is disposed around at least a portion of the gate.

[0018] An embodiment of a second aspect of the present application provides an array substrate, comprising a substrate and a transistor of any one of the above-mentioned embodiments arranged on one side of the substrate.

[0019] According to an implementation of the second aspect of the present application, there are multiple gates, and gates are arranged on the inner and outer sides of at least part of the active layer, wherein the gate located on the inner side of the active layer is surrounded by the active layer, and the gate located on the outer side of the active layer is arranged around the active layer.

[0020] According to any of the aforementioned embodiments of the second aspect of the present application, the array substrate includes a regulation voltage signal terminal and a control voltage signal terminal. Among the gates located on the inner and outer sides of the active layer, the gate on one side is connected to the regulation voltage signal terminal, and the gate on the other side is connected to the control voltage signal terminal.

[0021] An embodiment of a third aspect of the present application provides a display device, comprising an array substrate according to any one of the above embodiments.

[0022] An embodiment of a fourth aspect of the present application provides a method for preparing an array substrate, comprising:

[0023] Performing patterning on the substrate to be prepared to form a substrate, wherein a receiving groove is provided on the substrate;

[0024] A first conductor portion is formed in the receiving groove, wherein the first conductor portion includes a first conductor layer and a second conductor layer alternately stacked;

[0025] A second conductor portion is formed on the first conductor portion, wherein the second conductor portion includes a first conductor layer and a second conductor layer alternately stacked, the first conductor layer of the second conductor portion is connected to the first conductor layer of the first conductor portion to form a gate, the second conductor layer of the second conductor portion is connected to the second conductor layer of the first conductor portion to form an active layer, and one of the gate and the active layer is arranged around the other.

[0026] The fourth aspect of the present application also provides a method for preparing an array substrate, including:

[0027] The substrate to be prepared is subjected to patterning treatment to form a substrate, wherein a receiving groove is provided on the substrate, wherein the receiving groove has more than two first bottom walls and a second bottom wall provided between two adjacent first bottom walls along a preset direction, and the second bottom wall is located on a side of the first bottom wall away from an opening of the receiving groove;

[0028] A first conductor layer is formed in the receiving groove, two ends of the first conductor layer in a preset direction are connected to the first bottom wall, and the first conductor layer is spaced apart from the second bottom wall;

[0029] A second conductor layer is formed on the first conductor layer and surrounds the first conductor layer, wherein one of the first conductor layer and the second conductor layer is a gate and the other is an active layer.

[0030] In a transistor provided in an embodiment of the present application, the transistor includes an active layer and a gate. By arranging one of the active layer and the gate around the other, a relatively sufficient relative area is provided between the active layer and the gate, and the outer surface of the gate can be relatively fully opposite to the active layer, so that the field effect of the gate can be relatively fully utilized, so that the gate can better improve the conductivity of the active layer under the action of a control signal, thereby improving the current output capacity per unit area of ​​the transistor, so that the transistor can output a larger current, thereby improving the working performance of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a cross-sectional schematic diagram of a transistor provided in an embodiment of the present application;

[0033] Figure 2 yes Figure 1 Schematic diagram of the cross section at AA in the middle;

[0034] Figure 3 is a cross-sectional schematic diagram of a transistor provided in another embodiment of the present application;

[0035] Figure 4 yes Figure 3 Schematic diagram of the cross section at BB;

[0036] Figure 5 is a cross-sectional schematic diagram of a transistor provided in yet another embodiment of the present application;

[0037] Figure 6 yes Figure 5 Schematic diagram of the cross section at CC;

[0038] Figure 7 is a cross-sectional schematic diagram of a transistor provided in yet another embodiment of the present application;

[0039] Figure 8 yes Figure 7 Schematic diagram of the cross section at DD in the middle;

[0040] Fig. 9 is a cross-sectional schematic diagram of a transistor provided in yet another embodiment of the present application;

[0041] Fig.10 yes Fig. 9 Schematic diagram of the cross section at EE;

[0042] Fig.11 It is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0043] Figures 12 to 16 is a schematic diagram of a manufacturing process of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0044] Fig.17 is a schematic flow chart of a method for preparing an array substrate provided in another embodiment of the present application;

[0045] Figures 18 to 21It is a schematic diagram of a manufacturing process of a method for manufacturing an array substrate provided in another embodiment of the present application.

[0046] Description of reference numerals:

[0047] 1. array substrate; 1a. first conductor layer; 1b. second conductor layer; 11. first conductor portion; 12. second conductor portion;

[0048] 10. Transistor;

[0049] 100, active layer; 200, gate; 300, source; 400, drain; 500, insulating layer; 600, via; 700, insulating material;

[0050] 20, substrate; 21, receiving groove; 211, first bottom wall; 212, second bottom wall;

[0051] X - Preset direction. DETAILED DESCRIPTION

[0052] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0053] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0054] It should be understood that when describing the layers of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0055] Transistors are single components based on semiconductor materials. They have multiple functions such as detection, rectification, amplification, switching, voltage regulation, and signal modulation. Transistors can be used for a variety of digital and analog functions. Transistors are widely used in various electrical appliances. For example, transistors can be used in display panels based on technologies such as organic light emitting diodes (OLED) and light emitting diodes (LED). However, the performance of current transistors needs to be improved.

[0056] To solve the above problems, the embodiments of the present application provide a transistor, an array substrate, a display device and a method for preparing the array substrate. The following will describe various embodiments of the transistor, array substrate, display device and method for preparing the array substrate in conjunction with the accompanying drawings.

[0057] Figure 1 is a schematic diagram of the structure of a transistor 10 provided in an embodiment of the present application, Figure 2 is a cross-sectional schematic diagram of a transistor 10 provided in an embodiment of the present application, Figure 3 is a schematic structural diagram of a transistor 10 provided in another embodiment of the present application, Figure 4 FIG. 1 is a cross-sectional schematic diagram of a transistor 10 provided in another embodiment of the present application. The X direction in the figure is a preset direction.

[0058] like Figures 1 to 4 As shown, an embodiment of the first aspect of the present application provides a transistor 10, including an active layer 100 and a gate 200, wherein one of the active layer 100 and the gate 200 is arranged to surround the other.

[0059] In a transistor 10 provided in an embodiment of the present application, the transistor 10 includes an active layer 100 and a gate 200. By arranging one of the active layer 100 and the gate 200 around the other, a relatively sufficient relative area is provided between the active layer 100 and the gate 200, and the outer surface of the gate 200 can be relatively fully opposed to the active layer 100, so that the field effect of the gate 200 can be relatively fully utilized, so that the gate 200 can better improve the conductivity of the active layer 100 under the action of a control signal, thereby improving the current output capacity per unit area of ​​the transistor 10, so that the transistor 10 can output a larger current, thereby improving the working performance of the transistor 10.

[0060] In some embodiments of the present application, the transistor 10 may be a field effect transistor (FET).

[0061] Optionally, one of the active layer 100 and the gate 200 is disposed around the other, such as Figure 1 and Figure 2 As shown, it can mean that the gate 200 can be arranged around the active layer 100, and / or as Figure 3 and Figure 4 As shown, it may also mean that the active layer 100 may be disposed around the gate 200 .

[0062] Optionally, the active layer 100 and the gate 200 can be extended and formed along a preset direction X. Among the adjacent active layers 100 and gates 200, one is an outer layer and the other is an inner layer. The outer layer can be arranged around the inner layer, so that the active layer 100 and the gate 200 can be extended and arranged in the preset direction X more conveniently, which is convenient for the connection and relative position arrangement of the transistor 10 and other devices.

[0063] In some embodiments, the preset direction X may be a straight line direction or a curved line direction. In other embodiments, the preset direction X may include multiple straight line directions connected end to end, or the preset direction X may include multiple straight line directions and curved line directions connected end to end, thereby improving the convenience of arranging the active layer 100 and the gate 200, and further facilitating the connection and relative position arrangement of the transistor 10 with other devices.

[0064] In some optional embodiments, in the preset direction X, the cross-sectional shape of the active layer 100 and the gate 200 may be tubular or columnar, for example, the outer layer may be tubular, and the inner layer may be tubular or columnar. By reasonably setting the cross-sectional shape of the active layer 100 and the gate 200 in the preset direction X, the relative area between the active layer 100 and the gate 200 can be well adjusted, so that the output current of the transistor 10 can be well adjusted.

[0065] Optionally, when the outer layer is arranged around the inner layer, if the inner layer is an active layer 100 and the active layer 100 is not arranged around other devices, the cross-sectional shape of the active layer 100 in the preset direction X may be columnar, for example, the cross-sectional shape of the active layer 100 may be cylindrical or prism-shaped; or if the inner layer is a gate 200 and the gate 200 is not arranged around other devices, the cross-sectional shape of the gate 200 in the preset direction X may be columnar, for example, the cross-sectional shape of the gate 200 may be cylindrical or prism-shaped.

[0066] Optionally, when the outer layer is arranged around the inner layer, if the outer layer is a gate 200, the cross-sectional shape of the gate 200 in the preset direction X may be tubular, for example, the cross-sectional shape of the gate 200 may be a circular tube or a polygonal tube; or if the outer layer is an active layer 100, the cross-sectional shape of the active layer 100 in the preset direction X may be tubular, for example, the cross-sectional shape of the active layer 100 may be a circular tube or a polygonal tube.

[0067] In some optional embodiments, the transistor 10 further includes a source 300 and a drain 400 respectively disposed at two ends of the active layer 100 in a preset direction X. When the gate 200 receives a control signal, the gate 200 can change the conductive property of the active layer 100 so that the active layer 100 can conduct the electrical connection between the source 300 and the drain 400, thereby realizing the turning on of the transistor 10.

[0068] In some optional embodiments, the transistor 10 further includes an insulating layer 500 disposed between the gate 200 and the active layer 100. Optionally, the insulating layer 500 may also be disposed between the gate 200 and the source 300 and the drain 400.

[0069] Optionally, the insulating layer 500 is disposed around at least a portion of the active layer 100, and / or the insulating layer 500 is disposed around at least a portion of the gate 200. Optionally, the insulating layer 500 may also be disposed around at least a portion of the source 300 and the drain 400.

[0070] In these optional embodiments, by setting the insulating layer 500, the insulating layer 500 can better limit the direct contact between the active layer 100 and the gate 200, and the insulating layer 500 can also better limit the direct contact between the source 300 and the drain 400 and the gate 200, thereby better improving the working reliability of the transistor 10.

[0071] In some embodiments of the present application, there are various ways to connect the gate 200 , the source 300 , and the drain 400 to external devices.

[0072] In some embodiments, the gate 200 , the source 300 , and the drain 400 may be connected to external devices by way of vias 600 .

[0073] Optional, such as Figure 1 As shown, when the source 300 is surrounded by part of the active layer 100, part of the gate 200, part of the source 300 and / or part of the drain 400 located on the outside thereof, the source 300 can pass through part of the gate 200, part of the active layer 100, part of the source 300 and / or part of the drain 400 located on the outside thereof by means of a via 600, thereby realizing the connection between the source 300 and an external device.

[0074] Optional, such as Figure 1 As shown, when the drain 400 is surrounded by part of the active layer 100, part of the gate 200, part of the source 300 and / or part of the drain 400 located on the outside thereof, the drain 400 can pass through part of the gate 200, part of the active layer 100, part of the source 300 and / or part of the drain 400 located on the outside thereof by means of a via 600, thereby realizing the connection between the drain 400 and an external device.

[0075] Optional, such as Figure 3 As shown, when the gate 200 is surrounded by part of the active layer 100, part of the gate 200, part of the source 300 and / or part of the drain 400 located on the outside thereof, the gate 200 can pass through part of the active layer 100, part of the gate 200, part of the source 300 and / or part of the drain 400 located on the outside thereof by means of a via 600, thereby realizing the connection between the gate 200 and an external device.

[0076] In these optional embodiments, when the gate 200, the source 300 and the drain 400 are connected to external devices through the via 600, an insulating material 700 may be provided on the inner wall of the via 600, so that short circuit is less likely to occur inside the transistor 10, thereby improving the operating reliability of the transistor 10.

[0077] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a transistor 10 provided in yet another embodiment of the present application.

[0078] like Figure 5 As shown, in other embodiments, when one of the adjacent active layers 100 and gates 200 is an outer layer and the other is an inner layer, and the outer layer is arranged around the inner layer, the extension dimension of the outer layer in the preset direction X is smaller than the extension dimension of the inner layer in the preset direction X.

[0079] Optionally, an extension dimension of any active layer 100 in the preset direction X is greater than an extension dimension of a portion of the active layer 100 and / or a portion of the gate 200 located outside the active layer 100 in the preset direction X.

[0080] Optionally, an extension dimension of any gate 200 in the preset direction X is greater than an extension dimension of a portion of the active layer 100 and / or a portion of the gate 200 located outside the gate 200 in the preset direction X.

[0081] In these optional embodiments, by reasonably setting the extension dimensions of the active layer 100 and the gate 200 in the preset direction X, at least one end of the active layer 100 in the preset direction X can be exposed from the layer structure of the transistor 10 located outside it, for example, at least one end of the active layer 100 in the preset direction X can be exposed from part of the active layer 100 and / or part of the gate 200 located outside it, so as to facilitate the connection of the source 300 and the drain 400 at both ends of the active layer 100 in the preset direction X with external devices; and / or, at least one end of the gate 200 in the preset direction X can be exposed from the layer structure of the transistor 10 located outside it, for example, at least one end of the gate 200 in the preset direction X can be exposed from part of the active layer 100 and / or part of the gate 200 located outside it, so as to facilitate the connection of the gate 200 with external devices.

[0082] Optionally, the extension dimension of the insulating layer 500 in the preset direction X may be less than or equal to the extension dimension of the device surrounding it in the preset direction X. For example, the extension dimension of the insulating layer 500 in the preset direction X may be less than or equal to the extension dimension of the active layer 100 surrounding it in the preset direction X, so as to facilitate the connection between the source 300 and the drain 400 at both ends of the active layer 100 in the preset direction X and external devices; and / or, the extension dimension of the insulating layer 500 in the preset direction X may be less than or equal to the extension dimension of the gate 20 surrounding it in the preset direction X, so as to facilitate at least one end of the gate 200 in the preset direction X to be exposed from the layer structure of the transistor 10 located on the side away from the virtual extension line.

[0083] In some embodiments of the present application, there are multiple ways to set the number of active layers 100 and gates 200 in the transistor 10. In some optional embodiments, the number of active layers 100 and gates 200 may both be one. Optionally, the gate 200 may be arranged around the active layer 100, so that the active layer 100 can be better affected by the gate 200 on its peripheral side, thereby better improving the conductivity of the active layer 100, and improving the current output capacity per unit area of ​​the transistor 10, so that the transistor 10 can output a larger current. Or optionally, the active layer 100 may be arranged around the gate 200, so that the gate 200 can have a larger surface area on its peripheral side to be opposite to the active layer 100, and the outer surface of the gate 200 can be relatively fully opposite to the active layer 100, so that the field effect of the gate 200 can be relatively fully utilized, thereby improving the current output capacity per unit area of ​​the transistor 10.

[0084] like Figure 5 As shown, in other optional embodiments, at least one of the active layer 100 and the gate 200 is multiple in number, and at least part of the active layer 100 and at least part of the gate 200 are arranged in a colloid-surrounded manner with each other, so that the field effect of the gate 200 acting on both sides can be more fully utilized to improve the current output capacity per unit area of ​​the transistor 10, or both sides of the active layer 100 can be more fully affected by the gate 200 to further improve the conductive performance of the active layer 100.

[0085] Figure 6 yes Figure 5 Schematic diagram of the cross section at CC.

[0086] like Figure 5 and Figure 6 As shown, optionally, there are multiple active layers 100 , and active layers 100 are arranged on the inner and outer sides of at least part of the gate 200 , wherein the active layer 100 located on the inner side of the gate 200 is surrounded by the gate 200 , and the active layer 100 located on the outer side of the gate 200 is arranged around the gate 200 .

[0087] By reasonably setting the surrounding relationship between multiple active layers 100 and the gate 200, the gate 200 can be sandwiched between two adjacent active layers 100, and the gate 200 can have a good relative area with the active layers 100 on both sides, so that the field effect of the gate 200 acting on both sides can be more fully utilized, that is, the gate 200 can act on the active layers 100 on both sides at the same time under the action of the control signal to change the conductive properties of the active layer 100, which can better improve the current output capacity per unit area of ​​the transistor 10, so that the transistor 10 can output a larger current.

[0088] In some embodiments, in the active layer 100 located on the inner and outer sides of the gate 200, the source 300 connected to the active layer 100 on one side can be connected to the same device as the source 300 connected to the active layer 100 on the other side, and the drain 400 connected to the active layer 100 on one side can be connected to the same device as the drain 400 connected to the active layer 100 on the other side, so that when the gate 200 acts on the active layers 100 on both sides at the same time under the action of the control signal, the two groups of source 300 and drain 400 located on both sides of the gate 200 can output current to the same device at the same time, so as to better improve the current output by the transistor 10 to the device, thereby improving the working performance of the transistor 10.

[0089] Optionally, in the active layer 100 located on the inner side and the outer side of the gate 200, the source electrode 300 connected to the active layer 100 on one side can be located on the same side of the gate 200 in the preset direction X as the source electrode 300 connected to the active layer 100 on the other side, so that the source electrodes 300 connected to the active layers 100 on both sides are connected to the same device. Optionally, in the active layer 100 located on the inner side and the outer side of the gate 200, the drain electrode 400 connected to the active layer 100 on one side can be located on the same side of the gate 200 in the preset direction X as the drain electrode 400 connected to the active layer 100 on the other side, so that the drain electrodes 400 connected to the active layers 100 on both sides are connected to the same device.

[0090] Optionally, the active layer 100 located on the inner and outer sides of the gate 200 both include a P-type active layer; or, the active layer 100 located on the inner and outer sides of the gate 200 both include an N-type active layer, so that the gate 200 can, under the action of a control signal, conduct the electrical connection between the source 300 and the drain 400 on one side of the gate 200, and can also conduct the electrical connection between the source 300 and the drain 400 on the other side of the gate 200, so that the two groups of source 300 and drain 400 located on the inner and outer sides of the gate 200 can output current to the same device at the same time, thereby better improving the current output by the transistor 10 to the device. Under the action of the control signal, the gate 200 can disconnect the electrical connection between the source 300 and the drain 400 on one side of the gate 200, and can also disconnect the electrical connection between the source 300 and the drain 400 on the other side of the gate 200, so that the two groups of source 300 and drain 400 located on the inner and outer sides of the gate 200 can stop outputting current to the same device at the same time.

[0091] In other embodiments, in the active layer 100 located on the inner and outer sides of the gate 200, the source 300 connected to the active layer 100 on one side can be connected to different devices respectively with the source 300 connected to the active layer 100 on the other side, and / or, the drain 400 connected to the active layer 100 on one side can be connected to different devices respectively with the drain 400 connected to the active layer 100 on the other side, so that by transmitting a control signal to the gate 200, the transistor 10 can be simultaneously controlled to output current to different devices or stop outputting current, so as to better improve the control capability of the transistor 10, thereby improving the working performance of the transistor 10.

[0092] Optionally, in the active layer 100 located on the inner and outer sides of the gate 200, the active layer 100 on one side includes a P-type active layer, and the active layer 100 on the other side includes an N-type active layer, so that the gate 200 can, under the action of a control signal, turn on the electrical connection between the source 300 and the drain 400 on one side thereof to output current to an external device, and can disconnect the electrical connection between the source 300 and the drain 400 on the other side thereof to stop outputting current to an external device, that is, when the transistor 10 receives a certain control signal, it can deliver current to one connected device while stopping delivering current to another connected device, so as to better improve the control capability of the transistor 10, thereby improving the operating performance of the transistor 10.

[0093] Alternatively, the active layers 100 located on the inner and outer sides of the gate 200 both include P-type active layers; or, the active layers 100 located on the inner and outer sides of the gate 200 both include N-type active layers, so that the gate 200, under the action of a control signal, can simultaneously conduct the electrical connection between the source 300 and the drain 400 on one side of the gate 200 and the electrical connection between the source 300 and the drain 400 on the other side of the gate 200, so that the two groups of source 300 and drain 400 located on the inner and outer sides of the gate 200 can output current to different devices at the same time. Under the action of the control signal, the gate 200 can disconnect the electrical connection between the source 300 and the drain 400 on one side of the gate 200, and can also disconnect the electrical connection between the source 300 and the drain 400 on the other side of the gate 200, so that the two groups of source 300 and drain 400 located on the inner and outer sides of the gate 200 can stop outputting current to different devices at the same time.

[0094] Figure 7 is a cross-sectional schematic diagram of a transistor 10 provided in yet another embodiment of the present application, Figure 8 yes Figure 7 Schematic diagram of the cross section at DD in the middle.

[0095] like Figure 7 and Figure 8 As shown, optionally, there are multiple gates 200, and gates 200 are arranged on the inner and outer sides of at least part of the active layer 100, wherein the gate 200 located on the inner side of the active layer 100 is surrounded by the active layer 100, and the gate 200 located on the outer side of the active layer 100 is arranged around the active layer 100.

[0096] By reasonably arranging the surrounding relationship between multiple gates 200 and the active layer 100, the active layer 100 can be sandwiched between two adjacent gates 200, both sides of the active layer 100 can be opposite to the gates 200, and can be affected by the two gates 200 at the same time to better change its own conductivity, so that the thickness of the active layer 100 in the radial direction of the virtual extension line can be more fully utilized for conduction.

[0097] In some embodiments, the gates 200 located on the inner and outer sides of the active layer 100 may be connected to the same control signal terminal. For example, the gates 200 located on the inner and outer sides of the active layer 100 may be connected to the control voltage signal terminal to receive the control signal together, so that the gates 200 on both sides of the active layer 100 can act on the middle active layer 100 together under the action of the control signal, so that the active layer 100 can have a relatively sufficient thickness for conduction, thereby better improving the conductivity of the active layer 100, and further enabling the transistor 10 to output a larger current.

[0098] In other embodiments, the gates 200 located on the inner and outer sides of the active layer 100 may be connected to different control signal terminals, respectively. For example, in the gates 200 located on the inner and outer sides of the active layer 100, the gate 200 on one side may be connected to the control voltage signal terminal to receive the control signal, and the gate 200 on the other side may be connected to the control voltage signal terminal to receive the control signal. Optionally, the control signal may be a fixed voltage to control the voltage of the control signal, so that the conductivity of the active layer 100 can be modulated under the joint action of the gates 200 on both sides thereof, which can better improve the controllability of the conductivity of the active layer 100, thereby improving the working reliability of the transistor 10.

[0099] Fig. 9 is a cross-sectional schematic diagram of a transistor 10 provided in another embodiment of the present application, Fig.10 yes Fig. 9 Schematic diagram of the cross section at EE.

[0100] like Fig. 9 and Fig.10 As shown, optionally, there are multiple active layers 100 and multiple gates 200 , and at least part of the gates 200 are arranged around at least part of the active layer 100 , and / or at least part of the active layer 100 is arranged around at least part of the gates 200 .

[0101] Optionally, the active layer 100 and the gate 200 are alternately arranged to surround each other.

[0102] In these optional embodiments, when the number of active layers 100 and the number of gates 200 are both multiple, the transistor 10 may include multiple mutually nested layer structures. For example, in the aforementioned embodiment, a gate 200 surrounds an active layer 100 as a first structure, an active layer 100 surrounds a gate 200 as a second structure, an active layer 100 is arranged on the inner and outer sides of a gate 200 as a third structure, and an active layer 100 is arranged on the inner and outer sides of an active layer 100 as a fourth structure. The transistor 10 may include multiple mutually nested first structures, second structures, third structures and / or fourth structures, so that the transistor 10 can have the beneficial effects that each structure in the aforementioned embodiments can have, which will not be repeated here, thereby being able to better improve the current output capability, controllability and working reliability of the transistor 10.

[0103] An embodiment of a second aspect of the present application provides an array substrate, comprising a substrate and a transistor 10 of any one of the above-mentioned embodiments arranged on one side of the substrate.

[0104] In some optional embodiments, when there are multiple gates 200, the gates 200 are arranged on the inner and outer sides of at least part of the active layer 100, and the gates 200 located on the inner side of the active layer 100 are surrounded by the active layer 100, and the gates 200 located on the outer side of the active layer 100 are arranged around the active layer 100, the array substrate may include a regulation voltage signal terminal and a control voltage signal terminal, and among the gates located on the inner and outer sides of the active layer 100, the gates 200 on one side are connected to the regulation voltage signal terminal, and the gates 200 on the other side are connected to the control voltage signal terminal.

[0105] In this embodiment, among the gates 200 located on the inner and outer sides of the active layer 100, the gate 200 on one side can be connected to the control voltage signal terminal to receive the control signal, and the gate 200 on the other side can be connected to the regulation voltage signal terminal to receive the regulation signal. Optionally, the regulation signal can be a fixed voltage to regulate the voltage of the control signal, so that the conductivity of the active layer 100 can be modulated under the joint action of the gates 200 on both sides thereof, which can better improve the controllability of the conductivity of the active layer 100, thereby improving the working reliability of the transistor 10.

[0106] The embodiment of the third aspect of the present application provides a display device, including the array substrate of any of the above-mentioned embodiments. Since the display device provided by the embodiment of the third aspect of the present application includes the array substrate of any of the above-mentioned second aspects, the display device provided by the embodiment of the third aspect of the present application has the beneficial effects of the array substrate of any of the above-mentioned second aspects, which will not be described in detail here.

[0107] The display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0108] In addition, since the display device provided in the third aspect embodiment of the present application includes the transistor 10 of any embodiment of the first aspect above, when the display device has a larger pixel density unit (Pixels Per Inch, PPI), the transistor 10 can provide a larger current, thereby improving the display reliability of the display device.

[0109] The fourth aspect of the present application provides a method for preparing an array substrate 1. The array substrate 1 may be any array substrate provided by any of the second aspect embodiments described above. Figures 12 to 16 Also see Fig.11 As shown, Fig.14 yes Fig.13 The cross-sectional diagram at FF in the middle, Fig.16 yes Fig.15 The cross-sectional schematic diagram at GG in the figure, the preparation method comprises:

[0110] Step S01: Fig.12 As shown, a substrate 20 to be prepared is patterned to form a substrate 20 , and a receiving groove 21 is provided on the substrate 20 .

[0111] Step S02: Fig.13 and Fig.14 As shown, a first conductor portion 11 is formed in the receiving groove 21 , and the first conductor portion 11 includes first conductor layers 1 a and second conductor layers 1 b that are alternately stacked.

[0112] Step S03: Fig.15 and Fig.16 As shown, a second conductor portion 12 is formed on the first conductor portion 11, wherein the second conductor portion 12 includes a first conductor layer 1a and a second conductor layer 1b that are alternately stacked, the first conductor layer 1a of the second conductor portion 12 is connected to the first conductor layer 1a of the first conductor portion 11 to form a gate 200, the second conductor layer 1b of the second conductor portion 12 is connected to the second conductor layer 1b of the first conductor portion 11 to form an active layer 100, and one of the gate 200 and the active layer 100 is arranged to surround the other.

[0113] Optionally, an insulating layer 500 may be further disposed between adjacent active layers 100 and gates 200 .

[0114] Optionally, one of the gate 200 and the active layer 100 is disposed around the other, which may refer to Fig.15and Fig.16 The gate 200 shown may be disposed around the active layer 100 , and / or, it may also mean that the active layer 100 may be disposed around the gate 200 .

[0115] The fourth aspect of the present application also provides a method for preparing an array substrate 1. The array substrate 1 may be any array substrate provided by any of the second aspect embodiments described above. Figures 18 to 20 Also see Fig.17 As shown, Fig.21 yes Fig. 20 The cross-sectional schematic diagram at HH in FIG. 1 , the preparation method comprises:

[0116] Step S01: Fig.18 As shown, the substrate 20 to be prepared is patterned to form the substrate 20, and a receiving groove 21 is provided on the substrate 20. The receiving groove 21 has more than two first bottom walls 211 and a second bottom wall 212 arranged between two adjacent first bottom walls 211 along a preset direction, and the second bottom wall 212 is located on the side of the first bottom wall 211 away from the opening of the receiving groove 21.

[0117] Step S02: Fig.19 As shown, a first conductor layer 1 a is formed in the receiving groove 21 , two ends of the first conductor layer 1 a in a preset direction are connected to the first bottom wall 211 , and the first conductor layer 1 a is spaced apart from the second bottom wall 212 .

[0118] Step S03: Fig. 20 and Fig.21 As shown, a second conductor layer 1 b is formed on the first conductor layer 1 a and surrounds the first conductor layer 1 a , wherein one of the first conductor layer 1 a and the second conductor layer 1 b is a gate 200 and the other is an active layer 100 .

[0119] Optionally, an insulating layer 500 may be further disposed between adjacent active layers 100 and gates 200 .

[0120] Optionally, there are various methods for forming the second conductor layer 1b surrounding the first conductor layer 1a on the first conductor layer 1a. For example, the second conductor layer 1b may be formed on the first conductor layer 1a by deposition.

[0121] Optionally, by reasonably setting the interval between the first bottom wall 211 and the second bottom wall 212, for example, by setting a larger interval between the first bottom wall 211 and the second bottom wall 212, so that there is a larger spacing between the first conductor layer 1a and the second bottom wall 212, it is convenient to form a portion of the second conductor layer 1b on the side of the first conductor layer 1a facing the second bottom wall 212, thereby facilitating the formation of the second conductor layer 1b arranged around the first conductor layer 1a.

[0122] According to the embodiments of the present application as above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A transistor, characterized in that: The invention comprises an active layer and a gate, wherein one of the active layer and the gate is arranged around the other. 2 . The transistor according to claim 1 , wherein at least one of the active layer and the gate is provided in plural numbers, and at least part of the active layer and at least part of the gate are arranged alternately and surrounding each other.

3. The transistor according to claim 2, characterized in that There are multiple active layers, and at least part of the gates are provided with the active layers on the inner side and the outer side. The active layer located inside the gate is surrounded by the gate, and the active layer located outside the gate is surrounded by the gate; Preferably, in the active layers located on the inner and outer sides of the gate, the active layer on one side includes a P-type active layer, and the active layer on the other side includes an N-type active layer; or, the active layers located on the inner and outer sides of the gate both include a P-type active layer; or, the active layers located on the inner and outer sides of the gate both include an N-type active layer.

4. The transistor according to claim 2, characterized in that There are multiple gates, and at least some of the active layers are provided with the gates on the inner side and the outer side. The gate located inside the active layer is surrounded by the active layer, and the gate located outside the active layer is surrounded by the active layer.

5. The transistor according to claim 2, characterized in that There are a plurality of active layers and a plurality of gates, at least some of the gates are arranged around the active layers, and / or at least some of the active layers are arranged around the gates; Preferably, the active layer and the gate are arranged alternately and surrounding each other; Preferably, the active layer is provided on the inner side and the outer side of at least part of the gate, and among the active layers located on the inner side and the outer side of the gate, the active layer on one side includes a P-type active layer, and the active layer on the other side includes an N-type active layer; or, the active layers located on the inner side and the outer side of the gate both include a P-type active layer; or, the active layers located on the inner side and the outer side of the gate both include an N-type active layer.

6. The transistor according to claim 1, characterized in that The active layer and the gate are extended and formed along a preset direction, and one of the adjacent active layer and the gate is an outer layer and the other is an inner layer, the outer layer is arranged around the inner layer, and the outer layer is tubular; Preferably, the transistor further comprises a source electrode and a drain electrode respectively arranged at two ends of the active layer in the preset direction; Preferably, the extension dimension of the outer layer in the preset direction is smaller than the extension dimension of the inner layer in the preset direction; Preferably, the transistor further comprises an insulating layer disposed between the gate and the active layer; Preferably, the insulating layer is disposed around at least a portion of the active layer, and / or the insulating layer is disposed around at least a portion of the gate.

7. An array substrate, characterized in that: A transistor comprising a substrate and a transistor according to any one of claims 1 to 6 arranged on one side of the substrate; Preferably, there are multiple gates, and the gates are disposed on the inner side and the outer side of at least part of the active layer, wherein the gate located on the inner side of the active layer is surrounded by the active layer, and the gate located on the outer side of the active layer is disposed around the active layer; Preferably, the array substrate includes a regulation voltage signal terminal and a control voltage signal terminal. Among the gates located on the inner and outer sides of the active layer, the gate on one side is connected to the regulation voltage signal terminal, and the gate on the other side is connected to the control voltage signal terminal.

8. A display device, characterized in that: Comprising the array substrate as claimed in claim 7.

9. A method for preparing an array substrate, characterized in that: include: Performing patterning on a substrate to be prepared to form a substrate, wherein a receiving groove is provided on the substrate; A first conductor portion is formed in the receiving groove, wherein the first conductor portion includes a first conductor layer and a second conductor layer alternately stacked; A second conductor portion is formed on the first conductor portion, wherein the second conductor portion includes first conductor layers and second conductor layers that are alternately stacked, the first conductor layer of the second conductor portion is connected to the first conductor layer of the first conductor portion to form a gate, the second conductor layer of the second conductor portion is connected to the second conductor layer of the first conductor portion to form an active layer, and one of the gate and the active layer is arranged to surround the other.

10. A method for preparing an array substrate, characterized in that: include: Performing patterning on a substrate to be prepared to form a substrate, wherein the substrate is provided with a receiving groove, the receiving groove having more than two first bottom walls and a second bottom wall provided between two adjacent first bottom walls along a preset direction, and the second bottom wall is located on a side of the first bottom wall away from an opening of the receiving groove; A first conductor layer is formed in the containing groove, wherein two ends of the first conductor layer in a preset direction are connected to the first bottom wall, and the first conductor layer is spaced apart from the second bottom wall; A second conductor layer is formed on the first conductor layer and surrounds the first conductor layer, wherein one of the first conductor layer and the second conductor layer is a gate and the other is an active layer.

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