Cascaded GaN power device

Abstract

The invention discloses a cascaded GaN power device, and relates to the technical field of semiconductors. The cascaded GaN power device comprises a GaN device, a Si MOS (Metal Oxide Semiconductor) tube and a resistor, the source electrode of the GaN device is connected with the drain electrode of the Si MOS tube; the grid electrode of the GaN device is connected with one end of the resistor; the other end of the resistor is connected with the source electrode of the Si MOS tube; the drain electrode of the GaN device is used as the drain electrode of the cascaded GaN power device; the grid electrode of the Si MOS tube is used as the grid electrode of the cascaded GaN power device; and the source electrode of the Si MOS tube is used as the source electrode of the cascaded GaN power device. The structure is simple, and the EMI characteristic can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a cascaded GaN power device. Background Art

[0002] GaN power devices, thanks to the excellent properties of the material, have great advantages in high temperature, high voltage and high frequency applications. The main advantages of GaN power devices are high switching frequency and low switching loss. The former can increase the power density of the module to reduce the volume, and the latter can improve the efficiency of the module.

[0003] GaN power devices are divided into two types: enhancement type and depletion type. When used in circuits, enhancement type devices are required. At present, there are two ways to implement enhancement type GaN power devices. One is a GaN device with a p-GaN structure, which is itself an enhancement type; the other is a cascade power device. In a cascade power device, the Si MOS tube controls the opening and closing of the GaN device. When the Si MOS tube is turned on, the gate voltage of the GaN device quickly drops below the threshold voltage, and the channel of the GaN device is turned on, and the entire cascade power device begins to turn on. When the Si MOS tube is turned off, the gate voltage of the GaN device exceeds its threshold voltage, and the channel of the GaN device is turned off, and the entire cascade power device begins to turn off. The switch of the GaN device is subject to the opening of the SiMOS tube, and its opening and closing time is difficult to control, and the electromagnetic interference (EMI) characteristics are poor. Therefore, how to design a simple cascade GaN power device with improved EMI characteristics is crucial. Summary of the invention

[0004] The purpose of the present application is to provide a cascaded GaN power device with a simple structure and improved EMI characteristics.

[0005] To achieve the above objectives, this application provides the following solutions: The present application provides a cascaded GaN power device, comprising: a GaN device, a Si MOS tube and a resistor; The source of the GaN device is connected to the drain of the Si MOS tube; the gate of the GaN device is connected to one end of the resistor; the other end of the resistor is connected to the source of the Si MOS tube; the drain of the GaN device serves as the drain of the cascaded GaN power device; the gate of the Si MOS tube serves as the gate of the cascaded GaN power device; and the source of the Si MOS tube serves as the source of the cascaded GaN power device.

[0006] Optionally, the GaN device comprises: a substrate, a source, a gate, a drain, a passivation layer and an epitaxial structure; the epitaxial structure comprises: a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer epitaxially grown sequentially from bottom to top on the substrate; A source groove is provided at one end of the passivation layer; the source groove extends downward from the top surface of one end of the passivation layer to the GaN channel layer; the source electrode is provided in the source groove, and the source electrode is connected to the two-dimensional free electron gas formed inside the GaN channel layer; A drain groove is provided at the other end of the passivation layer; the drain groove extends downward from the top surface of the other end of the passivation layer into the GaN channel layer; the drain is provided in the drain groove, and the drain is connected to the two-dimensional free electron gas formed inside the GaN channel layer; The gate is arranged on the top surface of the passivation layer and is close to the source electrode and spaced apart from the source electrode.

[0007] Optionally, the GaN device is a depletion-mode GaN device.

[0008] Optionally, the passivation layer is obtained by depositing SiO2, SiN or Al2O3 by PECVD, LPCVD or ALD.

[0009] Optionally, the resistor is formed by a two-dimensional free electron gas formed inside the GaN channel layer.

[0010] Optionally, the resistance of the resistor is 8 ohms.

[0011] Optionally, the cascade-type GaN power device further comprises: a resistance electrode; The resistor electrode is arranged on the GaN device; the resistor is connected to the resistor electrode; and the resistor electrode is connected to the source of the Si MOS tube.

[0012] Optionally, the source, the gate and the drain are all manufactured using a semiconductor process.

[0013] Optionally, the semiconductor process includes: photolithography, sputtering and etching.

[0014] Optionally, the epitaxial structure is obtained by epitaxial growth in a MOCVD device.

[0015] According to the specific embodiments provided in this application, this application has the following technical effects: The present application provides a cascaded GaN power device, which includes: a GaN device, a SiMOS tube and a resistor; the source of the GaN device is connected to the drain of the Si MOS tube; the gate of the GaN device is connected to one end of the resistor; the other end of the resistor is connected to the source of the Si MOS tube; the drain of the GaN device serves as the drain of the cascaded GaN power device; the gate of the SiMOS tube serves as the gate of the cascaded GaN power device; and the source of the Si MOS tube serves as the source of the cascaded GaN power device. Since the present application only adds one resistor to the cascade structure of the GaN device and the Si MOS tube, the structure of the GaN power device of the present application is simple; and due to the existence of the resistor, the turn-on time of the GaN device can be slowed down, thereby improving the EMI characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is the circuit structure diagram corresponding to the common source and common gate structure; Figure 2 This is the circuit structure diagram corresponding to the cascaded GaN power device; Figure 3 A top view of a GaN device; Figure 4 It is a top view of the GaN device along the dotted line a as the cutting line; Figure 5 It is a cross-sectional view corresponding to the GaN device after being cut along the dotted line a; Figure 6 It is a top view of the GaN device along the dotted line b as the cutting line; Figure 7 The corresponding cross-sectional view of the GaN device is cut along the dotted line b; Figure 8 It is a top view of the GaN device along the dotted line c as the cutting line; Fig. 9 The corresponding cross-sectional view of the GaN device is cut along the dotted line c.

[0018] Reference numerals: GaN device-1, Si MOS tube-2, gate of Si MOS tube-G1, source of Si MOS tube-S1, drain of SiMOS tube-D1, gate of GaN device-G2, source of GaN device-S2, drain of GaN device-D2, resistor-R. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In practical applications, cascade power devices use Si MOS tubes to control the switch of depletion-mode GaN devices to achieve enhancement mode. In this cascade structure, the source of the Si MOS tube is connected to the gate of the depletion-mode GaN device, and the drain of the Si MOS tube is connected to the source of the depletion-mode GaN device, so it is also called a common source and common gate structure. Figure 1 As shown in the figure, since the switch of GaN device is restricted by the opening of Si MOS tube, its opening and closing time is difficult to control and the EMI characteristics are poor.

[0021] In order to improve the EMI characteristics, it is necessary to make the GaN device turn on slower. Based on this, the present application proposes a new type of cascaded GaN power device. During the device manufacturing process, an AlGaN / GaN heterojunction is used to connect a resistor in series to the gate of the depletion-mode GaN device. When cascaded with the Si MOS tube, the gate of the depletion-mode GaN device is cascaded with the source of the Si MOS tube through this series resistor. Due to the existence of the resistor, the turn-on time of the GaN device is slowed down and the EMI characteristics are improved. Compared with other EMI improvement cascade devices, the present application is simpler in structure and only requires one resistor to be implemented without adding other components. Therefore, the area utilization rate of subsequent GaN chips is higher and it has more mass production value. The GaN chip is obtained by integrating GaN devices, Si MOS tubes and resistors.

[0022] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0023] like Figure 2 As shown, an embodiment of the present application provides a cascade-type GaN power device, including: a GaN device 1, a SiMOS tube 2 and a resistor R.

[0024] The source S2 of the GaN device is connected to the drain D1 of the Si MOS tube; the gate G2 of the GaN device is connected to one end of the resistor R; the other end of the resistor R is connected to the source S1 of the Si MOS tube; the drain D2 of the GaN device serves as the drain of the cascaded GaN power device; the gate G1 of the Si MOS tube serves as the gate of the cascaded GaN power device; and the source S1 of the Si MOS tube serves as the source of the cascaded GaN power device.

[0025] The GaN device includes: a substrate, a source, a gate, a drain, a passivation layer and an epitaxial structure; the epitaxial structure includes: a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer epitaxially grown from bottom to top on the substrate. The epitaxial structure is obtained by epitaxial growth in an MOCVD device.

[0026] A source groove is provided at one end of the passivation layer; the source groove extends downward from the top surface of one end of the passivation layer into the GaN channel layer; the source is provided in the source groove, and the source is connected to the two-dimensional free electron gas formed inside the GaN channel layer.

[0027] A drain groove is provided at the other end of the passivation layer; the drain groove extends downward from the top surface of the other end of the passivation layer into the GaN channel layer; the drain is provided in the drain groove, and the drain is connected to the two-dimensional free electron gas formed inside the GaN channel layer.

[0028] The gate is arranged on the top surface of the passivation layer and is close to the source electrode and spaced apart from the source electrode.

[0029] The source, gate and drain are all manufactured by using semiconductor processes, including photolithography, sputtering and etching.

[0030] In one embodiment, the GaN device 1 is a depletion-mode GaN device. The passivation layer is obtained by depositing SiO2, SiN or Al2O3 by PECVD, LPCVD or ALD. The resistor is formed by the two-dimensional free electron gas formed inside the GaN channel layer. The resistance value of the resistor R is 8 ohms.

[0031] In one embodiment, the cascade-type GaN power device further includes: a resistor electrode.

[0032] The resistance electrode is arranged on the GaN device 1; the resistor R is connected to the resistance electrode; and the resistance electrode is connected to the source S1 of the Si MOS tube.

[0033] Figure 3It is a top view of the GaN device mentioned in this application. The gate G2 of the GaN device is connected to the gate finger on the GaN chip through the gate lead. The resistor R is a resistor formed by the AlGaN / GaN, i.e., AlGaN barrier layer and the two-dimensional electron gas under the GaN channel layer. The resistor electrode (R electrode) is also made on the GaN device. When it is cascaded with the Si MOS tube later, the R electrode is directly connected to the source of the Si MOS tube. Figure 3 The area circled by the dotted line is the area where the resistor is located. Because the resistor R is composed of the two-dimensional electron gas formed by the heterojunction of the AlGaN barrier layer and the GaN channel layer, the three areas of the resistor R, the R electrode, and the gate G2 of the GaN device are non-injection areas. Except for these three areas, the other areas in the dotted line box are injection areas. The injection area refers to the use of ion implantation to destroy the two-dimensional electron gas below, so that the area becomes an insulating area.

[0034] To further illustrate the structure of the GaN device of the present application, a top view and a cross-sectional view of each region of the GaN device are analyzed. Figure 4 It is a top view along the dotted line a as the cutting line. When the dotted line a is the cutting line, the source finger, gate finger and drain finger corresponding to the GaN device in the GaN chip are cut. Figure 5 It is the cross-sectional view corresponding to the dotted line a, which includes the substrate, GaN buffer layer, GaN channel layer and AlGaN barrier layer from bottom to top.

[0035] The steps for forming these structures are: placing the substrate into a metal-organic chemical vapor deposition (MOCVD) device, and epitaxially growing a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer on the substrate in sequence, thus forming an epitaxial structure. A passivation layer is deposited on top of the AlGaN barrier layer (the deposition material can be SiO2, SiN, Al2O3, etc.), and the deposition method can be plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc. Then, semiconductor processes such as photolithography, sputtering, and etching are used to make the source, gate, and drain.

[0036] Figure 6 It is a top view of the GaN device along the dotted line b as the cutting line. The dotted line b is the cutting line along the R electrode, the resistor R, and the gate G2 of the GaN device; Figure 7is the corresponding cross-sectional view cut along the dotted line b. The resistance R depends on the conductivity of the two-dimensional electron gas ( Figure 7 As shown by the dotted line in the middle), the R electrode and the gate G2 of the GaN device are connected to the resistor R. When cascaded with the Si MOS tube, the source of the Si MOS tube is connected to the R electrode.

[0037] For the selection of resistor R, the recommended resistance is between 3 ohms and 20 ohms, and the typical resistance is 8 ohms. If the resistance is too small, it will not have much effect on the turn-on time, and the turn-on will still be very fast, but the EMI performance will be relatively poor; if the resistance is too large, when turning off, due to RC delay, a large stress will be formed on the Si MOS tube, causing the Si MOS tube to avalanche.

[0038] Figure 8 It is a top view of the GaN device along the dotted line c, which is a cutting line that cuts the gate G2 of the GaN device from the gate lead. Fig. 9 The corresponding cross-sectional view is cut along the dotted line c. The gate G2 of the GaN device is connected to the gate finger through the gate lead.

[0039] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A cascaded GaN power device, characterized in that: The cascaded GaN power device comprises: a GaN device, a SiMOS tube and a resistor; The source of the GaN device is connected to the drain of the Si MOS tube; the gate of the GaN device is connected to one end of the resistor; the other end of the resistor is connected to the source of the Si MOS tube; the drain of the GaN device serves as the drain of the cascaded GaN power device; the gate of the Si MOS tube serves as the gate of the cascaded GaN power device; and the source of the Si MOS tube serves as the source of the cascaded GaN power device.

2. The cascaded GaN power device according to claim 1, characterized in that: The GaN device comprises: a substrate, a source, a gate, a drain, a passivation layer and an epitaxial structure; the epitaxial structure comprises: a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer epitaxially grown sequentially from bottom to top on the substrate; A source groove is provided at one end of the passivation layer; the source groove extends downward from the top surface of one end of the passivation layer to the GaN channel layer; the source electrode is provided in the source groove, and the source electrode is connected to the two-dimensional free electron gas formed inside the GaN channel layer; A drain groove is provided at the other end of the passivation layer; the drain groove extends downward from the top surface of the other end of the passivation layer into the GaN channel layer; the drain is provided in the drain groove, and the drain is connected to the two-dimensional free electron gas formed inside the GaN channel layer; The gate is arranged on the top surface of the passivation layer and is close to the source electrode and spaced apart from the source electrode.

3. The cascaded GaN power device according to claim 1, characterized in that: The GaN device is a depletion-mode GaN device.

4. The cascaded GaN power device according to claim 2, characterized in that: The passivation layer is obtained by depositing SiO2, SiN or Al2O3 using PECVD, LPCVD or ALD.

5. The cascaded GaN power device according to claim 2, characterized in that: The resistor is formed by a two-dimensional free electron gas formed inside the GaN channel layer.

6. The cascaded GaN power device according to claim 1, characterized in that: The resistance value of the resistor is 8 ohms.

7. The cascaded GaN power device according to claim 1, characterized in that: The cascade-type GaN power device further includes: a resistor electrode; The resistor electrode is arranged on the GaN device; the resistor is connected to the resistor electrode; and the resistor electrode is connected to the source of the Si MOS tube.

8. The cascaded GaN power device according to claim 2, characterized in that: The source electrode, the gate electrode and the drain electrode are all manufactured by using semiconductor technology.

9. The cascaded GaN power device according to claim 8, characterized in that: The semiconductor process includes photolithography, sputtering and etching.

10. The cascaded GaN power device according to claim 2, characterized in that: The epitaxial structure is obtained by epitaxial growth in MOCVD equipment.

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