Semiconductor device including multi-bridge channel field effect transistor

Abstract

A semiconductor device includes: a lower interlayer insulating layer; a first active pattern and a second active pattern on the lower interlayer insulating layer; a gate electrode on the first active pattern and the second active pattern; a first source region on a first side of the gate electrode; a second source region on a second side of the gate electrode; a third source region on the first side of the gate electrode; a drain region on a second side of the gate electrode; a first contact adjacent to the gate electrode and connected to the first source region and the third source region; a second contact adjacent to the gate electrode and connected to the second source region; a third contact adjacent to the gate electrode and connected to the drain region; a lower wiring layer inside the lower interlayer insulating layer; and a via connecting the lower wiring layer and the first contact portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0103325 filed on August 8, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present inventive concept relate to a semiconductor device, and more particularly, to a semiconductor device including a multi-bridge channel field effect transistor (MBCFET). TM ) semiconductor devices. Background Art

[0004] As one of scaling technologies for increasing the density of integrated circuit devices, a multi-gate transistor for forming a silicon body having a fin shape or a nanowire shape on a substrate and for forming a gate on a surface of the silicon body has been developed.

[0005] Since the multi-gate transistor uses a three-dimensional channel, the multi-gate transistor can be easily scaled. In addition, even if the gate length of the multi-gate transistor is not increased, the current control capability can be increased. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0006] According to an embodiment of the present invention, a semiconductor device includes: a lower interlayer insulating layer; a first active pattern and a second active pattern extending in a first horizontal direction on the lower interlayer insulating layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; a gate electrode extending in a second horizontal direction on the first active pattern and the second active pattern; a first source region disposed on a first side of the gate electrode and disposed on the first active pattern; a second source region disposed on a second side of the gate electrode and disposed on the first active pattern, the second side being opposite to the first side of the gate electrode in the first horizontal direction; a third source region disposed on the first side of the gate electrode and disposed on the second active pattern; a drain region disposed on the second side of the gate electrode and disposed on the second active pattern; a first contact portion extending in the second horizontal direction on the first side of the gate electrode, wherein , a first contact portion is connected to each of the first source region and the third source region; a second contact portion extends in the second horizontal direction on the second side of the gate electrode, wherein the second contact portion is connected to the second source region; a third contact portion extends in the second horizontal direction on the second side of the gate electrode, wherein the third contact portion is spaced apart from the second contact portion in the second horizontal direction, and the third contact portion is connected to the drain region; a lower wiring layer is arranged inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction between the first active pattern and the second active pattern, wherein at least a portion of the lower wiring layer protrudes from the upper surface of the lower interlayer insulating layer in a vertical direction below the first contact portion; and a through hole is arranged between the first source region and the third source region, wherein the through hole connects the lower wiring layer and the first contact portion, wherein each of the second contact portion and the third contact portion is electrically insulated from the lower wiring layer between the second source region and the drain region.

[0007] According to an embodiment of the present invention, a semiconductor device includes: a lower interlayer insulating layer; a first active pattern and a second active pattern extending in a first horizontal direction on the lower interlayer insulating layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode extending in a second horizontal direction on the first active pattern and the second active pattern, wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are sequentially spaced apart from each other in the first horizontal direction; a gate cutout extending in the first horizontal direction between the first active pattern and the second active pattern, wherein the gate cutout Each of the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode is separated in a second horizontal direction; a first source region is disposed on the first active pattern and between the first gate electrode and the second gate electrode; a second source region is disposed on the first active pattern and between the second gate electrode and the third gate electrode; a first drain region is disposed on the first active pattern and between the third gate electrode and the fourth gate electrode; a third source region is disposed on the second active pattern and between the first gate electrode and the second gate electrode; a second drain region is disposed on the second active pattern and between the second gate electrode and the third gate electrode; a fourth source region is disposed on the second active pattern and between the third gate electrode and the fourth gate electrode; a first contact extending in the second horizontal direction between the first gate electrode and the second gate electrode, wherein the first contact is connected to each of the first source region and the third source region; a second contact extending in the second horizontal direction between the second gate electrode and the third gate electrode, wherein the second contact is connected to the second source region; a third contact extending in the second horizontal direction between the third gate electrode and the fourth gate electrode, wherein the third contact is connected to the first drain region; a fourth contact extending in the second horizontal direction between the second gate electrode and the third gate electrode, wherein the fourth contact is spaced apart from the second contact in the second horizontal direction, and the fourth contact is connected to the second drain region; five contacts extending in a second horizontal direction between the third gate electrode and the fourth gate electrode, wherein the fifth contact is spaced apart from the third contact in the second horizontal direction and the fifth contact is connected to the fourth source region; a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction below the gate cut; and a through hole intersecting the gate cut, wherein the through hole connects the lower wiring layer and the first contact, wherein each of the second contact and the fourth contact is electrically insulated from the lower wiring layer between the second gate electrode and the third gate electrode, and wherein each of the third contact and the fifth contact is electrically insulated from the lower wiring layer between the third gate electrode and the fourth gate electrode.

[0008] According to an embodiment of the present invention, a semiconductor device includes: a lower interlayer insulating layer; a first active pattern and a second active pattern extending in a first horizontal direction on the lower interlayer insulating layer, the second active pattern being spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; a first plurality of nanosheets stacked on the first active pattern spaced apart from each other in a vertical direction; a second plurality of nanosheets stacked on the second active pattern spaced apart from each other in a vertical direction; a gate electrode extending in a second horizontal direction on the first active pattern and the second active pattern, wherein the gate electrode at least partially surrounds the first plurality of nanosheets and the second plurality of nanosheets; a gate cutout formed between the first active pattern and the second active pattern; The gate electrodes are separated in a second horizontal direction by a gate cutout; a first source region disposed on a first side of the gate electrode on the first active pattern; a second source region disposed on a second side of the gate electrode on the first active pattern, the second side being opposite to the first side of the gate electrode in the first horizontal direction; a third source region disposed on the first side of the gate electrode on the second active pattern; a drain region disposed on the second side of the gate electrode on the second active pattern; a first contact portion extending in a second horizontal direction on the first side of the gate electrode, wherein the first contact portion is connected to each of the first source region and the third source region; a second contact portion extending in the second horizontal direction on the second side of the gate electrode, wherein the second contact portion is connected to each of the first source region and the third source region; and wherein the second contact is connected to the second source region; a third contact extending in a second horizontal direction on a second side of the gate electrode, wherein the third contact is spaced apart from the second contact in the second horizontal direction and connected to the drain region; a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction between the first active pattern and the second active pattern, wherein at least a portion of the lower wiring layer protrudes from an upper surface of the lower interlayer insulating layer in a vertical direction below the first contact, wherein the lower wiring layer overlaps with each of the first active pattern and the second active pattern in a vertical direction; a through hole disposed between the first source region and the third source region, wherein the through hole is integrally formed with the first contact A through hole is formed, wherein the through hole intersects the gate cut and connects the lower wiring layer and the first contact portion; a lower insulating layer is arranged between the upper surface of the lower interlayer insulating layer and the lower surface of each of the first active pattern and the second active pattern, and the lower insulating layer contacts the lower wiring layer; and a field insulating layer is arranged on the upper surface of the lower interlayer insulating layer, wherein the field insulating layer at least partially surrounds each of the sidewalls of the lower insulating layer, the sidewalls of the first active pattern, and the sidewalls of the second active pattern, wherein each of the second contact portion and the third contact portion is electrically insulated from the lower wiring layer between the second source region and the drain region, and wherein the upper surface of the lower insulating layer is formed to be higher than the upper surface of the lower wiring layer between the first source region and the third source region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and features of the present inventive concept will become more apparent by describing in detail embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0010] Figure 1 is a layout diagram showing a semiconductor device according to an embodiment of the inventive concept;

[0011] Figure 2 is along Figure 1 A cross-sectional view taken along line AA';

[0012] Figure 3 is along Figure 1 A cross-sectional view taken along line BB';

[0013] Figure 4 is along Figure 1 A cross-sectional view taken along line CC';

[0014] Figure 5 is along Figure 1 A cross-sectional view taken along line D-D';

[0015] Figure 6 is along Figure 1 A cross-sectional view taken along line EE';

[0016] Figure 7 is along Figure 1 A cross-sectional view taken along line F-F';

[0017] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 , Fig.35 , Fig.36 , Fig.37 , Fig.38 , Fig.39 , Fig.40 , Fig.41 , Fig.42 , Fig.43 , Fig.44 , Fig.45 , Fig.46 , Fig.47 , Fig.48 , Fig.49 , Fig.50 , Fig.51 , Fig.52 , Fig.53 , Fig.54 , Fig.55 and Fig.56 is a diagram illustrating an intermediate step of a method for manufacturing a semiconductor device according to an embodiment of the inventive concept;

[0018] Fig.57 and Fig.58 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept;

[0019] Fig.59 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept;

[0020] Fig.60 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept;

[0021] Fig.61 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept;

[0022] Fig.62 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept; and

[0023] Fig.63 and Fig.64 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] As shown in the figure, as an example, a semiconductor device according to an embodiment of the present invention includes a multi-bridge channel field effect transistor (MBCFET TM ), the multi-bridge channel field effect transistor includes a nanosheet, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, the semiconductor device may include a fin transistor (FinFET), a tunneling transistor (tunneling FET), or a three-dimensional (3D) transistor including a channel region having a fin pattern shape. In addition, the semiconductor device according to an embodiment of the inventive concept may include a bipolar junction transistor, or a lateral diffused metal oxide semiconductor (LDMOS) transistor.

[0025] In the following, reference will be made to Figures 1 to 7Semiconductor devices according to embodiments of the inventive concept are described.

[0026] Figure 1 is a layout diagram illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 2 is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 is along Figure 1 A cross-sectional view taken along line BB'. Figure 4 is along Figure 1 A cross-sectional view taken along line CC'. Figure 5 is along Figure 1 A cross-sectional view taken along line D-D'. Figure 6 is along Figure 1 A cross-sectional view taken along line EE'. Figure 7 is along Figure 1 A cross-sectional view taken along line F-F'.

[0027] refer to Figures 1 to 7 , a semiconductor device according to an embodiment of the inventive concept includes a lower interlayer insulating layer 100, a first active pattern F1 and a second active pattern F2, a lower insulating layer 101, a field insulating layer 105, a first plurality of nanosheets NW1 to an eighth plurality of nanosheets NW8, a first gate electrode G1 to a fourth gate electrode G4, a first gate spacer 111 to a fourth gate spacer 114, a gate insulating layer 121, a capping pattern 122, a first source region S1 to a fourth source region S4, a first drain region D1 and a second drain region D2. Region D2, the first etch stop layer 130, the first upper interlayer insulating layer 140, the gate cut GC, the first contact portion CA1 to the fifth contact portion CA5, the first contact separation layer CAS1 and the second contact separation layer CAS2, the through hole VPR, the lower wiring layer 150, the second etch stop layer 160, the second upper interlayer insulating layer 165, the first via V1 to the fourth via V4, the third upper interlayer insulating layer 170, and the first upper wiring layer to the third upper wiring layer 181, 182 and 183.

[0028] The lower interlayer insulating layer 100 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. The low dielectric constant material may include, for example, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylchlorotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), eastern silazane (TOSZ), fluorinated silicate glass (FSG), polyimide nanofoam (e.g., polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but the inventive concept is not limited thereto.

[0029] Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be a direction parallel to the upper surface of the lower interlayer insulating layer 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 may be a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. For example, the vertical direction DR3 may be a direction perpendicular to the upper surface of the lower interlayer insulating layer 100.

[0030] Each of the first active pattern F1 and the second active pattern F2 may extend in the first horizontal direction DR1 on the upper surface of the lower interlayer insulating layer 100. The second active pattern F2 may be spaced apart from the first active pattern F1 in the second horizontal direction DR2. For example, each of the first active pattern F1 and the second active pattern F2 may include silicon, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, each of the first active pattern F1 and the second active pattern F2 may include silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0031] The lower insulating layer 101 may be disposed on an upper surface of the lower interlayer insulating layer 100. The lower insulating layer 101 may protrude from the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3. For example, the lower insulating layer 101 may be disposed between the upper surface of the lower interlayer insulating layer 100 and the lower surface of the first active pattern F1. The lower insulating layer 101 may be disposed between the upper surface of the lower interlayer insulating layer 100 and the lower surface of the second active pattern F2. For example, the sidewall of the lower insulating layer 101 may be aligned with each of the sidewall of the first active pattern F1 and the sidewall of the second active pattern F2. The lower insulating layer 101 may include an insulating material. The lower insulating layer 101 may include a material different from that of the field insulating layer 105. For example, the lower insulating layer 101 may include a material having an etching selectivity relative to the field insulating layer 105.

[0032] The field insulating layer 105 may be disposed on the upper surface of the lower interlayer insulating layer 100. The field insulating layer 105 may at least partially surround the sidewalls of the lower insulating layer 101, the sidewalls of the first active pattern F1, and the sidewalls of the second active pattern F2. For example, at least a portion of each of the first active pattern F1 and the second active pattern F2 may protrude more than the upper surface of the field insulating layer 105 in the vertical direction DR3, but the inventive concept is not limited thereto. The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

[0033] The first to fourth plurality of nanosheets NW1, NW2, NW3, and NW4 may be respectively disposed on the first active pattern F1. The second plurality of nanosheets NW2 may be spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1. The third plurality of nanosheets NW3 may be spaced apart from the second plurality of nanosheets NW2 in the first horizontal direction DR1. The fourth plurality of nanosheets NW4 may be spaced apart from the third plurality of nanosheets NW3 in the first horizontal direction DR1.

[0034] The fifth to eighth plurality of nanosheets NW5, NW6, NW7, and NW8 may be respectively disposed on the second active pattern F2. The sixth plurality of nanosheets NW6 may be spaced apart from the fifth plurality of nanosheets NW5 in the first horizontal direction DR1. The seventh plurality of nanosheets NW7 may be spaced apart from the sixth plurality of nanosheets NW6 in the first horizontal direction DR1. The eighth plurality of nanosheets NW8 may be spaced apart from the seventh plurality of nanosheets NW7 in the first horizontal direction DR1. Each of the fifth to eighth plurality of nanosheets NW5, NW6, NW7, and NW8 may be spaced apart from each of the first to fourth plurality of nanosheets NW1, NW2, NW3, and NW4 in the second horizontal direction DR2.

[0035] Each of the first to eighth plurality of nanosheets NW1 to NW8 may include a plurality of nanosheets stacked in the vertical direction DR3 and spaced apart from each other. Figures 1 to 3 It is shown that each of the first plurality of nanosheets NW1 to the eighth plurality of nanosheets NW8 includes three nanosheets stacked and spaced apart from each other in the vertical direction DR3, but this is only for convenience of description, and the inventive concept is not limited thereto. In an embodiment of the inventive concept, each of the first plurality of nanosheets NW1 to the eighth plurality of nanosheets NW8 may include four or more nanosheets stacked and spaced apart from each other in the vertical direction DR3.

[0036] For example, each of the first to eighth plurality of nanosheets NW1 to NW8 may include silicon (Si), but the inventive concept is not limited thereto. In an embodiment of the inventive concept, each of the first to eighth plurality of nanosheets NW1 to NW8 may include silicon germanium (SiGe).

[0037] Each of the first to fourth gate electrodes G1, G2, G3, and G4 may extend in the second horizontal direction DR2 on the first active pattern F1, the second active pattern F2, and the field insulating layer 105. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The third gate electrode G3 may be spaced apart from the second gate electrode G2 in the first horizontal direction DR1. The fourth gate electrode G4 may be spaced apart from the third gate electrode G3 in the first horizontal direction DR1.

[0038] The first gate electrode G1 may at least partially surround each of the first plurality of nanosheets NW1 and the fifth plurality of nanosheets NW5. The second gate electrode G2 may at least partially surround each of the second plurality of nanosheets NW2 and the sixth plurality of nanosheets NW6. The third gate electrode G3 may at least partially surround each of the third plurality of nanosheets NW3 and the seventh plurality of nanosheets NW7. The fourth gate electrode G4 may at least partially surround each of the fourth plurality of nanosheets NW4 and the eighth plurality of nanosheets NW8.

[0039] Each of the first to fourth gate electrodes G1, G2, G3, and G4 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbon At least one of tantalum nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. Each of the first to fourth gate electrodes G1, G2, G3, and G4 may include a conductive metal oxide, a conductive metal oxynitride, and the like, and may include an oxidized form of the above materials.

[0040] The first gate spacer 111 may extend in the second horizontal direction DR2 and along both sidewalls of the first gate electrode G1 on the upper surface of the uppermost nanosheet of the first plurality of nanosheets NW1, the upper surface of the uppermost nanosheet of the fifth plurality of nanosheets NW5, and the field insulating layer 105. The second gate spacer 112 may extend in the second horizontal direction DR2 and along both sidewalls of the second gate electrode G2 on the upper surface of the uppermost nanosheet of the second plurality of nanosheets NW2, the upper surface of the uppermost nanosheet of the sixth plurality of nanosheets NW6, and the field insulating layer 105. The third gate spacer 113 may extend in the second horizontal direction DR2 and along both sidewalls of the third gate electrode G3 on the upper surface of the uppermost nanosheet of the third plurality of nanosheets NW3, the upper surface of the uppermost nanosheet of the seventh plurality of nanosheets NW7, and the field insulating layer 105. The fourth gate spacer 114 may extend in the second horizontal direction DR2 and along both sidewalls of the fourth gate electrode G4 on an upper surface of an uppermost nanosheet of the fourth plurality of nanosheets NW4 , an upper surface of an uppermost nanosheet of the eighth plurality of nanosheets NW8 , and the field insulating layer 105 .

[0041] Each of the first to fourth gate spacers 111, 112, 113, and 114 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), or at least one of a combination thereof, but the inventive concept is not limited thereto.

[0042] The gate insulating layer 121 may be disposed between the first gate electrode G1 and the first gate spacer 111. The gate insulating layer 121 may be disposed between the second gate electrode G2 and the second gate spacer 112. The gate insulating layer 121 may be disposed between the third gate electrode G3 and the third gate spacer 113. The gate insulating layer 121 may be disposed between the fourth gate electrode G4 and the fourth gate spacer 114. The gate insulating layer 121 may be disposed on the sidewall of each of the first to fourth gate electrodes G1, G2, G3, and G4 in the first horizontal direction DR1. The gate insulating layer 121 may be disposed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and each of the first active pattern F1 and the second active pattern F2. The gate insulating layer 121 may be disposed between each of the first to fourth gate electrodes G1, G2, G3, and G4 and the field insulating layer 105. For example, the gate insulating layer 121 may extend along side surfaces of the first to fourth gate electrodes G1 , G2 , G3 , and G4 .

[0043] The gate insulating layer 121 may be disposed between the first gate electrode G1 and each of the first plurality of nanosheets NW1 and the fifth plurality of nanosheets NW5. The gate insulating layer 121 may be disposed between the second gate electrode G2 and each of the second plurality of nanosheets NW2 and the sixth plurality of nanosheets NW6. The gate insulating layer 121 may be disposed between the third gate electrode G3 and each of the third plurality of nanosheets NW3 and the seventh plurality of nanosheets NW7. The gate insulating layer 121 may be disposed between the fourth gate electrode G4 and each of the fourth plurality of nanosheets NW4 and the eighth plurality of nanosheets NW8.

[0044] The gate insulating layer 121 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and / or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0045] The semiconductor device according to the embodiment of the inventive concept may include a negative capacitance (NC) FET based on a negative capacitor.For example, the gate insulating layer 121 may include a ferroelectric material layer having ferroelectric characteristics and a paraelectric material layer having paraelectric characteristics.

[0046] The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series, and the capacitance of each capacitor has a positive value, the total capacitance is reduced more than the capacitance of each individual capacitor. In addition, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and may be greater than the absolute value of each individual capacitor.

[0047] When a ferroelectric material layer having negative capacitance and a paraelectric material layer having positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series can be increased. Based on the increased total capacitance value, a transistor having a ferroelectric material layer can have a subthreshold swing (SS) of less than about 60 mV / decade at about room temperature.

[0048] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. In this case, for example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped in hafnium oxide. For another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr) and oxygen (O).

[0049] The ferroelectric material layer may also include a dopant doped with. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and / or tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the ferroelectric material of the ferroelectric material layer.

[0050] For example, when the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), or yttrium (Y).

[0051] When the dopant is aluminum (Al), the ferroelectric material layer may include about 3 at % to about 8 at % (atomic %) of aluminum. In this case, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0052] When the dopant is silicon (Si), the ferroelectric material layer may include about 2 at% to about 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include about 2 at% to about 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include about 1 at% to about 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include about 50 at% to about 80 at% zirconium.

[0053] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, silicon oxide, or at least one of metal oxides having a high dielectric constant. For example, the metal oxide included in the paraelectric material layer may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and / aluminum oxide.

[0054] The ferroelectric material layer and the paraelectric material layer may include the same material as each other. Although the ferroelectric material layer has ferroelectric properties, the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0055] The ferroelectric material layer may have a thickness with ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, about 0.5 nm to about 10 nm, but the inventive concept is not limited thereto. Since the threshold thickness indicating the ferroelectric properties may vary according to each ferroelectric material, the thickness of the ferroelectric material layer may vary according to the ferroelectric material.

[0056] For example, the gate insulating layer 121 may include one ferroelectric material layer. For example, the gate insulating layer 121 may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer 121 may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked with each other.

[0057] The capping pattern 122 may extend in the second horizontal direction DR2 and may be disposed on each of the first to fourth gate electrodes G1 to G4, the gate insulating layer 121, and the first to fourth gate spacers 111, 112, 113, and 114. The capping pattern 122 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or at least one of a combination thereof, but the inventive concept is not limited thereto.

[0058] The first source region S1 may be disposed on the first active pattern F1 and may be disposed between the first gate electrode G1 and the second gate electrode G2. The second source region S2 may be disposed on the first active pattern F1 and may be disposed between the second gate electrode G2 and the third gate electrode G3. The first drain region D1 may be disposed on the first active pattern F1 and may be disposed between the third gate electrode G3 and the fourth gate electrode G4. The third source region S3 may be disposed on the second active pattern F2 and may be disposed between the first gate electrode G1 and the second gate electrode G2. The second drain region D2 may be disposed on the second active pattern F2 and may be disposed between the second gate electrode G2 and the third gate electrode G3. The fourth source region S4 may be disposed on the second active pattern F2 and may be disposed between the third gate electrode G3 and the fourth gate electrode G4.

[0059] For example, each of the first to fourth source regions S1, S2, S3, and S4, and the first drain region D1 and the second drain region D2 may be in contact with the gate insulating layer 121, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, an internal spacer may be disposed between each of the first to fourth source regions S1, S2, S3, and S4, and the first drain region D1 and the second drain region D2, and the gate insulating layer 121. In this case, the internal spacer may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), or at least one of a combination thereof.

[0060] The first upper interlayer insulating layer 140 may cover each of the first to fourth source regions S1, S2, S3, and S4, and the first drain region D1 and the second drain region D2, and may be disposed on the field insulating layer 105. The first upper interlayer insulating layer 140 may at least partially surround the sidewalls of each of the first to fourth gate spacers 111, 112, 113, and 114, and the capping pattern 122. For example, the upper surface of the first upper interlayer insulating layer 140 may be formed on the same plane as the upper surface of the capping pattern 122, but the inventive concept is not limited thereto. The first upper interlayer insulating layer 140 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material.

[0061] The first etch stop layer 130 may be disposed between each of the first to fourth source regions S1, S2, S3, and S4, and the first drain region D1 and the second drain region D2, and the first upper interlayer insulating layer 140. The first etch stop layer 130 may be disposed between the sidewall of each of the first to fourth gate spacers 111, 112, 113, and 114 and the capping pattern 122, and may be disposed between the sidewall of each of the first to fourth gate spacers 111, 112, 113, and 114 and the first upper interlayer insulating layer 140. The first etch stop layer 130 may be disposed between the field insulating layer 105 and the first upper interlayer insulating layer 140. For example, the first etch stop layer 130 may be formed to be conformal. The first etch stop layer 130 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material.

[0062] The gate cutout GC may extend in the first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2. For example, the gate cutout GC may separate the first to fourth gate electrodes G1, G2, G3, and G4 from each other in the second horizontal direction DR2. For example, the gate cutout GC may extend from the upper surface of the capping pattern 122 to the inside of the field insulating layer 105. For example, the gate cutout GC may extend from the upper surface of the first upper interlayer insulating layer 140 to the inside of the field insulating layer 105.

[0063] For example, the gate cutout GC may be disposed between the first source region S1 and the third source region S3, between the second source region S2 and the second drain region D2, and between the first drain region D1 and the fourth source region S4. For example, the gate cutout GC may be spaced apart from each of the first to fourth source regions S1, S2, S3, and S4, and the first drain region D1 and the second drain region D2 in the second horizontal direction DR2. The gate cutout GC may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), or one of a combination thereof, but the inventive concept is not limited thereto.

[0064] Each of the first to fifth contact portions CA1 to CA5 may be disposed within the first upper interlayer insulating layer 140. The first contact portion CA1 may extend in the second horizontal direction DR2 and may be disposed between the first gate electrode G1 and the second gate electrode G2. The first contact portion CA1 may intersect the gate cutout GC. For example, the gate cutout GC is not disposed in a portion in which the first contact portion CA1 is disposed. For example, the first contact portion CA1 may be separated from the gate cutout GC in the first horizontal direction DR1. The first contact portion CA1 may be connected to each of the first source region S1 and the third source region S3.

[0065] The second contact CA2 may extend in the second horizontal direction DR2 and may be disposed between the second gate electrode G2 and the third gate electrode G3. For example, the gate cutout GC may be spaced apart from the second contact CA2 in the second horizontal direction DR2. The second contact CA2 may be connected to the second source region S2. The third contact CA3 may extend in the second horizontal direction DR2 and may be disposed between the third gate electrode G3 and the fourth gate electrode G4. For example, the gate cutout GC may be spaced apart from the third contact CA3 in the second horizontal direction DR2. The third contact CA3 may be connected to the first drain region D1.

[0066] The fourth contact CA4 may extend in the second horizontal direction DR2 and may be disposed between the second gate electrode G2 and the third gate electrode G3. The fourth contact CA4 may be spaced apart from the second contact CA2 in the second horizontal direction DR2. For example, the fourth contact CA4 may be spaced apart from the gate cutout GC in the second horizontal direction DR2. The fourth contact CA4 may be connected to the second drain region D2. The fifth contact CA5 may extend in the second horizontal direction DR2 and may be disposed between the third gate electrode G3 and the fourth gate electrode G4. The fifth contact CA5 may be spaced apart from the third contact CA3 in the second horizontal direction DR2. For example, the fifth contact CA5 may be spaced apart from the gate cutout GC in the second horizontal direction DR2. The fifth contact CA5 may be connected to the fourth source region S4.

[0067] For example, each of the first to fifth contact portions CA1 to CA5 may be formed of a single layer. Each of the first to fifth contact portions CA1 to CA5 may include a conductive material. For example, each of the first to fifth contact portions CA1 to CA5 may include at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and / or molybdenum (Mo).

[0068] The silicide layer SL may be disposed between the first contact CA1 and each of the first source region S1 and the third source region S3. The silicide layer SL may be disposed between the second contact CA2 and the second source region S2. The silicide layer SL may be disposed between the third contact CA3 and the first drain region D1. The silicide layer SL may be disposed between the fourth contact CA4 and the second drain region D2. The silicide layer SL may be disposed between the fifth contact CA5 and the fourth source region S4. The silicide layer SL may include, for example, a metal silicide material.

[0069] Each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may be disposed within the first upper interlayer insulating layer 140. For example, each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may be disposed on the gate cutout GC. For example, an upper surface of each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may be formed on the same plane as upper surfaces of the second contact portion CA2, the third contact portion CA3, the fourth contact portion CA4, and the fifth contact portion CA5. For example, each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may partially penetrate the first upper interlayer insulating layer 140.

[0070] The first contact separation layer CAS1 may be disposed between the second contact portion CA2 and the fourth contact portion CA4. The first contact separation layer CAS1 may separate the second contact portion CA2 and the fourth contact portion CA4 from each other in the second horizontal direction DR2. The second contact separation layer CAS2 may be disposed between the third contact portion CA3 and the fifth contact portion CA5. The second contact separation layer CAS2 may separate the third contact portion CA3 and the fifth contact portion CA5 from each other in the second horizontal direction DR2. For example, the width of the first contact separation layer CAS1 in the second horizontal direction DR2 may be greater than the width of the second contact separation layer CAS2 in the second horizontal direction DR2.

[0071] For example, the lower surface of each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may be formed to be lower than the lower surface of each of the first contact portion CA1 to the fifth contact portion CA5, but the inventive concept is not limited thereto. Each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may include a material different from that of the first upper interlayer insulating layer 140. For example, each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may include, for example, at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or a combination thereof.

[0072] The through hole VPR may be disposed inside the first upper interlayer insulating layer 140. The through hole VPR may be disposed between the first gate electrode G1 and the second gate electrode G2. The through hole VPR may be disposed between the first source region S1 and the third source region S3. The sidewall of the through hole VPR may be spaced apart from the first etch stop layer 130 disposed on the sidewall of each of the first source region S1 and the third source region S3 in the second horizontal direction DR2. The through hole VPR may be disposed below the first contact CA1. The through hole VPR may be connected to the lower surface of the first contact CA1. For example, the upper surface of the through hole VPR may contact the lower surface of the first contact CA1.

[0073] For example, the through hole VPR may intersect the gate cutout GC. The through hole VPR is not disposed between the second source region S2 and the second drain region D2. In addition, the through hole VPR is not disposed between the first drain region D1 and the fourth source region S4. For example, the through hole VPR may be disposed between the first source region S1 and the third source region S3.

[0074] For example, the through hole VPR may be formed integrally with the first contact portion CA1. For example, the through hole VPR may be formed of a single layer. For example, the through hole VPR may include the same material as that of the first contact portion CA1. For example, the through hole VPR may include, for example, at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). For example, as the through hole VPR approaches the lower surface of the first contact portion CA1, the width of the through hole VPR in the second horizontal direction DR2 may continuously increase.

[0075] The lower wiring trench 150T may be formed inside the lower interlayer insulating layer 100. The lower wiring trench 150T may extend in the first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2. For example, at least a portion of the lower wiring trench 150T may be formed in the field insulating layer 105. For example, the lower wiring trench 150T may be formed inside each of the lower interlayer insulating layer 100 and the field insulating layer 105, and may be between the first source region S1 and the third source region S3. For example, both sidewalls of the lower wiring trench 150T in the second horizontal direction DR2 may be defined by the lower interlayer insulating layer 100 and the lower insulating layer 101 between the first source region S1 and the third source region S3. For example, in the remaining region except for the region between the first source region S1 and the third source region S3, the lower wiring trench 150T is not formed in the field insulating layer 105, but the inventive concept is not limited thereto.

[0076] The lower wiring layer 150 may be disposed inside the lower wiring trench 150T. The lower wiring layer 150 may extend in the first horizontal direction DR1 and may be disposed between the first active pattern F1 and the second active pattern F2. For example, the lower wiring layer 150 may overlap with the gate cutout GC in the vertical direction DR3. For example, the lower wiring layer 150 may overlap with the lower insulating layer 101 in the vertical direction DR3. For example, the lower wiring layer 150 may overlap with each of the first active pattern F1 and the second active pattern F2 in the vertical direction DR3. For example, the lower wiring layer 150 may be spaced apart from each of the first active pattern F1 and the second active pattern F2.

[0077] For example, at least a portion of the lower wiring layer 150 may protrude in the vertical direction DR3 from the upper surface of the lower interlayer insulating layer 100 between the first source region S1 and the third source region S3. For example, the upper surface of the lower insulating layer 101 may be formed to be higher than the upper surface of the lower wiring layer 150 between the first source region S1 and the third source region S3. For example, the sidewall of the lower wiring layer 150 may contact the sidewall of the lower insulating layer 101 between the first source region S1 and the third source region S3. For example, the upper surface of the lower wiring layer 150 may contact the field insulating layer 105, the first etch stop layer 130, the first upper interlayer insulating layer 140, and the via VPR between the first source region S1 and the third source region S3.

[0078] For example, the upper surface of the lower wiring layer 150 may be formed on the same plane as the upper surface of the lower interlayer insulating layer 100 below each of the first to fourth gate electrodes G1, G2, G3, and G4. The upper surface of the lower wiring layer 150 may be formed on the same plane as the upper surface of the lower interlayer insulating layer 100 between the second source region S2 and the second drain region D2. The upper surface of the lower wiring layer 150 may be formed on the same plane as the upper surface of the lower interlayer insulating layer 100 between the first drain region D1 and the fourth source region S4.

[0079] For example, the upper surface of the lower wiring layer 150 may contact each of the lower surface of the lower insulating layer 101 and the lower surface of the field insulating layer 105 below each of the first to fourth gate electrodes G1, G2, G3, and G4. The upper surface of the lower wiring layer 150 may contact each of the lower surface of the lower insulating layer 101 and the lower surface of the field insulating layer 105 between the first drain region D1 and the fourth source region S4.

[0080] For example, the upper surface of the lower wiring layer 150 may be spaced apart from the gate cutout GC in the vertical direction DR3 and may be disposed below each of the first to fourth gate electrodes G1, G2, G3, and G4. The upper surface of the lower wiring layer 150 may be spaced apart from the gate cutout GC in the vertical direction DR3 between the second source region S2 and the second drain region D2. The upper surface of the lower wiring layer 150 may be spaced apart from the gate cutout GC in the vertical direction DR3 between the first drain region D1 and the fourth source region S4.

[0081] The lower wiring layer 150 may include a conductive material. For example, the lower wiring layer 150 may be a power rail or a ground rail. Figures 4 to 7 The lower wiring layer 150 is shown to be formed of a single layer, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, the lower wiring layer 150 may be formed of multiple layers. For example, as the lower wiring layer 150 approaches the lower surface of the lower interlayer insulating layer 100, the width of the lower wiring layer 150 in the second horizontal direction DR2 may continuously increase.

[0082] For example, the lower wiring layer 150 may be electrically connected to the first contact CA1 through the via VPR. For example, the lower wiring layer 150 may be electrically insulated from each of the second contact CA2 and the fourth contact CA4 between the second source region S2 and the second drain region D2. For example, the lower wiring layer 150 may be electrically insulated from each of the second contact CA2 and the fourth contact CA4 between the second gate electrode G2 and the third gate electrode G3. In addition, the lower wiring layer 150 may be electrically insulated from each of the third contact CA3 and the fifth contact CA5 between the first drain region D1 and the fourth source region S4. For example, the lower wiring layer 150 may be electrically insulated from each of the third contact CA3 and the fifth contact CA5 between the third gate electrode G3 and the fourth gate electrode G4.

[0083] The second etch stop layer 160 may be disposed on an upper surface of each of the first upper interlayer insulating layer 140, the capping pattern 122, the gate cutout GC, the first and second contact separation layers CAS1 to CAS2, and the first to fifth contacts CA1 to CA5. Figures 2 to 7 1 and 2. The second etch stop layer 160 is shown as being formed by a single layer, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, the second etch stop layer 160 may be formed by multiple layers. The second etch stop layer 160 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. A second upper interlayer insulating layer 165 may be disposed on the second etch stop layer 160. The second upper interlayer insulating layer 165 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material.

[0084] The first via hole V1 may be connected to the first contact portion CA1 by passing through the second upper interlayer insulating layer 165 and the second etch stop layer 160 in the vertical direction DR1. The second via hole V2 may be connected to the third contact portion CA3 by passing through the second upper interlayer insulating layer 165 and the second etch stop layer 160 in the vertical direction DR3. The third via hole V3 may be connected to the fourth contact portion CA4 by passing through the second upper interlayer insulating layer 165 and the second etch stop layer 160 in the vertical direction DR3. The fourth via hole V4 may be connected to the fifth contact portion CA5 by passing through the second upper interlayer insulating layer 165 and the second etch stop layer 160 in the vertical direction DR3.

[0085] Figures 2 to 7It is shown that each of the first to fourth vias V1, V2, V3, and V4 is formed of a single layer, but this is for ease of description, and the inventive concept is not limited thereto. In an embodiment of the inventive concept, each of the first to fourth vias V1, V2, V3, and V4 may be formed of multiple layers. Each of the first to fourth vias V1, V2, V3, and V4 may include a conductive material.

[0086] The third upper interlayer insulating layer 170 may be disposed on the second upper interlayer insulating layer 165. The third upper interlayer insulating layer 170 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. Each of the first to third upper wiring layers 181, 182, and 183 may be disposed within the third upper interlayer insulating layer 170. For example, each of the first to third upper wiring layers 181, 182, and 183 may extend in the first horizontal direction DR1.

[0087] For example, the second upper wiring layer 182 may be spaced apart from the first upper wiring layer 181 in the second horizontal direction DR2. The third upper wiring layer 183 may be spaced apart from the second upper wiring layer 182 in the second horizontal direction DR2. For example, the first upper wiring layer 181 may be electrically connected to the third contact portion CA3 through the second via V2. The second upper wiring layer 182 may be electrically connected to the first contact portion CA1 through the first via V1. In addition, the second upper wiring layer 182 may be electrically connected to the fifth contact portion CA5 through the fourth via V4. The third upper wiring layer 183 may be electrically connected to the fourth contact portion CA4 through the third via V3.

[0088] Each of the first to third upper wiring layers 181, 182, and 183 may include a conductive material. Figures 2 to 7 It is shown that each of the first to third upper wiring layers 181, 182, and 183 is formed of a single layer, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, each of the first to third upper wiring layers 181, 182, and 183 may be formed of multiple layers. For example, as each of the first to third upper wiring layers 181, 182, and 183 approaches the upper surface of the second upper interlayer insulating layer 165, the width of each of the first to third upper wiring layers 181, 182, and 183 in the second horizontal direction DR2 may be continuously reduced.

[0089] In the semiconductor device according to the embodiment of the present invention, the through hole VPR is formed only under the contact CA1 disposed on the two source regions S1 and S3, and the through hole VPR is not formed under the remaining contact parts CA2, CA3, CA4 and CA5. Therefore, in the semiconductor device according to the embodiment of the present invention, the area in which the through hole VPR is formed can be minimized, so that the process difficulty can be reduced, and the integration of the semiconductor device can be improved.

[0090] In the following, reference will be made to Figures 2 to 56 A method for fabricating a semiconductor device according to an embodiment of the inventive concept is described.

[0091] Figures 8 to 56 are diagrams illustrating intermediate steps of a method for fabricating a semiconductor device according to an embodiment of the inventive concept.

[0092] refer to Figure 8 and Fig. 9 , a stacked structure 20 may be formed on a substrate 10. The substrate 10 may be a silicon substrate or a silicon on insulator (SOI). In addition, the substrate 10 may include, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide, but the inventive concept is not limited thereto.

[0093] The stacked structure 20 may include a first semiconductor layer 21 and a second semiconductor layer 22 alternately stacked on the substrate 10. For example, the first semiconductor layer 21 may be formed on the lowermost portion of the stacked structure 20, and the second semiconductor layer 22 may be formed on the uppermost portion of the stacked structure 20, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, the first semiconductor layer 21 may also be formed on the uppermost portion of the stacked structure 20. The first semiconductor layer 21 may include, for example, silicon germanium (SiGe). The second semiconductor layer 22 may include, for example, silicon (Si).

[0094] Then, a portion of the stack structure 20 may be etched. While etching the stack structure 20, a portion of the substrate 10 may be etched. A first active pattern F1 and a second active pattern F2 may be respectively formed below the stack structure 20 on the upper surface of the substrate 10 by an etching process. Each of the first active pattern F1 and the second active pattern F2 may extend in the first horizontal direction DR1. The second active pattern F2 may be spaced apart from the first active pattern F1 in the second horizontal direction DR2.

[0095] Subsequently, a field insulating layer 105 may be formed on the upper surface of the substrate 10. The field insulating layer 105 may surround the sidewalls of each of the first active pattern F1 and the second active pattern F2. A pad oxide layer 30 may be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls of the first active pattern F1, the exposed sidewalls of the second active pattern F2, the sidewalls and the upper surface of the stacked structure 20. For example, the pad oxide layer 30 may be formed to be conformal. For example, the pad oxide layer 30 may be conformally formed on the field insulating layer 105, the exposed sidewalls of the first active pattern F1, the exposed sidewalls of the second active pattern F2, the sidewalls and the upper surface of the stacked structure 20. The pad oxide layer 30 may include, for example, silicon oxide (SiO 2 ).

[0096] refer to Fig.10 and Fig.11 , the first to fourth dummy gates DG1, DG2, DG3, and DG4, and the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4 extending in the second horizontal direction DR2 on the pad oxide layer 30 may be formed on the stacked structure 20 and the field insulating layer 105. The first dummy capping pattern DC1 may be formed on the first dummy gate DG1. The second dummy capping pattern DC2 may be formed on the second dummy gate DG2. The third dummy capping pattern DC3 may be formed on the third dummy gate DG3, and the fourth dummy capping pattern DC4 may be formed on the fourth dummy gate DG4.

[0097] The second dummy gate DG2 and the second dummy capping pattern DC2 may be spaced apart from the first dummy gate DG1 and the first dummy capping pattern DC1 in the first horizontal direction DR1. The third dummy gate DG3 and the third dummy capping pattern DC3 may be spaced apart from the second dummy gate DG2 and the second dummy capping pattern DC2 in the first horizontal direction DR1. The fourth dummy gate DG4 and the fourth dummy capping pattern DC4 may be spaced apart from the third dummy gate DG3 and the third dummy capping pattern DC3 in the first horizontal direction DR1.

[0098] While forming the first to fourth dummy gates DG1, DG2, DG3 and DG4 and the first to fourth dummy capping patterns DC1, DC2, DC3 and DC4, the remaining pad oxide layer 30 except for the portion overlapping with each of the first to fourth dummy gates DG1, DG2, DG3 and DG4 in the vertical direction DR3 on the substrate 10 can be removed.

[0099] A spacer material layer SM may be formed to cover the sidewalls of each of the first to fourth dummy gates DG1, DG2, DG3, and DG4, the sidewalls and upper surfaces of each of the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4, the exposed sidewalls and upper surfaces of the stacked structure 20, and the upper surface of the field insulating layer 105. For example, the spacer material layer SM may be conformally formed on the sidewalls and upper surfaces of each of the first to fourth dummy gates DG1, DG2, DG3, and DG4, the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4, the exposed sidewalls and upper surfaces of the stacked structure 20, and the upper surface of the field insulating layer 105. The spacer material layer SM may include, for example, at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or a combination thereof.

[0100] refer to Figure 12 to Figure 14 , the stack structure may be etched using the first to fourth dummy gates DG1, DG2, DG3, and DG4 and the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4 as masks ( Fig.10 20) to form the first to third source / drain trenches ST1, ST2, and ST3. For example, the first source / drain trench ST1 may be formed on the first active pattern F1 between the first dummy gate DG1 and the second dummy gate DG2. The second source / drain trench ST2 may be formed on the first active pattern F1 between the second dummy gate DG2 and the third dummy gate DG3. The third source / drain trench ST3 may be formed on the first active pattern F1 between the third dummy gate DG3 and the fourth dummy gate DG4. For example, each of the first to third source / drain trenches ST1, ST2, and ST3 may extend into the first active pattern F1. A source / drain trench having a shape similar to each of the first to third source / drain trenches ST1 to ST3 may be formed on the second active pattern F2.

[0101] While forming the first to third source / drain trenches ST1, ST2, and ST3, the spacer material layer ( ) formed on the upper surface of each of the first to fourth dummy capping patterns DC1, DC2, DC3, and DC4 may be etched. Fig.10 The spacer material layer (SM) remaining on the sidewall of each of the first to fourth dummy gates DG1, DG2, DG3 and DG4 is formed on the sidewall of each of the first to fourth dummy gates DG1, DG2, DG3 and DG4. Fig.10The gate spacers (SM) may be first to fourth gate spacers 111, 112, 113, and 114.

[0102] After forming the first to third source / drain trenches ST1, ST2, and ST3, the second semiconductor layer ( Fig.10 22) may be the first plurality of nanosheets to the eighth plurality of nanosheets ( Figure 2 and Figure 3 NW1 to NW8).

[0103] refer to Figures 15 to 17 , can be in the first source / drain trench ( Fig.12 The first source region S1 is formed inside the second source / drain trench ( Fig.12 The second source region S2 is formed inside the third source / drain trench ( Fig.12 ST3) forms the first drain region D1. In addition, the fifth plurality of nanosheets ( Figure 3 NW5) and the sixth multiple nanosheets ( Figure 3 The third source region ( Figure 3 S3). It can be found in the sixth nanosheet ( Figure 3 NW6) and the seventh nanosheet ( Figure 3 The second drain region ( Figure 3 D2 in the figure, and can be found in the seventh nanosheet ( Figure 3 NW7) and the eighth multiple nanosheets ( Figure 3 The fourth source region ( Figure 3 in S4).

[0104] Subsequently, a first etch stop layer 130 may be formed on an exposed surface of the field insulating layer 105, an exposed surface of each of the first to fourth source regions S1 to S4, an exposed surface of each of the first and second drain regions D1 and D2, and an exposed sidewall of each of the first to fourth gate spacers 111, 112, 113, and 114. Then, a first upper interlayer insulating layer 140 may be formed on the first etch stop layer 130. Subsequently, a planarization process may be performed so that an upper surface of each of the first to fourth dummy gates DG1, DG2, DG3, and DG4 may be exposed.

[0105] refer to Fig.18 and Fig.19 , the first to fourth dummy gates DG1 , DG2 , DG3 , and DG4 , the first semiconductor layer 21 , and the pad oxide layer 30 may be etched.

[0106] refer to Fig. 20 and Fig.21 , a gate insulating layer 121, first to fourth gate electrodes G1, G2, G3 and G4, and a capping pattern 122 may be sequentially formed on portions where the first to fourth dummy gates DG1, DG2, DG3 and DG4, the first semiconductor layer 21 and the pad oxide layer 30 are etched away.

[0107] refer to Figure 22 to Figure 25 , a gate cutout may be formed between the first active pattern F1 and the second active pattern F2. The gate cutout GC may extend in the first horizontal direction DR1. For example, the gate cutout GC may separate the second gate electrode G2 in the second horizontal direction DR2. The gate cutout GC may extend from each of the upper surface of the capping pattern 122 and the upper surface of the first upper interlayer insulating layer 140 to the inside of the field insulating layer 105.

[0108] Then, a first contact separation layer CAS1 and a second contact separation layer CAS2 may be formed inside the first upper interlayer insulating layer 140. For example, an upper surface of each of the first contact separation layer CAS1 and the second contact separation layer CAS2 may be formed on the same plane as an upper surface of the first upper interlayer insulating layer 140. For example, the first contact separation layer CAS1 may be formed between the second source region S2 and the second drain region D2. The second contact separation layer CAS2 may be formed between the first drain region D1 and the fourth source region S4.

[0109] refer to Figures 26 to 30 , the first contact trench CT1 to the fifth contact trench CT5 may be formed inside the first upper interlayer insulating layer 140. For example, the first contact trench CT1 may be formed on each of the first source region S1 and the third source region S3. The second contact trench CT2 may be formed on the second source region S2. The third contact trench CT3 may be formed on the first drain region D1. The fourth contact trench CT4 may be formed on the second drain region D2. For example, the side surface of the first contact separation layer CAS1 may be exposed by the second contact trench CT2 and the fourth contact trench CT4. The fifth contact trench CT5 may be formed on the fourth source region S4. For example, the side surface of the second contact separation layer CAS2 may be exposed by the third contact trench CT3 and the fifth contact trench CT5.

[0110] refer to Figure 31 to Figure 33, a passivation layer 40 may be formed on each of the first upper interlayer insulating layer 140, the first contact separation layer CAS1, the second contact separation layer CAS2, the first to fourth source regions S1 to S4, and the first and second drain regions D1 and D2. The passivation layer 40 may include, for example, a spin-on hard mask (SOH). Subsequently, a mask pattern M may be formed on the passivation layer 40. The mask pattern M may expose a portion of the passivation layer 40 formed between the first source region S1 and the third source region S3.

[0111] Then, the passivation layer 40, the first upper interlayer insulating layer 140, and the gate cut GC may be etched using the mask pattern M as a mask to form a via trench VPRT. For example, a lower surface of the via trench VPRT may be defined by a portion of the gate cut GC and the first etch stop layer 130 formed on the upper surface of the field insulating layer 105.

[0112] refer to Figure 34 to Figure 36 , the mask pattern M and the passivation layer 40 may be removed. As a result, the first contact trench CT1 may be formed on the via trench VPRT. In addition, second to fifth contact trenches CT2 , CT3 , CT4 , and CT5 may be formed inside the first upper interlayer insulating layer 140 .

[0113] refer to Figures 37 to 41 , can be in the through hole trench ( Fig.34 A through hole VPR is formed in the VPRT of the first contact trench ( Fig.34 The first contact CA1 is formed inside the through hole VPR of the CT1. The through hole VPR and the first contact CA1 may be formed by the same manufacturing process. The through hole VPR and the first contact CA1 may be formed integrally. In addition, the through hole VPR and the first contact CA1 may include the same material as each other.

[0114] In the second contact trench ( Fig.35 The second contact CA2 can be formed in the third contact groove ( Fig.36 The third contact CA3 can be formed in the fourth contact groove ( Fig.35 The fourth contact CA4 is formed inside the fifth contact trench ( Fig.36 A fifth contact portion CA5 is formed inside the CT5).

[0115] refer to Figure 42 to Figure 47, a second etch stop layer 160 and a second upper interlayer insulating layer 165 may be sequentially formed on the upper surface of each of the first upper interlayer insulating layer 140, the capping pattern 122, the gate cutout GC, the first contact separation layer CAS1 and the second contact separation layer CAS2, and the first contact portion CA1 to the fifth contact portion CA5. Subsequently, first to fourth via holes V1, V2, V3, and V4 connected to the first contact portion CA1, the third contact portion CA3, the fourth contact portion CA4, and the fifth contact portion CA5, respectively, may be formed by passing through the second upper interlayer insulating layer 165 and the second etch stop layer 160 in the vertical direction DR3. Subsequently, a third upper interlayer insulating layer 170, and first to third upper wiring layers 181, 182, and 183 may be formed on the second upper interlayer insulating layer 165.

[0116] refer to Figures 48 to 50 , the substrate can be etched ( Figure 42 to Figure 47 10) to expose the lower surface of the field insulating layer 105. A portion of the first active pattern F1 and a portion of the second active pattern F2 may be etched. For example, a lower surface of each of the remaining first active pattern F1 and the second active pattern F2 may be formed to be higher than an upper surface of the field insulating layer 105 adjacent to the gate cut GC.

[0117] refer to Figure 51 to Figure 53 A lower insulating layer 101 may be formed in a portion where each of the first and second active patterns F1 and F2 is partially etched. Subsequently, a planarization process may be performed so that lower surfaces of the lower insulating layer 101 and the field insulating layer 105 may be formed on substantially the same plane.

[0118] refer to Figure 54 to Figure 56 , a lower interlayer insulating layer 100 may be formed on a lower surface of each of the lower insulating layer 101 and the field insulating layer 105. A lower wiring trench 150T may be formed in the lower interlayer insulating layer 100. The lower wiring trench 150T may extend in the first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2.

[0119] For example, the upper surface of the lower wiring trench 150T may expose the lower surface of the via VPR between the first source region S1 and the third source region S3. For example, both sidewalls of the lower wiring trench 150T in the second horizontal direction DR2 may be formed in the lower interlayer insulating layer 100 and the lower insulating layer 101 between the first source region S1 and the third source region S3. For example, the upper surface of the lower wiring trench 150T may be defined by the lower surface of the field insulating layer 105 in the remaining region except for the region between the first source region S1 and the third source region S3.

[0120] refer to Figures 2 to 7, a lower wiring layer 150 may be formed inside the lower wiring trench 150T. The lower wiring layer 150 may extend in the first horizontal direction DR1 between the first active pattern F1 and the second active pattern F2. The lower wiring layer 150 may be connected to the via VPR between the first source region S1 and the third source region S3. Through this manufacturing process, a Figures 2 to 7 The semiconductor device shown.

[0121] In the following, reference will be made to Fig.57 and Fig.58 A semiconductor device according to an embodiment of the present invention is described. The following description will be based on Figures 1 to 7 The semiconductor devices are shown to be different, and redundant descriptions may be omitted or briefly discussed.

[0122] Fig.57 and Fig.58 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0123] refer to Fig.57 and Fig.58 In the semiconductor device according to the embodiment of the inventive concept, the via VPR2 and each of the first to third contacts CA21, CA22 and CA23 may be formed of a double layer. The fourth contact and the fifth contact may also be formed of a double layer.

[0124] For example, each of the through hole VPR2, and the first to third contacts CA21, CA22, and CA23 may include a contact barrier layer 291 and a contact filling layer 292. The contact barrier layer 291 may form the sidewall and bottom surface of each of the through hole VPR2, and the first to third contacts CA21, CA22, and CA23, but the contact barrier layer 291 is not disposed between the through hole VPR2 and the first contact CA21. The contact filling layer 292 may be disposed on the contact barrier layer 291 in each of the through hole VPR2, and the first to third contacts CA21, CA22, and CA23. For example, the upper surface of the contact filling layer 292 of the through hole VPR2 may be in contact with the lower surface of the contact filling layer 292 of the first contact CA21.

[0125] Each of the contact barrier layer 291 and the contact filling layer 292 may include a conductive material. The contact barrier layer 291 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and / or rhodium (Rh). The contact filling layer 292 may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and / or molybdenum (Mo).

[0126] In the following, reference will be made to Fig.59 A semiconductor device according to an embodiment of the present invention is described. The following description will be based on Figures 1 to 7 The differences between the semiconductor devices shown in .

[0127] Fig.59 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0128] refer to Fig.59 , in the semiconductor device according to the embodiment of the inventive concept, the lower wiring layer 350 may be spaced apart from the lower insulating layer 301 in the second horizontal direction DR2 .

[0129] For example, the lower wiring trench 350T may be formed between the lower insulating layer 301 disposed under the first active pattern F1 and the lower insulating layer 301 disposed under the second active pattern F2. The lower wiring layer 350 may be disposed inside the lower wiring trench 350T. The lower wiring layer 350 may be spaced apart from each of the lower insulating layer 301 disposed under the first active pattern F1 and the lower insulating layer 301 disposed under the second active pattern F2 in the second horizontal direction DR2.

[0130] For example, the lower wiring layer 350 does not overlap each of the first active pattern F1 and the second active pattern F2 in the vertical direction DR3. In addition, the lower wiring layer 350 does not overlap each of the lower insulating layer 301 disposed under the first active pattern F1 and the second active pattern F2 in the vertical direction DR3.

[0131] In the following, reference will be made to Fig.60 A semiconductor device according to an embodiment of the present invention is described. The following description will be based on Figures 1 to 7 The semiconductor devices are shown to be different, and redundant descriptions may be omitted or briefly discussed.

[0132] Fig.60is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0133] refer to Fig.60 In the semiconductor device according to the embodiment of the present inventive concept, the lower wiring layer 450 may be spaced apart from each of the first active pattern F41 and the second active pattern F42 in the second horizontal direction DR2. In addition, the lower insulating layer ( Figures 2 to 7 101).

[0134] For example, the lower surface of each of the first active pattern F41 and the second active pattern F42 may contact the upper surface of the lower interlayer insulating layer 100. The lower wiring trench 450T may be formed between the first active pattern F41 and the second active pattern F42. The lower wiring layer 450 may be disposed inside the lower wiring trench 450T. The lower wiring layer 450 may be spaced apart from each of the first active pattern F41 and the second active pattern F42 in the second horizontal direction DR2. For example, the lower wiring layer 450 does not overlap each of the first active pattern F41 and the second active pattern F42 in the vertical direction DR3.

[0135] In the following, reference will be made to Fig.61 A semiconductor device according to an embodiment of the present invention is described. The following description will be based on Figures 1 to 7 The semiconductor devices are shown to be different, and redundant descriptions may be omitted or briefly discussed.

[0136] Fig.61 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0137] refer to Fig.61 , in the semiconductor device according to the embodiment of the inventive concept, a portion of the sidewall of the through hole VPR5 in the second horizontal direction DR2 may contact the first etch stop layer 130 .

[0138] For example, the through hole VPR5 may include a first portion VPR5_1 in contact with the lower wiring layer 150, and a second portion VPR5_2 in contact with the first contact portion CA1. For example, the sidewall of the first portion VPR5_1 of the through hole VPR5 in the second horizontal direction DR2 may be spaced apart from the first etch stop layer 130 disposed on the sidewall of each of the first source region S1 and the third source region S3 in the second horizontal direction DR2. The first upper interlayer insulating layer 140 may be disposed between the first etch stop layer 130 and the sidewall of the first portion VPR5_1 of the through hole VPR5. For example, the sidewall of the second portion VPR5_2 of the through hole VPR5 in the second horizontal direction DR2 may be in contact with the first etch stop layer 130 disposed on the sidewall of each of the first source region S1 and the third source region S3.

[0139] In the following, reference will be made to Fig.62 A semiconductor device according to an embodiment of the present invention is described. The following description will be based on Figures 1 to 7 The semiconductor devices are shown to be different, and redundant descriptions may be omitted or briefly discussed.

[0140] Fig.62 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0141] refer to Fig.62 , in the semiconductor device according to an embodiment of the inventive concept, the entire sidewall of the via hole VPR6 may contact the first etch stop layer 130 .

[0142] For example, the sidewall of the via hole VPR6 in the second horizontal direction DR2 may completely contact the first etch stop layer 130 between the first and third source regions S1 and S3. For example, the first upper interlayer insulating layer 140 is not disposed between the sidewall of the via hole VPR6 and the first etch stop layer 130.

[0143] In the following, reference will be made to Fig.63 and Fig.64 A semiconductor device according to an embodiment of the present invention is described. The following description will be based on Figures 1 to 7 The semiconductor devices are shown to be different, and redundant descriptions may be omitted or briefly discussed.

[0144] Fig.63 and Fig.64 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0145] refer to Fig.63 and Fig.64 , in the semiconductor device according to an embodiment of the inventive concept, the lower wiring layer 750 may extend in the second horizontal direction DR2.

[0146] For example, the lower wiring trench 750T may be formed inside the lower interlayer insulating layer 100. The lower wiring trench 750T may extend in the second horizontal direction DR2 between the first gate electrode G1 and the second gate electrode G2. The lower wiring trench 750T may extend in the vertical direction DR3 below each of the first source region S1 and the third source region S3. For example, the upper surface of the lower wiring trench 750T may be defined as the lower surface of each of the first source region S1 and the third source region S3 below each of the first source region S1 and the third source region S3.

[0147] For example, the lower wiring layer 750 may be disposed inside the lower wiring trench 750T. The lower wiring layer 750 may extend in the second horizontal direction DR2 between the first gate electrode G1 and the second gate electrode G2. The lower wiring layer 750 may protrude from the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3 below each of the first source region S1 and the third source region S3. The sidewall of the lower wiring layer 750 protruding from the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3 may be surrounded by the first active pattern F61 and the field insulating layer 105. For example, the lower wiring layer 750 may contact the lower surface of each of the first source region S1 and the third source region S3.

[0148] Although the inventive concepts have been described with reference to exemplary embodiments thereof, persons skilled in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concepts.

Claims

1. A semiconductor device, comprising: Lower interlayer insulation layer; a first active pattern and a second active pattern extending in a first horizontal direction on the lower interlayer insulating layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; a gate electrode extending in the second horizontal direction on the first active pattern and the second active pattern; a first source region disposed on a first side of the gate electrode and on the first active pattern; a second source region disposed on a second side of the gate electrode and on the first active pattern, the second side being opposite to the first side of the gate electrode in the first horizontal direction; a third source region disposed on the first side of the gate electrode and on the second active pattern; a drain region disposed on the second side of the gate electrode and on the second active pattern; a first contact extending in the second horizontal direction on the first side of the gate electrode, wherein the first contact is connected to each of the first source region and the third source region; a second contact extending in the second horizontal direction on the second side of the gate electrode, wherein the second contact is connected to the second source region; a third contact extending in the second horizontal direction on the second side of the gate electrode, wherein the third contact is spaced apart from the second contact in the second horizontal direction and connected to the drain region; a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction between the first active pattern and the second active pattern, wherein at least a portion of the lower wiring layer protrudes from an upper surface of the lower interlayer insulating layer in a vertical direction below the first contact portion; and a through hole disposed between the first source region and the third source region, wherein the through hole connects the lower wiring layer and the first contact portion, Wherein, each of the second contact portion and the third contact portion is electrically insulated from the lower wiring layer between the second source region and the drain region.

2. The semiconductor device according to claim 1, further comprising a gate cutout extending in the first horizontal direction between the first active pattern and the second active pattern, wherein The gate cut separates the gate electrodes in the second horizontal direction.

3. The semiconductor device according to claim 1, wherein The first contact portion and the through hole are integrally formed.

4. The semiconductor device according to claim 3, wherein: Each of the first contact portion and the through hole is formed of a single material.

5. The semiconductor device according to claim 1, wherein An upper surface of the lower wiring layer is formed on the same plane as the upper surface of the lower interlayer insulating layer between the second source region and the drain region.

6. The semiconductor device according to claim 1, wherein An upper surface of the lower wiring layer is formed on the same plane as the upper surface of the lower interlayer insulating layer under the gate electrode.

7. The semiconductor device according to claim 1, wherein The lower wiring layer is spaced apart from each of the first active pattern and the second active pattern.

8. The semiconductor device according to claim 1, wherein The lower wiring layer overlaps each of the first active pattern and the second active pattern in a vertical direction.

9. The semiconductor device according to claim 1, further comprising: a lower insulating layer disposed between the upper surface of the lower interlayer insulating layer and a lower surface of each of the first active pattern and the second active pattern, wherein the lower insulating layer contacts the lower wiring layer; and A field insulating layer is disposed on the upper surface of the lower interlayer insulating layer, wherein the field insulating layer at least partially surrounds each of: a sidewall of the lower insulating layer, a sidewall of the first active pattern, and a sidewall of the second active pattern.

10. The semiconductor device according to claim 9, wherein The upper surface of the lower insulating layer is formed to be higher than the upper surface of the lower wiring layer between the first source region and the third source region.

11. The semiconductor device according to claim 9, wherein: The lower insulating layer is spaced apart from the lower wiring layer in the second horizontal direction.

12. The semiconductor device according to claim 1, further comprising: an etch stop layer, disposed along a sidewall of the first source region in the second horizontal direction; as well as an upper interlayer insulating layer covering the etch stop layer, Wherein, the through hole is spaced apart from the etching stop layer in the second horizontal direction.

13. A semiconductor device comprising: Lower interlayer insulation layer; a first active pattern and a second active pattern extending in a first horizontal direction on the lower interlayer insulating layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode extending in the second horizontal direction on the first active pattern and the second active pattern, wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are sequentially spaced apart from each other in the first horizontal direction; a gate cutout extending in the first horizontal direction between the first active pattern and the second active pattern, wherein the gate cutout separates each of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode in the second horizontal direction; a first source region disposed on the first active pattern and between the first gate electrode and the second gate electrode; a second source region disposed on the first active pattern and between the second gate electrode and the third gate electrode; a first drain region disposed on the first active pattern and between the third gate electrode and the fourth gate electrode; a third source region disposed on the second active pattern and between the first gate electrode and the second gate electrode; a second drain region disposed on the second active pattern and between the second gate electrode and the third gate electrode; a fourth source region disposed on the second active pattern and between the third gate electrode and the fourth gate electrode; a first contact extending in the second horizontal direction between the first gate electrode and the second gate electrode, wherein the first contact is connected to each of the first source region and the third source region; a second contact extending in the second horizontal direction between the second gate electrode and the third gate electrode, wherein the second contact is connected to the second source region; a third contact portion extending in the second horizontal direction between the third gate electrode and the fourth gate electrode, wherein the third contact portion is connected to the first drain region; a fourth contact extending in the second horizontal direction between the second gate electrode and the third gate electrode, wherein the fourth contact is spaced apart from the second contact in the second horizontal direction and connected to the second drain region; a fifth contact extending in the second horizontal direction between the third gate electrode and the fourth gate electrode, wherein the fifth contact is spaced apart from the third contact in the second horizontal direction and connected to the fourth source region; a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction below the gate cutout; and a through hole intersecting the gate cutout, wherein the through hole connects the lower wiring layer and the first contact portion, wherein each of the second contact portion and the fourth contact portion is electrically insulated from the lower wiring layer between the second gate electrode and the third gate electrode, and Wherein, each of the third contact portion and the fifth contact portion is electrically insulated from the lower wiring layer between the third gate electrode and the fourth gate electrode.

14. The semiconductor device according to claim 13, wherein: The gate cut is spaced apart from each of the second to fifth contacts in the second horizontal direction.

15. The semiconductor device according to claim 13, wherein: The gate cut is spaced apart from the lower wiring layer in a vertical direction between the second source region and the second drain region, and between the first drain region and the fourth source region.

16. The semiconductor device according to claim 13, wherein: The gate cut is spaced apart from the lower wiring layer in a vertical direction under the second gate electrode.

17. The semiconductor device according to claim 13, wherein: The lower wiring layer does not overlap each of the first active pattern and the second active pattern in a vertical direction.

18. The semiconductor device according to claim 13, further comprising: an etch stop layer, disposed along a sidewall of the first source region in the second horizontal direction; as well as an upper interlayer insulating layer covering the etch stop layer, Wherein, at least a portion of the through hole is in contact with the etching stop layer.

19. The semiconductor device according to claim 13, wherein: The first contact portion and the through hole are formed integrally, wherein each of the first contact portion and the through hole comprises a contact barrier layer and a contact filling layer, wherein the contact barrier layer forms a side wall and a bottom surface of the first contact portion and a side wall and a bottom surface of the through hole, and the contact filling layer is disposed on the contact barrier layer, and Wherein, the contact filling layer of the through hole contacts the contact filling layer of the first contact portion.

20. A semiconductor device comprising: Lower interlayer insulation layer; a first active pattern and a second active pattern extending in a first horizontal direction on the lower interlayer insulating layer, the second active pattern being spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; a first plurality of nanosheets stacked on the first active pattern and spaced apart from each other in a vertical direction; a second plurality of nanosheets stacked on the second active pattern and spaced apart from each other in the vertical direction; a gate electrode extending in the second horizontal direction on the first active pattern and the second active pattern, wherein the gate electrode at least partially surrounds the first plurality of nanosheets and the second plurality of nanosheets; a gate cutout extending in the first horizontal direction between the first active pattern and the second active pattern, wherein the gate cutout separates the gate electrodes in the second horizontal direction; a first source region disposed on a first side of the gate electrode on the first active pattern; a second source region disposed on a second side of the gate electrode on the first active pattern, the second side being opposite to the first side of the gate electrode in the first horizontal direction; a third source region disposed on the first side of the gate electrode on the second active pattern; a drain region disposed on the second side of the gate electrode on the second active pattern; a first contact extending in the second horizontal direction on the first side of the gate electrode, wherein the first contact is connected to each of the first source region and the third source region; a second contact extending in the second horizontal direction on the second side of the gate electrode, wherein the second contact is connected to the second source region; a third contact extending in the second horizontal direction on the second side of the gate electrode, wherein the third contact is spaced apart from the second contact in the second horizontal direction and connected to the drain region; a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction between the first active pattern and the second active pattern, wherein at least a portion of the lower wiring layer protrudes from an upper surface of the lower interlayer insulating layer in the vertical direction below the first contact portion, and wherein the lower wiring layer overlaps each of the first active pattern and the second active pattern in the vertical direction; a through hole disposed between the first source region and the third source region, wherein the through hole is formed integrally with the first contact portion, wherein the through hole intersects the gate cutout and connects the lower wiring layer and the first contact portion; a lower insulating layer disposed between the upper surface of the lower interlayer insulating layer and a lower surface of each of the first active pattern and the second active pattern, the lower insulating layer contacting the lower wiring layer; and a field insulating layer disposed on the upper surface of the lower interlayer insulating layer, wherein the field insulating layer at least partially surrounds each of: a sidewall of the lower insulating layer, a sidewall of the first active pattern, and a sidewall of the second active pattern, wherein each of the second contact portion and the third contact portion is electrically insulated from the lower wiring layer between the second source region and the drain region, and The upper surface of the lower insulating layer is formed to be higher than the upper surface of the lower wiring layer between the first source region and the third source region.

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