Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, an isolation structure and a first conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a platform structure disposed in the planar device region and a plurality of fin structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate, and the isolation structure includes a first portion and a second portion. A first portion of the isolation structure is disposed on the planar device region and covers a sidewall of the plateau structure, and a second portion of the isolation structure is disposed on the fin device region and between the plurality of fin-shaped structures. The first conductive structure is disposed on the planar device region. The first conductive structure is partially disposed on the platform structure in a vertical direction and partially disposed on the first portion of the isolation structure in the vertical direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device including a planar device region and a fin device region and a manufacturing method thereof. Background Art

[0002] The technology of semiconductor integrated circuits continues to advance and grow over time, and each new generation of products has a smaller and more complex circuit design than the previous generation. The number and density of functional components on each chip area must be continuously increased due to product innovation requirements, which of course means that the geometric dimensions of each component must become smaller and smaller. In integrated circuits, transistors are very important semiconductor components. In recent years, the relevant industry has proposed replacing planar transistor components with three-dimensional or non-planar multi-gate transistor components such as fin field effect transistors (FinFET) components. However, the manufacturing method of fin devices will affect the structure and characteristics of other devices in the integrated circuit, so how to improve the integration of the manufacturing methods between fin devices and other devices to meet product requirements is still the direction of continuous efforts by people in the relevant field. Summary of the invention

[0003] The present invention provides a semiconductor device and a manufacturing method thereof, which utilizes an isolation structure to cover the sidewall of a platform structure and extends a conductive structure onto the isolation structure, thereby improving the electrical performance of the planar device to meet product requirements.

[0004] One embodiment of the present invention provides a semiconductor device, including a semiconductor substrate, an isolation structure and a first conductive structure. The semiconductor substrate has a planar device region and a fin device region, and the semiconductor substrate includes a platform structure and a plurality of fin structures. The platform structure is disposed in the planar device region, and the plurality of fin structures are disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate, and the isolation structure includes a first portion and a second portion. The first portion is disposed on the planar device region and covers the sidewall of the platform structure, and the second portion is disposed on the fin device region and is located between the plurality of fin structures. The first conductive structure is disposed on the planar device region, and the first conductive structure is partially disposed on the platform structure in a vertical direction and partially disposed on the first portion of the isolation structure in a vertical direction.

[0005] In some embodiments, the semiconductor substrate further includes a base layer, wherein the platform structure and each fin-shaped structure protrude upward from an upper surface of the base layer, and a width of the platform structure is greater than a width of each fin-shaped structure.

[0006] In some embodiments, an upper surface of the first portion of the isolation structure is higher than an upper surface of the second portion of the isolation structure in a vertical direction.

[0007] In some embodiments, an upper surface of the first portion of the isolation structure is higher than or coplanar with an upper surface of the platform structure in a vertical direction.

[0008] In some embodiments, the first portion of the isolation structure includes a first region and a second region, the second region is connected to the first region, the first region is located between the sidewall of the platform structure and the second region, and the upper surface of the first region is higher than the upper surface of the second region in the vertical direction.

[0009] In some embodiments, an uppermost sidewall of the mesa structure is covered by a first portion of the isolation structure.

[0010] In some embodiments, the first portion of the isolation structure directly contacts an uppermost sidewall of the mesa structure.

[0011] In some embodiments, a bottom surface of the first conductive structure disposed over the first portion of the isolation structure in the vertical direction is higher than an upper surface of the mesa structure in the vertical direction.

[0012] In some embodiments, the semiconductor device further includes a second conductive structure disposed on the fin device region, the second conductive structure being disposed on the second portion of the isolation structure and spanning across the plurality of fin structures.

[0013] In some embodiments, the first conductive structure is connected to the second conductive structure.

[0014] One embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. A semiconductor substrate is provided, the semiconductor substrate having a planar device region and a fin device region, and the semiconductor substrate includes a platform structure and a plurality of fin structures. The platform structure is disposed in the planar device region, and the plurality of fin structures are disposed in the fin device region. An isolation structure is formed on the semiconductor substrate, and the isolation structure includes a first portion and a second portion. The first portion is disposed on the planar device region and covers the sidewall of the platform structure, and the second portion is disposed on the fin device region and is located between the plurality of fin structures. A first conductive structure is formed on the planar device region, the first conductive structure being partially disposed on the platform structure in a vertical direction and partially disposed on the first portion of the isolation structure in a vertical direction.

[0015] In some embodiments, a method for forming an isolation structure includes forming an insulating material on a semiconductor substrate, wherein a first portion of the insulating material is formed on a planar device region and covers the sidewalls of the platform structure, and a second portion of the insulating material is formed on a fin device region and is located between a plurality of fin structures; and performing an etching process on the insulating material to remove a portion of the second portion of the insulating material and expose an upper portion of each fin structure, wherein a mask layer covers the platform structure and at least a portion of the first portion of the insulating material during the etching process, and a portion of the first portion of the insulating material is removed by the etching process.

[0016] In some embodiments, after the etching process, an upper surface of the second portion of the insulating material is lower than an upper surface of each fin structure in a vertical direction.

[0017] In some embodiments, after the etching process, the uppermost sidewall of the mesa structure is covered by the first portion of the insulating material.

[0018] In some embodiments, the second portion of the insulating material is partially removed by the etching process to form a second portion of the isolation structure.

[0019] In some embodiments, the method of forming an isolation structure also includes performing a removal process after the etching process, wherein the mask layer is removed before the removal process, and the first portion of the insulating material is partially removed by the etching process and the removal process to become the first portion of the isolation structure.

[0020] In some embodiments, the first portion of the isolation structure includes a first region and a second region, the second region is connected to the first region, wherein the first region is located between the sidewall of the platform structure and the second region, and the upper surface of the first region is higher than the upper surface of the second region in a vertical direction.

[0021] In some embodiments, after the removal process, a sidewall of an uppermost portion of the mesa structure is covered by a first region of the first portion of the isolation structure.

[0022] In some embodiments, the manufacturing method further includes forming a second conductive structure on the fin device region, wherein the second conductive structure is disposed on the second portion of the isolation structure and straddles the plurality of fin structures.

[0023] In some embodiments, the first conductive structure and the second conductive structure are formed by the same manufacturing process and are connected to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0025] Figures 2 to 6FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein

[0026] Figure 3 for Figure 2 Schematic diagram of the situation afterwards;

[0027] Figure 4 for Figure 3 Schematic diagram of the situation afterwards;

[0028] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0029] Figure 6 for Figure 5 Schematic diagram of the situation afterwards;

[0030] Figure 7 is a schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0031] Figure 8 is a schematic diagram of a semiconductor device according to a third embodiment of the present invention;

[0032] Fig. 9 FIG. 4 is a schematic diagram of a semiconductor device according to a fourth embodiment of the present invention.

[0033] Explanation of symbols

[0034] 10: Semiconductor substrate

[0035] 10A: Base

[0036] 10C: Fin structure

[0037] 10F: Fin structure

[0038] 10P: Platform Structure

[0039] 22: Mask layer

[0040] 22A: Part 1

[0041] 22B: Part 2

[0042] 24: Insulation layer

[0043] 26: Insulation layer

[0044] 28: Insulation layer

[0045] 29: Insulation material

[0046] 29A: Part 1

[0047] 29B: Part 2

[0048] 30: Mask layer

[0049] 32: Dielectric materials

[0050] 32A: Interface layer

[0051] 32B: Interface layer

[0052] 34A: Interstitial

[0053] 34B: Interstitial

[0054] 36: Dielectric layer

[0055] 91: Etching process

[0056] 92: Remove crafting process

[0057] 101: Semiconductor Device

[0058] 102: Semiconductor device

[0059] 103: Semiconductor device

[0060] 104: Semiconductor device

[0061] BS: Bottom surface

[0062] BS1: Bottom surface

[0063] BS2: Bottom surface

[0064] BS3: Bottom surface

[0065] BS4: Bottom surface

[0066] CS: Conductive Structure

[0067] CS1: First conductive structure

[0068] CS2: Second conductive structure

[0069] D1: Vertical direction

[0070] D2: Horizontal direction

[0071] DL: Dielectric Layer

[0072] DL1: Dielectric layer

[0073] DL2: Dielectric layer

[0074] GS1: First gate structure

[0075] GS2: Second gate structure

[0076] IS: Isolation Structure

[0077] LS: Ladder structure

[0078] P1: Part 1

[0079] P2: Part 2

[0080] R1: Planar device area

[0081] R2: Fin device area

[0082] SP1: Part 1

[0083] SP2: Part 2

[0084] SS1: District 1

[0085] SS2: District 2

[0086] SW: Sidewall

[0087] TS: Top surface

[0088] TS1: Top surface

[0089] TS2: Top surface

[0090] TS3: Top surface

[0091] TS4: Top surface

[0092] TS5: Top surface

[0093] TS6: Top surface

[0094] TS7: Upper surface

[0095] TS8: Upper surface

[0096] W1: Width

[0097] W2: Width DETAILED DESCRIPTION

[0098] The following detailed description of the present invention has disclosed enough details to enable those skilled in the art to practice the present invention. The embodiments set forth below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

[0099] Before further describing each embodiment, specific terms used throughout the text are explained below.

[0100] The meanings of the terms "on," "over," and "over" should be interpreted in the broadest manner, so that "on" means not only "directly on" something, but also includes being on something with other intervening features or layers therebetween, and "over" or "over" means not only being "on" or "over" something, but also includes being "on" or "over" something with no other intervening features or layers therebetween (i.e., directly on something).

[0101] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the requested element, nor do they represent the order of one requested element and another requested element, or the order in the manufacturing method. The use of these ordinals is only used to clearly distinguish a requested element with a certain name from another requested element with the same name.

[0102] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material is left after the etching is complete. When "etching" a material, at least a portion of the material may be retained after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0103] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a material layer to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0104] See also Figure 1 . Figure 1 FIG. 1 is a schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 1As shown, the semiconductor device 101 includes a semiconductor substrate 10, an isolation structure IS, and a first conductive structure CS1. The semiconductor substrate 10 has a planar device region R1 and a fin device region R2, and the semiconductor substrate 10 includes a mesa structure 10P and a plurality of fin structures 10F. The mesa structure 10P is disposed in the planar device region R1, and the plurality of fin structures 10F are disposed in the fin device region R2. The isolation structure IS is disposed on the semiconductor substrate 10, and the isolation structure IS includes a first portion P1 and a second portion P2. The first portion P1 is disposed on the planar device region R1 and covers the sidewall SW of the mesa structure 10P, and the second portion P2 is disposed on the fin device region R2 and is located between the plurality of fin structures 10F. The first conductive structure CS1 is disposed on the planar device region R1, and the first conductive structure CS1 is partially disposed on the mesa structure 10P in a vertical direction D1 and partially disposed on the first portion P1 of the isolation structure IS in the vertical direction D1. By covering the side wall SW of the platform structure 10P with the first portion P1 of the isolation structure IS and extending the first conductive structure CS1 onto the first portion P1 of the isolation structure IS, the electrical performance of the planar device corresponding to the first conductive structure CS1 can be improved, for example but not limited to improving the capacitance stability of a planar metal-oxide-semiconductor capacitor (MOSCAP) device to meet the requirements of related products.

[0105] In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. The semiconductor substrate 10 may be defined with the above-mentioned planar device region R1 and fin device region R2, and the planar device region R1 and the fin device region R2 may be separated from each other or disposed adjacently according to design requirements. In addition, the semiconductor substrate 10 may also include a base layer 10A, which may be partially located in the planar device region R1 and partially located in the fin device region R2, the platform structure 10P may protrude upward along the vertical direction D1 from the upper surface TS of the base layer 10A located in the planar device region R1, and each fin-shaped structure 10F may protrude upward along the vertical direction D1 from the upper surface TS of the base layer 10A located in the fin device region R2. The material composition of at least a portion (e.g., the upper portion) of the base layer 10A may be the same or similar to the material composition of the platform structure 10P and / or the material composition of the fin structure 10F, and the base layer 10A may be directly connected to the platform structure 10P and the fin structure 10F, respectively. For example, the base layer 10A, the platform structure 10P, and the fin structure 10F may include the same semiconductor material (e.g., silicon), and the platform structure 10P and / or the fin structure 10F may be implanted with the required dopants through a doping process according to design requirements (e.g., the electrical adjustment requirements of the corresponding semiconductor device), but is not limited to this. In other words, the platform structure 10P and the fin structure 10F may be structures formed by patterning the semiconductor substrate 10, respectively, and the conductive type and / or doping conditions of the platform structure 10P and the fin structure 10F may be the same or different according to design requirements.

[0106] In some embodiments, the vertical direction D1 can be regarded as the thickness direction of the semiconductor substrate 10 or / and the base layer 10A. The base layer 10A can have an upper surface TS and a bottom surface BS opposite to each other in the vertical direction D1, and the isolation structure IS and the first conductive structure CS1 can be disposed on one side of the upper surface TS of the base layer 10A. The horizontal direction substantially orthogonal to the vertical direction D1 (e.g., the horizontal direction D2 and other directions orthogonal to the vertical direction D1) can be substantially parallel to the upper surface TS and / or the bottom surface BS of the base layer 10A, but is not limited thereto. The distance between the relatively high position or / and component in the vertical direction D1 and the bottom surface BS of the base layer 10A in the vertical direction D1 described herein may be greater than the distance between the relatively low position or / and component in the vertical direction D1 and the bottom surface BS of the base layer 10A in the vertical direction D1, the lower part or bottom of each component may be closer to the bottom surface BS of the base layer 10A in the vertical direction D1 than the upper part or top of the component, another component above a certain component may be regarded as relatively far away from the bottom surface BS of the base layer 10A in the vertical direction D1, and another component below a certain component may be regarded as relatively close to the bottom surface BS of the base layer 10A in the vertical direction D1. It is worth noting that the upper surface of a certain component described herein may include the topmost surface of the component in the vertical direction D1, and the bottom surface of a certain component may include the bottommost surface of the component in the vertical direction D1, but it is not limited thereto. In addition, the situation in which a specific component is set between two other objects in a certain direction described herein may include but is not limited to the situation in which the component is sandwiched between the two objects in this direction.

[0107] In some embodiments, each fin structure 10F may extend along another horizontal direction different from the horizontal direction D2 (for example, but not limited to, another horizontal direction orthogonal to the horizontal direction D2), and the length of each fin structure 10F in the horizontal direction D2 may be regarded as the width of each fin structure 10F, and the width of the platform structure 10P (for example, the length of the platform structure 10P in the horizontal direction D2) may be significantly greater than the width of each fin structure 10F, but is not limited thereto. In addition, the semiconductor substrate 10 may further include a fin structure 10C protruding upward from the upper surface TS of the base layer 10A located in the fin device region R2 along the vertical direction D1, and the height of the fin structure 10C in the vertical direction D1 may be less than the height of each fin structure 10F in the vertical direction D1. The fin structure 10C may be completely covered by the isolation structure IS, and the fin structure 10C may be regarded as a structure remaining on the base layer 10A after the fin structure 10F undergoes a fin removal process or a fin cutting process, but is not limited thereto.

[0108] In some embodiments, the isolation structure IS may include a single layer or multiple layers of insulating materials such as silicon oxide, silicon nitride or other suitable insulating materials. For example, the isolation structure IS may include an insulating layer 24, an insulating layer 26 and an insulating layer 28 arranged in a stacked manner, the insulating layer 24 may include an oxide insulating material formed by an in-situ steam generation (ISSG) technique, the insulating layer 26 may include an oxide insulating material formed by an atomic layer deposition (ALD) process, and the insulating layer 28 may include an oxide insulating material formed by spin coating, but the invention is not limited thereto. In some embodiments, the upper surface (e.g., the upper surface TS6) of the first portion P1 of the isolation structure IS may be higher than the upper surface TS8 of the second portion P2 of the isolation structure IS in the vertical direction D1, and the upper surface TS6 of the first portion P1 of the isolation structure IS may be higher than the upper surface TS1 of the platform structure 10P in the vertical direction D1 or may be substantially coplanar with the upper surface TS1 of the platform structure 10P. In addition, the upper surface TS8 of the second portion P2 of the isolation structure IS may be lower than the upper surface TS2 of each fin structure 10F in the vertical direction D1, the upper portion of each fin structure 10F is not covered by the isolation structure IS, and the upper surface TS2 of each fin structure 10F and the upper surface TS1 of the platform structure 10P may be substantially coplanar, but not limited to this. In some embodiments, the first portion P1 of the isolation structure IS may include a first region SS1 and a second region SS2, the second region SS2 may be directly connected to the first region SS1, the first region SS1 may be located between the sidewall SW of the platform structure 10P and the second region SS2 in the horizontal direction (for example, but not limited to the horizontal direction D2), and the first region SS1 may directly contact the sidewall SW of the platform structure 10P. Furthermore, an upper surface TS6 of the first region SS1 may be higher than an upper surface TS7 of the second region SS2 in the vertical direction D1, and an upper surface TS6 of the first region SS1 may be higher than or coplanar with an upper surface TS1 of the mesa structure 10P in the vertical direction D1.

[0109] In some embodiments, the sidewall SW of the platform structure 10P may be completely covered by the isolation structure IS (e.g., the insulating layer 24 of the first portion P1) in the horizontal direction, so the uppermost sidewall SW of the platform structure 10P in the vertical direction D1 may be covered by the first portion P1 of the isolation structure IS in the horizontal direction, and the first portion P1 of the isolation structure IS (e.g., the insulating layer 24) may directly contact the uppermost sidewall SW of the platform structure 10P. The first conductive structure CS1 may be partially disposed on the platform structure 10P and partially disposed on the first portion P1 (e.g., the first region SS1) of the isolation structure IS, and the bottom surface BS3 of the first conductive structure CS1 disposed on the isolation structure IS may be higher than the upper surface TS1 of the platform structure 10P in the vertical direction D1. In some embodiments, the semiconductor device 101 may further include a dielectric layer DL1 disposed on the planar device region R1, and the dielectric layer DL1 may be partially disposed on the platform structure 10P in the vertical direction D1 and partially disposed on the first portion P1 (e.g., the first region SS1) of the isolation structure IS in the vertical direction D1. The dielectric layer DL1 disposed on the platform structure 10P may be sandwiched between the first conductive structure CS1 and the platform structure 10P in the vertical direction D1, and the dielectric layer DL1 disposed on the first portion P1 of the isolation structure IS may be at least partially sandwiched between the first conductive structure CS1 and the first portion P1 of the isolation structure IS in the vertical direction D1, and the dielectric layer DL1 and the first conductive structure CS1 may form a first gate structure GS1, but is not limited to this. In some embodiments, the first conductive structure CS1, the platform structure 10P, and the dielectric material (such as but not limited to the dielectric layer DL1) sandwiched between the first conductive structure CS1 and the platform structure 10P can form at least a portion of a planar metal-oxide-semiconductor capacitor (MOSCAP) device, and the first conductive structure CS1 can be regarded as an electrode (such as an upper electrode) in the capacitor device, and the first conductive structure CS1 can be extended to be disposed on the isolation structure IS by covering the sidewall SW of the platform structure 10P through the first portion P1 of the isolation structure IS, thereby increasing the overlapping area between the first conductive structure CS1 and the platform structure 10P in the vertical direction D1 and avoiding the first conductive structure CS1 or / and the first gate structure GS1 covering the sidewall SW of the platform structure 10P to affect the electrical properties of the planar capacitor device (such as but not limited to the capacitance stability), but the invention is not limited thereto. In some embodiments, the first conductive structure CS1 and the platform structure 10P can also be used to form other suitable planar devices.

[0110] In some embodiments, the semiconductor device 101 may further include a second conductive structure CS2 and a dielectric layer DL2, wherein the second conductive structure CS2 and the dielectric layer DL2 are disposed on the fin device region R2, and the second conductive structure CS2 is disposed on the dielectric layer DL2. The second conductive structure CS2 and the dielectric layer DL2 are disposed on the second portion P2 of the isolation structure IS and straddle the plurality of fin structures 10F, so that the dielectric layer DL2 may be partially sandwiched between the second conductive structure CS2 and the isolation structure IS and partially sandwiched between the second conductive structure CS2 and the fin structure 10F. In some embodiments, the dielectric layer DL2 and the second conductive structure CS2 may constitute a second gate structure GS2, and the second conductive structure CS2, the fin structure 10F, and the dielectric material (such as but not limited to the dielectric layer DL2) sandwiched between the second conductive structure CS2 and the fin structure 10F may form at least a portion of a fin-type semiconductor device (such as a transistor, a capacitor, or other suitable semiconductor devices), but is not limited thereto. In some embodiments, the first conductive structure CS1 and the second conductive structure CS2 may respectively include a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate structure formed by stacking a work function layer and a low resistance layer, and the material composition of the first conductive structure CS1 and the material composition of the second conductive structure CS2 may be the same or different from each other depending on design requirements. The low resistance layer may include, for example, tungsten, aluminum, copper, titanium aluminide, titanium or other suitable low resistance materials, and the work function layer may include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl3), aluminum titanium nitride (TiAlN) or other suitable conductive work function materials. The dielectric layer DL1 and the dielectric layer DL2 may include gate oxide, high-k dielectric material or other suitable dielectric materials respectively, and the material composition of the dielectric layer DL1 and the material composition of the dielectric layer DL2 may be the same or different depending on design requirements.

[0111] In some embodiments, the bottom surface BS1 of the first gate structure GS1 disposed on the isolation structure IS may be higher than the upper surface TS1 of the platform structure 10P in the vertical direction D1 or substantially coplanar with the upper surface TS1 of the platform structure 10P, and the bottom surface BS1 of the first gate structure GS1 disposed on the isolation structure IS may be higher than the bottom surface BS2 of the second gate structure GS2 disposed on the isolation structure IS and the bottom surface BS4 of the second conductive structure CS2 in the vertical direction D1. In addition, in some embodiments, the semiconductor device 101 may further include an interface layer 32A, an interface layer 32B, a spacer 34A, a spacer 34B, and a dielectric layer 36. The interface layer 32A may be disposed on the platform structure 10P and sandwiched between the platform structure 10P and the dielectric layer DL1 in the vertical direction D1, and the interface layer 32B may be disposed on the fin structure 10F not covered by the isolation structure IS and sandwiched between the fin structure 10F and the dielectric layer DL2. In some embodiments, the interface layer 32A and the interface layer 32B may respectively include an oxide dielectric material (e.g., an oxide material formed by an on-site vapor generation technique) or other suitable dielectric materials, and the material composition of the interface layer 32A and the material composition of the interface layer 32B may be the same or different from each other depending on design requirements. The spacer 34A may be disposed on the planar device region R1, the spacer 34A may be disposed on the second region SS2 of the first portion P1 of the isolation structure IS in the vertical direction D1, and the spacer 34A may be disposed on the sidewall of the first gate structure GS1 and the sidewall of the first region SS1 of the first portion P1 of the isolation structure IS in the horizontal direction. The spacer 34B may be disposed on the fin device region R2, the spacer 34B may be disposed on the isolation structure IS in the vertical direction D1, and the spacer 34B may be disposed on the sidewall of the second gate structure GS2 in the horizontal direction. In some embodiments, the spacers 34A and the spacers 34B may respectively include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials, and the material composition of the spacers 34A and the material composition of the spacers 34B may be the same or different from each other depending on the design requirements. The dielectric layer 36 may be disposed on the planar device region R1 and the fin device region R2. The dielectric layer 36 disposed on the planar device region R1 may surround the spacers 34A and the first gate structure GS1 in the horizontal direction, and the dielectric layer 36 disposed on the fin device region R2 may surround the spacers 34B and the second gate structure GS2 in the horizontal direction. In some embodiments, the dielectric layer 36 may include a single layer or multiple layers of dielectric materials, for example, the dielectric layer 36 may include an etch stop layer and a dielectric material disposed on the etch stop layer and having a different material composition from the etch stop layer, but is not limited thereto.

[0112] See also Figure 1 as well as Figures 2 to 6 . Figures 2 to 6FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 3 Draws Figure 2 The following diagram shows the situation: Figure 4 Draws Figure 3 The following diagram shows the situation: Figure 5 Draws Figure 4 The following diagram shows the situation: Figure 6 Draws Figure 5 In some embodiments, Figure 1 can be considered as depicting Figure 6 The following is a schematic diagram of the situation, but it is not limited to this. Figure 1 As shown, the method for manufacturing a semiconductor device of the present embodiment may include the following steps. A semiconductor substrate 10 is provided, the semiconductor substrate 10 has a planar device region R1 and a fin device region R2, and the semiconductor substrate 10 includes a platform structure 10P and a plurality of fin structures 10F. The platform structure 10P is disposed in the planar device region R1, and the plurality of fin structures 10F are disposed in the fin device region R2. An isolation structure IS is formed on the semiconductor substrate 10, and the isolation structure IS includes a first portion P1 and a second portion P2. The first portion P1 is disposed on the planar device region R1 and covers the sidewall SW of the platform structure 10P, and the second portion P2 is disposed on the fin device region R2 and is located between the plurality of fin structures 10F. Then, a first conductive structure CS1 is formed on the planar device region R1, and the first conductive structure CS1 is partially disposed on the platform structure 10P in the vertical direction D1 and partially disposed on the first portion P1 of the isolation structure IS in the vertical direction D1.

[0113] Further explanation, the preparation method of the present invention may include but is not limited to the following steps. Figure 2As shown, the above-mentioned platform structure 10P and fin structure 10F can be formed by patterning the semiconductor substrate 10, and the fin structure 10C can be regarded as a structure remaining on the base layer 10A after a fin removal process or a fin cutting process is performed on a portion of the fin structure 10F, but it is not limited thereto. Each fin structure 10F can extend along another horizontal direction different from the horizontal direction D2, and the length of each fin structure 10F in the horizontal direction D2 can be regarded as the width W2 of each fin structure 10F, and the width W1 of the platform structure 10P (for example, the length of the platform structure 10P in the horizontal direction D2) can be significantly greater than the width W2 of each fin structure 10F. In some embodiments, a mask layer 22 can be formed on the semiconductor substrate 10 before the above-mentioned patterning process, and after the patterning process, the mask layer 22 may include a first portion 22A located on the platform structure 10P and a second portion 22B located on the fin structure 10F. After the platform structure 10P, the fin structure 10F, and the fin structure 10C are formed, an insulating material 29 may be formed on the semiconductor substrate 10, a first portion 29A of the insulating material 29 may be formed on the planar device region R1 and cover the sidewall SW of the platform structure 10P, and a second portion 29B of the insulating material 29 may be formed on the fin device region R2 and located between the plurality of fin structures 10F. The insulating material 29 may include a single layer or multiple layers of insulating material, such as the insulating layer 24, the insulating layer 26, and the insulating layer 28 stacked as described above, but not limited thereto. In some embodiments, the insulating material 29 may be subjected to a planarization process, so that the upper surface of the insulating material 29 and the upper surface of the mask layer 22 may be substantially coplanar, but not limited thereto.

[0114] like Figures 2 to 4As shown, an etching process 91 may be performed on the insulating material 29 to remove a portion of the second portion 29B of the insulating material 29 and the second portion 22B of the mask layer 22 to expose the upper portion of each fin structure 10F. Therefore, after the etching process 91, the upper surface TS5 of the second portion 29B of the insulating material 29 may be lower than the upper surface TS2 of each fin structure 10F in the vertical direction D1. In some embodiments, the second portion 29B of the insulating material 29 may be partially removed by the etching process 91 to become the second portion P2 of the isolation structure IS described above. In some embodiments, before the etching process 91, a mask layer 30 may be formed on the planar device region R1, and the mask layer 30 may cover the platform structure 10P and the first portion 22A of the mask layer 22 in the vertical direction D1, and the mask layer 30 may cover at least a portion of the first portion 29A of the insulating material 29 in the vertical direction D1. The mask layer 30 may be used as an etching mask in the etching process 91, and the mask layer 30 may include photoresist or other suitable mask materials. Therefore, in the etching process 91, the mask layer 30 may cover the platform structure 10P and at least a portion of the first portion 29A of the insulating material 29, and a portion of the first portion 29A of the insulating material 29 (e.g., a portion of the first portion 29A that is not covered by the mask layer 30 in the vertical direction D1) may be removed by the etching process 91. Therefore, after the etching process 91, the upper surface TS3 of the portion of the first portion 29A of the insulating material 29 that is directly connected to the platform structure 10P may be higher than the upper surface TS4 of the portion of the first portion 29A of the insulating material 29 that is farther away from the platform structure 10P in the vertical direction D1, and the sidewall SW of the uppermost portion of the platform structure 10P may be covered by the first portion 29A of the insulating material 29 both during and after the etching process 91.

[0115] like Figures 3 to 5As shown, after the etching process 91, a removal process 92 may be performed, and the mask layer 30 may be removed before the removal process 92. The first portion 29A of the insulating material 29 may be partially removed by the etching process 91 and the removal process 92 to become the first portion P1 of the isolation structure IS mentioned above, and the upper surface TS5 of the second portion P2 of the isolation structure IS may be slightly lowered by the removal process 92 to become the upper surface TS8 mentioned above. Therefore, the first portion P1 of the isolation structure IS may include the first region SS1 and the second region SS2 mentioned above, and the surface step difference between the first region SS1 and the second region SS2 may be regarded as a step structure LS, but is not limited thereto. In addition, the first portion 22A of the mask layer 22 may be removed by the removal process 92 to expose the upper surface TS1 of the platform structure 10P. In some embodiments, the removal process 92 may include an etching process, a cleaning process or other suitable removal methods, such as a removal method with a low destruction or / and etching rate for the platform structure 10P and the fin structure 10F, so as to reduce damage to the platform structure 10P and the fin structure 10F. For example, the first portion 22A of the mask layer 22 may be removed by selecting a relatively high isotropic wet etching or wet cleaning process, but is not limited to this. In addition, after the removal process 92, the uppermost sidewall SW of the platform structure 10P may still be covered by the first region SS1 of the first portion P1 of the isolation structure IS, so as to prevent the subsequently formed conductive structure from covering the sidewall SW of the platform structure 10P. It is worth noting that in the present invention, the method of forming the isolation structure IS may include but is not limited to the above-mentioned Figures 2 to 5 The steps shown in the figure can be formed by other suitable methods as required by the design. Figure 5 The isolation structure IS shown in .

[0116] like Figure 6 As shown, after forming the isolation structure IS, the above-mentioned interface layer 32A and interface layer 32B may be formed. In some embodiments, the interface layer 32A and interface layer 32B may be formed by an on-site vapor generation technique, so the interface layer 32A may be formed on the upper surface TS1 of the exposed platform structure 10P and the interface layer 32B may be formed on the surface of the exposed fin structure 10F, and the material composition of the interface layer 32A may be substantially the same as the material composition of the interface layer 32B (for example, both are dielectric material 32), but this is not limited to this. Then, as Figure 1As shown, the above-mentioned spacers 34A, 34B, dielectric layer 36, dielectric layer DL1, dielectric layer DL2, first conductive structure CS1 and second conductive structure CS2 are formed. The first conductive structure CS1 and dielectric layer DL1 may be formed on the planar device region R1, and the first conductive structure CS1 and dielectric layer DL1 may be partially located on the interface layer 32A and partially located on the first portion P1 of the isolation structure IS. The second conductive structure CS2 and dielectric layer DL2 may be formed on the fin device region R2, and the second conductive structure CS2 and dielectric layer DL2 may be located on the second portion P2 of the isolation structure IS and straddled on multiple fin structures 10F. In some embodiments, the first gate structure GS1 and the second gate structure GS2 can be formed by a replacement metal gate (RMG), so the spacer 34A, the spacer 34B and the dielectric layer 36 can be formed before the first gate structure GS1 and the second gate structure GS2, and the upper surface of the dielectric layer 36, the upper surface of the first gate structure GS1 and the upper surface of the second gate structure GS2 can be substantially coplanar, but is not limited to this.

[0117] The following will describe different embodiments of the present invention, and for simplicity, the following description will mainly describe the differences between the embodiments, and will not repeat the same parts. In addition, the same elements in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0118] See also Figure 7 . Figure 7 FIG. 1 is a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 7As shown, in the semiconductor device 102, the first conductive structure CS1 and the second conductive structure CS2 may be directly connected. For example, a dielectric layer DL and a conductive structure CS may be formed on the planar device region R1 and the fin device region R2, the dielectric layer DL on the planar device region R1 may be located on the platform structure 10P, the interface layer 32A and the first portion P1 of the isolation structure IS, the dielectric layer DL on the fin device region R2 may be located on the fin structure 10F, the interface layer 32A and the second portion P2 of the isolation structure IS, and the conductive structure CS may be formed on the dielectric layer DL. The conductive structure CS may include a non-metallic conductive material (e.g., doped polysilicon) or a metal conductive material, such as a metal gate structure formed by stacking a work function layer and a low resistance layer, and the dielectric layer DL may include a gate oxide, a high dielectric constant (high-k) dielectric material or other suitable dielectric materials. The conductive structure CS disposed on the planar device region R1 may be regarded as the above-mentioned first conductive structure CS1, and the conductive structure CS disposed on the fin device region R2 may be regarded as the above-mentioned second conductive structure CS2, the first conductive structure CS1 and the dielectric layer DL disposed on the planar device region R1 may constitute the above-mentioned first gate structure GS1, and the second conductive structure CS2 and the dielectric layer DL disposed on the fin device region R2 may constitute the above-mentioned second gate structure GS2. In other words, the first conductive structure CS1 and the second conductive structure CS2 may be formed together by the same manufacturing process and directly connected to each other, and the material composition of the first conductive structure CS1 may be the same as the material composition of the second conductive structure CS2.

[0119] See also Figure 8 . Figure 8 FIG. 1 is a schematic diagram of a semiconductor device 103 according to a third embodiment of the present invention. Figure 8 As shown, in the semiconductor device 103, the spacer 34A may be partially formed on the upper surface TS6 of the first region SS1 of the first portion P1 of the isolation structure IS and partially formed on the upper surface TS7 of the second region SS2 of the first portion P1 of the isolation structure IS. For example, the first portion SP1 of the spacer 34A may be located on the upper surface TS6 of the first region SS1 in the vertical direction D1 and cover the sidewall of the first gate structure GS1 in the horizontal direction, and the second portion SP2 of the spacer 34A may be located on the upper surface TS7 of the second region SS2 in the vertical direction D1 and cover the sidewall of the first region SS1 in the horizontal direction. In some embodiments, the spacer 34B and the first portion SP1 and the second portion SP2 of the spacer 34A may have the same material composition, and the first portion SP1 and the second portion SP2 of the spacer 34A may be separated from each other and not directly connected, but the present invention is not limited thereto.

[0120] See also Fig. 9 . Fig. 9FIG. 1 is a schematic diagram of a semiconductor device 104 according to a fourth embodiment of the present invention. Fig. 9 As shown, in the semiconductor device 104, the upper surface of the first portion P1 of the isolation structure IS (e.g., the upper surface TS6 of the first region SS1) may be higher than the upper surface TS1 of the platform structure 10P in the vertical direction D1, so the first portion P1 of the isolation structure IS (e.g., the first region SS1) may completely cover the sidewall SW of the platform structure 10P in the horizontal direction and partially cover the sidewall of the interface layer 32A, but the invention is not limited thereto. Therefore, the bottom surface BS1 of the first gate structure GS1 formed on the first portion P1 of the isolation structure IS and the bottom surface BS3 of the first conductive structure CS1 formed on the first portion P1 of the isolation structure IS may be higher than the upper surface TS1 of the platform structure 10P in the vertical direction D1, respectively.

[0121] In summary, in the semiconductor device and the manufacturing method thereof of the present invention, when the first portion of the isolation structure covers the sidewall of the platform structure, the first conductive structure can extend to the first portion of the isolation structure, thereby increasing the overlapping area between the first conductive structure and the platform structure and avoiding the first conductive structure covering the sidewall of the platform structure and affecting the electrical performance of the planar device. For example, when the planar device is a planar metal oxide semiconductor capacitor device, the capacitance value of the capacitor device can be increased or / and the capacitance stability of the capacitor device can be improved to meet the requirements of related products.

[0122] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: A semiconductor substrate having a planar device region and a fin device region, wherein the semiconductor substrate comprises: a platform structure disposed in the planar device area; and a plurality of fin-shaped structures disposed in the fin-type device area; An isolation structure is provided on the semiconductor substrate, wherein the isolation structure comprises: A first portion is disposed on the planar device area and covers a sidewall of the platform structure; and a second portion disposed on the fin device region and located between the plurality of fin-shaped structures; and A first conductive structure is disposed on the planar device region, wherein the first conductive structure is partially disposed on the platform structure in a vertical direction and partially disposed on the first portion of the isolation structure in the vertical direction.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate further comprises: The base layer, wherein the platform structure and each of the fin-shaped structures protrude upward from the upper surface of the base layer, and the width of the platform structure is greater than the width of each of the fin-shaped structures. 3 . The semiconductor device as claimed in claim 1 , wherein an upper surface of the first portion of the isolation structure is higher than an upper surface of the second portion of the isolation structure in the vertical direction. 4 . The semiconductor device as claimed in claim 1 , wherein an upper surface of the first portion of the isolation structure is higher than an upper surface of the mesa structure or is coplanar with the upper surface of the mesa structure in the vertical direction.

5. The semiconductor device of claim 1 , wherein the first portion of the isolation structure comprises: District 1; and The second area is connected to the first area, wherein the first area is located between the side wall of the platform structure and the second area, and the upper surface of the first area is higher than the upper surface of the second area in the vertical direction. The semiconductor device as claimed in claim 1 , wherein an uppermost sidewall of the mesa structure is covered by the first portion of the isolation structure. 7 . The semiconductor device of claim 1 , wherein the first portion of the isolation structure directly contacts an uppermost sidewall of the mesa structure. 8 . The semiconductor device of claim 1 , wherein a bottom surface of the first conductive structure disposed on the first portion of the isolation structure in the vertical direction is higher than an upper surface of the mesa structure in the vertical direction.

9. The semiconductor device according to claim 1, further comprising: A second conductive structure is disposed on the fin device region, wherein the second conductive structure is disposed on the second portion of the isolation structure and straddles the plurality of fin structures. 10 . The semiconductor device as claimed in claim 9 , wherein the first conductive structure is connected to the second conductive structure.

11. A method for manufacturing a semiconductor device, comprising: A semiconductor substrate is provided, wherein the semiconductor substrate has a planar device region and a fin device region, wherein the semiconductor substrate comprises: a platform structure disposed in the planar device area; and a plurality of fin-shaped structures disposed in the fin-type device area; An isolation structure is formed on the semiconductor substrate, wherein the isolation structure comprises: A first portion is disposed on the planar device area and covers a sidewall of the platform structure; and a second portion disposed on the fin device region and located between the plurality of fin-shaped structures; and A first conductive structure is formed on the planar device region, wherein the first conductive structure is partially disposed on the platform structure in a vertical direction and partially disposed on the first portion of the isolation structure in the vertical direction.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein a method of forming the isolation structure comprises: forming an insulating material on the semiconductor substrate, wherein a first portion of the insulating material is formed on the planar device region and covers the sidewall of the mesa structure, and a second portion of the insulating material is formed on the fin device region and is located between the plurality of fin structures; as well as The insulating material is subjected to an etching process to remove a portion of the second portion of the insulating material and expose an upper portion of each of the fin structures, wherein the mask layer covers the platform structure and at least a portion of the first portion of the insulating material during the etching process, and a portion of the first portion of the insulating material is removed by the etching process. 13 . The method for fabricating a semiconductor device according to claim 12 , wherein after the etching process, an upper surface of the second portion of the insulating material is lower than an upper surface of each of the fin structures in the vertical direction. 14 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein after the etching process, an uppermost sidewall of the mesa structure is covered by the first portion of the insulating material. 15 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein the second portion of the insulating material is partially removed by the etching process to become the second portion of the isolation structure.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the method for forming the isolation structure further comprises: A removal process is performed after the etching process, wherein the mask layer is removed before the removal process, and the first portion of the insulating material is partially removed by the etching process and the removal process to become the first portion of the isolation structure.

17. The method for fabricating a semiconductor device according to claim 16, wherein the first portion of the isolation structure comprises: District 1; and The second area is connected to the first area, wherein the first area is located between the side wall of the platform structure and the second area, and the upper surface of the first area is higher than the upper surface of the second area in the vertical direction. 18 . The method for manufacturing a semiconductor device according to claim 17 , wherein after the removal process, a sidewall of an uppermost portion of the mesa structure is covered by the first region of the first portion of the isolation structure.

19. The method for manufacturing a semiconductor device according to claim 11, further comprising: A second conductive structure is formed on the fin device region, wherein the second conductive structure is disposed on the second portion of the isolation structure and spans the plurality of fin structures. 20 . The method for manufacturing a semiconductor device as claimed in claim 19 , wherein the first conductive structure and the second conductive structure are formed by a same manufacturing process and are connected to each other.

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