Verification device for detector chip material performance and process capability

Abstract

The present invention relates to a verification device for the material performance and process capability of a detector chip, and belongs to the field of infrared detector chip manufacturing. The infrared detector material of the nBp stacked structure grown on a GaSb substrate integrates: a chip structure with photosensitive element areas of different sizes; a plurality of metal-insulating layer-semiconductor structures, wherein the capacitance area of ​​at least one metal-insulating layer-semiconductor structure is 1000-20000 times that of other capacitance areas; a transmission line model structure formed by rectangular electrodes with unequal intervals distributed in the n-type electrode layer and the p-type electrode layer; a plurality of groups of photosensitive elements, and each group of photosensitive elements includes a photosensitive element to be tested and four adjacent photosensitive elements of the same area. The verification device can comprehensively evaluate the material performance and process capability of the detector chip, and provide important reference data for iterative material structure design and optimization of chip manufacturing process parameters.

Description

Technical Field

[0001] The invention belongs to the technical field of infrared detector chip manufacturing, in particular to a verification device for the material performance and process capability of a detector chip. Background Art

[0002] Infrared detectors are widely used in aerospace, precision guidance, night vision imaging, medical imaging, gas detection and analysis, etc. As the core component of infrared detection system, the performance index and process capability of infrared detector chip are crucial to infrared detection manufacturing.

[0003] The preparation method of detector chip is usually the selection of materials and material structure - chip structure design - photolithography etching - chip passivation - photolithography electrode window opening - metallization electrode preparation, etc. In terms of materials and material structure, it is divided into pn structure such as HgCdTe, InSb, nBp structure (n-type-barrier-p-type), PIN structure (p-type-intrinsic-n-type) and superlattice InAs / GaSb structure and other material structures. The semiconductor material to be used is determined according to the response band of the detector application and the chip operating temperature.

[0004] The structural design of the chip includes: the number of elements of the photosensitive surface, such as: unit, multi-element, linear array or area array, the size of the photosensitive element and the center distance between the photosensitive elements, etc. The required chip structure is generally achieved through the design of the photolithography board; according to the requirements of the chip structure and process, multiple photolithography and etching are usually used, including: photosensitive surface pattern lithography and photosensitive surface table etching, and the etching is divided into wet etching and dry etching. Regardless of the etching method, the etched photosensitive surface side is required to be neat, smooth and free of residue. The detector chip passivation process usually uses SiO2 and Si3N4 grown by plasma enhanced chemical vapor deposition (PECVD), Al2O3 grown by atomic layer deposition (ALD), sputtered ZnS, etc., or anodization + the above-mentioned thin film medium. Its main purpose is to passivate the dangling bonds on the chip surface and reduce the surface leakage current. The electrode preparation process is usually a vacuum thermal evaporation method to evaporate metal electrodes, mostly using Ti / Pt / Au or Cr / Au, etc. Metallization requires good ohmic contact between the metal and the semiconductor interface.

[0005] In the past, the evaluation of material performance and process capability of detector chips often used verification devices with a single evaluation function, such as only evaluating the current-voltage (IV) characteristics or only evaluating the capacitance-voltage (CV) characteristics, which cannot be evaluated and analyzed comprehensively and comprehensively because multiple indicators of the chip affect each other. In order to solve the above technical problems, the present invention proposes a verification device for the material performance and process capability of detector chips. Summary of the invention

[0006] The device for verifying the material performance and process capability of the detector chip is a (n-type-barrier-p-type) nBp stacked structure grown on a GaSb substrate, in which the n-type layer is Si-doped InAsSb, the absorption layer is non-actively doped InAsSb, the barrier layer (B) is AlAsSb, and the p-type layer is Be-doped InAsSb infrared detector material. After multiple photolithography and etching at different depths, the following functional areas and corresponding structures are realized. This photolithography and etching method is equivalent to the commonly used infrared detector preparation method and is an existing technology for technicians in this field. One difference is that the area for the capacitance-voltage (CV) characteristic test requires the metal-insulator-semiconductor (MIS) structure to be made on the surface of the absorption layer of the infrared detector material.

[0007] The present invention integrates: a chip structure with photosensitive element areas of different sizes; a plurality of metal-insulating layer-semiconductor structures, wherein at least one MIS structure has a capacitor area that is 1000-20000 times that of the other MIS structures, and the capacitor is used as a common electrode during capacitance-voltage characteristic testing; a transmission line model structure formed by rectangular electrodes with unequal intervals distributed on an n-type electrode layer and a p-type electrode layer; a plurality of groups of photosensitive elements, wherein each group of photosensitive elements includes a photosensitive element to be tested and four adjacent photosensitive elements of the same area, wherein the spacings between the four adjacent photosensitive elements and the photosensitive element to be tested are the same, and the spacings in different groups of photosensitive elements are different, and in each group of photosensitive elements, a metallization layer covers four adjacent photosensitive elements, and the photosensitive element to be tested tests the responses of the adjacent photosensitive elements shielded by the four metallization layers under the irradiation of a small light spot, and the response of each of the four adjacent photosensitive elements divided by the response of the photosensitive element to be tested is the crosstalk rate.

[0008] The superlattice infrared detector material grown on a GaSb substrate by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOVCD) adopts an nBp stacking structure, which includes a p-type layer, an absorption layer, a barrier layer, and an n-type layer grown in sequence from the substrate to the surface, wherein the n-type layer is Si-doped InAsSb, the absorption layer is non-actively doped InAsSb, the barrier layer (B) is AlAsSb, and the p-type layer is Be-doped InAsSb. The electrode layers in this verification device are all made of Cr / Au prepared by electron thermal evaporation, and the passivation layer is made of Si3N4 prepared by chemical vapor deposition (CVD).

[0009] The chip structure of different photosensitive element areas used to test IV characteristics is composed of multiple square photosensitive elements with a side length of 15µm×15µm-2000µm×2000µm. The IV characteristic test is to obtain the curve between the p-type layer total electrode and the n-type electrode on each photosensitive element, thereby obtaining the dark current measured with different voltages.

[0010] The MIS (metal-insulating layer-semiconductor) structure with measurable CV characteristics used to characterize the effect of the chip surface passivation process is a circular or square capacitor of different sizes, wherein at least one of the capacitor areas in the MIS structure is 1000-20000 times the capacitor area in other MIS structures. The capacitor is used as a common electrode during the CV characteristic test and is a large-area capacitor, while the other capacitors are small-area capacitors. In theory, the large-area capacitor is much larger than other small-area capacitors, and the present invention recommends that the area of ​​the large-area capacitor is 1000-20000 times the area of ​​other small-area capacitors. The large-area capacitor is in a series relationship with other small-area capacitors, so the result measured by the large-area capacitor is approximately equal to the result of the small-area capacitor in practical applications. The capacitor is a MIS structure of different sizes formed after passivation and metallization on the absorption layer, photolithography, and corrosion.

[0011] The transmission line model structure that characterizes the ohmic contact between the n-type electrode layer and the p-type electrode layer of the detector chip is a rectangular electrode structure with unequal intervals distributed on the n-type layer and the p-type layer respectively. The surface contact resistance can be obtained according to the transmission line model theory.

[0012] The photosensitive element structure for characterizing shielded background and non-shielded background radiation shares the same area with the chip structure for characterizing the IV characteristic test mentioned above, except that the two rows of photosensitive elements for measuring IV characteristics are arranged side by side, one of which is shielded by a metal layer. The shielding layer is a metalized metal layer that blocks the photosensitive surface. The dark current measured by the shielded row of photosensitive elements is the dark current shielded by the chip test temperature, and the other adjacent row of photosensitive elements is non-shielded, and the dark current measured is the dark current of the ambient background radiation.

[0013] The structure for characterizing the electrical crosstalk between photosensitive elements is a plurality of groups of photosensitive elements, each group of photosensitive elements includes a photosensitive element to be tested (central photosensitive element) and four adjacent photosensitive elements of the same area, the spacing between the four adjacent photosensitive elements and the photosensitive element to be tested is the same; the above spacing is different in different groups of photosensitive elements; in each group of photosensitive elements, the metallization layer covers the four adjacent photosensitive elements, and the photosensitive element to be tested tests the responses of the four adjacent photosensitive elements under the irradiation of a small light spot, and the response signal is obtained between the total electrode of the p-type layer and the n-type electrode on each photosensitive element, and the electrical crosstalk response data at different spacings can be obtained, and the response of each of the four adjacent photosensitive elements divided by the response of the photosensitive element to be tested is the crosstalk rate.

[0014] The infrared detector material of the nBp stacked structure characterized by the verification device can be a detector material grown by either molecular beam epitaxy (MBE) or metal organic compound vapor deposition (MOCVD).

[0015] The test platform for the verification device is a low-temperature variable temperature probe station and a semiconductor parameter tester including an IV characteristic test module, a CV characteristic test module, and an infrared electric radiation small light spot generation system. The low-temperature variable temperature probe station used has a test temperature range of 20K-300K, and variable temperature testing (temperature interval 20K) is used to characterize the material and device characteristics at different temperatures.

[0016] The processing and analysis of the test results and the obtained test data are equivalent to the infrared detector theory and device performance analysis methods commonly used by technicians in this field. For example, the IV characteristic test of photosensitive elements of different sizes can obtain different dark currents, dynamic impedances, and leakage currents corresponding to different bias voltages and different temperatures. The shielded and unshielded photosensitive elements can obtain dark currents under low temperature backgrounds and room temperature backgrounds respectively. The product of the impedance of photosensitive elements of different sizes and the area of ​​the photosensitive elements is used to establish the ratio of the perimeter and area of ​​different photosensitive elements to evaluate the effect of the passivation process.

[0017] CV characteristic test can analyze the interface state formed by chip passivation, factors affecting surface leakage current, etc., so as to evaluate the effect and repeatability of the passivation process.

[0018] The transmission line model with different electrode spacings for the n-type layer and the p-type layer can obtain the contact resistance of the n-type layer and the p-type layer respectively, thereby obtaining the influence of the electrode metal type and the level of the electrode preparation process. It can also partially reflect the doping status of the material in contact with the electrode, or reflect whether the electrode preparation process parameters meet the device index requirements.

[0019] The crosstalk between photosensitive elements depends on the spacing between the photosensitive element to be measured and the adjacent photosensitive element. The size of the mutual crosstalk can be obtained by using adjacent photosensitive element structures with different spacings, which provides a basis for the final spacing structure design of the detector or takes necessary measures to suppress it.

[0020] The technical solution of the present invention has the following advantages over the prior art:

[0021] Through the special structural design of the photolithography pattern and the chip photosensors, the present invention can collect rich performance information of detector materials and device processes in many aspects, thereby characterizing the impact of material and device design on the performance of infrared detectors and providing data support for iterative design and improvement of materials and device processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 It is a partial schematic diagram of the overall structure and functional areas of the present invention.

[0024] Figure 2 It is a partial schematic diagram of the distribution of various chips and electrodes of the present invention.

[0025] Figure 3 Schematic diagram of each functional layer of the present invention.

[0026] Description of reference numerals:

[0027] 1. CV characteristic test area; 2. n-type contact resistance transmission line model area; 3. p-type contact resistance transmission line model area; 4. IV characteristic test area; 5. Electrical crosstalk performance test area; 6. CV test area metal electrode; 7. Passivation layer; 8. p-type layer; 9. Absorption layer; 10. Barrier layer; 11. n-type layer; 12. p-type layer metal electrode; 13. n-type layer metal electrode; 14. GaSb substrate. DETAILED DESCRIPTION

[0028] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0029] In the present invention, unless otherwise explained, technical and scientific terms used in the present invention have the same meanings as commonly understood by those skilled in the art to which the present invention belongs. Example 1

[0030] Reference Figure 1 , 2 As shown in Figure 3, this embodiment uses a superlattice infrared detector material grown on a GaSb substrate by molecular beam epitaxy (MBE) method, and adopts an nBp stacking structure. The nBp stacking structure includes a p-type layer, an absorption layer, a barrier layer, and an n-type layer grown in sequence from the substrate to the surface layer, wherein the n-type layer is Si-doped InAsSb, the absorption layer is non-actively doped InAsSb, the barrier layer (B) is AlAsSb, and the p-type layer is Be-doped InAsSb. The electrode layers in the verification device are all made of Cr / Au prepared by electron thermal evaporation; the passivation layer is made of SiO2 prepared by CVD method.

[0031] The above-mentioned verification device refers to a verification device for the material performance and process capability of the detector chip provided in this embodiment, and the verification device can characterize the performance and related process capability of the above-mentioned superlattice infrared detector material adopting the nBp stacking structure.

[0032] Understandably, Figures 1 to 3 It is a partial schematic diagram of the above-mentioned verification device, including:

[0033] From the GaSb substrate 14 to the CV characteristic test area 1 , there are the GaSb substrate 14 , the p-type layer 8 , the absorption layer 9 , the passivation layer 7 , and the CV characteristic test area 1 in sequence; wherein the CV characteristic test area 1 includes a CV test area metal electrode 6 .

[0034] From the GaSb substrate 14 to the n-type contact resistance transmission line model region 2, there are the GaSb substrate 14, the p-type layer 8, the absorption layer 9, the barrier layer 10, the n-type layer 11, and the n-type contact resistance transmission line model region 2 in sequence.

[0035] From the GaSb substrate 14 to the p-type contact resistance transmission line model region 3 , there are the GaSb substrate 14 , the p-type layer 8 , and the p-type contact resistance transmission line model region 3 in sequence.

[0036] From the GaSb substrate 14 to the IV characteristic test area 4, there are the GaSb substrate 14, the p-type layer 8, the absorption layer 9, the barrier layer 10, the n-type layer 11, and the IV characteristic test area 4. Among them, the IV characteristic test area 4 is a common area for characterizing the photosensitive element structure for shielding background and non-shielding background radiation, and the chip structure for characterizing the IV characteristic test. The IV characteristic test is to obtain its curve between the p-type layer metal electrode 12 and the n-type electrode on each photosensitive element.

[0037] From the GaSb substrate 14 to the electrical crosstalk performance test area 5, there are the GaSb substrate 14, the p-type layer 8, the absorption layer 9, the barrier layer 10, the n-type layer 11, and the electrical crosstalk performance test area 5. The electrical crosstalk performance test area 5 includes the n-type layer metal electrode 13.

[0038] The specific structure provided below in this embodiment 1 is a complete structure of the above-mentioned verification device.

[0039] The chip structure for testing IV characteristics of different sizes of photosensitive element areas is composed of two rows of ten square photosensitive elements, and the side lengths of the photosensitive elements are 15µm, 25µm, 30µm, 40µm, 50µm, 100µm, 200µm, 500µm, 1000µm, and 1500µm respectively.

[0040] The structure of photosensitive elements used to characterize shielded background and non-shielded background radiation, in the IV characteristic test area, one of the two rows of photosensitive elements measuring IV characteristics is shielded, the shielding layer is a metalized metal layer that blocks the photosensitive surface, the dark current measured by the shielded row of photosensitive elements is the dark current shielded by the chip test temperature, the other adjacent row of photosensitive elements is not shielded by the metal layer, and the dark current measured is the dark current of the ambient background radiation. The entire photosensitive surface of the shielded row of photosensitive element chips is covered with a metal layer, which means that the background radiation is shielded during the test, and the covered electrode (metal layer) is equivalent to adding a cold screen on the chip with the same temperature as the chip.

[0041] The MIS structure for measuring CV characteristics used to characterize the effect of the chip surface passivation process is a square capacitor. The capacitor is a MIS structure of different sizes formed after passivation and metallization on the absorption layer, photolithography, and etching. Among them, there is a square capacitor with a side length of 3000µm. This capacitor can be used as a common electrode for CV characteristic testing and is a large-area capacitor; the others are 25µm, 50µm, and 80µm respectively, which are small-area capacitors to meet the requirement that large-area capacitors are much larger than small-area capacitors; large-area capacitors are in series with other small-area capacitors, so the results measured by large-area capacitors are approximately equal to those of small-area capacitors in practical applications.

[0042] The transmission line model structure used to characterize the ohmic contact of the n-type electrode layer and the p-type electrode layer on the detector chip has a working principle that is one of the commonly used models for characterizing ohmic contact resistance in semiconductor device theory. The specific model of the present invention is that rectangular electrodes with unequal spacing are distributed on the n-type layer and the p-type layer. There are 7 electrodes of the same area on the n-type layer and the p-type layer. The side length of each electrode is 80µm×10µm, and the spacing between them is 20µm, 30µm, 50µm, 80µm, 100µm, and 150µm respectively. The resistance of two adjacent electrodes is measured as the ordinate, and the spacing between adjacent electrodes is the abscissa. The electrode contact resistance can be obtained by fitting a straight line.

[0043] The chip structure used to characterize the electrical crosstalk between photosensitive elements is divided into three groups, each group has five photosensitive elements of the same size, divided into the photosensitive element to be tested and four adjacent photosensitive elements. The spacing between the four adjacent photosensitive elements and the photosensitive element to be tested is the same. In this example, the size of the photosensitive elements is 50µm×50µm. The spacing between the photosensitive element to be tested and the adjacent photosensitive elements in the three groups (the distance between the edges of the photosensitive elements) is different to measure the response crosstalk under the spacing. The spacing between the photosensitive element to be tested and the adjacent photosensitive elements in the three groups is 10µm, 15µm and 20µm respectively. The metallization layer covers the four adjacent photosensitive elements. The photosensitive element to be tested in the center tests the response of the four adjacent photosensitive elements under the illumination of a small light spot. The response of each of the four adjacent photosensitive elements divided by the response of the photosensitive element to be tested is the crosstalk rate.

[0044] The evaluation of the above-mentioned verification devices is carried out in a low-temperature variable temperature probe station and test instruments, which include a semiconductor parameter tester for testing IV and CV characteristic modules, an infrared electric radiation small light spot generation system, etc. The low-temperature variable temperature probe station used has a test temperature range of 20K-300K. The variable temperature test (temperature interval 20K) is used to characterize the material and device characteristics at different temperatures. The test results and the obtained test data can be used to evaluate the level and capability of the characterized detector material and device process according to the usual infrared detector-related theory and mechanism analysis.

Claims

1. A device for verifying the material performance and process capability of a detector chip, characterized in that: The infrared detector material of nBp stacked structure grown on GaSb substrate integrates: chip structure with different sizes of photosensitive element areas; multiple metal-insulating layer-semiconductor structures, and at least one of the metal-insulating layer-semiconductor structures has a capacitor area that is 1000-20000 times that of other capacitor areas, and the capacitor is used as a common electrode during capacitance-voltage characteristic testing; a transmission line model structure formed by rectangular electrodes with unequal intervals distributed on the n-type electrode layer and the p-type electrode layer; multiple groups of photosensitive elements, and each group of photosensitive elements includes a photosensitive element to be tested and four adjacent photosensitive elements of the same area, the spacing between the four adjacent photosensitive elements and the photosensitive element to be tested is the same, and the spacing in different groups of photosensitive elements is different, in each group of photosensitive elements, the metallization layer covers the four adjacent photosensitive elements, and the photosensitive element to be tested tests the response of the adjacent photosensitive elements shielded by the four metallization layers under the irradiation of a small light spot, and the response of each of the four adjacent photosensitive elements is divided by the response of the photosensitive element to be tested to obtain the crosstalk rate.

2. The device for verifying the material performance and process capability of the detector chip according to claim 1, characterized in that: The nBp stacked structure includes a p-type layer, an absorption layer, a barrier layer, and an n-type layer grown in sequence from the substrate to the surface, wherein the n-type layer is Si-doped InAsSb, the absorption layer is non-actively doped InAsSb, the barrier layer is AlAsSb, and the p-type layer is Be-doped InAsSb; the electrode layers in the verification device are all made of Cr / Au, and the passivation layer is made of Si3N4 prepared by chemical vapor deposition method.

3. The device for verifying the material performance and process capability of the detector chip according to claim 1, characterized in that: The chip structure with different sizes of photosensitive element areas is composed of multiple square photosensitive elements and the side length of each photosensitive element is 15µm×15µm-2000µm×2000µm.

4. The device for verifying the material performance and process capability of the detector chip according to claim 1, characterized in that: The metal-insulator-semiconductor structure for measuring capacitance-voltage characteristics is a circle or square of different sizes, and is formed by photolithography and etching after passivation and metallization on the absorption layer.

5. The device for verifying the material performance and process capability of the detector chip according to claim 1, characterized in that: The chip structure with different sizes of photosensitive element areas is used to test the current-voltage characteristics and characterize the shielded background and unshielded background radiation. The photosensitive elements in the chip structure with different sizes of photosensitive element areas are divided into two rows of shielded and unshielded. The shielding layer is a metallized layer that blocks the photosensitive surface. The dark current measured by the shielded row of photosensitive elements is the dark current shielded by the chip test temperature. The photosensitive elements in the other adjacent row are shielded by a non-metallic layer, and the dark current measured is the dark current of the environmental background radiation.

6. The device for verifying the material performance and process capability of the detector chip according to claim 1, characterized in that: The infrared detector material of the nBp stacked structure characterized by the verification device can be a detector material grown by either a molecular beam epitaxy method or a metal organic compound vapor deposition method.

7. The device for verifying the material performance and process capability of the detector chip according to claim 1, characterized in that: The test platform for evaluating the verification device is a low-temperature variable temperature probe station and a semiconductor parameter tester including a current-voltage characteristic test module, a capacitance-voltage characteristic test module, and an infrared electric radiation small light spot generation system.

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